Lines Matching refs:RS
393 #define RS RBS + 1 macro
394 #define RT RS
400 #define RSQ RS + 1
1806 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
1807 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
1808 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
1809 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
1810 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
1811 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
1812 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
1813 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
1820 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
1821 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
1822 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
1823 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
1824 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
1825 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
1826 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
1827 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
1828 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
1829 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
1830 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
1831 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
1832 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
1833 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
1834 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
1993 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
1994 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
1995 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
1996 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
1997 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
1998 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
1999 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2000 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2001 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2002 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2003 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2004 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2005 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2007 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2009 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2010 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2011 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2012 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2013 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2014 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2015 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2016 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2017 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2018 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2020 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2021 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2022 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2023 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2024 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2025 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2026 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2027 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2028 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2029 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2030 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2031 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2032 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2033 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2040 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2042 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2043 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2044 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2045 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2046 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2047 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2048 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2049 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2050 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2051 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2052 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2053 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2054 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2055 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2056 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2057 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2058 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2059 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2060 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2061 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2062 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2063 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2065 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2066 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2067 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2068 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2069 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2070 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2071 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2072 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2073 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2074 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2075 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2076 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2077 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2078 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2080 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2081 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2082 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2083 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2084 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2085 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2086 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2093 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2094 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2095 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2096 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2097 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2098 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2099 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2100 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2101 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2102 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2104 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2105 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2106 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2107 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2108 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2109 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2110 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2117 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2118 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2119 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2120 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2121 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2122 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2123 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2124 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2125 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2126 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2128 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2129 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2130 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2132 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2134 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2135 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2136 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2137 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2138 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2139 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2140 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2141 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2142 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2143 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2145 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2146 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2147 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2148 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2149 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2151 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2152 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2153 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2154 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2155 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2156 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2158 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2159 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2160 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2161 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2162 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2163 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2164 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2165 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2166 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2167 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2169 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2171 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2172 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2173 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2174 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2175 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2176 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2178 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2179 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2180 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2181 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2182 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2183 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2185 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2187 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2188 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2189 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2190 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2194 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2197 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2198 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2199 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2200 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2202 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2203 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2205 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2207 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2208 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2209 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2210 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2211 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2212 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2213 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2214 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2216 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2217 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2218 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2219 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2221 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2222 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2223 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2224 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2226 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2227 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2228 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2229 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2231 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2232 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2233 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2234 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2236 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2238 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2239 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2979 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2980 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2982 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2983 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2985 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2986 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2987 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2988 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2989 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2990 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2991 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2992 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2994 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2995 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3002 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3003 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3004 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3005 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3006 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3007 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3010 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3011 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3013 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3014 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3016 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3017 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3019 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3020 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3022 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3023 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3025 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3026 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3028 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3029 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3030 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3031 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3032 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3033 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3035 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3036 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3038 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3039 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3041 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3042 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3044 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3045 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3046 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3047 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3049 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3050 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3136 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3137 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3138 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3139 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3141 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3142 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3143 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3144 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3146 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3147 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3149 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3150 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3152 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3153 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3184 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3185 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3187 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3188 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3212 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3213 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3215 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3240 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3246 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3248 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3249 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3250 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3251 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3257 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3281 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3282 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3283 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3285 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3287 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3289 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3291 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3292 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3294 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3296 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3298 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3299 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3301 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3302 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3304 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3311 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
3313 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3315 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3316 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3318 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3319 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3321 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3323 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3343 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3345 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3347 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3349 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3350 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3352 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3353 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3355 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3392 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3393 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3397 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3399 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3400 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3404 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3406 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3433 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3434 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3447 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3448 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3716 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3728 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3730 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3732 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
3746 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3747 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3749 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3750 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3752 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3758 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3760 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3769 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3770 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3771 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3772 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3774 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3775 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3776 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3777 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3778 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3779 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3780 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3781 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3782 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3783 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3784 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3785 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3786 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3787 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3788 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3789 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3790 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3791 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3792 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3793 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3794 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3795 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3796 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3797 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3798 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3799 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3800 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3801 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3802 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3803 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3804 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3805 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3806 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3807 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3808 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3826 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3827 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3828 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3829 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3830 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3831 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3832 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3833 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3834 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3835 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3836 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3837 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3838 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3839 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3840 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
3841 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3842 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3843 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3844 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3845 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3846 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3847 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3848 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3849 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3850 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3851 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3852 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3853 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3854 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3855 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3856 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3857 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3858 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3859 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3860 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3861 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3862 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3863 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3864 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3865 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3866 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3867 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3868 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3869 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
3870 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3871 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3872 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3873 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3874 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3875 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3876 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3877 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3878 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3879 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3880 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3881 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3882 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3883 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3884 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3885 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3886 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3887 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3888 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3889 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3890 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3891 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3892 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3893 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3894 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3895 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3896 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3897 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3898 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3899 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3900 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3901 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3902 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3903 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3904 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3905 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3906 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3907 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3908 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3909 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3910 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3911 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3912 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3913 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3914 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3915 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3916 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3917 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3918 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3919 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3920 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3921 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3922 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
3923 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
3924 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
3925 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
3926 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
3927 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
3928 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
3929 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
3930 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
3931 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
3932 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3933 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3934 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3935 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3936 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
3937 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
3938 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
3939 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
3940 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
3941 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
3942 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
3943 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
3944 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
3945 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
3946 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
3947 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
3948 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
3949 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
3950 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
3951 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
3952 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
3953 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
3954 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
3955 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
3956 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
3957 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
3958 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
3959 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
3960 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
3961 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
3962 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
3963 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
3964 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
3965 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
3966 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
3967 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
3968 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
3969 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
3970 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
3971 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
3972 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
3973 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
3974 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
3975 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
3976 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
3977 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
3978 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3982 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3983 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3989 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4019 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4038 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4039 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4040 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4041 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4043 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4044 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4046 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4047 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4049 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4050 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4083 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4091 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4093 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4094 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4096 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4097 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4101 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4102 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4104 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4105 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4107 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4113 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4114 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4118 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4119 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4123 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4124 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4126 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4127 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4137 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4138 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4151 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4152 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4153 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4154 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4156 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4157 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4171 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4172 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4173 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4174 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4194 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4196 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4198 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4199 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4201 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4202 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4204 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4205 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4206 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4207 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4209 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4211 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4217 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4219 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4220 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4222 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4223 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4225 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4234 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4240 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4241 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4250 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4296 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4297 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4299 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4300 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4302 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4304 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4314 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4316 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4321 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4322 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4356 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4357 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4358 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4359 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4360 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4361 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4481 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4482 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4488 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4490 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },