Lines Matching refs:VT
680 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { in getATOMIC() argument
683 switch (VT.SimpleTy) { \ in getATOMIC()
801 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
805 setIndexedLoadAction(IM, VT, Expand); in initActions()
806 setIndexedStoreAction(IM, VT, Expand); in initActions()
810 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
813 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
814 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
815 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
816 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
817 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
818 setOperationAction(ISD::SMIN, VT, Expand); in initActions()
819 setOperationAction(ISD::SMAX, VT, Expand); in initActions()
820 setOperationAction(ISD::UMIN, VT, Expand); in initActions()
821 setOperationAction(ISD::UMAX, VT, Expand); in initActions()
824 setOperationAction(ISD::SADDO, VT, Expand); in initActions()
825 setOperationAction(ISD::SSUBO, VT, Expand); in initActions()
826 setOperationAction(ISD::UADDO, VT, Expand); in initActions()
827 setOperationAction(ISD::USUBO, VT, Expand); in initActions()
828 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
829 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
832 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
835 if (VT.isVector()) { in initActions()
836 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in initActions()
837 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
838 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
839 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
856 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { in initActions()
857 setOperationAction(ISD::FLOG , VT, Expand); in initActions()
858 setOperationAction(ISD::FLOG2, VT, Expand); in initActions()
859 setOperationAction(ISD::FLOG10, VT, Expand); in initActions()
860 setOperationAction(ISD::FEXP , VT, Expand); in initActions()
861 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
862 setOperationAction(ISD::FFLOOR, VT, Expand); in initActions()
863 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
864 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
865 setOperationAction(ISD::FNEARBYINT, VT, Expand); in initActions()
866 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
867 setOperationAction(ISD::FRINT, VT, Expand); in initActions()
868 setOperationAction(ISD::FTRUNC, VT, Expand); in initActions()
869 setOperationAction(ISD::FROUND, VT, Expand); in initActions()
896 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { in canOpTrap()
897 assert(isTypeLegal(VT)); in canOpTrap()
918 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { in getTypeConversion()
920 if (VT.isSimple()) { in getTypeConversion()
921 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
940 if (!VT.isVector()) { in getTypeConversion()
941 assert(VT.isInteger() && "Float types must be simple"); in getTypeConversion()
942 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
945 EVT NVT = VT.getRoundIntegerType(Context); in getTypeConversion()
946 assert(NVT != VT && "Unable to round integer VT"); in getTypeConversion()
956 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
960 unsigned NumElts = VT.getVectorNumElements(); in getTypeConversion()
961 EVT EltVT = VT.getVectorElementType(); in getTypeConversion()
973 if (!VT.isPow2VectorType()) { in getTypeConversion()
1040 if (!VT.isPow2VectorType()) { in getTypeConversion()
1041 EVT NVT = VT.getPow2VectorType(Context); in getTypeConversion()
1046 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); in getTypeConversion()
1050 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1055 unsigned NumElts = VT.getVectorNumElements(); in getVectorTypeBreakdownMVT()
1056 MVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdownMVT()
1172 MVT VT) const { in findRepresentativeClass()
1173 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1296 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1297 if (isTypeLegal(VT)) in computeRegisterProperties()
1300 MVT EltVT = VT.getVectorElementType(); in computeRegisterProperties()
1301 unsigned NElts = VT.getVectorNumElements(); in computeRegisterProperties()
1303 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); in computeRegisterProperties()
1318 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); in computeRegisterProperties()
1335 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1348 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1352 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1353 if (NVT == VT) { in computeRegisterProperties()
1357 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); in computeRegisterProperties()
1359 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1362 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector in computeRegisterProperties()
1366 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1390 EVT VT) const { in getSetCCResultType()
1391 assert(!VT.isVector() && "No default SetCC type for vectors!"); in getSetCCResultType()
1408 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, in getVectorTypeBreakdown() argument
1412 unsigned NumElts = VT.getVectorNumElements(); in getVectorTypeBreakdown()
1419 LegalizeTypeAction TA = getTypeAction(Context, VT); in getVectorTypeBreakdown()
1421 EVT RegisterEVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
1431 EVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdown()
1486 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1498 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1500 if (VT.bitsLT(MinVT)) in GetReturnInfo()
1501 VT = MinVT; in GetReturnInfo()
1504 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); in GetReturnInfo()
1505 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); in GetReturnInfo()
1519 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); in GetReturnInfo()