116   bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
120                           unsigned RegA, unsigned RegB, unsigned Dist);
537 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {  in regsAreCompatible()  argument
538   if (RegA == RegB)  in regsAreCompatible()
540   if (!RegA || !RegB)  in regsAreCompatible()
542   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
668     unsigned RegA = MI->getOperand(0).getReg();  in commuteInstruction()  local
669     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
678 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){  in isProfitableToConv3Addr()  argument
688   unsigned ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
697                                               unsigned RegA, unsigned RegB,  in convertInstTo3Addr()  argument
728   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1447     unsigned RegA = DstMO.getReg();  in processTiedPairs()  local
1454     if (RegA == RegB) {  in processTiedPairs()
1461     LastCopiedReg = RegA;  in processTiedPairs()
1473              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1478                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1484       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1485         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1492         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1506       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1507         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1526     if (TargetRegisterInfo::isVirtualRegister(RegA) &&  in processTiedPairs()
1528       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1529     MO.setReg(RegA);  in processTiedPairs()
1536     SrcRegMap[RegA] = RegB;  in processTiedPairs()