Lines Matching refs:DAG
577 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
578 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
581 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
582 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
583 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
584 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG); in LowerOperation()
586 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG); in LowerOperation()
587 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
588 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW); in LowerOperation()
590 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
591 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
592 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
594 SDValue Result = LowerLOAD(Op, DAG); in LowerOperation()
601 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
602 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG); in LowerOperation()
612 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2)); in LowerOperation()
621 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
622 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
623 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
624 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
626 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
641 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
645 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
648 return DAG.getCopyFromReg(DAG.getEntryNode(), in LowerOperation()
649 SDLoc(DAG.getEntryNode()), Reg, VT); in LowerOperation()
659 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, in LowerOperation()
660 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32)); in LowerOperation()
661 return DAG.getTargetExtractSubreg( in LowerOperation()
665 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
671 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(), in LowerOperation()
672 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32); in LowerOperation()
673 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(), in LowerOperation()
674 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32); in LowerOperation()
677 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL, in LowerOperation()
678 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32), in LowerOperation()
681 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL, in LowerOperation()
682 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32), in LowerOperation()
694 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL, in LowerOperation()
695 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), in LowerOperation()
698 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL, in LowerOperation()
699 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32), in LowerOperation()
701 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
755 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
757 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
758 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
759 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
760 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
764 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
765 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
766 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
767 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
775 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
779 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
780 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
781 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
782 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
784 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
786 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
787 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
788 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
790 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
792 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
794 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
796 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
800 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
802 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
804 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
806 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
808 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
810 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
812 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
814 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
816 return LowerImplicitParameter(DAG, VT, DL, 8); in LowerOperation()
820 return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4); in LowerOperation()
824 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, in LowerOperation()
827 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, in LowerOperation()
830 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, in LowerOperation()
833 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, in LowerOperation()
836 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, in LowerOperation()
839 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, in LowerOperation()
843 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1)); in LowerOperation()
847 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerOperation()
858 SelectionDAG &DAG) const { in ReplaceNodeResults()
861 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
865 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG)); in ReplaceNodeResults()
873 if (expandFP_TO_SINT(N, Result, DAG)) in ReplaceNodeResults()
879 SDValue RES = LowerSDIVREM(Op, DAG); in ReplaceNodeResults()
886 LowerUDIVREM64(Op, DAG, Results); in ReplaceNodeResults()
892 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG, in vectorToVerticalVector() argument
902 Args.push_back(DAG.getNode( in vectorToVerticalVector()
904 DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout())))); in vectorToVerticalVector()
907 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
911 SelectionDAG &DAG) const { in LowerEXTRACT_VECTOR_ELT()
921 Vector = vectorToVerticalVector(DAG, Vector); in LowerEXTRACT_VECTOR_ELT()
922 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
927 SelectionDAG &DAG) const { in LowerINSERT_VECTOR_ELT()
937 Vector = vectorToVerticalVector(DAG, Vector); in LowerINSERT_VECTOR_ELT()
938 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
940 return vectorToVerticalVector(DAG, Insert); in LowerINSERT_VECTOR_ELT()
943 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const { in LowerTrig()
949 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
950 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
951 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
952 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
953 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
965 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
966 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
967 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
971 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
972 DAG.getConstantFP(3.14159265359, DL, MVT::f32)); in LowerTrig()
975 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const { in LowerSHLParts()
982 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSHLParts()
983 SDValue One = DAG.getConstant(1, DL, VT); in LowerSHLParts()
985 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSHLParts()
986 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts()
987 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSHLParts()
988 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
995 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
996 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
998 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
999 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow); in LowerSHLParts()
1000 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
1002 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
1005 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
1006 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1008 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
1011 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const { in LowerSRXParts()
1018 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSRXParts()
1019 SDValue One = DAG.getConstant(1, DL, VT); in LowerSRXParts()
1023 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSRXParts()
1024 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts()
1025 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSRXParts()
1026 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
1033 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
1034 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
1036 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1037 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
1038 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); in LowerSRXParts()
1040 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1041 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
1043 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1044 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
1046 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
1049 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG, in LowerUADDSUBO() argument
1057 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
1059 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
1060 DAG.getValueType(MVT::i1)); in LowerUADDSUBO()
1062 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
1064 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
1067 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const { in LowerFPTOUINT()
1069 return DAG.getNode( in LowerFPTOUINT()
1073 Op, DAG.getConstantFP(0.0f, DL, MVT::f32), in LowerFPTOUINT()
1074 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1078 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter() argument
1082 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), in LowerImplicitParameter()
1088 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
1089 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
1104 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC()
1116 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in LowerSELECT_CC()
1143 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
1149 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1157 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1177 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1185 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1198 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
1199 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
1214 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1217 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1218 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1226 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT); in LowerSELECT_CC()
1227 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT); in LowerSELECT_CC()
1229 HWTrue = DAG.getConstant(-1, DL, CompareVT); in LowerSELECT_CC()
1230 HWFalse = DAG.getConstant(0, DL, CompareVT); in LowerSELECT_CC()
1238 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1240 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1243 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
1253 SelectionDAG &DAG) const { in stackPtrToRegIndex()
1269 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1270 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1302 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { in LowerSTORE()
1309 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG); in LowerSTORE()
1321 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1324 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1326 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, in LowerSTORE()
1327 DAG.getConstant(2, DL, MVT::i32)); in LowerSTORE()
1328 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr, in LowerSTORE()
1329 DAG.getConstant(0x00000003, DL, VT)); in LowerSTORE()
1330 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1331 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1332 DAG.getConstant(3, DL, VT)); in LowerSTORE()
1333 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift); in LowerSTORE()
1334 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift); in LowerSTORE()
1339 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1340 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1343 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src); in LowerSTORE()
1345 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL, in LowerSTORE()
1351 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(), in LowerSTORE()
1352 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
1353 Ptr, DAG.getConstant(2, DL, MVT::i32))); in LowerSTORE()
1358 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1370 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG); in LowerSTORE()
1376 const MachineFunction &MF = DAG.getMachineFunction(); in LowerSTORE()
1381 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG); in LowerSTORE()
1394 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerSTORE()
1395 DAG.getConstant(PtrIncr, DL, MVT::i32)); in LowerSTORE()
1396 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, in LowerSTORE()
1397 Value, DAG.getConstant(i, DL, MVT::i32)); in LowerSTORE()
1399 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, in LowerSTORE()
1401 DAG.getTargetConstant(Channel, DL, MVT::i32)); in LowerSTORE()
1403 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores); in LowerSTORE()
1406 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value); in LowerSTORE()
1408 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr, in LowerSTORE()
1409 DAG.getTargetConstant(0, DL, MVT::i32)); // Channel in LowerSTORE()
1456 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const in LowerLOAD()
1465 if (SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG)) in LowerLOAD()
1471 LoadNode->getMemOperand()->getValue(), DAG.getDataLayout()))) { in LowerLOAD()
1473 SDValue Ptr = DAG.getZExtOrTrunc( in LowerLOAD()
1475 getPointerTy(DAG.getDataLayout(), AMDGPUAS::PRIVATE_ADDRESS)); in LowerLOAD()
1476 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1477 DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1478 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(), in LowerLOAD()
1480 DAG.getTargetConstant(0, DL, MVT::i32), in LowerLOAD()
1486 ScalarizeVectorLoad(Op, DAG), in LowerLOAD()
1489 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1507 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in LowerLOAD()
1508 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in LowerLOAD()
1509 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in LowerLOAD()
1517 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, in LowerLOAD()
1521 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1522 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1523 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1524 DAG.getConstant(LoadNode->getAddressSpace() - in LowerLOAD()
1530 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1531 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1538 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1551 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr, in LowerLOAD()
1557 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1558 DAG.getValueType(MemVT)); in LowerLOAD()
1561 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1569 const MachineFunction &MF = DAG.getMachineFunction(); in LowerLOAD()
1574 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG); in LowerLOAD()
1587 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, in LowerLOAD()
1588 DAG.getConstant(PtrIncr, DL, MVT::i32)); in LowerLOAD()
1589 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT, in LowerLOAD()
1591 DAG.getTargetConstant(Channel, DL, MVT::i32), in LowerLOAD()
1595 Loads[i] = DAG.getUNDEF(ElemVT); in LowerLOAD()
1597 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4); in LowerLOAD()
1598 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads); in LowerLOAD()
1600 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT, in LowerLOAD()
1602 DAG.getTargetConstant(0, DL, MVT::i32), // Channel in LowerLOAD()
1611 return DAG.getMergeValues(Ops, DL); in LowerLOAD()
1614 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { in LowerBRCOND()
1619 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(), in LowerBRCOND()
1631 SDLoc DL, SelectionDAG &DAG, in LowerFormalArguments() argument
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
1635 *DAG.getContext()); in LowerFormalArguments()
1636 MachineFunction &MF = DAG.getMachineFunction(); in LowerFormalArguments()
1641 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns); in LowerFormalArguments()
1657 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
1662 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), in LowerFormalArguments()
1690 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1691 DAG.getConstant(Offset, DL, MVT::i32), in LowerFormalArguments()
1692 DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1711 SelectionDAG &DAG, SDValue VectorEntry, in CompactSwizzlableVector() argument
1731 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1734 NewBldVec[i] = DAG.getUNDEF(MVT::f32); in CompactSwizzlableVector()
1742 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType()); in CompactSwizzlableVector()
1749 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), in CompactSwizzlableVector()
1753 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, in ReorganizeVector() argument
1787 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), in ReorganizeVector()
1793 SDValue Swz[4], SelectionDAG &DAG, in OptimizeSwizzle() argument
1799 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap); in OptimizeSwizzle()
1803 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1807 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap); in OptimizeSwizzle()
1811 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1824 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine() local
1832 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0), in PerformDAGCombine()
1858 return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0), in PerformDAGCombine()
1861 DAG.getConstant(-1, dl, MVT::i32), // True in PerformDAGCombine()
1862 DAG.getConstant(0, dl, MVT::i32), // False in PerformDAGCombine()
1900 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); in PerformDAGCombine()
1912 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : in PerformDAGCombine()
1913 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); in PerformDAGCombine()
1918 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in PerformDAGCombine()
1935 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(), in PerformDAGCombine()
1977 return DAG.getSelectCC(SDLoc(N), in PerformDAGCombine()
2005 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL); in PerformDAGCombine()
2006 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2035 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL); in PerformDAGCombine()
2036 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2045 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) { in FoldOperand() argument
2047 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo()); in FoldOperand()
2055 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2061 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2114 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32); in FoldOperand()
2157 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2159 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()
2170 SelectionDAG &DAG) const { in PostISelFolding()
2172 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo()); in PostISelFolding()
2222 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG)) in PostISelFolding()
2223 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops); in PostISelFolding()
2228 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG)) in PostISelFolding()
2229 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops); in PostISelFolding()
2242 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32); in PostISelFolding()
2243 return DAG.getMachineNode(Src.getMachineOpcode(), DL, in PostISelFolding()
2279 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG)) in PostISelFolding()
2280 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops); in PostISelFolding()