Lines Matching refs:TII
101 const ARMBaseInstrInfo &TII, in isCSRestore() argument
124 const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
131 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
134 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
139 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
143 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
208 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
218 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
234 const TargetInstrInfo &TII, in emitAligningInstructions() argument
257 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
262 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
271 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
275 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
283 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
300 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
327 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, in emitPrologue()
335 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize), in emitPrologue()
340 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP); in emitPrologue()
418 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, in emitPrologue()
449 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
453 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
462 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
470 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
474 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
482 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), in emitPrologue()
495 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
522 dl, TII, FramePtr, ARM::SP, in emitPrologue()
529 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
536 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
571 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
595 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
617 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
628 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP); in emitPrologue()
647 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
657 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
659 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
661 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
676 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
680 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitPrologue()
699 const ARMBaseInstrInfo &TII = in fixTCReturn() local
714 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); in fixTCReturn()
728 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). in fixTCReturn()
749 const ARMBaseInstrInfo &TII = in emitEpilogue() local
768 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize); in emitEpilogue()
775 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); in emitEpilogue()
776 if (!isCSRestore(MBBI, TII, CSRegs)) in emitEpilogue()
794 ARMCC::AL, 0, TII); in emitEpilogue()
806 ARMCC::AL, 0, TII); in emitEpilogue()
807 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitEpilogue()
814 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
817 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitEpilogue()
823 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); in emitEpilogue()
836 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize()); in emitEpilogue()
846 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize); in emitEpilogue()
950 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPushInst() local
994 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
999 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), in emitPushInst()
1023 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPopInst() local
1067 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1082 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) in emitPopInst()
1113 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Spills() local
1152 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1162 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1169 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1185 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), in emitAlignedDPRCS2Spills()
1203 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1215 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1225 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1273 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Restores() local
1292 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1302 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1318 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1329 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1337 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1407 const ARMBaseInstrInfo &TII) { in GetFunctionSizeInBytes() argument
1411 FnSize += TII.GetInstSizeInBytes(&MI); in GetFunctionSizeInBytes()
1533 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
1633 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); in determineCalleeSaves()
1774 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
1803 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
1809 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
1893 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
1947 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))) in adjustForSegmentedStacks()
1950 AddDefaultPred(BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
1959 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
1963 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
1967 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
1972 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
1975 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
1982 AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)) in adjustForSegmentedStacks()
1985 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
1997 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
2001 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
2006 AddDefaultPred(BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0) in adjustForSegmentedStacks()
2019 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0) in adjustForSegmentedStacks()
2026 AddDefaultPred(BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
2032 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB) in adjustForSegmentedStacks()
2044 AddDefaultPred(AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), in adjustForSegmentedStacks()
2047 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
2054 AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)) in adjustForSegmentedStacks()
2057 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
2064 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))) in adjustForSegmentedStacks()
2067 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
2077 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2081 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2086 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tBL))) in adjustForSegmentedStacks()
2089 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
2096 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) in adjustForSegmentedStacks()
2098 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
2101 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
2108 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2119 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))) in adjustForSegmentedStacks()
2123 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2132 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2137 AddDefaultPred(BuildMI(AllocMBB, DL, TII.get(Opcode))); in adjustForSegmentedStacks()
2142 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))) in adjustForSegmentedStacks()
2146 AddDefaultPred(BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
2155 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2162 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
2166 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()