Lines Matching refs:DAG
1360 SDLoc dl, SelectionDAG &DAG, in LowerCallResult() argument
1366 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
1367 *DAG.getContext(), Call); in LowerCallResult()
1388 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1393 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1399 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1402 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1403 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1404 DAG.getConstant(0, dl, MVT::i32)); in LowerCallResult()
1407 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1411 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1416 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1417 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1418 DAG.getConstant(1, dl, MVT::i32)); in LowerCallResult()
1421 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1431 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1445 SDLoc dl, SelectionDAG &DAG, in LowerMemOpCallTo() argument
1449 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl); in LowerMemOpCallTo()
1450 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
1452 return DAG.getStore(Chain, dl, Arg, PtrOff, in LowerMemOpCallTo()
1457 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, in PassF64ArgInRegs() argument
1465 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1466 DAG.getVTList(MVT::i32, MVT::i32), Arg); in PassF64ArgInRegs()
1475 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, in PassF64ArgInRegs()
1476 getPointerTy(DAG.getDataLayout())); in PassF64ArgInRegs()
1479 dl, DAG, NextVA, in PassF64ArgInRegs()
1490 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
1502 MachineFunction &MF = DAG.getMachineFunction(); in LowerCall()
1516 Outs, OutVals, Ins, DAG); in LowerCall()
1530 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerCall()
1531 *DAG.getContext(), Call); in LowerCall()
1546 Chain = DAG.getCALLSEQ_START(Chain, in LowerCall()
1547 DAG.getIntPtrConstant(NumBytes, dl, true), dl); in LowerCall()
1550 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout())); in LowerCall()
1570 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1573 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1576 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1579 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1586 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1587 DAG.getConstant(0, dl, MVT::i32)); in LowerCall()
1588 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerCall()
1589 DAG.getConstant(1, dl, MVT::i32)); in LowerCall()
1591 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, in LowerCall()
1596 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, in LowerCall()
1602 dl, DAG, VA, Flags)); in LowerCall()
1605 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
1632 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); in LowerCall()
1635 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32); in LowerCall()
1636 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); in LowerCall()
1637 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, in LowerCall()
1640 DAG.InferPtrAlignment(AddArg)); in LowerCall()
1653 auto PtrVT = getPointerTy(DAG.getDataLayout()); in LowerCall()
1655 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl); in LowerCall()
1656 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff); in LowerCall()
1657 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl); in LowerCall()
1658 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset); in LowerCall()
1659 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl, in LowerCall()
1661 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl, in LowerCall()
1664 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
1666 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs, in LowerCall()
1673 dl, DAG, VA, Flags)); in LowerCall()
1678 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
1687 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, in LowerCall()
1704 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, in LowerCall()
1718 auto PtrVt = getPointerTy(DAG.getDataLayout()); in LowerCall()
1735 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4); in LowerCall()
1736 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1737 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), CPAddr, in LowerCall()
1746 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, in LowerCall()
1749 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4); in LowerCall()
1750 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1751 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), CPAddr, in LowerCall()
1767 Callee = DAG.getNode( in LowerCall()
1769 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY)); in LowerCall()
1770 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), Callee, in LowerCall()
1779 DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0, TargetFlags); in LowerCall()
1782 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), in LowerCall()
1783 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee), in LowerCall()
1791 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags); in LowerCall()
1803 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, in LowerCall()
1805 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4); in LowerCall()
1806 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerCall()
1807 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), CPAddr, in LowerCall()
1810 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerCall()
1811 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel); in LowerCall()
1818 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags); in LowerCall()
1849 Ops.push_back(DAG.getRegister(RegsToPass[i].first, in LowerCall()
1870 Ops.push_back(DAG.getRegisterMask(Mask)); in LowerCall()
1876 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
1879 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops); in LowerCall()
1883 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops); in LowerCall()
1886 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true), in LowerCall()
1887 DAG.getIntPtrConstant(0, dl, true), InFlag, dl); in LowerCall()
1893 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, in LowerCall()
2012 SelectionDAG& DAG) const { in IsEligibleForTailCallOptimization()
2013 const Function *CallerF = DAG.getMachineFunction().getFunction(); in IsEligibleForTailCallOptimization()
2075 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1, in IsEligibleForTailCallOptimization()
2076 *DAG.getContext(), Call); in IsEligibleForTailCallOptimization()
2080 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2, in IsEligibleForTailCallOptimization()
2081 *DAG.getContext(), Call); in IsEligibleForTailCallOptimization()
2104 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction(). in IsEligibleForTailCallOptimization()
2115 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs, in IsEligibleForTailCallOptimization()
2116 *DAG.getContext(), Call); in IsEligibleForTailCallOptimization()
2120 MachineFunction &MF = DAG.getMachineFunction(); in IsEligibleForTailCallOptimization()
2175 SDLoc DL, SelectionDAG &DAG) { in LowerInterruptReturn() argument
2176 const MachineFunction &MF = DAG.getMachineFunction(); in LowerInterruptReturn()
2202 DAG.getConstant(LROffset, DL, MVT::i32, false)); in LowerInterruptReturn()
2204 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps); in LowerInterruptReturn()
2212 SDLoc dl, SelectionDAG &DAG) const { in LowerReturn()
2218 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
2219 *DAG.getContext(), Call); in LowerReturn()
2230 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn()
2247 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2254 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
2255 DAG.getConstant(0, dl, MVT::i32)); in LowerReturn()
2256 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2257 DAG.getVTList(MVT::i32, MVT::i32), Half); in LowerReturn()
2259 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2263 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2265 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2269 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2273 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, in LowerReturn()
2274 DAG.getConstant(1, dl, MVT::i32)); in LowerReturn()
2278 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2279 DAG.getVTList(MVT::i32, MVT::i32), Arg); in LowerReturn()
2280 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2284 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2286 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2290 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
2295 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2309 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") && in LowerReturn()
2313 return LowerInterruptReturn(RetOps, dl, DAG); in LowerReturn()
2316 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
2408 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) { in LowerWRITE_REGISTER() argument
2416 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue, in LowerWRITE_REGISTER()
2417 DAG.getConstant(0, DL, MVT::i32)); in LowerWRITE_REGISTER()
2418 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue, in LowerWRITE_REGISTER()
2419 DAG.getConstant(1, DL, MVT::i32)); in LowerWRITE_REGISTER()
2421 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops); in LowerWRITE_REGISTER()
2430 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { in LowerConstantPool() argument
2437 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, in LowerConstantPool()
2440 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, in LowerConstantPool()
2442 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); in LowerConstantPool()
2450 SelectionDAG &DAG) const { in LowerBlockAddress()
2451 MachineFunction &MF = DAG.getMachineFunction(); in LowerBlockAddress()
2455 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerBlockAddress()
2460 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); in LowerBlockAddress()
2467 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerBlockAddress()
2469 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); in LowerBlockAddress()
2470 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, in LowerBlockAddress()
2475 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32); in LowerBlockAddress()
2476 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); in LowerBlockAddress()
2482 SelectionDAG &DAG) const { in LowerToTLSGeneralDynamicModel()
2484 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerToTLSGeneralDynamicModel()
2486 MachineFunction &MF = DAG.getMachineFunction(); in LowerToTLSGeneralDynamicModel()
2492 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerToTLSGeneralDynamicModel()
2493 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); in LowerToTLSGeneralDynamicModel()
2494 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, in LowerToTLSGeneralDynamicModel()
2499 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerToTLSGeneralDynamicModel()
2500 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); in LowerToTLSGeneralDynamicModel()
2506 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); in LowerToTLSGeneralDynamicModel()
2510 TargetLowering::CallLoweringInfo CLI(DAG); in LowerToTLSGeneralDynamicModel()
2512 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()), in LowerToTLSGeneralDynamicModel()
2513 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args), in LowerToTLSGeneralDynamicModel()
2524 SelectionDAG &DAG, in LowerToTLSExecModels() argument
2529 SDValue Chain = DAG.getEntryNode(); in LowerToTLSExecModels()
2530 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerToTLSExecModels()
2532 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); in LowerToTLSExecModels()
2535 MachineFunction &MF = DAG.getMachineFunction(); in LowerToTLSExecModels()
2544 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerToTLSExecModels()
2545 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); in LowerToTLSExecModels()
2546 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, in LowerToTLSExecModels()
2551 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerToTLSExecModels()
2552 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); in LowerToTLSExecModels()
2554 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, in LowerToTLSExecModels()
2562 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerToTLSExecModels()
2563 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); in LowerToTLSExecModels()
2564 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, in LowerToTLSExecModels()
2571 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); in LowerToTLSExecModels()
2575 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { in LowerGlobalTLSAddress()
2586 return LowerToTLSGeneralDynamicModel(GA, DAG); in LowerGlobalTLSAddress()
2589 return LowerToTLSExecModels(GA, DAG, model); in LowerGlobalTLSAddress()
2595 SelectionDAG &DAG) const { in LowerGlobalAddressELF()
2596 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerGlobalAddressELF()
2604 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerGlobalAddressELF()
2605 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressELF()
2606 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), in LowerGlobalAddressELF()
2611 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); in LowerGlobalAddressELF()
2612 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); in LowerGlobalAddressELF()
2614 Result = DAG.getLoad(PtrVT, dl, Chain, Result, in LowerGlobalAddressELF()
2622 if (Subtarget->useMovt(DAG.getMachineFunction())) { in LowerGlobalAddressELF()
2626 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, in LowerGlobalAddressELF()
2627 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); in LowerGlobalAddressELF()
2629 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); in LowerGlobalAddressELF()
2630 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGlobalAddressELF()
2631 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerGlobalAddressELF()
2638 SelectionDAG &DAG) const { in LowerGlobalAddressDarwin()
2639 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerGlobalAddressDarwin()
2644 if (Subtarget->useMovt(DAG.getMachineFunction())) in LowerGlobalAddressDarwin()
2652 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY); in LowerGlobalAddressDarwin()
2653 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G); in LowerGlobalAddressDarwin()
2656 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, in LowerGlobalAddressDarwin()
2662 SelectionDAG &DAG) const { in LowerGlobalAddressWindows()
2664 assert(Subtarget->useMovt(DAG.getMachineFunction()) && in LowerGlobalAddressWindows()
2670 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerGlobalAddressWindows()
2678 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, in LowerGlobalAddressWindows()
2679 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0, in LowerGlobalAddressWindows()
2682 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, in LowerGlobalAddressWindows()
2688 SelectionDAG &DAG) const { in LowerGLOBAL_OFFSET_TABLE()
2691 MachineFunction &MF = DAG.getMachineFunction(); in LowerGLOBAL_OFFSET_TABLE()
2694 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerGLOBAL_OFFSET_TABLE()
2698 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", in LowerGLOBAL_OFFSET_TABLE()
2700 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerGLOBAL_OFFSET_TABLE()
2701 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerGLOBAL_OFFSET_TABLE()
2702 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerGLOBAL_OFFSET_TABLE()
2705 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerGLOBAL_OFFSET_TABLE()
2706 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); in LowerGLOBAL_OFFSET_TABLE()
2710 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { in LowerEH_SJLJ_SETJMP()
2712 SDValue Val = DAG.getConstant(0, dl, MVT::i32); in LowerEH_SJLJ_SETJMP()
2713 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, in LowerEH_SJLJ_SETJMP()
2714 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), in LowerEH_SJLJ_SETJMP()
2719 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { in LowerEH_SJLJ_LONGJMP()
2721 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), in LowerEH_SJLJ_LONGJMP()
2722 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32)); in LowerEH_SJLJ_LONGJMP()
2726 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, in LowerINTRINSIC_WO_CHAIN() argument
2735 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
2738 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerINTRINSIC_WO_CHAIN()
2739 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); in LowerINTRINSIC_WO_CHAIN()
2742 MachineFunction &MF = DAG.getMachineFunction(); in LowerINTRINSIC_WO_CHAIN()
2745 EVT PtrVT = getPointerTy(DAG.getDataLayout()); in LowerINTRINSIC_WO_CHAIN()
2753 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); in LowerINTRINSIC_WO_CHAIN()
2754 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); in LowerINTRINSIC_WO_CHAIN()
2756 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, in LowerINTRINSIC_WO_CHAIN()
2761 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
2762 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); in LowerINTRINSIC_WO_CHAIN()
2770 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2776 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, in LowerATOMIC_FENCE() argument
2786 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), in LowerATOMIC_FENCE()
2787 DAG.getConstant(0, dl, MVT::i32)); in LowerATOMIC_FENCE()
2803 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0), in LowerATOMIC_FENCE()
2804 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32), in LowerATOMIC_FENCE()
2805 DAG.getConstant(Domain, dl, MVT::i32)); in LowerATOMIC_FENCE()
2808 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, in LowerPREFETCH() argument
2830 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), in LowerPREFETCH()
2831 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32), in LowerPREFETCH()
2832 DAG.getConstant(isData, dl, MVT::i32)); in LowerPREFETCH()
2835 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { in LowerVASTART() argument
2836 MachineFunction &MF = DAG.getMachineFunction(); in LowerVASTART()
2842 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); in LowerVASTART()
2843 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); in LowerVASTART()
2845 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), in LowerVASTART()
2851 SDValue &Root, SelectionDAG &DAG, in GetF64FormalArgument() argument
2853 MachineFunction &MF = DAG.getMachineFunction(); in GetF64FormalArgument()
2864 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument()
2872 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); in GetF64FormalArgument()
2873 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, in GetF64FormalArgument()
2878 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument()
2882 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
2894 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, in StoreByValRegs() argument
2911 MachineFunction &MF = DAG.getMachineFunction(); in StoreByValRegs()
2926 auto PtrVT = getPointerTy(DAG.getDataLayout()); in StoreByValRegs()
2928 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT); in StoreByValRegs()
2936 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in StoreByValRegs()
2938 DAG.getStore(Val.getValue(1), dl, Val, FIN, in StoreByValRegs()
2941 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT)); in StoreByValRegs()
2945 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in StoreByValRegs()
2951 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, in VarArgStyleRegisters() argument
2956 MachineFunction &MF = DAG.getMachineFunction(); in VarArgStyleRegisters()
2964 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr, in VarArgStyleRegisters()
2975 SDLoc dl, SelectionDAG &DAG, in LowerFormalArguments() argument
2978 MachineFunction &MF = DAG.getMachineFunction(); in LowerFormalArguments()
2985 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
2986 *DAG.getContext(), Prologue); in LowerFormalArguments()
3035 auto PtrVT = getPointerTy(DAG.getDataLayout()); in LowerFormalArguments()
3053 Chain, DAG, dl); in LowerFormalArguments()
3058 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); in LowerFormalArguments()
3059 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, in LowerFormalArguments()
3064 Chain, DAG, dl); in LowerFormalArguments()
3066 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerFormalArguments()
3067 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3069 DAG.getIntPtrConstant(0, dl)); in LowerFormalArguments()
3070 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3072 DAG.getIntPtrConstant(1, dl)); in LowerFormalArguments()
3074 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()
3093 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
3103 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3106 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
3107 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
3108 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3111 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
3112 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
3113 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3142 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, CurOrigArg, in LowerFormalArguments()
3145 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT)); in LowerFormalArguments()
3153 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); in LowerFormalArguments()
3154 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, in LowerFormalArguments()
3165 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, in LowerFormalArguments()
3206 SDValue &ARMcc, SelectionDAG &DAG, in getARMCmp() argument
3218 RHS = DAG.getConstant(C - 1, dl, MVT::i32); in getARMCmp()
3225 RHS = DAG.getConstant(C - 1, dl, MVT::i32); in getARMCmp()
3232 RHS = DAG.getConstant(C + 1, dl, MVT::i32); in getARMCmp()
3239 RHS = DAG.getConstant(C + 1, dl, MVT::i32); in getARMCmp()
3258 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in getARMCmp()
3259 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); in getARMCmp()
3264 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, in getVFPCmp() argument
3269 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); in getVFPCmp()
3271 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); in getVFPCmp()
3272 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); in getVFPCmp()
3278 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { in duplicateCmp()
3282 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); in duplicateCmp()
3288 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); in duplicateCmp()
3291 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); in duplicateCmp()
3293 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); in duplicateCmp()
3297 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, in getARMXALUOOp() argument
3315 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32); in getARMXALUOOp()
3316 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS); in getARMXALUOOp()
3317 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS); in getARMXALUOOp()
3320 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); in getARMXALUOOp()
3321 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS); in getARMXALUOOp()
3322 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS); in getARMXALUOOp()
3325 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32); in getARMXALUOOp()
3326 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS); in getARMXALUOOp()
3327 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS); in getARMXALUOOp()
3330 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); in getARMXALUOOp()
3331 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS); in getARMXALUOOp()
3332 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS); in getARMXALUOOp()
3341 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { in LowerXALUO()
3343 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) in LowerXALUO()
3348 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc); in LowerXALUO()
3349 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerXALUO()
3352 SDValue TVal = DAG.getConstant(1, dl, MVT::i32); in LowerXALUO()
3353 SDValue FVal = DAG.getConstant(0, dl, MVT::i32); in LowerXALUO()
3356 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal, in LowerXALUO()
3359 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); in LowerXALUO()
3360 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerXALUO()
3364 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT()
3374 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0))) in LowerSELECT()
3379 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc); in LowerSELECT()
3380 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
3384 OverflowCmp, DAG); in LowerSELECT()
3416 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); in LowerSELECT()
3418 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG); in LowerSELECT()
3425 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond, in LowerSELECT()
3426 DAG.getConstant(1, dl, Cond.getValueType())); in LowerSELECT()
3428 return DAG.getSelectCC(dl, Cond, in LowerSELECT()
3429 DAG.getConstant(0, dl, Cond.getValueType()), in LowerSELECT()
3484 SDValue Cmp, SelectionDAG &DAG) const { in getCMOV()
3486 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3487 DAG.getVTList(MVT::i32, MVT::i32), FalseVal); in getCMOV()
3488 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3489 DAG.getVTList(MVT::i32, MVT::i32), TrueVal); in getCMOV()
3496 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow, in getCMOV()
3498 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh, in getCMOV()
3499 ARMcc, CCR, duplicateCmp(Cmp, DAG)); in getCMOV()
3501 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High); in getCMOV()
3503 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, in getCMOV()
3508 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { in LowerSELECT_CC()
3518 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC, in LowerSELECT_CC()
3524 RHS = DAG.getConstant(0, dl, LHS.getValueType()); in LowerSELECT_CC()
3551 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
3552 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); in LowerSELECT_CC()
3553 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG); in LowerSELECT_CC()
3578 swapSides = DAG.isKnownNeverNaN(LHS) && !DAG.isKnownNeverNaN(RHS); in LowerSELECT_CC()
3585 swapSides = DAG.isKnownNeverNaN(RHS) && !DAG.isKnownNeverNaN(LHS); in LowerSELECT_CC()
3598 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { in LowerSELECT_CC()
3643 if (!DAG.isKnownNeverNaN(RHS)) in LowerSELECT_CC()
3645 return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS); in LowerSELECT_CC()
3648 if (!DAG.isKnownNeverNaN(LHS)) in LowerSELECT_CC()
3652 return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS); in LowerSELECT_CC()
3655 if (!DAG.isKnownNeverNaN(RHS)) in LowerSELECT_CC()
3657 return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS); in LowerSELECT_CC()
3660 if (!DAG.isKnownNeverNaN(LHS)) in LowerSELECT_CC()
3664 return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS); in LowerSELECT_CC()
3682 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in LowerSELECT_CC()
3683 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); in LowerSELECT_CC()
3684 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
3685 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG); in LowerSELECT_CC()
3687 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32); in LowerSELECT_CC()
3689 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); in LowerSELECT_CC()
3690 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG); in LowerSELECT_CC()
3718 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { in bitcastf32Toi32() argument
3720 return DAG.getConstant(0, SDLoc(Op), MVT::i32); in bitcastf32Toi32()
3723 return DAG.getLoad(MVT::i32, SDLoc(Op), in bitcastf32Toi32()
3731 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, in expandf64Toi32() argument
3736 RetVal1 = DAG.getConstant(0, dl, MVT::i32); in expandf64Toi32()
3737 RetVal2 = DAG.getConstant(0, dl, MVT::i32); in expandf64Toi32()
3743 RetVal1 = DAG.getLoad(MVT::i32, dl, in expandf64Toi32()
3751 SDValue NewPtr = DAG.getNode(ISD::ADD, dl, in expandf64Toi32()
3752 PtrType, Ptr, DAG.getConstant(4, dl, PtrType)); in expandf64Toi32()
3753 RetVal2 = DAG.getLoad(MVT::i32, dl, in expandf64Toi32()
3767 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { in OptimizeVFPBrcond()
3788 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32); in OptimizeVFPBrcond()
3791 LHS = DAG.getNode(ISD::AND, dl, MVT::i32, in OptimizeVFPBrcond()
3792 bitcastf32Toi32(LHS, DAG), Mask); in OptimizeVFPBrcond()
3793 RHS = DAG.getNode(ISD::AND, dl, MVT::i32, in OptimizeVFPBrcond()
3794 bitcastf32Toi32(RHS, DAG), Mask); in OptimizeVFPBrcond()
3795 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); in OptimizeVFPBrcond()
3796 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
3797 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in OptimizeVFPBrcond()
3803 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
3804 expandf64Toi32(RHS, DAG, RHS1, RHS2); in OptimizeVFPBrcond()
3805 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); in OptimizeVFPBrcond()
3806 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask); in OptimizeVFPBrcond()
3808 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in OptimizeVFPBrcond()
3809 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in OptimizeVFPBrcond()
3811 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops); in OptimizeVFPBrcond()
3817 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { in LowerBR_CC()
3826 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC, in LowerBR_CC()
3832 RHS = DAG.getConstant(0, dl, LHS.getValueType()); in LowerBR_CC()
3839 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); in LowerBR_CC()
3840 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
3841 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in LowerBR_CC()
3850 SDValue Result = OptimizeVFPBrcond(Op, DAG); in LowerBR_CC()
3858 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32); in LowerBR_CC()
3859 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); in LowerBR_CC()
3860 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
3861 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); in LowerBR_CC()
3863 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
3865 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32); in LowerBR_CC()
3867 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
3872 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { in LowerBR_JT()
3878 EVT PTy = getPointerTy(DAG.getDataLayout()); in LowerBR_JT()
3880 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); in LowerBR_JT()
3881 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI); in LowerBR_JT()
3882 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy)); in LowerBR_JT()
3883 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); in LowerBR_JT()
3889 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, in LowerBR_JT()
3893 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, in LowerBR_JT()
3897 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); in LowerBR_JT()
3898 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI); in LowerBR_JT()
3900 Addr = DAG.getLoad(PTy, dl, Chain, Addr, in LowerBR_JT()
3904 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI); in LowerBR_JT()
3908 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { in LowerVectorFP_TO_INT() argument
3915 return DAG.UnrollVectorOp(Op.getNode()); in LowerVectorFP_TO_INT()
3921 return DAG.UnrollVectorOp(Op.getNode()); in LowerVectorFP_TO_INT()
3923 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0)); in LowerVectorFP_TO_INT()
3924 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op); in LowerVectorFP_TO_INT()
3927 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const { in LowerFP_TO_INT()
3930 return LowerVectorFP_TO_INT(Op, DAG); in LowerFP_TO_INT()
3939 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1, in LowerFP_TO_INT()
3946 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { in LowerVectorINT_TO_FP() argument
3953 return DAG.UnrollVectorOp(Op.getNode()); in LowerVectorINT_TO_FP()
3959 return DAG.UnrollVectorOp(Op.getNode()); in LowerVectorINT_TO_FP()
3975 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); in LowerVectorINT_TO_FP()
3976 return DAG.getNode(Opc, dl, VT, Op); in LowerVectorINT_TO_FP()
3979 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const { in LowerINT_TO_FP()
3982 return LowerVectorINT_TO_FP(Op, DAG); in LowerINT_TO_FP()
3991 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1, in LowerINT_TO_FP()
3998 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { in LowerFCOPYSIGN()
4012 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, in LowerFCOPYSIGN()
4013 DAG.getTargetConstant(EncodedVal, dl, MVT::i32)); in LowerFCOPYSIGN()
4016 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
4017 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
4018 DAG.getConstant(32, dl, MVT::i32)); in LowerFCOPYSIGN()
4020 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
4022 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
4024 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, in LowerFCOPYSIGN()
4025 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
4026 DAG.getConstant(32, dl, MVT::i32)); in LowerFCOPYSIGN()
4028 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, in LowerFCOPYSIGN()
4029 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
4030 DAG.getConstant(32, dl, MVT::i32)); in LowerFCOPYSIGN()
4031 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
4032 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
4034 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), in LowerFCOPYSIGN()
4036 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); in LowerFCOPYSIGN()
4037 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, in LowerFCOPYSIGN()
4038 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); in LowerFCOPYSIGN()
4040 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, in LowerFCOPYSIGN()
4041 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), in LowerFCOPYSIGN()
4042 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); in LowerFCOPYSIGN()
4044 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); in LowerFCOPYSIGN()
4045 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, in LowerFCOPYSIGN()
4046 DAG.getConstant(0, dl, MVT::i32)); in LowerFCOPYSIGN()
4048 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); in LowerFCOPYSIGN()
4056 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4058 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); in LowerFCOPYSIGN()
4061 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN()
4062 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32); in LowerFCOPYSIGN()
4063 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
4065 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
4066 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); in LowerFCOPYSIGN()
4067 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, in LowerFCOPYSIGN()
4068 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
4072 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4075 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); in LowerFCOPYSIGN()
4076 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); in LowerFCOPYSIGN()
4077 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerFCOPYSIGN()
4080 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ in LowerRETURNADDR()
4081 MachineFunction &MF = DAG.getMachineFunction(); in LowerRETURNADDR()
4085 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) in LowerRETURNADDR()
4092 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); in LowerRETURNADDR()
4093 SDValue Offset = DAG.getConstant(4, dl, MVT::i32); in LowerRETURNADDR()
4094 return DAG.getLoad(VT, dl, DAG.getEntryNode(), in LowerRETURNADDR()
4095 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), in LowerRETURNADDR()
4101 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); in LowerRETURNADDR()
4104 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { in LowerFRAMEADDR()
4107 MachineFunction &MF = DAG.getMachineFunction(); in LowerFRAMEADDR()
4115 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); in LowerFRAMEADDR()
4117 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, in LowerFRAMEADDR()
4126 SelectionDAG &DAG) const { in getRegisterByName()
4139 SelectionDAG &DAG) { in ExpandREAD_REGISTER() argument
4146 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL, in ExpandREAD_REGISTER()
4147 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other), in ExpandREAD_REGISTER()
4151 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), in ExpandREAD_REGISTER()
4161 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { in ExpandBITCAST() argument
4162 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in ExpandBITCAST()
4175 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, in ExpandBITCAST()
4176 DAG.getConstant(0, dl, MVT::i32)); in ExpandBITCAST()
4177 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, in ExpandBITCAST()
4178 DAG.getConstant(1, dl, MVT::i32)); in ExpandBITCAST()
4179 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
4180 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); in ExpandBITCAST()
4186 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() && in ExpandBITCAST()
4188 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
4189 DAG.getVTList(MVT::i32, MVT::i32), in ExpandBITCAST()
4190 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
4192 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
4193 DAG.getVTList(MVT::i32, MVT::i32), Op); in ExpandBITCAST()
4195 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
4207 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) { in getZeroVector() argument
4210 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32); in getZeroVector()
4212 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); in getZeroVector()
4213 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in getZeroVector()
4219 SelectionDAG &DAG) const { in LowerShiftRightParts()
4232 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerShiftRightParts()
4233 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); in LowerShiftRightParts()
4234 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts()
4235 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerShiftRightParts()
4236 DAG.getConstant(VTBits, dl, MVT::i32)); in LowerShiftRightParts()
4237 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts()
4238 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
4239 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); in LowerShiftRightParts()
4241 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftRightParts()
4242 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), in LowerShiftRightParts()
4243 ISD::SETGE, ARMcc, DAG, dl); in LowerShiftRightParts()
4244 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); in LowerShiftRightParts()
4245 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, in LowerShiftRightParts()
4249 return DAG.getMergeValues(Ops, dl); in LowerShiftRightParts()
4255 SelectionDAG &DAG) const { in LowerShiftLeftParts()
4266 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, in LowerShiftLeftParts()
4267 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); in LowerShiftLeftParts()
4268 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts()
4269 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, in LowerShiftLeftParts()
4270 DAG.getConstant(VTBits, dl, MVT::i32)); in LowerShiftLeftParts()
4271 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts()
4272 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts()
4274 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
4275 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerShiftLeftParts()
4276 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32), in LowerShiftLeftParts()
4277 ISD::SETGE, ARMcc, DAG, dl); in LowerShiftLeftParts()
4278 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerShiftLeftParts()
4279 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()
4283 return DAG.getMergeValues(Ops, dl); in LowerShiftLeftParts()
4287 SelectionDAG &DAG) const { in LowerFLT_ROUNDS_()
4293 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in LowerFLT_ROUNDS_()
4294 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, in LowerFLT_ROUNDS_()
4296 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
4297 DAG.getConstant(1U << 22, dl, MVT::i32)); in LowerFLT_ROUNDS_()
4298 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, in LowerFLT_ROUNDS_()
4299 DAG.getConstant(22, dl, MVT::i32)); in LowerFLT_ROUNDS_()
4300 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, in LowerFLT_ROUNDS_()
4301 DAG.getConstant(3, dl, MVT::i32)); in LowerFLT_ROUNDS_()
4304 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, in LowerCTTZ() argument
4313 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X); in LowerCTTZ()
4314 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX); in LowerCTTZ()
4320 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT, in LowerCTTZ()
4321 DAG.getTargetConstant(1, dl, ElemTy)); in LowerCTTZ()
4322 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One); in LowerCTTZ()
4323 return DAG.getNode(ISD::CTPOP, dl, VT, Bits); in LowerCTTZ()
4331 DAG.getNode(ARMISD::VMOVIMM, dl, VT, in LowerCTTZ()
4332 DAG.getTargetConstant(NumBits - 1, dl, ElemTy)); in LowerCTTZ()
4333 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); in LowerCTTZ()
4334 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ); in LowerCTTZ()
4347 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT, in LowerCTTZ()
4348 DAG.getTargetConstant(0x1eff, dl, MVT::i32)); in LowerCTTZ()
4349 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF); in LowerCTTZ()
4351 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT, in LowerCTTZ()
4352 DAG.getTargetConstant(1, dl, ElemTy)); in LowerCTTZ()
4353 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One); in LowerCTTZ()
4358 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits); in LowerCTTZ()
4359 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8); in LowerCTTZ()
4363 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit, in LowerCTTZ()
4364 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32), in LowerCTTZ()
4370 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit, in LowerCTTZ()
4371 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32), in LowerCTTZ()
4377 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, in LowerCTTZ()
4378 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32), in LowerCTTZ()
4386 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); in LowerCTTZ()
4387 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); in LowerCTTZ()
4403 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) { in getCTPOP16BitCounts() argument
4408 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts()
4409 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0); in getCTPOP16BitCounts()
4410 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1); in getCTPOP16BitCounts()
4411 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2); in getCTPOP16BitCounts()
4412 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3); in getCTPOP16BitCounts()
4425 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) { in lowerCTPOP16BitElements() argument
4429 SDValue BitCounts = getCTPOP16BitCounts(N, DAG); in lowerCTPOP16BitElements()
4431 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts); in lowerCTPOP16BitElements()
4432 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended, in lowerCTPOP16BitElements()
4433 DAG.getIntPtrConstant(0, DL)); in lowerCTPOP16BitElements()
4435 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, in lowerCTPOP16BitElements()
4436 BitCounts, DAG.getIntPtrConstant(0, DL)); in lowerCTPOP16BitElements()
4437 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted); in lowerCTPOP16BitElements()
4460 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) { in lowerCTPOP32BitElements() argument
4466 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0)); in lowerCTPOP32BitElements()
4467 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG); in lowerCTPOP32BitElements()
4468 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements()
4469 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0); in lowerCTPOP32BitElements()
4470 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1); in lowerCTPOP32BitElements()
4473 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2); in lowerCTPOP32BitElements()
4474 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended, in lowerCTPOP32BitElements()
4475 DAG.getIntPtrConstant(0, DL)); in lowerCTPOP32BitElements()
4477 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2, in lowerCTPOP32BitElements()
4478 DAG.getIntPtrConstant(0, DL)); in lowerCTPOP32BitElements()
4479 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted); in lowerCTPOP32BitElements()
4483 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG, in LowerCTPOP() argument
4493 return lowerCTPOP32BitElements(N, DAG); in LowerCTPOP()
4495 return lowerCTPOP16BitElements(N, DAG); in LowerCTPOP()
4498 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, in LowerShift() argument
4511 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, in LowerShift()
4512 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl, in LowerShift()
4523 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, in LowerShift()
4524 getZeroVector(ShiftVT, DAG, dl), in LowerShift()
4529 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, in LowerShift()
4530 DAG.getConstant(vshiftInt, dl, MVT::i32), in LowerShift()
4534 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, in Expand64BitShift() argument
4555 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), in Expand64BitShift()
4556 DAG.getConstant(0, dl, MVT::i32)); in Expand64BitShift()
4557 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), in Expand64BitShift()
4558 DAG.getConstant(1, dl, MVT::i32)); in Expand64BitShift()
4563 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi); in Expand64BitShift()
4566 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); in Expand64BitShift()
4569 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
4572 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { in LowerVSETCC() argument
4617 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4618 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4626 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0); in LowerVSETCC()
4627 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
4661 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0)); in LowerVSETCC()
4662 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1)); in LowerVSETCC()
4688 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break; in LowerVSETCC()
4690 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break; in LowerVSETCC()
4692 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break; in LowerVSETCC()
4694 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break; in LowerVSETCC()
4696 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break; in LowerVSETCC()
4698 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1); in LowerVSETCC()
4701 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1); in LowerVSETCC()
4704 Result = DAG.getSExtOrTrunc(Result, dl, VT); in LowerVSETCC()
4707 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
4716 unsigned SplatBitSize, SelectionDAG &DAG, in isNEONModifiedImm() argument
4833 if (DAG.getDataLayout().isBigEndian()) in isNEONModifiedImm()
4848 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32); in isNEONModifiedImm()
4851 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG, in LowerConstantFP() argument
4878 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32); in LowerConstantFP()
4879 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32, in LowerConstantFP()
4881 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant, in LowerConstantFP()
4882 DAG.getConstant(0, DL, MVT::i32)); in LowerConstantFP()
4900 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), in LowerConstantFP()
4904 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT, in LowerConstantFP()
4907 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
4910 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
4912 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, in LowerConstantFP()
4913 DAG.getConstant(0, DL, MVT::i32)); in LowerConstantFP()
4917 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT, in LowerConstantFP()
4921 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal); in LowerConstantFP()
4924 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant); in LowerConstantFP()
4927 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32, in LowerConstantFP()
4929 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant, in LowerConstantFP()
4930 DAG.getConstant(0, DL, MVT::i32)); in LowerConstantFP()
5208 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, in IsSingleInstrConstant() argument
5217 return DAG.getConstant(Val, dl, MVT::i32); in IsSingleInstrConstant()
5220 return DAG.getConstant(Val, dl, MVT::i32); in IsSingleInstrConstant()
5227 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, in LowerBUILD_VECTOR() argument
5242 DAG, dl, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
5245 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); in LowerBUILD_VECTOR()
5246 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
5253 DAG, dl, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
5256 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); in LowerBUILD_VECTOR()
5257 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); in LowerBUILD_VECTOR()
5264 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32); in LowerBUILD_VECTOR()
5265 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val); in LowerBUILD_VECTOR()
5312 return DAG.getUNDEF(VT); in LowerBUILD_VECTOR()
5317 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
5344 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
5345 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), in LowerBUILD_VECTOR()
5346 Value, DAG.getConstant(index, dl, MVT::i32)), in LowerBUILD_VECTOR()
5347 DAG.getConstant(index, dl, MVT::i32)); in LowerBUILD_VECTOR()
5349 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT, in LowerBUILD_VECTOR()
5352 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value); in LowerBUILD_VECTOR()
5363 Ops.push_back(DAG.getConstant(I, dl, MVT::i32)); in LowerBUILD_VECTOR()
5364 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); in LowerBUILD_VECTOR()
5372 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, in LowerBUILD_VECTOR()
5374 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in LowerBUILD_VECTOR()
5375 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
5376 Val = LowerBUILD_VECTOR(Val, DAG, ST); in LowerBUILD_VECTOR()
5378 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
5381 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); in LowerBUILD_VECTOR()
5383 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); in LowerBUILD_VECTOR()
5395 SDValue shuffle = ReconstructShuffle(Op, DAG); in LowerBUILD_VECTOR()
5407 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerBUILD_VECTOR()
5410 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); in LowerBUILD_VECTOR()
5411 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
5412 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
5422 SDValue Vec = DAG.getUNDEF(VT); in LowerBUILD_VECTOR()
5427 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32); in LowerBUILD_VECTOR()
5428 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
5439 SelectionDAG &DAG) const { in ReconstructShuffle()
5498 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; in ReconstructShuffle()
5528 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5530 DAG.getIntPtrConstant(NumElts, dl)); in ReconstructShuffle()
5534 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5536 DAG.getIntPtrConstant(0, dl)); in ReconstructShuffle()
5540 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5542 DAG.getIntPtrConstant(0, dl)); in ReconstructShuffle()
5543 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
5545 DAG.getIntPtrConstant(NumElts, dl)); in ReconstructShuffle()
5546 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, in ReconstructShuffle()
5547 DAG.getConstant(VEXTOffsets[i], dl, in ReconstructShuffle()
5573 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], in ReconstructShuffle()
5624 SDValue RHS, SelectionDAG &DAG, in GeneratePerfectShuffle() argument
5655 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); in GeneratePerfectShuffle()
5656 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); in GeneratePerfectShuffle()
5665 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
5668 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
5671 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
5676 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, in GeneratePerfectShuffle()
5677 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32)); in GeneratePerfectShuffle()
5681 return DAG.getNode(ARMISD::VEXT, dl, VT, in GeneratePerfectShuffle()
5683 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32)); in GeneratePerfectShuffle()
5686 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
5690 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
5694 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
5701 SelectionDAG &DAG) { in LowerVECTOR_SHUFFLEv8i8() argument
5710 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32)); in LowerVECTOR_SHUFFLEv8i8()
5713 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, in LowerVECTOR_SHUFFLEv8i8()
5714 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask)); in LowerVECTOR_SHUFFLEv8i8()
5716 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, in LowerVECTOR_SHUFFLEv8i8()
5717 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask)); in LowerVECTOR_SHUFFLEv8i8()
5721 SelectionDAG &DAG) { in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16() argument
5728 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
5733 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS, in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
5734 DAG.getConstant(ExtractNum, DL, MVT::i32)); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
5737 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { in LowerVECTOR_SHUFFLE() argument
5761 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); in LowerVECTOR_SHUFFLE()
5775 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); in LowerVECTOR_SHUFFLE()
5777 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, in LowerVECTOR_SHUFFLE()
5778 DAG.getConstant(Lane, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
5786 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, in LowerVECTOR_SHUFFLE()
5787 DAG.getConstant(Imm, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
5791 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
5793 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
5795 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); in LowerVECTOR_SHUFFLE()
5799 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1, in LowerVECTOR_SHUFFLE()
5800 DAG.getConstant(Imm, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
5814 return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2) in LowerVECTOR_SHUFFLE()
5850 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT), in LowerVECTOR_SHUFFLE()
5852 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), in LowerVECTOR_SHUFFLE()
5877 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); in LowerVECTOR_SHUFFLE()
5885 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerVECTOR_SHUFFLE()
5886 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
5887 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
5891 Ops.push_back(DAG.getUNDEF(EltVT)); in LowerVECTOR_SHUFFLE()
5893 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, in LowerVECTOR_SHUFFLE()
5895 DAG.getConstant(ShuffleMask[i] & (NumElts-1), in LowerVECTOR_SHUFFLE()
5898 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerVECTOR_SHUFFLE()
5899 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerVECTOR_SHUFFLE()
5903 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG); in LowerVECTOR_SHUFFLE()
5906 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); in LowerVECTOR_SHUFFLE()
5914 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { in LowerINSERT_VECTOR_ELT() argument
5923 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { in LowerEXTRACT_VECTOR_ELT() argument
5933 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); in LowerEXTRACT_VECTOR_ELT()
5939 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { in LowerCONCAT_VECTORS() argument
5945 SDValue Val = DAG.getUNDEF(MVT::v2f64); in LowerCONCAT_VECTORS()
5949 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
5950 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), in LowerCONCAT_VECTORS()
5951 DAG.getIntPtrConstant(0, dl)); in LowerCONCAT_VECTORS()
5953 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
5954 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), in LowerCONCAT_VECTORS()
5955 DAG.getIntPtrConstant(1, dl)); in LowerCONCAT_VECTORS()
5956 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); in LowerCONCAT_VECTORS()
5962 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, in isExtendedBUILD_VECTOR() argument
5971 unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0; in isExtendedBUILD_VECTOR()
6015 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() argument
6018 if (isExtendedBUILD_VECTOR(N, DAG, true)) in isSignExtended()
6025 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() argument
6028 if (isExtendedBUILD_VECTOR(N, DAG, false)) in isZeroExtended()
6053 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG, in AddRequiredExtensionForVMULL() argument
6067 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()
6075 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) { in SkipLoadExtensionForVMULL() argument
6080 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(), in SkipLoadExtensionForVMULL()
6088 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy, in SkipLoadExtensionForVMULL()
6100 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) { in SkipExtensionForVMULL() argument
6102 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG, in SkipExtensionForVMULL()
6108 return SkipLoadExtensionForVMULL(LD, DAG); in SkipExtensionForVMULL()
6116 unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0; in SkipExtensionForVMULL()
6117 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32, in SkipExtensionForVMULL()
6133 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32)); in SkipExtensionForVMULL()
6135 return DAG.getNode(ISD::BUILD_VECTOR, dl, in SkipExtensionForVMULL()
6139 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { in isAddSubSExt() argument
6145 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
6150 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { in isAddSubZExt() argument
6156 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
6161 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { in LowerMUL() argument
6171 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
6172 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
6176 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
6177 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
6183 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
6186 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { in LowerMUL()
6189 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { in LowerMUL()
6209 SDValue Op1 = SkipExtensionForVMULL(N1, DAG); in LowerMUL()
6211 Op0 = SkipExtensionForVMULL(N0, DAG); in LowerMUL()
6215 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
6226 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL()
6227 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL()
6229 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
6230 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
6231 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
6232 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
6233 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
6237 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i8() argument
6241 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6242 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); in LowerSDIV_v4i8()
6243 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
6244 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
6247 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i8()
6248 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), in LowerSDIV_v4i8()
6254 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); in LowerSDIV_v4i8()
6255 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6256 Y = DAG.getConstant(0xb000, dl, MVT::i32); in LowerSDIV_v4i8()
6257 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); in LowerSDIV_v4i8()
6258 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); in LowerSDIV_v4i8()
6259 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
6261 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6262 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); in LowerSDIV_v4i8()
6267 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i16() argument
6272 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6273 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); in LowerSDIV_v4i16()
6274 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6275 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerSDIV_v4i16()
6280 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
6281 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), in LowerSDIV_v4i16()
6283 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
6284 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), in LowerSDIV_v4i16()
6286 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerSDIV_v4i16()
6291 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
6292 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6293 N1 = DAG.getConstant(0x89, dl, MVT::i32); in LowerSDIV_v4i16()
6294 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); in LowerSDIV_v4i16()
6295 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
6296 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6299 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6300 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
6304 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { in LowerSDIV() argument
6315 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
6316 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); in LowerSDIV()
6318 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
6319 DAG.getIntPtrConstant(4, dl)); in LowerSDIV()
6320 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
6321 DAG.getIntPtrConstant(4, dl)); in LowerSDIV()
6322 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
6323 DAG.getIntPtrConstant(0, dl)); in LowerSDIV()
6324 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
6325 DAG.getIntPtrConstant(0, dl)); in LowerSDIV()
6327 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
6328 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 in LowerSDIV()
6330 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
6331 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerSDIV()
6333 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
6336 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
6339 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { in LowerUDIV() argument
6350 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
6351 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); in LowerUDIV()
6353 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
6354 DAG.getIntPtrConstant(4, dl)); in LowerUDIV()
6355 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
6356 DAG.getIntPtrConstant(4, dl)); in LowerUDIV()
6357 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
6358 DAG.getIntPtrConstant(0, dl)); in LowerUDIV()
6359 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
6360 DAG.getIntPtrConstant(0, dl)); in LowerUDIV()
6362 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
6363 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 in LowerUDIV()
6365 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
6366 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerUDIV()
6368 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
6369 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl, in LowerUDIV()
6378 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
6379 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); in LowerUDIV()
6380 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
6381 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); in LowerUDIV()
6387 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
6388 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32), in LowerUDIV()
6390 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
6391 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), in LowerUDIV()
6393 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
6394 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerUDIV()
6395 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32), in LowerUDIV()
6397 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerUDIV()
6402 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
6403 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
6404 N1 = DAG.getConstant(2, dl, MVT::i32); in LowerUDIV()
6405 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); in LowerUDIV()
6406 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
6407 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
6410 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
6411 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
6415 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { in LowerADDC_ADDE_SUBC_SUBE() argument
6417 SDVTList VTs = DAG.getVTList(VT, MVT::i32); in LowerADDC_ADDE_SUBC_SUBE()
6430 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), in LowerADDC_ADDE_SUBC_SUBE()
6432 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), in LowerADDC_ADDE_SUBC_SUBE()
6436 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const { in LowerFSINCOS()
6444 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in LowerFSINCOS()
6445 auto PtrVT = getPointerTy(DAG.getDataLayout()); in LowerFSINCOS()
6447 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); in LowerFSINCOS()
6453 auto &DL = DAG.getDataLayout(); in LowerFSINCOS()
6457 SDValue SRet = DAG.getFrameIndex(FrameIdx, getPointerTy(DL)); in LowerFSINCOS()
6477 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL)); in LowerFSINCOS()
6479 TargetLowering::CallLoweringInfo CLI(DAG); in LowerFSINCOS()
6480 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) in LowerFSINCOS()
6481 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee, in LowerFSINCOS()
6487 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet, in LowerFSINCOS()
6491 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet, in LowerFSINCOS()
6492 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl)); in LowerFSINCOS()
6493 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add, in LowerFSINCOS()
6496 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT); in LowerFSINCOS()
6497 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, in LowerFSINCOS()
6501 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { in LowerAtomicLoadStore() argument
6513 SelectionDAG &DAG, in ReplaceREADCYCLECOUNTER() argument
6522 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
6523 DAG.getConstant(15, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
6524 DAG.getConstant(0, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
6525 DAG.getConstant(9, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
6526 DAG.getConstant(13, DL, MVT::i32), in ReplaceREADCYCLECOUNTER()
6527 DAG.getConstant(0, DL, MVT::i32) in ReplaceREADCYCLECOUNTER()
6530 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, in ReplaceREADCYCLECOUNTER()
6531 DAG.getVTList(MVT::i32, MVT::Other), Ops); in ReplaceREADCYCLECOUNTER()
6537 Cycles32 = DAG.getConstant(0, DL, MVT::i32); in ReplaceREADCYCLECOUNTER()
6538 OutChain = DAG.getEntryNode(); in ReplaceREADCYCLECOUNTER()
6542 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceREADCYCLECOUNTER()
6543 Cycles32, DAG.getConstant(0, DL, MVT::i32)); in ReplaceREADCYCLECOUNTER()
6548 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
6551 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG); in LowerOperation()
6552 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
6553 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
6558 return LowerGlobalAddressWindows(Op, DAG); in LowerOperation()
6560 return LowerGlobalAddressELF(Op, DAG); in LowerOperation()
6562 return LowerGlobalAddressDarwin(Op, DAG); in LowerOperation()
6564 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
6565 case ISD::SELECT: return LowerSELECT(Op, DAG); in LowerOperation()
6566 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
6567 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
6568 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
6569 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
6570 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); in LowerOperation()
6571 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); in LowerOperation()
6573 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); in LowerOperation()
6575 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); in LowerOperation()
6576 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); in LowerOperation()
6577 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); in LowerOperation()
6578 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); in LowerOperation()
6579 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); in LowerOperation()
6580 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); in LowerOperation()
6581 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); in LowerOperation()
6582 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, in LowerOperation()
6584 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); in LowerOperation()
6587 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); in LowerOperation()
6588 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); in LowerOperation()
6590 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); in LowerOperation()
6592 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget); in LowerOperation()
6593 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget); in LowerOperation()
6594 case ISD::SETCC: return LowerVSETCC(Op, DAG); in LowerOperation()
6595 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget); in LowerOperation()
6596 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); in LowerOperation()
6597 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
6598 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
6599 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
6600 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
6601 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); in LowerOperation()
6602 case ISD::MUL: return LowerMUL(Op, DAG); in LowerOperation()
6603 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
6604 case ISD::UDIV: return LowerUDIV(Op, DAG); in LowerOperation()
6608 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
6613 return LowerXALUO(Op, DAG); in LowerOperation()
6615 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); in LowerOperation()
6616 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); in LowerOperation()
6618 case ISD::UDIVREM: return LowerDivRem(Op, DAG); in LowerOperation()
6621 return LowerDYNAMIC_STACKALLOC(Op, DAG); in LowerOperation()
6623 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); in LowerOperation()
6624 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
6632 SelectionDAG &DAG) const { in ReplaceNodeResults()
6638 ExpandREAD_REGISTER(N, Results, DAG); in ReplaceNodeResults()
6641 Res = ExpandBITCAST(N, DAG); in ReplaceNodeResults()
6645 Res = Expand64BitShift(N, DAG, Subtarget); in ReplaceNodeResults()
6648 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget); in ReplaceNodeResults()
7922 SelectionDAG &DAG) { in isConditionalZeroOrAllOnes() argument
7956 OtherOp = DAG.getConstant(0, dl, VT); in isConditionalZeroOrAllOnes()
7959 OtherOp = DAG.getConstant(1, dl, VT); in isConditionalZeroOrAllOnes()
7961 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, in isConditionalZeroOrAllOnes()
7996 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse() local
8002 NonConstantVal, DAG)) in combineSelectAndUse()
8007 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT, in combineSelectAndUse()
8013 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, in combineSelectAndUse()
8098 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL() local
8099 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in AddCombineToVPADDL()
8105 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl, in AddCombineToVPADDL()
8106 TLI.getPointerTy(DAG.getDataLayout()))); in AddCombineToVPADDL()
8124 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops); in AddCombineToVPADDL()
8126 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineToVPADDL()
8248 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitMLAL() local
8257 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode), in AddCombineTo64bitMLAL()
8258 DAG.getVTList(MVT::i32, MVT::i32), Ops); in AddCombineTo64bitMLAL()
8262 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult); in AddCombineTo64bitMLAL()
8265 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult); in AddCombineTo64bitMLAL()
8357 SelectionDAG &DAG = DCI.DAG; in PerformVMULCombine() local
8377 return DAG.getNode(Opcode, DL, VT, in PerformVMULCombine()
8378 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
8379 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); in PerformVMULCombine()
8385 SelectionDAG &DAG = DCI.DAG; in PerformMULCombine() local
8416 Res = DAG.getNode(ISD::ADD, DL, VT, in PerformMULCombine()
8418 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
8420 DAG.getConstant(Log2_32(MulAmt - 1), DL, in PerformMULCombine()
8424 Res = DAG.getNode(ISD::SUB, DL, VT, in PerformMULCombine()
8425 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
8427 DAG.getConstant(Log2_32(MulAmt + 1), DL, in PerformMULCombine()
8436 Res = DAG.getNode(ISD::SUB, DL, VT, in PerformMULCombine()
8438 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
8440 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL, in PerformMULCombine()
8444 Res = DAG.getNode(ISD::ADD, DL, VT, in PerformMULCombine()
8446 DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
8448 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL, in PerformMULCombine()
8450 Res = DAG.getNode(ISD::SUB, DL, VT, in PerformMULCombine()
8451 DAG.getConstant(0, DL, MVT::i32), Res); in PerformMULCombine()
8458 Res = DAG.getNode(ISD::SHL, DL, VT, in PerformMULCombine()
8459 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32)); in PerformMULCombine()
8474 SelectionDAG &DAG = DCI.DAG; in PerformANDCombine() local
8476 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformANDCombine()
8488 DAG, dl, VbicVT, VT.is128BitVector(), in PerformANDCombine()
8492 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); in PerformANDCombine()
8493 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); in PerformANDCombine()
8494 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); in PerformANDCombine()
8517 SelectionDAG &DAG = DCI.DAG; in PerformORCombine() local
8519 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformORCombine()
8531 DAG, dl, VorrVT, VT.is128BitVector(), in PerformORCombine()
8535 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); in PerformORCombine()
8536 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); in PerformORCombine()
8537 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); in PerformORCombine()
8559 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { in PerformORCombine()
8580 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
8584 return DAG.getNode(ISD::BITCAST, dl, VT, Result); in PerformORCombine()
8634 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, in PerformORCombine()
8635 DAG.getConstant(Val, DL, MVT::i32), in PerformORCombine()
8636 DAG.getConstant(Mask, DL, MVT::i32)); in PerformORCombine()
8660 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), in PerformORCombine()
8661 DAG.getConstant(amt, DL, MVT::i32)); in PerformORCombine()
8662 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, in PerformORCombine()
8663 DAG.getConstant(Mask, DL, MVT::i32)); in PerformORCombine()
8676 Res = DAG.getNode(ISD::SRL, DL, VT, N00, in PerformORCombine()
8677 DAG.getConstant(lsb, DL, MVT::i32)); in PerformORCombine()
8678 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, in PerformORCombine()
8679 DAG.getConstant(Mask2, DL, MVT::i32)); in PerformORCombine()
8686 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && in PerformORCombine()
8697 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), in PerformORCombine()
8698 DAG.getConstant(~Mask, DL, MVT::i32)); in PerformORCombine()
8711 SelectionDAG &DAG = DCI.DAG; in PerformXORCombine() local
8713 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformXORCombine()
8744 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0), in PerformBFICombine()
8770 SelectionDAG &DAG = DCI.DAG; in PerformVMOVRRDCombine() local
8773 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, in PerformVMOVRRDCombine()
8778 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformVMOVRRDCombine()
8779 DAG.getConstant(4, DL, MVT::i32)); in PerformVMOVRRDCombine()
8780 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, in PerformVMOVRRDCombine()
8785 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); in PerformVMOVRRDCombine()
8786 if (DCI.DAG.getDataLayout().isBigEndian()) in PerformVMOVRRDCombine()
8797 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { in PerformVMOVDRRCombine() argument
8808 return DAG.getNode(ISD::BITCAST, SDLoc(N), in PerformVMOVDRRCombine()
8836 SelectionDAG &DAG = DCI.DAG; in PerformBUILD_VECTORCombine() local
8838 SDValue RV = PerformVMOVDRRCombine(N, DAG); in PerformBUILD_VECTORCombine()
8852 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); in PerformBUILD_VECTORCombine()
8857 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); in PerformBUILD_VECTORCombine()
8858 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops); in PerformBUILD_VECTORCombine()
8859 return DAG.getNode(ISD::BITCAST, dl, VT, BV); in PerformBUILD_VECTORCombine()
8917 SelectionDAG &DAG = DCI.DAG; in PerformARMBUILD_VECTORCombine() local
8919 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); in PerformARMBUILD_VECTORCombine()
8921 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformARMBUILD_VECTORCombine()
8930 SDValue Vec = DAG.getUNDEF(VecVT); in PerformARMBUILD_VECTORCombine()
8941 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V); in PerformARMBUILD_VECTORCombine()
8945 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32); in PerformARMBUILD_VECTORCombine()
8946 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx); in PerformARMBUILD_VECTORCombine()
8948 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec); in PerformARMBUILD_VECTORCombine()
8966 SelectionDAG &DAG = DCI.DAG; in PerformInsertEltCombine() local
8968 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformInsertEltCombine()
8970 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); in PerformInsertEltCombine()
8971 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); in PerformInsertEltCombine()
8975 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine()
8977 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); in PerformInsertEltCombine()
8982 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { in PerformVECTOR_SHUFFLECombine() argument
9006 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformVECTOR_SHUFFLECombine()
9013 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, in PerformVECTOR_SHUFFLECombine()
9029 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat, in PerformVECTOR_SHUFFLECombine()
9030 DAG.getUNDEF(VT), NewMask.data()); in PerformVECTOR_SHUFFLECombine()
9040 SelectionDAG &DAG = DCI.DAG; in CombineBaseUpdate() local
9190 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2)); in CombineBaseUpdate()
9209 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32)); in CombineBaseUpdate()
9215 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal); in CombineBaseUpdate()
9218 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, in CombineBaseUpdate()
9231 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal); in CombineBaseUpdate()
9256 SelectionDAG &DAG = DCI.DAG; in CombineVLDDUP() local
9303 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1)); in CombineVLDDUP()
9306 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()
9361 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformVDUPLANECombine()
9370 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformLOADCombine()
9390 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
9391 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformSTORECombine()
9409 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(), in PerformSTORECombine()
9414 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal); in PerformSTORECombine()
9417 ShuffleVec[i] = DAG.getDataLayout().isBigEndian() in PerformSTORECombine()
9424 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec, in PerformSTORECombine()
9425 DAG.getUNDEF(WideVec.getValueType()), in PerformSTORECombine()
9441 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), in PerformSTORECombine()
9444 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff); in PerformSTORECombine()
9446 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, DL, in PerformSTORECombine()
9447 TLI.getPointerTy(DAG.getDataLayout())); in PerformSTORECombine()
9453 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in PerformSTORECombine()
9455 DAG.getIntPtrConstant(I, DL)); in PerformSTORECombine()
9456 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr, in PerformSTORECombine()
9459 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr, in PerformSTORECombine()
9463 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in PerformSTORECombine()
9473 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
9474 bool isBigEndian = DAG.getDataLayout().isBigEndian(); in PerformSTORECombine()
9477 SDValue NewST1 = DAG.getStore(St->getChain(), DL, in PerformSTORECombine()
9482 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, in PerformSTORECombine()
9483 DAG.getConstant(4, DL, MVT::i32)); in PerformSTORECombine()
9484 return DAG.getStore(NewST1.getValue(0), DL, in PerformSTORECombine()
9496 SelectionDAG &DAG = DCI.DAG; in PerformSTORECombine() local
9499 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, in PerformSTORECombine()
9501 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); in PerformSTORECombine()
9502 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformSTORECombine()
9505 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); in PerformSTORECombine()
9510 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), in PerformSTORECombine()
9518 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformSTORECombine()
9562 SelectionDAG &DAG = DCI.DAG; in PerformVCVTCombine() local
9593 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, in PerformVCVTCombine()
9595 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), in PerformVCVTCombine()
9597 DAG.getConstant(Log2_64(C), dl, MVT::i32)); in PerformVCVTCombine()
9600 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv); in PerformVCVTCombine()
9617 SelectionDAG &DAG = DCI.DAG; in PerformVDIVCombine() local
9646 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PerformVDIVCombine()
9652 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, in PerformVDIVCombine()
9654 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), in PerformVDIVCombine()
9655 ConvInput, DAG.getConstant(Log2_64(C), dl, MVT::i32)); in PerformVDIVCombine()
9707 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { in PerformIntrinsicCombine() argument
9817 return DAG.getNode(VShiftOpc, dl, N->getValueType(0), in PerformIntrinsicCombine()
9818 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
9835 return DAG.getNode(VShiftOpc, dl, N->getValueType(0), in PerformIntrinsicCombine()
9837 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformIntrinsicCombine()
9854 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, in PerformShiftCombine() argument
9864 DAG.MaskedValueIsZero(N0.getOperand(0), in PerformShiftCombine()
9866 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1); in PerformShiftCombine()
9871 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformShiftCombine()
9884 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0), in PerformShiftCombine()
9885 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()
9895 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0), in PerformShiftCombine()
9896 DAG.getConstant(Cnt, dl, MVT::i32)); in PerformShiftCombine()
9904 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, in PerformExtendCombine() argument
9917 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in PerformExtendCombine()
9935 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane); in PerformExtendCombine()
9944 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, in PerformSELECT_CCCombine() argument
9966 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { in PerformSELECT_CCCombine()
9968 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { in PerformSELECT_CCCombine()
9987 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) in PerformSELECT_CCCombine()
9993 !DAG.getTarget().Options.UnsafeFPMath && in PerformSELECT_CCCombine()
9994 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) in PerformSELECT_CCCombine()
10009 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) in PerformSELECT_CCCombine()
10015 !DAG.getTarget().Options.UnsafeFPMath && in PerformSELECT_CCCombine()
10016 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) in PerformSELECT_CCCombine()
10024 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS); in PerformSELECT_CCCombine()
10029 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { in PerformCMOVCombine()
10064 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, in PerformCMOVCombine()
10068 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); in PerformCMOVCombine()
10069 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, in PerformCMOVCombine()
10075 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne); in PerformCMOVCombine()
10078 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
10079 DAG.getValueType(MVT::i1)); in PerformCMOVCombine()
10081 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
10082 DAG.getValueType(MVT::i8)); in PerformCMOVCombine()
10084 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
10085 DAG.getValueType(MVT::i16)); in PerformCMOVCombine()
10104 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); in PerformDAGCombine()
10108 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
10113 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); in PerformDAGCombine()
10116 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
10119 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
10120 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
10121 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); in PerformDAGCombine()
10516 SelectionDAG &DAG) { in getARMIndexedAddressParts() argument
10528 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0)); in getARMIndexedAddressParts()
10542 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0)); in getARMIndexedAddressParts()
10575 SelectionDAG &DAG) { in getT2IndexedAddressParts() argument
10585 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0)); in getT2IndexedAddressParts()
10589 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0)); in getT2IndexedAddressParts()
10604 SelectionDAG &DAG) const { in getPreIndexedAddressParts()
10625 Offset, isInc, DAG); in getPreIndexedAddressParts()
10628 Offset, isInc, DAG); in getPreIndexedAddressParts()
10643 SelectionDAG &DAG) const { in getPostIndexedAddressParts()
10664 isInc, DAG); in getPostIndexedAddressParts()
10667 isInc, DAG); in getPostIndexedAddressParts()
10690 const SelectionDAG &DAG, in computeKnownBitsForTargetNode() argument
10707 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); in computeKnownBitsForTargetNode()
10711 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1); in computeKnownBitsForTargetNode()
10884 SelectionDAG &DAG) const { in LowerAsmOperandForConstraint()
11035 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType()); in LowerAsmOperandForConstraint()
11043 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); in LowerAsmOperandForConstraint()
11046 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { in LowerDivRem()
11053 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); in LowerDivRem()
11064 SDValue InChain = DAG.getEntryNode(); in LowerDivRem()
11070 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in LowerDivRem()
11078 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), in LowerDivRem()
11079 getPointerTy(DAG.getDataLayout())); in LowerDivRem()
11084 TargetLowering::CallLoweringInfo CLI(DAG); in LowerDivRem()
11094 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { in LowerDYNAMIC_STACKALLOC()
11102 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size, in LowerDYNAMIC_STACKALLOC()
11103 DAG.getConstant(2, DL, MVT::i32)); in LowerDYNAMIC_STACKALLOC()
11106 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag); in LowerDYNAMIC_STACKALLOC()
11109 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerDYNAMIC_STACKALLOC()
11110 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag); in LowerDYNAMIC_STACKALLOC()
11112 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32); in LowerDYNAMIC_STACKALLOC()
11116 return DAG.getMergeValues(Ops, DL); in LowerDYNAMIC_STACKALLOC()
11119 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const { in LowerFP_EXTEND()
11127 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1, in LowerFP_EXTEND()
11131 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const { in LowerFP_ROUND()
11140 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1, in LowerFP_ROUND()