Lines Matching refs:v2f64
154 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); in addQRTypeForNEON()
435 addQRTypeForNEON(MVT::v2f64); in ARMTargetLowering()
445 setOperationAction(ISD::FADD, MVT::v2f64, Expand); in ARMTargetLowering()
446 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); in ARMTargetLowering()
447 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); in ARMTargetLowering()
450 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); in ARMTargetLowering()
451 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
455 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); in ARMTargetLowering()
458 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); in ARMTargetLowering()
460 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); in ARMTargetLowering()
461 setOperationAction(ISD::FABS, MVT::v2f64, Expand); in ARMTargetLowering()
462 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); in ARMTargetLowering()
463 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
464 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); in ARMTargetLowering()
465 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); in ARMTargetLowering()
466 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); in ARMTargetLowering()
467 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); in ARMTargetLowering()
468 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); in ARMTargetLowering()
469 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); in ARMTargetLowering()
470 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); in ARMTargetLowering()
471 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
473 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
474 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); in ARMTargetLowering()
475 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); in ARMTargetLowering()
476 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
477 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); in ARMTargetLowering()
478 setOperationAction(ISD::FMA, MVT::v2f64, Expand); in ARMTargetLowering()
536 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in ARMTargetLowering()
1014 case MVT::v4f32: case MVT::v2f64: in findRepresentativeClass()
1401 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1402 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1403 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1417 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1585 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
2145 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
2252 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
3051 if (VA.getLocVT() == MVT::v2f64) { in LowerFormalArguments()
3066 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerFormalArguments()
3067 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3070 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3083 else if (RegVT == MVT::v2f64) in LowerFormalArguments()
5945 SDValue Val = DAG.getUNDEF(MVT::v2f64); in LowerCONCAT_VECTORS()
5949 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
5953 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
10181 case MVT::v2f64: { in allowsMisalignedMemoryAccesses()
10214 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) { in getOptimalMemOpType()
10215 return MVT::v2f64; in getOptimalMemOpType()