Lines Matching refs:VT
65 static bool is32Bit(EVT VT) { in is32Bit() argument
66 switch (VT.getSimpleVT().SimpleTy) { in is32Bit()
138 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
139 if (isTypeLegal(VT)) { in SystemZTargetLowering()
141 setOperationAction(ISD::SETCC, VT, Custom); in SystemZTargetLowering()
144 setOperationAction(ISD::SELECT, VT, Expand); in SystemZTargetLowering()
147 setOperationAction(ISD::SELECT_CC, VT, Custom); in SystemZTargetLowering()
148 setOperationAction(ISD::BR_CC, VT, Custom); in SystemZTargetLowering()
163 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
164 if (isTypeLegal(VT)) { in SystemZTargetLowering()
166 setOperationAction(ISD::SDIV, VT, Expand); in SystemZTargetLowering()
167 setOperationAction(ISD::UDIV, VT, Expand); in SystemZTargetLowering()
168 setOperationAction(ISD::SREM, VT, Expand); in SystemZTargetLowering()
169 setOperationAction(ISD::UREM, VT, Expand); in SystemZTargetLowering()
170 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
171 setOperationAction(ISD::UDIVREM, VT, Custom); in SystemZTargetLowering()
175 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom); in SystemZTargetLowering()
176 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); in SystemZTargetLowering()
180 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); in SystemZTargetLowering()
184 setOperationAction(ISD::CTPOP, VT, Custom); in SystemZTargetLowering()
186 setOperationAction(ISD::CTPOP, VT, Expand); in SystemZTargetLowering()
189 setOperationAction(ISD::CTTZ, VT, Expand); in SystemZTargetLowering()
190 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in SystemZTargetLowering()
191 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); in SystemZTargetLowering()
192 setOperationAction(ISD::ROTR, VT, Expand); in SystemZTargetLowering()
195 setOperationAction(ISD::MULHS, VT, Expand); in SystemZTargetLowering()
196 setOperationAction(ISD::MULHU, VT, Expand); in SystemZTargetLowering()
197 setOperationAction(ISD::SMUL_LOHI, VT, Custom); in SystemZTargetLowering()
198 setOperationAction(ISD::UMUL_LOHI, VT, Custom); in SystemZTargetLowering()
202 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in SystemZTargetLowering()
243 for (MVT VT : MVT::integer_valuetypes()) { in SystemZTargetLowering() local
244 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
245 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
246 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
268 for (MVT VT : MVT::vector_valuetypes()) { in SystemZTargetLowering() local
271 if (getOperationAction(Opcode, VT) == Legal) in SystemZTargetLowering()
272 setOperationAction(Opcode, VT, Expand); in SystemZTargetLowering()
276 setTruncStoreAction(VT, InnerVT, Expand); in SystemZTargetLowering()
277 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
278 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
279 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
282 if (isTypeLegal(VT)) { in SystemZTargetLowering()
287 setOperationAction(ISD::LOAD, VT, Legal); in SystemZTargetLowering()
288 setOperationAction(ISD::STORE, VT, Legal); in SystemZTargetLowering()
289 setOperationAction(ISD::VSELECT, VT, Legal); in SystemZTargetLowering()
290 setOperationAction(ISD::BITCAST, VT, Legal); in SystemZTargetLowering()
291 setOperationAction(ISD::UNDEF, VT, Legal); in SystemZTargetLowering()
295 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in SystemZTargetLowering()
296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
301 for (MVT VT : MVT::integer_vector_valuetypes()) { in SystemZTargetLowering() local
302 if (isTypeLegal(VT)) { in SystemZTargetLowering()
304 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
305 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
306 setOperationAction(ISD::ADD, VT, Legal); in SystemZTargetLowering()
307 setOperationAction(ISD::SUB, VT, Legal); in SystemZTargetLowering()
308 if (VT != MVT::v2i64) in SystemZTargetLowering()
309 setOperationAction(ISD::MUL, VT, Legal); in SystemZTargetLowering()
310 setOperationAction(ISD::AND, VT, Legal); in SystemZTargetLowering()
311 setOperationAction(ISD::OR, VT, Legal); in SystemZTargetLowering()
312 setOperationAction(ISD::XOR, VT, Legal); in SystemZTargetLowering()
313 setOperationAction(ISD::CTPOP, VT, Custom); in SystemZTargetLowering()
314 setOperationAction(ISD::CTTZ, VT, Legal); in SystemZTargetLowering()
315 setOperationAction(ISD::CTLZ, VT, Legal); in SystemZTargetLowering()
316 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom); in SystemZTargetLowering()
317 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom); in SystemZTargetLowering()
320 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); in SystemZTargetLowering()
323 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
324 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
328 setOperationAction(ISD::SHL, VT, Custom); in SystemZTargetLowering()
329 setOperationAction(ISD::SRA, VT, Custom); in SystemZTargetLowering()
330 setOperationAction(ISD::SRL, VT, Custom); in SystemZTargetLowering()
334 setOperationAction(ISD::ROTL, VT, Expand); in SystemZTargetLowering()
335 setOperationAction(ISD::ROTR, VT, Expand); in SystemZTargetLowering()
339 setOperationAction(ISD::SETCC, VT, Custom); in SystemZTargetLowering()
356 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
357 if (isTypeLegal(VT)) { in SystemZTargetLowering()
359 setOperationAction(ISD::FRINT, VT, Legal); in SystemZTargetLowering()
363 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
364 setOperationAction(ISD::FFLOOR, VT, Legal); in SystemZTargetLowering()
365 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
366 setOperationAction(ISD::FTRUNC, VT, Legal); in SystemZTargetLowering()
367 setOperationAction(ISD::FROUND, VT, Legal); in SystemZTargetLowering()
371 setOperationAction(ISD::FSIN, VT, Expand); in SystemZTargetLowering()
372 setOperationAction(ISD::FCOS, VT, Expand); in SystemZTargetLowering()
373 setOperationAction(ISD::FREM, VT, Expand); in SystemZTargetLowering()
415 for (MVT VT : MVT::fp_valuetypes()) in SystemZTargetLowering() local
416 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in SystemZTargetLowering()
460 LLVMContext &, EVT VT) const { in getSetCCResultType()
461 if (!VT.isVector()) in getSetCCResultType()
463 return VT.changeVectorElementTypeToInteger(); in getSetCCResultType()
466 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { in isFMAFasterThanFMulAndFAdd()
467 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
469 if (!VT.isSimple()) in isFMAFasterThanFMulAndFAdd()
472 switch (VT.getSimpleVT().SimpleTy) { in isFMAFasterThanFMulAndFAdd()
485 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
500 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses() argument
661 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { in getRegForInlineAsmConstraint()
668 if (VT == MVT::i64) in getRegForInlineAsmConstraint()
670 else if (VT == MVT::i128) in getRegForInlineAsmConstraint()
675 if (VT == MVT::i64) in getRegForInlineAsmConstraint()
677 else if (VT == MVT::i128) in getRegForInlineAsmConstraint()
685 if (VT == MVT::f64) in getRegForInlineAsmConstraint()
687 else if (VT == MVT::f128) in getRegForInlineAsmConstraint()
698 if (VT == MVT::i32) in getRegForInlineAsmConstraint()
701 if (VT == MVT::i128) in getRegForInlineAsmConstraint()
708 if (VT == MVT::f32) in getRegForInlineAsmConstraint()
711 if (VT == MVT::f128) in getRegForInlineAsmConstraint()
718 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); in getRegForInlineAsmConstraint()
787 static void VerifyVectorType(MVT VT, EVT ArgVT) { in VerifyVectorType() argument
788 if (ArgVT.isVector() && !VT.isVector()) in VerifyVectorType()
794 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT); in VerifyVectorTypes()
799 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT); in VerifyVectorTypes()
2143 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT, in lowerGR128Binary() argument
2150 bool Is32Bit = is32Bit(VT); in lowerGR128Binary()
2151 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2152 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2237 EVT VT, SDValue CmpOp0, SDValue CmpOp1) { in getVectorCmp() argument
2247 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes); in getVectorCmp()
2249 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1); in getVectorCmp()
2254 static SDValue lowerVectorSETCC(SelectionDAG &DAG, SDLoc DL, EVT VT, in lowerVectorSETCC() argument
2266 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0); in lowerVectorSETCC()
2267 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1); in lowerVectorSETCC()
2268 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE); in lowerVectorSETCC()
2277 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0); in lowerVectorSETCC()
2278 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1); in lowerVectorSETCC()
2279 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT); in lowerVectorSETCC()
2288 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1); in lowerVectorSETCC()
2292 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0); in lowerVectorSETCC()
2301 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask); in lowerVectorSETCC()
2302 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask); in lowerVectorSETCC()
2313 EVT VT = Op.getValueType(); in lowerSETCC() local
2314 if (VT.isVector()) in lowerSETCC()
2315 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1); in lowerSETCC()
2397 EVT VT = Op.getValueType(); in lowerSELECT_CC() local
2399 if (!is32Bit(VT)) in lowerSELECT_CC()
2400 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result); in lowerSELECT_CC()
2402 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32); in lowerSELECT_CC()
2403 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt); in lowerSELECT_CC()
2404 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt); in lowerSELECT_CC()
2766 EVT VT = Op.getValueType(); in lowerSMUL_LOHI() local
2769 if (is32Bit(VT)) in lowerSMUL_LOHI()
2791 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63); in lowerSMUL_LOHI()
2792 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI()
2796 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64, in lowerSMUL_LOHI()
2798 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH); in lowerSMUL_LOHI()
2799 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL); in lowerSMUL_LOHI()
2800 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL); in lowerSMUL_LOHI()
2801 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum); in lowerSMUL_LOHI()
2808 EVT VT = Op.getValueType(); in lowerUMUL_LOHI() local
2811 if (is32Bit(VT)) in lowerUMUL_LOHI()
2820 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64, in lowerUMUL_LOHI()
2829 EVT VT = Op.getValueType(); in lowerSDIVREM() local
2834 if (is32Bit(VT)) { in lowerSDIVREM()
2847 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode, in lowerSDIVREM()
2854 EVT VT = Op.getValueType(); in lowerUDIVREM() local
2861 if (is32Bit(VT)) in lowerUDIVREM()
2862 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32, in lowerUDIVREM()
2865 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64, in lowerUDIVREM()
2928 EVT VT = Op.getValueType(); in lowerCTPOP() local
2933 if (VT.isVector()) { in lowerCTPOP()
2936 switch (VT.getVectorElementType().getSizeInBits()) { in lowerCTPOP()
2940 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in lowerCTPOP()
2942 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift); in lowerCTPOP()
2943 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp); in lowerCTPOP()
2944 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift); in lowerCTPOP()
2950 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp); in lowerCTPOP()
2957 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp); in lowerCTPOP()
2971 return DAG.getConstant(0, DL, VT); in lowerCTPOP()
2974 int64_t OrigBitSize = VT.getSizeInBits(); in lowerCTPOP()
2981 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op); in lowerCTPOP()
2986 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT)); in lowerCTPOP()
2988 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp, in lowerCTPOP()
2989 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT)); in lowerCTPOP()
2990 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp); in lowerCTPOP()
2995 Op = DAG.getNode(ISD::SRL, DL, VT, Op, in lowerCTPOP()
2996 DAG.getConstant(BitSize - 8, DL, VT)); in lowerCTPOP()
3456 EVT VT = VSN->getValueType(0); in getVPermMask() local
3457 unsigned NumElements = VT.getVectorNumElements(); in getVPermMask()
3458 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize(); in getVPermMask()
3577 GeneralShuffle(EVT vt) : VT(vt) {} in GeneralShuffle()
3591 EVT VT; member
3597 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize(); in addUndef()
3607 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize(); in add()
3612 EVT FromVT = Op.getNode() ? Op.getValueType() : VT; in add()
3663 return DAG.getUNDEF(VT); in getNode()
3734 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in getNode()
3747 static SDValue buildScalarToVector(SelectionDAG &DAG, SDLoc DL, EVT VT, in buildScalarToVector() argument
3753 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value); in buildScalarToVector()
3754 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops); in buildScalarToVector()
3757 return DAG.getUNDEF(VT); in buildScalarToVector()
3758 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value); in buildScalarToVector()
3763 static SDValue buildMergeScalars(SelectionDAG &DAG, SDLoc DL, EVT VT, in buildMergeScalars() argument
3767 return DAG.getUNDEF(VT); in buildMergeScalars()
3768 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1); in buildMergeScalars()
3771 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0); in buildMergeScalars()
3772 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT, in buildMergeScalars()
3773 buildScalarToVector(DAG, DL, VT, Op0), in buildMergeScalars()
3774 buildScalarToVector(DAG, DL, VT, Op1)); in buildMergeScalars()
3832 SDLoc DL, EVT VT, uint64_t Value, in tryBuildVectorReplicate() argument
3841 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in tryBuildVectorReplicate()
3859 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in tryBuildVectorReplicate()
3870 EVT VT = BVN->getValueType(0); in tryBuildVectorShuffle() local
3871 unsigned NumElements = VT.getVectorNumElements(); in tryBuildVectorShuffle()
3877 GeneralShuffle GS(VT); in tryBuildVectorShuffle()
3904 ResidueOps.push_back(DAG.getUNDEF(VT.getVectorElementType())); in tryBuildVectorShuffle()
3907 Op = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BVN), VT, ResidueOps); in tryBuildVectorShuffle()
3916 static SDValue buildVector(SelectionDAG &DAG, SDLoc DL, EVT VT, in buildVector() argument
3947 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single); in buildVector()
3950 if (VT == MVT::v2i64) in buildVector()
3954 if (VT == MVT::v2f64) in buildVector()
3955 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]); in buildVector()
3964 if (VT == MVT::v4f32) { in buildVector()
3965 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]); in buildVector()
3966 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]); in buildVector()
3979 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in buildVector()
4004 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Constants); in buildVector()
4017 Result = DAG.getNode(ISD::BITCAST, DL, VT, in buildVector()
4022 Result = DAG.getUNDEF(VT); in buildVector()
4028 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
4039 EVT VT = Op.getValueType(); in lowerBUILD_VECTOR() local
4049 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in lowerBUILD_VECTOR()
4070 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, in lowerBUILD_VECTOR()
4080 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize); in lowerBUILD_VECTOR()
4095 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op)) in lowerBUILD_VECTOR()
4096 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0)); in lowerBUILD_VECTOR()
4103 return buildVector(DAG, DL, VT, Ops); in lowerBUILD_VECTOR()
4110 EVT VT = Op.getValueType(); in lowerVECTOR_SHUFFLE() local
4111 unsigned NumElements = VT.getVectorNumElements(); in lowerVECTOR_SHUFFLE()
4116 assert(Index < VT.getVectorNumElements() && in lowerVECTOR_SHUFFLE()
4121 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index)); in lowerVECTOR_SHUFFLE()
4123 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0), in lowerVECTOR_SHUFFLE()
4127 GeneralShuffle GS(VT); in lowerVECTOR_SHUFFLE()
4155 EVT VT = Op.getValueType(); in lowerINSERT_VECTOR_ELT() local
4160 if (VT == MVT::v2f64 && in lowerINSERT_VECTOR_ELT()
4165 unsigned Mask = VT.getVectorNumElements() - 1; in lowerINSERT_VECTOR_ELT()
4171 MVT IntVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits()); in lowerINSERT_VECTOR_ELT()
4172 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
4176 return DAG.getNode(ISD::BITCAST, DL, VT, Res); in lowerINSERT_VECTOR_ELT()
4186 EVT VT = Op.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
4198 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT()
4202 return DAG.getNode(ISD::BITCAST, DL, VT, Res); in lowerEXTRACT_VECTOR_ELT()
4228 EVT VT = Op.getValueType(); in lowerShift() local
4229 unsigned ElemBitSize = VT.getVectorElementType().getSizeInBits(); in lowerShift()
4243 return DAG.getNode(ByScalar, DL, VT, Op0, Shift); in lowerShift()
4252 return DAG.getNode(ByScalar, DL, VT, Op0, Shift); in lowerShift()
4262 assert(Index < VT.getVectorNumElements() && in lowerShift()
4270 return DAG.getNode(ByScalar, DL, VT, Op0, Shift); in lowerShift()
4496 static bool canTreatAsByteVector(EVT VT) { in canTreatAsByteVector() argument
4497 return VT.isVector() && VT.getVectorElementType().getSizeInBits() % 8 == 0; in canTreatAsByteVector()
4557 EVT VT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()); in combineExtract() local
4558 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in combineExtract()
4561 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract() local
4562 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op); in combineExtract()
4563 if (VT != ResVT) { in combineExtract()
4654 EVT VT = N->getValueType(0); in PerformDAGCombine() local
4660 unsigned Extra = (VT.getSizeInBits() - in PerformDAGCombine()
4665 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT, in PerformDAGCombine()
4667 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext, in PerformDAGCombine()
4670 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, in PerformDAGCombine()
4689 EVT VT = Op1.getValueType(); in PerformDAGCombine() local
4690 unsigned ElemBytes = VT.getVectorElementType().getStoreSize(); in PerformDAGCombine()
4694 EVT InVT = VT.changeVectorElementTypeToInteger(); in PerformDAGCombine()
4697 if (VT != InVT) { in PerformDAGCombine()
4703 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); in PerformDAGCombine()