40 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_pipe_enabled()  local
50 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_save_palette()  local
59 		array = dev_priv->save_palette_a;  in i915_save_palette()
61 		array = dev_priv->save_palette_b;  in i915_save_palette()
69 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_restore_palette()  local
78 		array = dev_priv->save_palette_a;  in i915_restore_palette()
80 		array = dev_priv->save_palette_b;  in i915_restore_palette()
88 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_read_indexed()  local
96 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_read_ar()  local
105 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_write_ar()  local
114 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_write_indexed()  local
122 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_save_vga()  local
127 	dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);  in i915_save_vga()
130 	dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);  in i915_save_vga()
131 	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {  in i915_save_vga()
146 		dev_priv->saveCR[i] =  in i915_save_vga()
149 	dev_priv->saveCR[0x11] &= ~0x80;  in i915_save_vga()
153 	dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);  in i915_save_vga()
155 		dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);  in i915_save_vga()
157 	I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);  in i915_save_vga()
162 		dev_priv->saveGR[i] =  in i915_save_vga()
165 	dev_priv->saveGR[0x10] =  in i915_save_vga()
167 	dev_priv->saveGR[0x11] =  in i915_save_vga()
169 	dev_priv->saveGR[0x18] =  in i915_save_vga()
174 		dev_priv->saveSR[i] =  in i915_save_vga()
180 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_restore_vga()  local
185 	I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);  in i915_restore_vga()
186 	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {  in i915_restore_vga()
199 				   dev_priv->saveSR[i]);  in i915_restore_vga()
203 	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);  in i915_restore_vga()
205 		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);  in i915_restore_vga()
210 				   dev_priv->saveGR[i]);  in i915_restore_vga()
213 			   dev_priv->saveGR[0x10]);  in i915_restore_vga()
215 			   dev_priv->saveGR[0x11]);  in i915_restore_vga()
217 			   dev_priv->saveGR[0x18]);  in i915_restore_vga()
222 		i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);  in i915_restore_vga()
224 	I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);  in i915_restore_vga()
228 	I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);  in i915_restore_vga()
233 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_save_state()  local
237 	dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1);  in i915_save_state()
239 	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);  in i915_save_state()
244 		dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);  in i915_save_state()
247 	dev_priv->saveHWS = I915_READ(HWS_PGA);  in i915_save_state()
250 	dev_priv->saveDSPARB = I915_READ(DSPARB);  in i915_save_state()
253 	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);  in i915_save_state()
254 	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);  in i915_save_state()
255 	dev_priv->saveFPA0 = I915_READ(FPA0);  in i915_save_state()
256 	dev_priv->saveFPA1 = I915_READ(FPA1);  in i915_save_state()
257 	dev_priv->saveDPLL_A = I915_READ(DPLL_A);  in i915_save_state()
259 		dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);  in i915_save_state()
260 	dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);  in i915_save_state()
261 	dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);  in i915_save_state()
262 	dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);  in i915_save_state()
263 	dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);  in i915_save_state()
264 	dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);  in i915_save_state()
265 	dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);  in i915_save_state()
266 	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);  in i915_save_state()
268 	dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);  in i915_save_state()
269 	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);  in i915_save_state()
270 	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);  in i915_save_state()
271 	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);  in i915_save_state()
272 	dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);  in i915_save_state()
274 		dev_priv->saveDSPASURF = I915_READ(DSPASURF);  in i915_save_state()
275 		dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);  in i915_save_state()
278 	dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);  in i915_save_state()
281 	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);  in i915_save_state()
282 	dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);  in i915_save_state()
283 	dev_priv->saveFPB0 = I915_READ(FPB0);  in i915_save_state()
284 	dev_priv->saveFPB1 = I915_READ(FPB1);  in i915_save_state()
285 	dev_priv->saveDPLL_B = I915_READ(DPLL_B);  in i915_save_state()
287 		dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);  in i915_save_state()
288 	dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);  in i915_save_state()
289 	dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);  in i915_save_state()
290 	dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);  in i915_save_state()
291 	dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);  in i915_save_state()
292 	dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);  in i915_save_state()
293 	dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);  in i915_save_state()
294 	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);  in i915_save_state()
296 	dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);  in i915_save_state()
297 	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);  in i915_save_state()
298 	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);  in i915_save_state()
299 	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);  in i915_save_state()
300 	dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);  in i915_save_state()
302 		dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);  in i915_save_state()
303 		dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);  in i915_save_state()
306 	dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);  in i915_save_state()
309 	dev_priv->saveADPA = I915_READ(ADPA);  in i915_save_state()
312 	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);  in i915_save_state()
313 	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);  in i915_save_state()
314 	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);  in i915_save_state()
316 		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);  in i915_save_state()
318 		dev_priv->saveLVDS = I915_READ(LVDS);  in i915_save_state()
320 		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);  in i915_save_state()
321 	dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);  in i915_save_state()
322 	dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);  in i915_save_state()
323 	dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);  in i915_save_state()
328 	dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);  in i915_save_state()
329 	dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);  in i915_save_state()
330 	dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);  in i915_save_state()
331 	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);  in i915_save_state()
334 	dev_priv->saveIIR = I915_READ(IIR);  in i915_save_state()
335 	dev_priv->saveIER = I915_READ(IER);  in i915_save_state()
336 	dev_priv->saveIMR = I915_READ(IMR);  in i915_save_state()
339 	dev_priv->saveVGA0 = I915_READ(VGA0);  in i915_save_state()
340 	dev_priv->saveVGA1 = I915_READ(VGA1);  in i915_save_state()
341 	dev_priv->saveVGA_PD = I915_READ(VGA_PD);  in i915_save_state()
342 	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);  in i915_save_state()
345 	dev_priv->saveD_STATE = I915_READ(D_STATE);  in i915_save_state()
346 	dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);  in i915_save_state()
349 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);  in i915_save_state()
352 	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);  in i915_save_state()
356 		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));  in i915_save_state()
357 		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));  in i915_save_state()
360 		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));  in i915_save_state()
369 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_restore_state()  local
373 	pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1);  in i915_restore_state()
375 	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);  in i915_restore_state()
380 		I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);  in i915_restore_state()
383 	I915_WRITE(HWS_PGA, dev_priv->saveHWS);  in i915_restore_state()
386 	I915_WRITE(DSPARB, dev_priv->saveDSPARB);  in i915_restore_state()
390 	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {  in i915_restore_state()
391 		I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &  in i915_restore_state()
395 	I915_WRITE(FPA0, dev_priv->saveFPA0);  in i915_restore_state()
396 	I915_WRITE(FPA1, dev_priv->saveFPA1);  in i915_restore_state()
398 	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);  in i915_restore_state()
401 		I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);  in i915_restore_state()
405 	I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);  in i915_restore_state()
406 	I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);  in i915_restore_state()
407 	I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);  in i915_restore_state()
408 	I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);  in i915_restore_state()
409 	I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);  in i915_restore_state()
410 	I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);  in i915_restore_state()
411 	I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);  in i915_restore_state()
414 	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);  in i915_restore_state()
415 	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);  in i915_restore_state()
416 	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);  in i915_restore_state()
417 	I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);  in i915_restore_state()
418 	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);  in i915_restore_state()
420 		I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);  in i915_restore_state()
421 		I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);  in i915_restore_state()
424 	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);  in i915_restore_state()
428 	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);  in i915_restore_state()
432 	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {  in i915_restore_state()
433 		I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &  in i915_restore_state()
437 	I915_WRITE(FPB0, dev_priv->saveFPB0);  in i915_restore_state()
438 	I915_WRITE(FPB1, dev_priv->saveFPB1);  in i915_restore_state()
440 	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);  in i915_restore_state()
443 		I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);  in i915_restore_state()
447 	I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);  in i915_restore_state()
448 	I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);  in i915_restore_state()
449 	I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);  in i915_restore_state()
450 	I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);  in i915_restore_state()
451 	I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);  in i915_restore_state()
452 	I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);  in i915_restore_state()
453 	I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);  in i915_restore_state()
456 	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);  in i915_restore_state()
457 	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);  in i915_restore_state()
458 	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);  in i915_restore_state()
459 	I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);  in i915_restore_state()
460 	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);  in i915_restore_state()
462 		I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);  in i915_restore_state()
463 		I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);  in i915_restore_state()
466 	I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);  in i915_restore_state()
470 	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);  in i915_restore_state()
474 	I915_WRITE(ADPA, dev_priv->saveADPA);  in i915_restore_state()
478 		I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);  in i915_restore_state()
480 		I915_WRITE(LVDS, dev_priv->saveLVDS);  in i915_restore_state()
482 		I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);  in i915_restore_state()
484 	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);  in i915_restore_state()
485 	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);  in i915_restore_state()
486 	I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);  in i915_restore_state()
487 	I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);  in i915_restore_state()
488 	I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);  in i915_restore_state()
489 	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);  in i915_restore_state()
494 	I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);  in i915_restore_state()
495 	I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);  in i915_restore_state()
496 	I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);  in i915_restore_state()
497 	I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);  in i915_restore_state()
500 	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);  in i915_restore_state()
501 	I915_WRITE(VGA0, dev_priv->saveVGA0);  in i915_restore_state()
502 	I915_WRITE(VGA1, dev_priv->saveVGA1);  in i915_restore_state()
503 	I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);  in i915_restore_state()
507 	I915_WRITE (D_STATE, dev_priv->saveD_STATE);  in i915_restore_state()
508 	I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);  in i915_restore_state()
511 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);  in i915_restore_state()
514 	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);  in i915_restore_state()
517 		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);  in i915_restore_state()
518 		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);  in i915_restore_state()
521 		I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);  in i915_restore_state()