Lines Matching refs:dev_priv
37 struct drm_i915_private *dev_priv = dev->dev_private; in i915_pipe_enabled() local
54 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_palette() local
66 array = dev_priv->save_palette_a; in i915_save_palette()
68 array = dev_priv->save_palette_b; in i915_save_palette()
76 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_palette() local
88 array = dev_priv->save_palette_a; in i915_restore_palette()
90 array = dev_priv->save_palette_b; in i915_restore_palette()
98 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_indexed() local
106 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_ar() local
115 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_ar() local
124 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_indexed() local
132 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_vga() local
137 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); in i915_save_vga()
140 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); in i915_save_vga()
141 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { in i915_save_vga()
156 dev_priv->saveCR[i] = in i915_save_vga()
159 dev_priv->saveCR[0x11] &= ~0x80; in i915_save_vga()
163 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); in i915_save_vga()
165 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); in i915_save_vga()
167 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); in i915_save_vga()
172 dev_priv->saveGR[i] = in i915_save_vga()
175 dev_priv->saveGR[0x10] = in i915_save_vga()
177 dev_priv->saveGR[0x11] = in i915_save_vga()
179 dev_priv->saveGR[0x18] = in i915_save_vga()
184 dev_priv->saveSR[i] = in i915_save_vga()
190 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_vga() local
195 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); in i915_restore_vga()
196 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { in i915_restore_vga()
209 dev_priv->saveSR[i]); in i915_restore_vga()
213 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); in i915_restore_vga()
215 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); in i915_restore_vga()
220 dev_priv->saveGR[i]); in i915_restore_vga()
223 dev_priv->saveGR[0x10]); in i915_restore_vga()
225 dev_priv->saveGR[0x11]); in i915_restore_vga()
227 dev_priv->saveGR[0x18]); in i915_restore_vga()
232 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); in i915_restore_vga()
234 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); in i915_restore_vga()
238 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); in i915_restore_vga()
243 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_modeset_reg() local
250 dev_priv->saveCURACNTR = I915_READ(_CURACNTR); in i915_save_modeset_reg()
251 dev_priv->saveCURAPOS = I915_READ(_CURAPOS); in i915_save_modeset_reg()
252 dev_priv->saveCURABASE = I915_READ(_CURABASE); in i915_save_modeset_reg()
253 dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR); in i915_save_modeset_reg()
254 dev_priv->saveCURBPOS = I915_READ(_CURBPOS); in i915_save_modeset_reg()
255 dev_priv->saveCURBBASE = I915_READ(_CURBBASE); in i915_save_modeset_reg()
257 dev_priv->saveCURSIZE = I915_READ(CURSIZE); in i915_save_modeset_reg()
260 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); in i915_save_modeset_reg()
261 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); in i915_save_modeset_reg()
265 dev_priv->savePIPEACONF = I915_READ(_PIPEACONF); in i915_save_modeset_reg()
266 dev_priv->savePIPEASRC = I915_READ(_PIPEASRC); in i915_save_modeset_reg()
268 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0); in i915_save_modeset_reg()
269 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1); in i915_save_modeset_reg()
270 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A); in i915_save_modeset_reg()
272 dev_priv->saveFPA0 = I915_READ(_FPA0); in i915_save_modeset_reg()
273 dev_priv->saveFPA1 = I915_READ(_FPA1); in i915_save_modeset_reg()
274 dev_priv->saveDPLL_A = I915_READ(_DPLL_A); in i915_save_modeset_reg()
277 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD); in i915_save_modeset_reg()
278 dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A); in i915_save_modeset_reg()
279 dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A); in i915_save_modeset_reg()
280 dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A); in i915_save_modeset_reg()
281 dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A); in i915_save_modeset_reg()
282 dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A); in i915_save_modeset_reg()
283 dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A); in i915_save_modeset_reg()
285 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A); in i915_save_modeset_reg()
288 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1); in i915_save_modeset_reg()
289 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1); in i915_save_modeset_reg()
290 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1); in i915_save_modeset_reg()
291 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1); in i915_save_modeset_reg()
293 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL); in i915_save_modeset_reg()
294 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL); in i915_save_modeset_reg()
296 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1); in i915_save_modeset_reg()
297 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ); in i915_save_modeset_reg()
298 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS); in i915_save_modeset_reg()
300 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF); in i915_save_modeset_reg()
301 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A); in i915_save_modeset_reg()
302 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A); in i915_save_modeset_reg()
303 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A); in i915_save_modeset_reg()
304 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A); in i915_save_modeset_reg()
305 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A); in i915_save_modeset_reg()
306 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A); in i915_save_modeset_reg()
309 dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR); in i915_save_modeset_reg()
310 dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE); in i915_save_modeset_reg()
311 dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE); in i915_save_modeset_reg()
312 dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS); in i915_save_modeset_reg()
313 dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR); in i915_save_modeset_reg()
315 dev_priv->saveDSPASURF = I915_READ(_DSPASURF); in i915_save_modeset_reg()
316 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF); in i915_save_modeset_reg()
319 dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT); in i915_save_modeset_reg()
322 dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF); in i915_save_modeset_reg()
323 dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC); in i915_save_modeset_reg()
325 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0); in i915_save_modeset_reg()
326 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1); in i915_save_modeset_reg()
327 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B); in i915_save_modeset_reg()
329 dev_priv->saveFPB0 = I915_READ(_FPB0); in i915_save_modeset_reg()
330 dev_priv->saveFPB1 = I915_READ(_FPB1); in i915_save_modeset_reg()
331 dev_priv->saveDPLL_B = I915_READ(_DPLL_B); in i915_save_modeset_reg()
334 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD); in i915_save_modeset_reg()
335 dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B); in i915_save_modeset_reg()
336 dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B); in i915_save_modeset_reg()
337 dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B); in i915_save_modeset_reg()
338 dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B); in i915_save_modeset_reg()
339 dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B); in i915_save_modeset_reg()
340 dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B); in i915_save_modeset_reg()
342 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B); in i915_save_modeset_reg()
345 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1); in i915_save_modeset_reg()
346 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1); in i915_save_modeset_reg()
347 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1); in i915_save_modeset_reg()
348 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1); in i915_save_modeset_reg()
350 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL); in i915_save_modeset_reg()
351 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL); in i915_save_modeset_reg()
353 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1); in i915_save_modeset_reg()
354 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ); in i915_save_modeset_reg()
355 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS); in i915_save_modeset_reg()
357 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF); in i915_save_modeset_reg()
358 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B); in i915_save_modeset_reg()
359 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B); in i915_save_modeset_reg()
360 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B); in i915_save_modeset_reg()
361 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B); in i915_save_modeset_reg()
362 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B); in i915_save_modeset_reg()
363 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B); in i915_save_modeset_reg()
366 dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR); in i915_save_modeset_reg()
367 dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE); in i915_save_modeset_reg()
368 dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE); in i915_save_modeset_reg()
369 dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS); in i915_save_modeset_reg()
370 dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR); in i915_save_modeset_reg()
372 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF); in i915_save_modeset_reg()
373 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF); in i915_save_modeset_reg()
376 dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT); in i915_save_modeset_reg()
383 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); in i915_save_modeset_reg()
388 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); in i915_save_modeset_reg()
393 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); in i915_save_modeset_reg()
396 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); in i915_save_modeset_reg()
405 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_modeset_reg() local
418 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]); in i915_restore_modeset_reg()
423 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]); in i915_restore_modeset_reg()
429 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]); in i915_restore_modeset_reg()
431 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]); in i915_restore_modeset_reg()
453 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); in i915_restore_modeset_reg()
454 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); in i915_restore_modeset_reg()
459 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { in i915_restore_modeset_reg()
460 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & in i915_restore_modeset_reg()
465 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); in i915_restore_modeset_reg()
466 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); in i915_restore_modeset_reg()
468 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); in i915_restore_modeset_reg()
472 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD); in i915_restore_modeset_reg()
478 I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A); in i915_restore_modeset_reg()
479 I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A); in i915_restore_modeset_reg()
480 I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A); in i915_restore_modeset_reg()
481 I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A); in i915_restore_modeset_reg()
482 I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A); in i915_restore_modeset_reg()
483 I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A); in i915_restore_modeset_reg()
485 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A); in i915_restore_modeset_reg()
488 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); in i915_restore_modeset_reg()
489 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); in i915_restore_modeset_reg()
490 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); in i915_restore_modeset_reg()
491 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1); in i915_restore_modeset_reg()
493 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); in i915_restore_modeset_reg()
494 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); in i915_restore_modeset_reg()
496 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1); in i915_restore_modeset_reg()
497 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ); in i915_restore_modeset_reg()
498 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS); in i915_restore_modeset_reg()
500 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF); in i915_restore_modeset_reg()
501 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A); in i915_restore_modeset_reg()
502 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A); in i915_restore_modeset_reg()
503 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A); in i915_restore_modeset_reg()
504 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A); in i915_restore_modeset_reg()
505 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A); in i915_restore_modeset_reg()
506 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A); in i915_restore_modeset_reg()
510 I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE); in i915_restore_modeset_reg()
511 I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS); in i915_restore_modeset_reg()
512 I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC); in i915_restore_modeset_reg()
513 I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR); in i915_restore_modeset_reg()
514 I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE); in i915_restore_modeset_reg()
516 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF); in i915_restore_modeset_reg()
517 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF); in i915_restore_modeset_reg()
520 I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF); in i915_restore_modeset_reg()
524 I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR); in i915_restore_modeset_reg()
528 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { in i915_restore_modeset_reg()
529 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & in i915_restore_modeset_reg()
534 I915_WRITE(fpb0_reg, dev_priv->saveFPB0); in i915_restore_modeset_reg()
535 I915_WRITE(fpb1_reg, dev_priv->saveFPB1); in i915_restore_modeset_reg()
537 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); in i915_restore_modeset_reg()
541 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD); in i915_restore_modeset_reg()
547 I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B); in i915_restore_modeset_reg()
548 I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B); in i915_restore_modeset_reg()
549 I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B); in i915_restore_modeset_reg()
550 I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B); in i915_restore_modeset_reg()
551 I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B); in i915_restore_modeset_reg()
552 I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B); in i915_restore_modeset_reg()
554 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B); in i915_restore_modeset_reg()
557 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); in i915_restore_modeset_reg()
558 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); in i915_restore_modeset_reg()
559 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); in i915_restore_modeset_reg()
560 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1); in i915_restore_modeset_reg()
562 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); in i915_restore_modeset_reg()
563 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); in i915_restore_modeset_reg()
565 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1); in i915_restore_modeset_reg()
566 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ); in i915_restore_modeset_reg()
567 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS); in i915_restore_modeset_reg()
569 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF); in i915_restore_modeset_reg()
570 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B); in i915_restore_modeset_reg()
571 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B); in i915_restore_modeset_reg()
572 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B); in i915_restore_modeset_reg()
573 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B); in i915_restore_modeset_reg()
574 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B); in i915_restore_modeset_reg()
575 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B); in i915_restore_modeset_reg()
579 I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE); in i915_restore_modeset_reg()
580 I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS); in i915_restore_modeset_reg()
581 I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC); in i915_restore_modeset_reg()
582 I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR); in i915_restore_modeset_reg()
583 I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); in i915_restore_modeset_reg()
585 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF); in i915_restore_modeset_reg()
586 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); in i915_restore_modeset_reg()
589 I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF); in i915_restore_modeset_reg()
593 I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR); in i915_restore_modeset_reg()
597 I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS); in i915_restore_modeset_reg()
598 I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR); in i915_restore_modeset_reg()
599 I915_WRITE(_CURABASE, dev_priv->saveCURABASE); in i915_restore_modeset_reg()
600 I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS); in i915_restore_modeset_reg()
601 I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR); in i915_restore_modeset_reg()
602 I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE); in i915_restore_modeset_reg()
604 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); in i915_restore_modeset_reg()
611 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_display() local
614 dev_priv->saveDSPARB = I915_READ(DSPARB); in i915_save_display()
622 dev_priv->saveADPA = I915_READ(PCH_ADPA); in i915_save_display()
624 dev_priv->saveADPA = I915_READ(ADPA); in i915_save_display()
629 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()
630 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); in i915_save_display()
631 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); in i915_save_display()
632 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL); in i915_save_display()
633 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2); in i915_save_display()
634 dev_priv->saveLVDS = I915_READ(PCH_LVDS); in i915_save_display()
636 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); in i915_save_display()
637 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); in i915_save_display()
638 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); in i915_save_display()
639 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); in i915_save_display()
641 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); in i915_save_display()
643 dev_priv->saveLVDS = I915_READ(LVDS); in i915_save_display()
647 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); in i915_save_display()
650 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); in i915_save_display()
651 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); in i915_save_display()
652 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); in i915_save_display()
654 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); in i915_save_display()
655 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); in i915_save_display()
656 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); in i915_save_display()
661 dev_priv->saveDP_B = I915_READ(DP_B); in i915_save_display()
662 dev_priv->saveDP_C = I915_READ(DP_C); in i915_save_display()
663 dev_priv->saveDP_D = I915_READ(DP_D); in i915_save_display()
664 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M); in i915_save_display()
665 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M); in i915_save_display()
666 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N); in i915_save_display()
667 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N); in i915_save_display()
668 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M); in i915_save_display()
669 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M); in i915_save_display()
670 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N); in i915_save_display()
671 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N); in i915_save_display()
678 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); in i915_save_display()
680 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); in i915_save_display()
682 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); in i915_save_display()
683 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); in i915_save_display()
684 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); in i915_save_display()
685 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
690 dev_priv->saveVGA0 = I915_READ(VGA0); in i915_save_display()
691 dev_priv->saveVGA1 = I915_READ(VGA1); in i915_save_display()
692 dev_priv->saveVGA_PD = I915_READ(VGA_PD); in i915_save_display()
694 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); in i915_save_display()
696 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); in i915_save_display()
703 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_display() local
706 I915_WRITE(DSPARB, dev_priv->saveDSPARB); in i915_restore_display()
710 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M); in i915_restore_display()
711 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M); in i915_restore_display()
712 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N); in i915_restore_display()
713 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N); in i915_restore_display()
714 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M); in i915_restore_display()
715 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M); in i915_restore_display()
716 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N); in i915_restore_display()
717 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N); in i915_restore_display()
726 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); in i915_restore_display()
728 I915_WRITE(ADPA, dev_priv->saveADPA); in i915_restore_display()
732 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); in i915_restore_display()
735 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); in i915_restore_display()
737 I915_WRITE(LVDS, dev_priv->saveLVDS); in i915_restore_display()
740 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); in i915_restore_display()
743 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); in i915_restore_display()
744 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); in i915_restore_display()
745 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); in i915_restore_display()
746 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2); in i915_restore_display()
747 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); in i915_restore_display()
748 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); in i915_restore_display()
749 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); in i915_restore_display()
750 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL); in i915_restore_display()
752 dev_priv->saveMCHBAR_RENDER_STANDBY); in i915_restore_display()
754 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); in i915_restore_display()
755 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); in i915_restore_display()
756 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL); in i915_restore_display()
757 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); in i915_restore_display()
758 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); in i915_restore_display()
759 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); in i915_restore_display()
760 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); in i915_restore_display()
765 I915_WRITE(DP_B, dev_priv->saveDP_B); in i915_restore_display()
766 I915_WRITE(DP_C, dev_priv->saveDP_C); in i915_restore_display()
767 I915_WRITE(DP_D, dev_priv->saveDP_D); in i915_restore_display()
775 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); in i915_restore_display()
777 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); in i915_restore_display()
779 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); in i915_restore_display()
780 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); in i915_restore_display()
781 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); in i915_restore_display()
782 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); in i915_restore_display()
787 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); in i915_restore_display()
789 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); in i915_restore_display()
791 I915_WRITE(VGA0, dev_priv->saveVGA0); in i915_restore_display()
792 I915_WRITE(VGA1, dev_priv->saveVGA1); in i915_restore_display()
793 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); in i915_restore_display()
802 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_state() local
805 dev_priv->saveLBB = pci_read_config(dev->dev, LBB, 1); in i915_save_state()
808 dev_priv->saveHWS = I915_READ(HWS_PGA); in i915_save_state()
816 dev_priv->saveDEIER = I915_READ(DEIER); in i915_save_state()
817 dev_priv->saveDEIMR = I915_READ(DEIMR); in i915_save_state()
818 dev_priv->saveGTIER = I915_READ(GTIER); in i915_save_state()
819 dev_priv->saveGTIMR = I915_READ(GTIMR); in i915_save_state()
820 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR); in i915_save_state()
821 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR); in i915_save_state()
822 dev_priv->saveMCHBAR_RENDER_STANDBY = in i915_save_state()
824 dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG); in i915_save_state()
826 dev_priv->saveIER = I915_READ(IER); in i915_save_state()
827 dev_priv->saveIMR = I915_READ(IMR); in i915_save_state()
836 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
839 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); in i915_save_state()
843 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); in i915_save_state()
844 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); in i915_save_state()
847 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); in i915_save_state()
856 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_state() local
859 pci_write_config(dev->dev, LBB, dev_priv->saveLBB, 1); in i915_restore_state()
864 I915_WRITE(HWS_PGA, dev_priv->saveHWS); in i915_restore_state()
870 I915_WRITE(DEIER, dev_priv->saveDEIER); in i915_restore_state()
871 I915_WRITE(DEIMR, dev_priv->saveDEIMR); in i915_restore_state()
872 I915_WRITE(GTIER, dev_priv->saveGTIER); in i915_restore_state()
873 I915_WRITE(GTIMR, dev_priv->saveGTIMR); in i915_restore_state()
874 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR); in i915_restore_state()
875 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR); in i915_restore_state()
876 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG); in i915_restore_state()
878 I915_WRITE(IER, dev_priv->saveIER); in i915_restore_state()
879 I915_WRITE(IMR, dev_priv->saveIMR); in i915_restore_state()
883 I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); in i915_restore_state()
886 I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); in i915_restore_state()
889 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); in i915_restore_state()
890 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]); in i915_restore_state()
893 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); in i915_restore_state()