351 		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",  in intel_dp_check_edp()
459 		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);  in intel_dp_aux_ch()
607 			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);  in intel_dp_i2c_aux_ch()
618 			DRM_DEBUG_KMS("aux_ch native nack\n");  in intel_dp_i2c_aux_ch()
636 			DRM_DEBUG_KMS("aux_i2c nack\n");  in intel_dp_i2c_aux_ch()
639 			DRM_DEBUG_KMS("aux_i2c defer\n");  in intel_dp_i2c_aux_ch()
661 	DRM_DEBUG_KMS("i2c_init %s\n", name);  in intel_dp_i2c_init()
689 	DRM_DEBUG_KMS("DP link computation with max lane count %i "  in intel_dp_mode_fixup()
707 				DRM_DEBUG_KMS("DP link bw %02x lane "  in intel_dp_mode_fixup()
711 				DRM_DEBUG_KMS("DP link bw required %i available %i\n",  in intel_dp_mode_fixup()
870 		DRM_DEBUG_KMS("Enabling DP audio on pipe %c\n",  in intel_dp_mode_set()
950 	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",  in ironlake_wait_panel_status()
964 	DRM_DEBUG_KMS("Wait for panel power on\n");  in ironlake_wait_panel_on()
970 	DRM_DEBUG_KMS("Wait for panel power off time\n");  in ironlake_wait_panel_off()
976 	DRM_DEBUG_KMS("Wait for panel power cycle\n");  in ironlake_wait_panel_power_cycle()
1002 	DRM_DEBUG_KMS("Turn eDP VDD on\n");  in ironlake_edp_panel_vdd_on()
1010 		DRM_DEBUG_KMS("eDP VDD already on\n");  in ironlake_edp_panel_vdd_on()
1021 	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",  in ironlake_edp_panel_vdd_on()
1028 		DRM_DEBUG_KMS("eDP was not running\n");  in ironlake_edp_panel_vdd_on()
1046 		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",  in ironlake_panel_vdd_off_sync()
1068 	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);  in ironlake_edp_panel_vdd_off()
1098 	DRM_DEBUG_KMS("Turn eDP power on\n");  in ironlake_edp_panel_on()
1101 		DRM_DEBUG_KMS("eDP power already on\n");  in ironlake_edp_panel_on()
1140 	DRM_DEBUG_KMS("Turn eDP power off\n");  in ironlake_edp_panel_off()
1163 	DRM_DEBUG_KMS("\n");  in ironlake_edp_backlight_on()
1186 	DRM_DEBUG_KMS("\n");  in ironlake_edp_backlight_off()
1200 	DRM_DEBUG_KMS("\n");  in ironlake_edp_pll_on()
1547 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"  in intel_gen6_edp_signal_levels()
1578 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"  in intel_gen7_edp_signal_levels()
1707 			DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);  in intel_dp_start_link_train()
1728 			DRM_DEBUG_KMS("clock recovery OK\n");  in intel_dp_start_link_train()
1740 				DRM_DEBUG_KMS("too many full retries, give up\n");  in intel_dp_start_link_train()
1752 				DRM_DEBUG_KMS("too many voltage retries, give up\n");  in intel_dp_start_link_train()
1863 	DRM_DEBUG_KMS("\n");  in intel_dp_link_down()
1951 		DRM_DEBUG_KMS("Sink OUI: %02x%02x%02x\n",  in intel_dp_probe_oui()
1955 		DRM_DEBUG_KMS("Branch OUI: %02x%02x%02x\n",  in intel_dp_probe_oui()
2024 			DRM_DEBUG_KMS("CP or sink specific irq unhandled\n");  in intel_dp_check_link_status()
2028 		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",  in intel_dp_check_link_status()
2521 		DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",  in intel_dp_init()
2526 		DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",  in intel_dp_init()
2537 		DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",  in intel_dp_init()
2541 		DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",  in intel_dp_init()