41 		  int w, int h, u64 gpu_addr)  in set_render_target()  argument
59 	radeon_ring_write(ring, gpu_addr >> 8);  in set_render_target()
117 	u64 gpu_addr;  in set_shaders()  local
124 	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;  in set_shaders()
127 	radeon_ring_write(ring, gpu_addr >> 8);  in set_shaders()
138 	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;  in set_shaders()
141 	radeon_ring_write(ring, gpu_addr >> 8);  in set_shaders()
155 	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;  in set_shaders()
156 	cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);  in set_shaders()
161 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)  in set_vtx_resource()  argument
166 	sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |  in set_vtx_resource()
174 	radeon_ring_write(ring, gpu_addr & 0xffffffff);  in set_vtx_resource()
188 				    PACKET3_TC_ACTION_ENA, 48, gpu_addr);  in set_vtx_resource()
191 				    PACKET3_VC_ACTION_ENA, 48, gpu_addr);  in set_vtx_resource()
198 		 u64 gpu_addr, u32 size)  in set_tex_resource()  argument
221 			    PACKET3_TC_ACTION_ENA, size, gpu_addr);  in set_tex_resource()
227 	radeon_ring_write(ring, gpu_addr >> 8);  in set_tex_resource()
228 	radeon_ring_write(ring, gpu_addr >> 8);  in set_tex_resource()
291 	u64 gpu_addr;  in set_default_state()  local
440 	gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;  in set_default_state()
446 			  (gpu_addr & 0xFFFFFFFC));  in set_default_state()
447 	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);  in set_default_state()