Lines Matching refs:DMA_BLOCK
98 #define DMA_BLOCK (4 << _BLK_REG_SHFT) macro
148 #define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
150 #define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
151 #define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
152 #define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
153 #define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
154 #define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
155 #define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
156 #define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
157 #define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
159 #define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
161 #define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
162 #define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
163 #define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
164 #define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
165 #define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
166 #define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
167 #define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
169 #define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
170 #define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */