2370               amdgpu_state->vclk && amdgpu_state->dclk)  in si_should_disable_uvd_powertune()
3178               (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_before_set_eng_clock()
3185           amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3196               (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_after_set_eng_clock()
3203           amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
3478           if (rps->vclk || rps->dclk) {  in si_apply_state_adjust_rules()
5630           if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))  in si_is_state_ulv_compatible()
5667           if (amdgpu_state->vclk && amdgpu_state->dclk) {  in si_convert_power_state_to_smc()
7114                     rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in si_parse_pplib_non_clock_info()
7117                     rps->dclk = RV770_DEFAULT_DCLK_FREQ;  in si_parse_pplib_non_clock_info()
7120                     rps->dclk = 0;  in si_parse_pplib_non_clock_info()
7495                     seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in si_dpm_debugfs_print_current_performance_level()
7902           DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in si_dpm_print_power_state()
7974           *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));  in si_check_state_equal()