Lines Matching refs:WREG32
176 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_rreg()
187 WREG32(CIK_DIDT_IND_INDEX, (reg)); in cik_didt_wreg()
188 WREG32(CIK_DIDT_IND_DATA, (v)); in cik_didt_wreg()
238 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
250 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
252 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1846 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1904 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1905 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1910 … WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1911 … WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1913 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ci_mc_load_microcode()
1914 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ci_mc_load_microcode()
1920 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); in ci_mc_load_microcode()
1921 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); in ci_mc_load_microcode()
1922 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); in ci_mc_load_microcode()
1923 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); in ci_mc_load_microcode()
1929 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in ci_mc_load_microcode()
1931 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ci_mc_load_microcode()
1935 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1936 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ci_mc_load_microcode()
1937 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ci_mc_load_microcode()
2522 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2524 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2665 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2667 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2890 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2892 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
3033 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
3035 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
3067 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
3187 WREG32(PA_SC_RASTER_CONFIG, data); in cik_setup_rb()
3284 WREG32((0x2c14 + j), 0x00000000); in cik_gpu_init()
3285 WREG32((0x2c18 + j), 0x00000000); in cik_gpu_init()
3286 WREG32((0x2c1c + j), 0x00000000); in cik_gpu_init()
3287 WREG32((0x2c20 + j), 0x00000000); in cik_gpu_init()
3288 WREG32((0x2c24 + j), 0x00000000); in cik_gpu_init()
3291 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cik_gpu_init()
3292 WREG32(SRBM_INT_CNTL, 0x1); in cik_gpu_init()
3293 WREG32(SRBM_INT_ACK, 0x1); in cik_gpu_init()
3295 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in cik_gpu_init()
3357 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3358 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3359 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
3360 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3361 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3362 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3363 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3364 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3381 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cik_gpu_init()
3389 WREG32(SX_DEBUG_1, 0x20); in cik_gpu_init()
3391 WREG32(TA_CNTL_AUX, 0x00010000); in cik_gpu_init()
3395 WREG32(SPI_CONFIG_CNTL, tmp); in cik_gpu_init()
3397 WREG32(SQ_CONFIG, 1); in cik_gpu_init()
3399 WREG32(DB_DEBUG, 0); in cik_gpu_init()
3403 WREG32(DB_DEBUG2, tmp); in cik_gpu_init()
3407 WREG32(DB_DEBUG3, tmp); in cik_gpu_init()
3411 WREG32(CB_HW_CONTROL, tmp); in cik_gpu_init()
3413 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in cik_gpu_init()
3415 … WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | in cik_gpu_init()
3420 WREG32(VGT_NUM_INSTANCES, 1); in cik_gpu_init()
3422 WREG32(CP_PERFMON_CNTL, 0); in cik_gpu_init()
3424 WREG32(SQ_CONFIG, 0); in cik_gpu_init()
3426 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in cik_gpu_init()
3429 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cik_gpu_init()
3432 WREG32(VGT_GS_VERTEX_REUSE, 16); in cik_gpu_init()
3433 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cik_gpu_init()
3437 WREG32(HDP_MISC_CNTL, tmp); in cik_gpu_init()
3440 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in cik_gpu_init()
3442 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cik_gpu_init()
3443 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); in cik_gpu_init()
3497 WREG32(scratch, 0xCAFEDEAD); in cik_ring_test()
3822 WREG32(scratch, 0xCAFEDEAD); in cik_ib_test()
3906 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3910 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
3951 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3953 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3954 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3960 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3962 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3963 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3969 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3971 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3972 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3973 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
3979 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3981 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3982 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3986 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3988 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3989 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
3993 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
3995 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
3996 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4017 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); in cik_cp_gfx_start()
4018 WREG32(CP_ENDIAN_SWAP, 0); in cik_cp_gfx_start()
4019 WREG32(CP_DEVICE_ID, 1); in cik_cp_gfx_start()
4094 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cik_cp_gfx_resume()
4096 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cik_cp_gfx_resume()
4099 WREG32(CP_RB_WPTR_DELAY, 0); in cik_cp_gfx_resume()
4102 WREG32(CP_RB_VMID, 0); in cik_cp_gfx_resume()
4104 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cik_cp_gfx_resume()
4114 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4117 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4119 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4122 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in cik_cp_gfx_resume()
4123 … WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in cik_cp_gfx_resume()
4126 WREG32(SCRATCH_UMSK, 0); in cik_cp_gfx_resume()
4132 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4135 WREG32(CP_RB0_BASE, rb_addr); in cik_cp_gfx_resume()
4136 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); in cik_cp_gfx_resume()
4175 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4233 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_compute_stop()
4236 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_compute_stop()
4242 WREG32(CP_HQD_DEQUEUE_REQUEST, 0); in cik_compute_stop()
4243 WREG32(CP_HQD_PQ_RPTR, 0); in cik_compute_stop()
4244 WREG32(CP_HQD_PQ_WPTR, 0); in cik_compute_stop()
4260 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4271 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4307 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4309 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4310 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4321 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4323 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4324 … WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4331 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4333 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4334 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4339 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4341 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4342 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4566 WREG32(CP_CPF_DEBUG, tmp); in cik_cp_compute_resume()
4576 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); in cik_cp_compute_resume()
4577 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); in cik_cp_compute_resume()
4580 WREG32(CP_HPD_EOP_VMID, 0); in cik_cp_compute_resume()
4586 WREG32(CP_HPD_EOP_CONTROL, tmp); in cik_cp_compute_resume()
4647 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_cp_compute_resume()
4656 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
4664 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_cp_compute_resume()
4670 … WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); in cik_cp_compute_resume()
4671 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); in cik_cp_compute_resume()
4672 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
4678 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); in cik_cp_compute_resume()
4679 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in cik_cp_compute_resume()
4683 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()
4689 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); in cik_cp_compute_resume()
4690 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()
4708 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
4717 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); in cik_cp_compute_resume()
4718 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI, in cik_cp_compute_resume()
4729 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR, in cik_cp_compute_resume()
4731 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI, in cik_cp_compute_resume()
4748 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
4754 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
4759 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); in cik_cp_compute_resume()
4763 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); in cik_cp_compute_resume()
4982 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
4985 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
4991 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
4997 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5047 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5053 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5061 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5067 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5093 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP); in kv_save_regs_for_reset()
5094 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE | in kv_save_regs_for_reset()
5103 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5104 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff); in kv_restore_regs_for_reset()
5107 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5109 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5110 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff); in kv_restore_regs_for_reset()
5113 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5115 WREG32(GMCON_PGFSM_WRITE, 0x210000); in kv_restore_regs_for_reset()
5116 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff); in kv_restore_regs_for_reset()
5119 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5121 WREG32(GMCON_PGFSM_WRITE, 0x21003); in kv_restore_regs_for_reset()
5122 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff); in kv_restore_regs_for_reset()
5125 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5127 WREG32(GMCON_PGFSM_WRITE, 0x2b00); in kv_restore_regs_for_reset()
5128 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff); in kv_restore_regs_for_reset()
5131 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5133 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5134 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff); in kv_restore_regs_for_reset()
5137 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5139 WREG32(GMCON_PGFSM_WRITE, 0x420000); in kv_restore_regs_for_reset()
5140 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff); in kv_restore_regs_for_reset()
5143 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5145 WREG32(GMCON_PGFSM_WRITE, 0x120202); in kv_restore_regs_for_reset()
5146 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff); in kv_restore_regs_for_reset()
5149 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5151 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36); in kv_restore_regs_for_reset()
5152 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff); in kv_restore_regs_for_reset()
5155 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5157 WREG32(GMCON_PGFSM_WRITE, 0x373f3e); in kv_restore_regs_for_reset()
5158 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff); in kv_restore_regs_for_reset()
5161 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5163 WREG32(GMCON_PGFSM_WRITE, 0x3e1332); in kv_restore_regs_for_reset()
5164 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff); in kv_restore_regs_for_reset()
5166 WREG32(GMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
5167 WREG32(GMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
5168 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
5186 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
5189 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
5194 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5198 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5314 WREG32((0x2c14 + j), 0x00000000); in cik_mc_program()
5315 WREG32((0x2c18 + j), 0x00000000); in cik_mc_program()
5316 WREG32((0x2c1c + j), 0x00000000); in cik_mc_program()
5317 WREG32((0x2c20 + j), 0x00000000); in cik_mc_program()
5318 WREG32((0x2c24 + j), 0x00000000); in cik_mc_program()
5320 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in cik_mc_program()
5327 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in cik_mc_program()
5329 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in cik_mc_program()
5331 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in cik_mc_program()
5333 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in cik_mc_program()
5337 WREG32(MC_VM_FB_LOCATION, tmp); in cik_mc_program()
5339 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in cik_mc_program()
5340 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in cik_mc_program()
5341 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in cik_mc_program()
5342 WREG32(MC_VM_AGP_BASE, 0); in cik_mc_program()
5343 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in cik_mc_program()
5344 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in cik_mc_program()
5437 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); in cik_pcie_gart_tlb_flush()
5440 WREG32(VM_INVALIDATE_REQUEST, 0x1); in cik_pcie_gart_tlb_flush()
5466 WREG32(MC_VM_MX_L1_TLB_CNTL, in cik_pcie_gart_enable()
5474 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5480 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5481 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5485 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cik_pcie_gart_enable()
5486 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cik_pcie_gart_enable()
5487 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cik_pcie_gart_enable()
5488 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5490 WREG32(VM_CONTEXT0_CNTL2, 0); in cik_pcie_gart_enable()
5491 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5494 WREG32(0x15D4, 0); in cik_pcie_gart_enable()
5495 WREG32(0x15D8, 0); in cik_pcie_gart_enable()
5496 WREG32(0x15DC, 0); in cik_pcie_gart_enable()
5500 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in cik_pcie_gart_enable()
5501 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in cik_pcie_gart_enable()
5504 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cik_pcie_gart_enable()
5507 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in cik_pcie_gart_enable()
5512 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5514 WREG32(VM_CONTEXT1_CNTL2, 4); in cik_pcie_gart_enable()
5515 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5533 WREG32(CHUB_CONTROL, tmp); in cik_pcie_gart_enable()
5542 WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); in cik_pcie_gart_enable()
5543 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_gart_enable()
5544 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_gart_enable()
5545 WREG32(SH_MEM_BASES, 0); in cik_pcie_gart_enable()
5547 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5548 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5549 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5550 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5585 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
5586 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()
5588 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in cik_pcie_gart_disable()
5591 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
5597 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
5598 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
5802 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
5814 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
5850 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
5863 WREG32(RLC_CNTL, data); in cik_halt_rlc()
5882 WREG32(RLC_GPR_REG2, tmp); in cik_enter_rlc_safe_mode()
5903 WREG32(RLC_GPR_REG2, tmp); in cik_exit_rlc_safe_mode()
5915 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
5931 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
5958 WREG32(RLC_CGCG_CGLS_CTRL, tmp); in cik_rlc_resume()
5966 WREG32(RLC_LB_CNTR_INIT, 0); in cik_rlc_resume()
5967 WREG32(RLC_LB_CNTR_MAX, 0x00008000); in cik_rlc_resume()
5971 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in cik_rlc_resume()
5972 WREG32(RLC_LB_PARAMS, 0x00600408); in cik_rlc_resume()
5973 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
5976 WREG32(RLC_MC_CNTL, 0); in cik_rlc_resume()
5977 WREG32(RLC_UCODE_CNTL, 0); in cik_rlc_resume()
5988 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
5990 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_rlc_resume()
5991 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version)); in cik_rlc_resume()
6013 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6015 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_rlc_resume()
6016 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6023 WREG32(RLC_DRIVER_DMA_STATUS, 0); in cik_rlc_resume()
6043 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6044 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6046 WREG32(RLC_SERDES_WR_CTRL, tmp2); in cik_enable_cgcg()
6064 WREG32(RLC_CGCG_CGLS_CTRL, data); in cik_enable_cgcg()
6078 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6086 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6092 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6093 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6095 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6113 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6119 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6124 WREG32(RLC_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6130 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6136 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6142 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6143 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6145 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6178 WREG32(mc_cg_registers[i], data); in cik_enable_mc_ls()
6195 WREG32(mc_cg_registers[i], data); in cik_enable_mc_mgcg()
6205 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6206 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6211 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6216 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6229 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6234 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6239 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6244 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6261 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6270 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6305 WREG32(HDP_HOST_PATH_CNTL, data); in cik_enable_hdp_mgcg()
6321 WREG32(HDP_MEM_POWER_LS, data); in cik_enable_hdp_ls()
6409 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6423 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6436 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6449 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6549 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6554 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6559 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6564 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6620 WREG32(RLC_PG_AO_CU_MASK, tmp); in cik_init_ao_cu_mask()
6625 WREG32(RLC_MAX_PG_CU, tmp); in cik_init_ao_cu_mask()
6639 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_static_mgpg()
6653 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_dynamic_mgpg()
6665 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
6666 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6667 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6668 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6670 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
6672 WREG32(RLC_GPM_SCRATCH_DATA, 0); in cik_init_gfx_cgpg()
6675 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); in cik_init_gfx_cgpg()
6677 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); in cik_init_gfx_cgpg()
6683 WREG32(RLC_PG_CNTL, data); in cik_init_gfx_cgpg()
6685 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in cik_init_gfx_cgpg()
6686 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); in cik_init_gfx_cgpg()
6691 WREG32(CP_RB_WPTR_POLL_CNTL, data); in cik_init_gfx_cgpg()
6694 WREG32(RLC_PG_DELAY, data); in cik_init_gfx_cgpg()
6699 WREG32(RLC_PG_DELAY_2, data); in cik_init_gfx_cgpg()
6704 WREG32(RLC_AUTO_PG_CTRL, data); in cik_init_gfx_cgpg()
6867 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
6868 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6886 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
6887 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
6889 WREG32(IH_RB_RPTR, 0); in cik_disable_interrupts()
6890 WREG32(IH_RB_WPTR, 0); in cik_disable_interrupts()
6909 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
6912 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6914 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6916 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6917 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6918 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
6919 WREG32(CP_ME1_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
6920 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
6921 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
6922 WREG32(CP_ME2_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
6923 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
6925 WREG32(GRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
6927 WREG32(SRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
6929 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6930 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6932 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6933 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6936 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6937 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6941 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6942 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6945 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6946 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6949 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6950 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
6954 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in cik_disable_interrupt_state()
6958 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6960 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6962 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6964 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6966 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
6968 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7006 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7014 WREG32(INTERRUPT_CNTL, interrupt_cntl); in cik_irq_init()
7016 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7027 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in cik_irq_init()
7028 … WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in cik_irq_init()
7030 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
7033 WREG32(IH_RB_RPTR, 0); in cik_irq_init()
7034 WREG32(IH_RB_WPTR, 0); in cik_irq_init()
7041 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()
7203 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
7205 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7206 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
7208 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
7210 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in cik_irq_set()
7212 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()
7213 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7215 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7216 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7219 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7220 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7224 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set()
7226 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7230 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7232 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7236 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7238 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7242 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7243 WREG32(DC_HPD2_INT_CONTROL, hpd2); in cik_irq_set()
7244 WREG32(DC_HPD3_INT_CONTROL, hpd3); in cik_irq_set()
7245 WREG32(DC_HPD4_INT_CONTROL, hpd4); in cik_irq_set()
7246 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7247 WREG32(DC_HPD6_INT_CONTROL, hpd6); in cik_irq_set()
7294 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_ack()
7297 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7300 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7302 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7304 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7306 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7310 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7313 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7316 … WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7318 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7320 … WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7322 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7327 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7330 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7333 … WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7335 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7337 … WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7339 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7345 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7350 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7355 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7360 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7365 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7370 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7375 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7380 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7385 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7390 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7395 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7400 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7480 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
7867 WREG32(SRBM_INT_ACK, 0x1); in cik_irq_process()
8066 WREG32(IH_RB_RPTR, rptr); in cik_irq_process()
8770 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
8820 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
8823 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
9322 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9323 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9330 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9331 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9335 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); in dce8_program_watermarks()
9386 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in cik_get_gpu_clock_counter()