Lines Matching refs:getOpRegClass
404 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
408 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
2338 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
4895 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
5613 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
6604 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
6607 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
6610 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6614 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6644 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
8295 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
8444 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); in getDestEquivalentVGPRClass()
8458 const TargetRegisterClass *SrcRC = getOpRegClass(Inst, 1); in getDestEquivalentVGPRClass()