Lines Matching refs:instructions

46 @code{L32R} instructions in the text section.  Literals are grouped into
48 @code{ENTRY} instructions.  These options only affect literals referenced
49 via PC-relative @code{L32R} instructions; literals for absolute mode
50 @code{L32R} instructions are handled separately.
65 @code{L32R} instructions at the end.  These options only affect
66 literals referenced via PC-relative @code{L32R} instructions; literals
67 for absolute mode @code{L32R} instructions are handled separately.
75 Indicate to the assembler whether @code{L32R} instructions use absolute
87 that the assembler will always align instructions like @code{LOOP} that
93 Enable or disable transformation of call instructions to allow calls
104 Enable or disable all assembler transformations of Xtensa instructions,
107 rare cases when the instructions must be exactly as specified in the
119 Enable or disable transformation of jump instructions to allow jumps
160 FLIX instructions, which bundle multiple opcodes together in a single
228 versions behave as if the underscore carries through to the instructions
231 The underscore prefix only applies to individual instructions, not to
232 series of instructions.  For example, if a series of instructions have
234 instructions, but it may insert other instructions between them (e.g.,
236 modifying a series of instructions as a whole, use the
259 generation of density instructions where appropriate and automatic
269 @cindex density instructions
274 assembler automatically translates instructions from the core
275 Xtensa instruction set into equivalent instructions from the Xtensa code
282 It is a good idea @emph{not} to use the density instructions directly.
283 The assembler will automatically select dense instructions where
289 @cindex alignment of @code{LOOP} instructions
291 @cindex @code{LOOP} instructions, alignment
294 The Xtensa assembler will automatically align certain instructions, both
309 The target alignment optimization is done without adding instructions
311 density instructions in the code preceding a target, the assembler can
312 change the target alignment by widening some of those instructions to
313 the equivalent 24-bit instructions.  Extra bytes of padding can be
315 instructions.
319 The @code{LOOP} family of instructions must be aligned such that the
324 no-op instructions to satisfy it.  When no-op instructions are added,
329 fetch width when aligning @code{LOOP} instructions (except if the first
333 instructions to 4-byte boundaries, but that alignment is now the
343 instructions.  This process is known as @dfn{relaxation}.  This is
344 typically done for branch instructions because the distance of the
347 calls, @code{MOVI} instructions and other instructions with immediate
359 @cindex relaxation of branch instructions
360 @cindex branch instructions, relaxation
399 @cindex relaxation of call instructions
400 @cindex call instructions, relaxation
403 instructions (@code{CALL0}, @code{CALL4}, @code{CALL8} and
408 assembler can automatically relax immediate call instructions into
409 indirect call instructions.  This relaxation is done by loading the
443 @cindex relaxation of jump instructions
444 @cindex jump instructions, relaxation
533 @cindex @code{MOVI} instructions, relaxation
534 @cindex relaxation of @code{MOVI} instructions
537 materialized with @code{L32R} instructions.  Thus:
552 @cindex @code{L8UI} instructions, relaxation
553 @cindex @code{L16SI} instructions, relaxation
554 @cindex @code{L16UI} instructions, relaxation
555 @cindex @code{L32I} instructions, relaxation
556 @cindex relaxation of @code{L8UI} instructions
557 @cindex relaxation of @code{L16SI} instructions
558 @cindex relaxation of @code{L16UI} instructions
559 @cindex relaxation of @code{L32I} instructions
562 machine instructions can only be used with offsets from 0 to 510.  The
589 @cindex @code{ADDI} instructions, relaxation
590 @cindex relaxation of @code{ADDI} instructions
672 @code{no-transform} region both result in @code{ADD} machine instructions,
753 read-only 32-bit data accessed via @code{L32R} instructions.
776 @code{ENTRY} and @code{L32R} instructions; instead, the assembler puts
782 pools for PC-relative mode @code{L32R} instructions
787 pools are created automatically before @code{ENTRY} instructions and
790 @code{ENTRY} instructions, explicit @code{.literal_position} directives
797 PC-relative mode @code{L32R} instructions and @code{.lit4} for absolute
798 mode @code{L32R} instructions (@pxref{Absolute Literals Directive,
848 @code{L32R} instructions use the absolute addressing mode.
851 before @code{ENTRY} instructions, so the @code{.literal_position}
863 PC-relative @code{L32R} instructions).  The @code{.literal_position}
913 instructions.  These are relevant only for Xtensa configurations that
914 include the absolute addressing option for @code{L32R} instructions.
925 instructions and to place the literal values in the appropriate section.