364                     outb(FDC_RATE(ctlr), un->un_type->rate);   /* rate set */  in fd_check()
409           outb(FDC_DATA(ctlr), cmd);  in fdc_out()
459           outb(FDC_DOR(ctlr), DOR_RESET | DOR_DMAEN | unit  in motor_on()
468           outb(FDC_DOR(ctlr), DOR_RESET);                   /* reset & motor off */  in motor_off()
477           outb(FDC_DOR(ctlr), 0); /* fdc reset */  in fdReset()
479           outb(FDC_DOR(ctlr), DOR_RESET);  in fdReset()
656           outb(INT_CTL0, ICW1_AT);                /* ICW1 */  in irq_init()
657           outb(INT_CTL1, 0);                      /* ICW2 for master */  in irq_init()
658           outb(INT_CTL1, (1 << CASCADE_IRQ));     /* ICW3 tells slaves */  in irq_init()
659           outb(INT_CTL1, ICW4_AT);                /* ICW4 */  in irq_init()
661           outb(INT_CTL1, (INT_MASK = ~(1 << CASCADE_IRQ)));  in irq_init()
664           outb(INT2_CTL0, ICW1_AT);               /* ICW1 */  in irq_init()
665           outb(INT2_CTL1, 8);                               /* ICW2 for slave */  in irq_init()
666           outb(INT2_CTL1, CASCADE_IRQ);           /* ICW3 is slave nr */  in irq_init()
667           outb(INT2_CTL1, ICW4_AT);               /* ICW4 */  in irq_init()
669           outb(INT2_CTL1, (INT2_MASK = ~0));      /* IRQ 8-15 mask */  in irq_init()
685           outb(irc_no ? INT2_CTL1 : INT_CTL1, ~(1 << (irq_no >> (irc_no * 3))));  in irq_polling()
688                     outb(irc_no ? INT2_CTL0 : INT_CTL0, OCW3_PL);  in irq_polling()
701                     outb(INT2_CTL0, OCW2_CLEAR | (irq_no >> 3));  in irq_polling()
702                     outb(INT_CTL0, OCW2_CLEAR | CASCADE_IRQ);  in irq_polling()
704                     outb(INT_CTL0, OCW2_CLEAR | irq_no);  in irq_polling()
707           outb(INT_CTL1, INT_MASK);  in irq_polling()
708           outb(INT2_CTL1, INT2_MASK);  in irq_polling()
742           outb(DMA_RESET, 0);  in dma_setup()
744           outb(DMA_DEVCON, 0x00);  in dma_setup()
745           outb(DMA_INIT, DMA_RESET_VAL);          /* reset the dma controller */  in dma_setup()
747           outb(DMA_MODE, func == F_READ ? DMA_READ : DMA_WRITE);  in dma_setup()
748           outb(DMA_FLIPFLOP, 0);                  /* write anything to reset it */  in dma_setup()
750           outb(DMA_ADDR, (int)pbuf >>  0);  in dma_setup()
751           outb(DMA_ADDR, (int)pbuf >>  8);  in dma_setup()
752           outb(DMA_LTOP, (int)pbuf >> 16);  in dma_setup()
753           outb(DMA_HTOP, (int)pbuf >> 24);  in dma_setup()
755           outb(DMA_COUNT, (size - 1) >> 0);  in dma_setup()
756           outb(DMA_COUNT, (size - 1) >> 8);  in dma_setup()
757           outb(DMA_INIT, chan);                   /* some sort of enable */  in dma_setup()