Lines Matching refs:__BIT
104 #define WRX_ST_DD __BIT(0) /* descriptor done */
105 #define WRX_ST_EOP __BIT(1) /* end of packet */
106 #define WRX_ST_IXSM __BIT(2) /* ignore checksum indication */
107 #define WRX_ST_VP __BIT(3) /* VLAN packet */
108 #define WRX_ST_BPDU __BIT(4) /* ??? */
109 #define WRX_ST_TCPCS __BIT(5) /* TCP checksum performed */
110 #define WRX_ST_IPCS __BIT(6) /* IP checksum performed */
111 #define WRX_ST_PIF __BIT(7) /* passed in-exact filter */
114 #define WRX_ER_CE __BIT(0) /* CRC error */
115 #define WRX_ER_SE __BIT(1) /* symbol error */
116 #define WRX_ER_SEQ __BIT(2) /* sequence error */
117 #define WRX_ER_ICE __BIT(3) /* ??? */
118 #define WRX_ER_CXE __BIT(4) /* carrier extension error */
119 #define WRX_ER_TCPE __BIT(5) /* TCP checksum error */
120 #define WRX_ER_IPE __BIT(6) /* IP checksum error */
121 #define WRX_ER_RXE __BIT(7) /* Rx data error */
125 #define WRX_VLAN_CFI __BIT(12) /* Canonical Form Indicator */
147 #define EXTRXD_DD_MASK __BIT(0)
186 #define EXTRXC_ERROR_CE __BIT(4) /* The same as WRX_ER_CE. */
187 #define EXTRXC_ERROR_SE __BIT(5) /* The same as WRX_ER_SE. */
188 #define EXTRXC_ERROR_SEQ __BIT(6) /* The same as WRX_ER_SEQ. */
190 #define EXTRXC_ERROR_CXE __BIT(8) /* The same as WRX_ER_CXE. */
191 #define EXTRXC_ERROR_TCPE __BIT(9) /* The same as WRX_ER_TCPE. */
192 #define EXTRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */
193 #define EXTRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */
195 #define EXTRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */
196 #define EXTRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */
198 #define EXTRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */
199 #define EXTRXC_STATUS_UDPCS __BIT(4) /* UDP checksum calculated on packet. */
200 #define EXTRXC_STATUS_TCPCS __BIT(5) /* The same as WRX_ST_TCPCS. */
201 #define EXTRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */
203 #define EXTRXC_STATUS_TST __BIT(8) /* Time stamp taken. */
204 #define EXTRXC_STATUS_IPIDV __BIT(9) /* IP identification valid. */
205 #define EXTRXC_STATUS_UDPV __BIT(10) /* Valid UDP XSUM. */
207 #define EXTRXC_STATUS_ACK __BIT(15) /* ACK packet indication. */
231 #define NQRXD_A0_MASK __BIT(0)
232 #define NQRXD_NSE_MASK __BIT(0)
235 #define NQRXD_DD_MASK __BIT(0)
256 #define NQRXC_PKT_TYPE_ETQF_VALID_MASK __BIT(15)
257 #define NQRXC_PKT_TYPE_VLAN_MASK __BIT(16)
262 #define NQRXC_SPH_MASK __BIT(31)
288 #define NQRXC_PKT_TYPE_IPV4 __BIT(0)
289 #define NQRXC_PKT_TYPE_IPV4E __BIT(1)
290 #define NQRXC_PKT_TYPE_IPV6 __BIT(2)
291 #define NQRXC_PKT_TYPE_IPV6E __BIT(3)
292 #define NQRXC_PKT_TYPE_TCP __BIT(4)
293 #define NQRXC_PKT_TYPE_UDP __BIT(5)
294 #define NQRXC_PKT_TYPE_SCTP __BIT(6)
295 #define NQRXC_PKT_TYPE_NFS __BIT(7)
303 #define NQRXC_ERROR_HB0 __BIT(3) /* Header Buffer Overflow. */
306 #define NQRXC_ERROR_L4E __BIT(9) /* L4 error indication. */
307 #define NQRXC_ERROR_IPE __BIT(10) /* The same as WRX_ER_IPE. */
308 #define NQRXC_ERROR_RXE __BIT(11) /* The same as WRX_ER_RXE. */
311 #define NQRXC_STATUS_DD __BIT(0) /* The same as WRX_ST_DD. */
312 #define NQRXC_STATUS_EOP __BIT(1) /* The same as WRX_ST_EOP. */
314 #define NQRXC_STATUS_VP __BIT(3) /* The same as WRX_ST_VP. */
315 #define NQRXC_STATUS_UDPCS __BIT(4) /* UDP checksum or IP payload checksum. */
317 #define NQRXC_STATUS_L4I __BIT(5) /* L4 integrity check was done. */
318 #define NQRXC_STATUS_IPCS __BIT(6) /* The same as WRX_ST_IPCS. */
319 #define NQRXC_STATUS_PIF __BIT(7) /* The same as WRX_ST_PIF. */
321 #define NQRXC_STATUS_VEXT __BIT(9) /* First VLAN is found on a bouble VLAN packet. */
322 #define NQRXC_STATUS_UDPV __BIT(10) /* The packet contains a valid checksum field in a first fr…
323 #define NQRXC_STATUS_LLINT __BIT(11) /* The packet caused an immediate interrupt. */
324 #define NQRXC_STATUS_STRIPCRC __BIT(12) /* Ethernet CRC is stripped. */
326 #define NQRXC_STATUS_TSIP __BIT(15) /* Timestamp in packet. */
327 #define NQRXC_STATUS_TS __BIT(16) /* Time stamped packet. */
329 #define NQRXC_STATUS_LB __BIT(18) /* Sent by a local virtual machine (VM to VM swit…
330 #define NQRXC_STATUS_MC __BIT(19) /* Packet received from Manageability Controller …
351 #define WTX_CMD_EOP __BIT(24) /* end of packet */
352 #define WTX_CMD_IFCS __BIT(25) /* insert FCS */
353 #define WTX_CMD_RS __BIT(27) /* report status */
354 #define WTX_CMD_RPS __BIT(28) /* report packet sent */
355 #define WTX_CMD_DEXT __BIT(29) /* descriptor extension */
356 #define WTX_CMD_VLE __BIT(30) /* VLAN enable */
357 #define WTX_CMD_IDE __BIT(31) /* interrupt delay enable */
360 #define WTX_DTYP_MASK __BIT(20)
365 #define WTX_ST_DD __BIT(0) /* descriptor done */
366 #define WTX_ST_EC __BIT(1) /* excessive collisions */
367 #define WTX_ST_LC __BIT(2) /* late collision */
368 #define WTX_ST_TU __BIT(3) /* transmit underrun */
371 #define WTX_IXSM __BIT(0) /* IP checksum offload */
372 #define WTX_TXSM __BIT(1) /* TCP/UDP checksum offload */
388 #define WTX_TCPIP_CMD_TCP __BIT(24) /* 1 = TCP, 0 = UDP */
389 #define WTX_TCPIP_CMD_IP __BIT(25) /* 1 = IPv4, 0 = IPv6 */
390 #define WTX_TCPIP_CMD_TSE __BIT(26) /* segmentation context valid */
415 #define DESCRING_STATUS_FLUSH_REQ __BIT(8)
421 #define CTRL_FD __BIT(0) /* full duplex */
422 #define CTRL_BEM __BIT(1) /* big-endian mode */
423 #define CTRL_PRIOR __BIT(2) /* 0 = receive, 1 = fair */
424 #define CTRL_GIO_M_DIS __BIT(2) /* disabl PCI master access */
425 #define CTRL_LRST __BIT(3) /* link reset */
426 #define CTRL_ASDE __BIT(5) /* auto speed detect enable */
427 #define CTRL_SLU __BIT(6) /* set link up */
428 #define CTRL_ILOS __BIT(7) /* invert loss of signal */
434 #define CTRL_FRCSPD __BIT(11) /* force speed (Livengood) */
435 #define CTRL_FRCFDX __BIT(12) /* force full-duplex (Livengood) */
436 #define CTRL_D_UD_EN __BIT(13) /* Dock/Undock enable */
437 #define CTRL_D_UD_POL __BIT(14) /* Defined polarity of Dock/Undock indication in SDP[0] */
438 #define CTRL_F_PHY_R __BIT(15) /* Reset both PHY ports, through PHYRST_N pin */
439 #define CTRL_EXTLINK_EN __BIT(16) /* enable link status from external LINK_0 and LINK_1 pins …
440 #define CTRL_LANPHYPC_OVERRIDE __BIT(16) /* SW control of LANPHYPC */
441 #define CTRL_LANPHYPC_VALUE __BIT(17) /* SW value of LANPHYPC */
448 #define CTRL_MEHE __BIT(19) /* Memory Error Handling Enable(I217)*/
449 #define CTRL_RST __BIT(26) /* device reset */
450 #define CTRL_RFCE __BIT(27) /* Rx flow control enable */
451 #define CTRL_TFCE __BIT(28) /* Tx flow control enable */
452 #define CTRL_VME __BIT(30) /* VLAN Mode Enable */
453 #define CTRL_PHY_RESET __BIT(31) /* PHY reset (Cordova) */
458 #define STATUS_FD __BIT(0) /* full duplex */
459 #define STATUS_LU __BIT(1) /* link up */
460 #define STATUS_TCKOK __BIT(2) /* Tx clock running */
461 #define STATUS_RBCOK __BIT(3) /* Rx clock running */
464 #define STATUS_TXOFF __BIT(4) /* Tx paused */
465 #define STATUS_TBIMODE __BIT(5) /* fiber mode (Livengood) */
471 #define STATUS_LAN_INIT_DONE __BIT(9) /* Lan Init Completion by NVM */
472 #define STATUS_MTXCKOK __BIT(10) /* MTXD clock running */
473 #define STATUS_PHYRA __BIT(10) /* PHY Reset Asserted (PCH) */
474 #define STATUS_PCI66 __BIT(11) /* 66MHz bus (Livengood) */
475 #define STATUS_BUS64 __BIT(12) /* 64-bit bus (Livengood) */
476 #define STATUS_2P5_SKU __BIT(12) /* Value of the 2.5GBE SKU strap */
477 #define STATUS_PCIX_MODE __BIT(13) /* PCIX mode (Cordova) */
478 #define STATUS_2P5_SKU_OVER __BIT(13) /* Value of the 2.5GBE SKU override */
484 #define STATUS_GIO_M_ENA __BIT(19) /* GIO master enable */
485 #define STATUS_DEV_RST_SET __BIT(20) /* Device Reset Set */
494 #define EECD_SK __BIT(0) /* clock */
495 #define EECD_CS __BIT(1) /* chip select */
496 #define EECD_DI __BIT(2) /* data in */
497 #define EECD_DO __BIT(3) /* data out */
501 #define EECD_EE_REQ __BIT(6) /* (shared) EEPROM request */
502 #define EECD_EE_GNT __BIT(7) /* (shared) EEPROM grant */
503 #define EECD_EE_PRES __BIT(8) /* EEPROM present */
504 #define EECD_EE_SIZE __BIT(9) /* EEPROM size
506 #define EECD_EE_AUTORD __BIT(9) /* auto read done */
507 #define EECD_EE_ABITS __BIT(10) /* EEPROM address bits
510 #define EECD_EE_TYPE __BIT(13) /* EEPROM type
512 #define EECD_SEC1VAL __BIT(22) /* Sector One Valid */
516 #define FEXTNVM6_REQ_PLL_CLK __BIT(8)
517 #define FEXTNVM6_ENABLE_K1_ENTRY_CONDITION __BIT(9)
518 #define FEXTNVM6_K1_OFF_ENABLE __BIT(31)
527 #define CTRL_EXT_NSICR __BIT(0) /* Non Interrupt clear on read */
530 #define CTRL_EXT_LPCD __BIT(2) /* LCD Power Cycle Done */
540 #define CTRL_EXT_FORCE_SMBUS __BIT(11) /* Force SMBus mode */
541 #define CTRL_EXT_ASDCHK __BIT(12) /* ASD check */
542 #define CTRL_EXT_EE_RST __BIT(13) /* EEPROM reset */
543 #define CTRL_EXT_IPS __BIT(14) /* invert power state bit 0 */
544 #define CTRL_EXT_SPD_BYPS __BIT(15) /* speed select bypass */
545 #define CTRL_EXT_IPS1 __BIT(16) /* invert power state bit 1 */
546 #define CTRL_EXT_RO_DIS __BIT(17) /* relaxed ordering disabled */
547 #define CTRL_EXT_SDLPE __BIT(18) /* SerDes Low Power Enable */
548 #define CTRL_EXT_DMA_DYN_CLK __BIT(19) /* DMA Dynamic Gating Enable */
549 #define CTRL_EXT_PHYPDEN __BIT(20)
558 #define CTRL_EXT_EIAME __BIT(24) /* Extended Interrupt Auto Mask En */
561 #define CTRL_EXT_PBA __BIT(31) /* PBA Support */
573 #define MDIC_READY __BIT(28)
574 #define MDIC_I __BIT(29) /* interrupt on MDI complete */
575 #define MDIC_E __BIT(30) /* MDI error */
576 #define MDIC_DEST __BIT(31) /* Destination */
583 #define SCTL_CTL_READY __BIT(31)
598 #define FEXTNVM_SW_CONFIG __BIT(0) /* SW PHY Config En (ICH8 B0) */
599 #define FEXTNVM_SW_CONFIG_ICH8M __BIT(27) /* SW PHY Config En (>= ICH8 B1) */
646 #define CONNSW_AUTOSENSE_EN __BIT(0) /* Auto Sense Enable */
647 #define CONNSW_AUTOSENSE_CONF __BIT(1) /* Auto Sense Config Mode */
648 #define CONNSW_ENRGSRC __BIT(2) /* SerDes Energy Detect Src */
649 #define CONNSW_SERDESD __BIT(9) /* SerDes Signal Detect Ind. */
650 #define CONNSW_PHYSD __BIT(10) /* PHY Signal Detect Ind. */
651 #define CONNSW_PHY_PDN __BIT(11) /* Internal PHY in powerdown */
658 #define FEXTNVM3_PHY_CFG_COUNTER_50MS __BIT(27)
679 #define RAL_RDR1 __BIT(30) /* put packet in alt. rx ring */
680 #define RAL_AV __BIT(31) /* entry is valid */
691 #define ICR_TXDW __BIT(0) /* Tx desc written back */
692 #define ICR_TXQE __BIT(1) /* Tx queue empty */
693 #define ICR_LSC __BIT(2) /* link status change */
694 #define ICR_RXSEQ __BIT(3) /* receive sequence error */
695 #define ICR_RXDMT0 __BIT(4) /* Rx ring 0 nearly empty */
696 #define ICR_RXO __BIT(6) /* Rx overrun */
697 #define ICR_RXT0 __BIT(7) /* Rx ring 0 timer */
698 #define ICR_MDAC __BIT(9) /* MDIO access complete */
699 #define ICR_RXCFG __BIT(10) /* Receiving /C/ */
700 #define ICR_GPI(x) __BIT(11+(x)) /* general purpose interrupts */
701 #define ICR_RXQ(x) __BIT(20+(x)) /* 82574: Rx queue x interrupt x=0,1 */
702 #define ICR_TXQ(x) __BIT(22+(x)) /* 82574: Tx queue x interrupt x=0,1 */
703 #define ICR_OTHER __BIT(24) /* 82574: Other interrupt */
704 #define ICR_INT __BIT(31) /* device generated an interrupt */
724 #define FEXTNVM7_SIDE_CLK_UNGATE __BIT(2)
725 #define FEXTNVM7_DIS_SMB_PERST __BIT(5)
726 #define FEXTNVM7_DIS_PB_READ __BIT(18)
731 #define IVAR_VALID __BIT(7)
742 #define IVAR_VALID_82574 __BIT(3)
746 #define IVAR_INT_ON_ALL_WB __BIT(31)
753 #define SVCR_OFF_EN __BIT(0)
754 #define SVCR_OFF_MASKINT __BIT(12)
763 #define LTRV_SNOOP_REQ __BIT(15)
764 #define LTRV_SEND __BIT(30)
766 #define LTRV_NONSNOOP_REQ __BIT(31)
769 #define RCTL_EN __BIT(1) /* receiver enable */
770 #define RCTL_SBP __BIT(2) /* store bad packets */
771 #define RCTL_UPE __BIT(3) /* unicast promisc. enable */
772 #define RCTL_MPE __BIT(4) /* multicast promisc. enable */
773 #define RCTL_LPE __BIT(5) /* large packet enable */
788 #define RCTL_BAM __BIT(15) /* broadcast accept mode */
789 #define RCTL_RDMTS_HEX __BIT(16)
797 #define RCTL_DPF __BIT(22) /* discard pause frames */
798 #define RCTL_PMCF __BIT(23) /* pass MAC control frames */
799 #define RCTL_BSEX __BIT(25) /* buffer size extension (Livengood) */
800 #define RCTL_SECRC __BIT(26) /* strip Ethernet CRC */
804 #define RDTR_FPD __BIT(31) /* flush partial descriptor */
855 #define RXDCTL_GRAN __BIT(24) /* 0 = cacheline, 1 = descriptor */
883 #define TXCW_FD __BIT(5) /* Full Duplex */
884 #define TXCW_HD __BIT(6) /* Half Duplex */
885 #define TXCW_SYM_PAUSE __BIT(7) /* sym pause request */
886 #define TXCW_ASYM_PAUSE __BIT(8) /* asym pause request */
887 #define TXCW_TxConfig __BIT(30) /* Tx Config */
888 #define TXCW_ANE __BIT(31) /* Autonegotiate */
892 #define RXCW_NC __BIT(26) /* no carrier */
893 #define RXCW_IV __BIT(27) /* config invalid */
894 #define RXCW_CC __BIT(28) /* config change */
895 #define RXCW_C __BIT(29) /* /C/ reception */
896 #define RXCW_SYNCH __BIT(30) /* synchronized */
897 #define RXCW_ANC __BIT(31) /* autonegotiation complete */
903 #define TCTL_EN __BIT(1) /* transmitter enable */
904 #define TCTL_PSP __BIT(3) /* pad short packets */
907 #define TCTL_SWXOFF __BIT(22) /* software XOFF */
908 #define TCTL_RTLC __BIT(24) /* retransmit on late collision */
909 #define TCTL_NRTU __BIT(25) /* no retransmit on underrun */
910 #define TCTL_MULR __BIT(28) /* multiple request */
973 #define MDICNFG_COM_MDIO __BIT(30)
974 #define MDICNFG_DEST __BIT(31)
981 #define PHPM_SPD_EN __BIT(0) /* Smart Power Down */
982 #define PHPM_D0A_LPLU __BIT(1) /* D0 Low Power Link Up */
983 #define PHPM_NOND0A_LPLU __BIT(2) /* Non-D0a LPLU */
984 #define PHPM_NOND0A_GBE_DIS __BIT(3) /* Disable 1G in non-D0a */
985 #define PHPM_GO_LINK_D __BIT(5) /* Go Link Disconnect */
1078 #define GPIE_NSICR __BIT(0) /* Non Selective Interrupt Clear */
1079 #define GPIE_MULTI_MSIX __BIT(4) /* Multiple MSIX */
1080 #define GPIE_EIAME __BIT(30) /* Extended Interrupt Auto Mask Ena. */
1081 #define GPIE_PBA __BIT(31) /* PBA support */
1093 #define EITR_RX_QUEUE(x) __BIT(0+(x)) /* Rx Queue x Interrupt x=[0-3] */
1094 #define EITR_TX_QUEUE(x) __BIT(8+(x)) /* Tx Queue x Interrupt x=[0-3] */
1101 #define EITR_CNT_INGR __BIT(31) /* does not overwrite counter */
1116 #define TXDMAC_DPP __BIT(0) /* disable packet prefetch */
1133 #define TXDCTL_COUNT_DESC __BIT(22) /* Enable the counting of desc.
1250 #define PCS_CFG_PCS_EN __BIT(3)
1253 #define PCS_LCTL_FLV_LINK_UP __BIT(0) /* Forced Link Value */
1256 #define PCS_LCTL_FSV_100 __BIT(1) /* 100Mbps */
1257 #define PCS_LCTL_FSV_1000 __BIT(2) /* 1Gpbs */
1258 #define PCS_LCTL_FDV_FULL __BIT(3) /* Force Duplex Value */
1259 #define PCS_LCTL_FSD __BIT(4) /* Force Speed and Duplex */
1260 #define PCS_LCTL_FORCE_LINK __BIT(5) /* Force Link */
1261 #define PCS_LCTL_LINK_LATCH_LOW __BIT(6) /* Link Latch Low */
1262 #define PCS_LCTL_FORCE_FC __BIT(7) /* Force Flow Control */
1263 #define PCS_LCTL_AN_ENABLE __BIT(16) /* AN enable */
1264 #define PCS_LCTL_AN_RESTART __BIT(17) /* AN restart */
1265 #define PCS_LCTL_AN_TIMEOUT __BIT(18) /* AN Timeout Enable */
1266 #define PCS_LCTL_AN_SGMII_BYP __BIT(19) /* AN SGMII Bypass */
1267 #define PCS_LCTL_AN_SGMII_TRIG __BIT(20) /* AN SGMII Trigger */
1268 #define PCS_LCTL_FAST_LINKTIMER __BIT(24) /* Fast Link Timer */
1269 #define PCS_LCTL_LINK_OK_FIX_EN __BIT(25) /* Link OK Fix Enable */
1272 #define PCS_LSTS_LINKOK __BIT(0)
1277 #define PCS_LSTS_FDX __BIT(3)
1278 #define PCS_LSTS_AN_COMP __BIT(16)
1287 #define RXCSUM_IPOFL __BIT(8) /* IP checksum offload */
1288 #define RXCSUM_TUOFL __BIT(9) /* TCP/UDP checksum offload */
1289 #define RXCSUM_IPV6OFL __BIT(10) /* IPv6 checksum offload */
1290 #define RXCSUM_CRCOFL __BIT(11) /* SCTP CRC32 checksum offload */
1291 #define RXCSUM_IPPCSE __BIT(12) /* IP payload checksum enable */
1292 #define RXCSUM_PCSD __BIT(13) /* packet checksum disabled */
1297 #define WMREG_RFCTL_NFSWDIS __BIT(6) /* NFS Write Disable */
1298 #define WMREG_RFCTL_NFSRDIS __BIT(7) /* NFS Read Disable */
1299 #define WMREG_RFCTL_ACKDIS __BIT(12) /* ACK Accelerate Disable */
1300 #define WMREG_RFCTL_ACKD_DIS __BIT(13) /* ACK data Disable */
1301 #define WMREG_RFCTL_EXSTEN __BIT(15) /* Extended status Enable. 82574 only. */
1302 #define WMREG_RFCTL_IPV6EXDIS __BIT(16) /* IPv6 Extension Header Disable */
1303 #define WMREG_RFCTL_NEWIPV6EXDIS __BIT(17) /* New IPv6 Extension Header */
1313 #define WUFC_LNKC __BIT(0) /* Link Status Change Wakeup Enable */
1314 #define WUFC_MAG __BIT(1) /* Magic Packet Wakeup Enable */
1315 #define WUFC_EX __BIT(2) /* Directed Exact Wakeup Enable */
1316 #define WUFC_MC __BIT(3) /* Directed Multicast Wakeup En */
1317 #define WUFC_BC __BIT(4) /* Broadcast Wakeup Enable */
1318 #define WUFC_ARPDIR __BIT(5) /* ARP Request Packet Wakeup En */
1319 #define WUFC_IPV4 __BIT(6) /* Directed IPv4 Packet Wakeup En */
1320 #define WUFC_IPV6 __BIT(7) /* Directed IPv6 Packet Wakeup En */
1321 #define WUFC_NS __BIT(9) /* NS Wakeup En */
1322 #define WUFC_NSDIR __BIT(10) /* NS Directed En */
1323 #define WUFC_ARP __BIT(11) /* ARP request En */
1324 #define WUFC_FLEX_HQ __BIT(14) /* Flex Filters Host Queueing En */
1325 #define WUFC_NOTCO __BIT(15) /* ? */
1328 #define WUFC_FW_RST_WK __BIT(31) /* Wake on Firmware Reset Assert En */
1332 #define WUS_MNG __BIT(8) /* Manageability event */
1343 #define MRQC_ENABLE_RSS_MQ_82574 __BIT(0) /* enable RSS for 82574 */
1344 #define MRQC_ENABLE_RSS_MQ __BIT(1) /* enable hardware max RSS without VMDq */
1352 #define MRQC_DEFQ_NOT_RSS_FLT __SHFTIN(__BIT(1), MRQC_DEFQ_MASK)
1364 #define MRQC_DEFQ_IGNORED1 __SHFTIN(__BIT(2), MRQC_DEFQ_MASK)
1366 #define MRQC_DEFQ_IGNORED2 __SHFTIN(__BIT(2)|__BIT(0), MRQC_DEFQ_MASK)
1370 #define MRQC_RSS_FIELD_IPV4_TCP __BIT(16)
1371 #define MRQC_RSS_FIELD_IPV4 __BIT(17)
1372 #define MRQC_RSS_FIELD_IPV6_TCP_EX __BIT(18)
1373 #define MRQC_RSS_FIELD_IPV6_EX __BIT(19)
1374 #define MRQC_RSS_FIELD_IPV6 __BIT(20)
1375 #define MRQC_RSS_FIELD_IPV6_TCP __BIT(21)
1376 #define MRQC_RSS_FIELD_IPV4_UDP __BIT(22)
1377 #define MRQC_RSS_FIELD_IPV6_UDP __BIT(23)
1378 #define MRQC_RSS_FIELD_IPV6_UDP_EX __BIT(24)
1386 #define RETA_ENT_QINDEX_MASK_82574 __BIT(7) /*queue index for 82574 */
1392 #define MANC_SMBUS_EN __BIT(0)
1393 #define MANC_ASF_EN __BIT(1)
1394 #define MANC_ARP_EN __BIT(13)
1395 #define MANC_RECV_TCO_RESET __BIT(16)
1396 #define MANC_RECV_TCO_EN __BIT(17)
1397 #define MANC_BLK_PHY_RST_ON_IDE __BIT(18)
1398 #define MANC_RECV_ALL __BIT(19)
1399 #define MANC_EN_MAC_ADDR_FILTER __BIT(20)
1400 #define MANC_EN_MNG2HOST __BIT(21)
1401 #define MANC_EN_BMC2OS __BIT(28)
1441 #define H2ME_ULP __BIT(11)
1442 #define H2ME_ENFORCE_SETTINGS __BIT(12)
1448 #define FWSM_RSPCIPHY __BIT(6) /* Reset PHY on PCI reset */
1450 #define FWSM_ULP_CFG_DONE __BIT(10)
1451 #define FWSM_FW_VALID __BIT(15) /* FW established a valid mode */
1468 #define FEXTNVM9_IOSFSB_CLKGATE_DIS __BIT(11)
1469 #define FEXTNVM9_IOSFSB_CLKREQ_DIS __BIT(12)
1471 #define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */
1484 #define EEC_FLASH_DETECTED __BIT(19) /* FLASH */
1485 #define EEC_FLUPD __BIT(23) /* Update FLASH */
1541 #define NVM_CFG1_LVDID __BIT(0)
1542 #define NVM_CFG1_LSSID __BIT(1)
1543 #define NVM_CFG1_PME_CLOCK __BIT(2)
1544 #define NVM_CFG1_PM __BIT(3)
1545 #define NVM_CFG1_ILOS __BIT(4) /* Invert loss of signal */
1548 #define NVM_CFG1_IPS1 __BIT(8)
1549 #define NVM_CFG1_LRST __BIT(9)
1550 #define NVM_CFG1_FD __BIT(10)
1551 #define NVM_CFG1_FRCSPD __BIT(11)
1552 #define NVM_CFG1_IPS0 __BIT(12)
1553 #define NVM_CFG1_64_32_BAR __BIT(13)
1555 #define NVM_CFG2_CSR_RD_SPLIT __BIT(1)
1556 #define NVM_CFG2_82544_APM_EN __BIT(2)
1557 #define NVM_CFG2_64_BIT __BIT(3)
1558 #define NVM_CFG2_MAX_READ __BIT(4)
1559 #define NVM_CFG2_DMCR_MAP __BIT(5)
1560 #define NVM_CFG2_133_CAP __BIT(6)
1561 #define NVM_CFG2_MSI_DIS __BIT(7)
1562 #define NVM_CFG2_FLASH_DIS __BIT(8)
1564 #define NVM_CFG2_APM_EN __BIT(10)
1565 #define NVM_CFG2_ANE __BIT(11)
1567 #define NVM_CFG2_ASDE __BIT(14)
1568 #define NVM_CFG2_APM_PME __BIT(15)
1577 #define NVM_COMPAT_MAS_EN(x) __BIT(x) /* Media Auto Sense Enable */
1578 #define NVM_COMPAT_SERDES_FORCE_MODE __BIT(14) /* Don't use autonego */
1590 #define NVM_CFG3_PORTA_EXT_MDIO __BIT(2) /* External MDIO Interface */
1591 #define NVM_CFG3_PORTA_COM_MDIO __BIT(3) /* MDIO Interface is shared */
1592 #define NVM_CFG3_APME __BIT(10) /* APM Enable */
1593 #define NVM_CFG3_ILOS __BIT(13) /* Invert loss of signal */
1750 #define NQTX_CMD_EOP __BIT(24) /* end of packet */
1751 #define NQTX_CMD_IFCS __BIT(25) /* insert FCS */
1752 #define NQTX_CMD_RS __BIT(27) /* report status */
1753 #define NQTX_CMD_DEXT __BIT(29) /* descriptor extension */
1754 #define NQTX_CMD_VLE __BIT(30) /* VLAN enable */
1755 #define NQTX_CMD_TSE __BIT(31) /* TCP segmentation enable */
1766 #define NQTXD_FIELDS_IXSM __BIT(8) /* do IP checksum */
1767 #define NQTXD_FIELDS_TUXSM __BIT(9) /* do TCP/UDP checksum */
1778 #define NQTXC_CMD_SNAP __BIT(9)
1779 #define NQTXC_CMD_IPV_MASK __BIT(10)
1782 #define NQTXC_CMD_TP_MASK __BIT(11)