1 /*
2 * Definitions for low level routines and data structures
3 * for the Advanced Systems Inc. SCSI controllers chips.
4 *
5 * Copyright (c) 1998, 1999, 2000 Justin T. Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/dev/advansys/adwlib.h,v 1.4 2000/03/02 00:08:35 gibbs Exp $
33 * $DragonFly: src/sys/dev/disk/advansys/adwlib.h,v 1.4 2006/12/22 23:26:15 swildner Exp $
34 */
35 /*
36 * Ported from:
37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
38 *
39 * Copyright (c) 1995-1998 Advanced System Products, Inc.
40 * All Rights Reserved.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that redistributions of source
44 * code retain the above copyright notice and this comment without
45 * modification.
46 */
47
48 #ifndef _ADWLIB_H_
49 #define _ADWLIB_H_
50
51 #include "opt_adw.h"
52 #include "adwmcode.h"
53
54 #define ADW_DEF_MAX_HOST_QNG 253
55 #define ADW_DEF_MIN_HOST_QNG 16
56 #define ADW_DEF_MAX_DVC_QNG 63
57 #define ADW_DEF_MIN_DVC_QNG 4
58
59 #define ADW_MAX_TID 15
60 #define ADW_MAX_LUN 7
61
62 #define ADW_ALL_TARGETS 0xFFFF
63
64 #define ADW_TARGET_GROUP(tid) ((tid) & ~0x3)
65 #define ADW_TARGET_GROUP_SHIFT(tid) (((tid) & 0x3) * 4)
66 #define ADW_TARGET_GROUP_MASK(tid) (0xF << ADW_TARGET_GROUP_SHIFT(tid))
67
68 /*
69 * Board Register offsets.
70 */
71 #define ADW_INTR_STATUS_REG 0x0000
72 #define ADW_INTR_STATUS_INTRA 0x01
73 #define ADW_INTR_STATUS_INTRB 0x02
74 #define ADW_INTR_STATUS_INTRC 0x04
75 #define ADW_INTR_STATUS_INTRALL 0x07
76
77
78 #define ADW_SIGNATURE_WORD 0x0000
79 #define ADW_CHIP_ID_WORD 0x04C1
80
81 #define ADW_SIGNATURE_BYTE 0x0001
82 #define ADW_CHIP_ID_BYTE 0x25
83
84 #define ADW_INTR_ENABLES 0x0002 /*8 bit */
85 #define ADW_INTR_ENABLE_HOST_INTR 0x01
86 #define ADW_INTR_ENABLE_SEL_INTR 0x02
87 #define ADW_INTR_ENABLE_DPR_INTR 0x04
88 #define ADW_INTR_ENABLE_RTA_INTR 0x08
89 #define ADW_INTR_ENABLE_RMA_INTR 0x10
90 #define ADW_INTR_ENABLE_RST_INTR 0x20
91 #define ADW_INTR_ENABLE_DPE_INTR 0x40
92 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80
93
94 #define ADW_CTRL_REG 0x0002 /*16 bit*/
95 #define ADW_CTRL_REG_HOST_INTR 0x0100
96 #define ADW_CTRL_REG_SEL_INTR 0x0200
97 #define ADW_CTRL_REG_DPR_INTR 0x0400
98 #define ADW_CTRL_REG_RTA_INTR 0x0800
99 #define ADW_CTRL_REG_RMA_INTR 0x1000
100 #define ADW_CTRL_REG_RES_BIT14 0x2000
101 #define ADW_CTRL_REG_DPE_INTR 0x4000
102 #define ADW_CTRL_REG_POWER_DONE 0x8000
103 #define ADW_CTRL_REG_ANY_INTR 0xFF00
104 #define ADW_CTRL_REG_CMD_RESET 0x00C6
105 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5
106 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4
107 #define ADW_CTRL_REG_CMD_WR_PCI_CFG 0x00C3
108 #define ADW_CTRL_REG_CMD_RD_PCI_CFG 0x00C2
109
110 #define ADW_RAM_ADDR 0x0004
111 #define ADW_RAM_DATA 0x0006
112
113 #define ADW_RISC_CSR 0x000A
114 #define ADW_RISC_CSR_STOP 0x0000
115 #define ADW_RISC_TEST_COND 0x2000
116 #define ADW_RISC_CSR_RUN 0x4000
117 #define ADW_RISC_CSR_SINGLE_STEP 0x8000
118
119 #define ADW_SCSI_CFG0 0x000C
120 #define ADW_SCSI_CFG0_TIMER_MODEAB 0xC000 /*
121 * Watchdog, Second,
122 * and Selto timer CFG
123 */
124 #define ADW_SCSI_CFG0_PARITY_EN 0x2000
125 #define ADW_SCSI_CFG0_EVEN_PARITY 0x1000
126 #define ADW_SCSI_CFG0_WD_LONG 0x0800 /*
127 * Watchdog Interval,
128 * 1: 57 min, 0: 13 sec
129 */
130 #define ADW_SCSI_CFG0_QUEUE_128 0x0400 /*
131 * Queue Size,
132 * 1: 128 byte,
133 * 0: 64 byte
134 */
135 #define ADW_SCSI_CFG0_PRIM_MODE 0x0100
136 #define ADW_SCSI_CFG0_SCAM_EN 0x0080
137 #define ADW_SCSI_CFG0_SEL_TMO_LONG 0x0040 /*
138 * Sel/Resel Timeout,
139 * 1: 400 ms,
140 * 0: 1.6 ms
141 */
142 #define ADW_SCSI_CFG0_CFRM_ID 0x0020 /* SCAM id sel. */
143 #define ADW_SCSI_CFG0_OUR_ID_EN 0x0010
144 #define ADW_SCSI_CFG0_OUR_ID 0x000F
145
146
147 #define ADW_SCSI_CFG1 0x000E
148 #define ADW_SCSI_CFG1_BIG_ENDIAN 0x8000
149 #define ADW_SCSI_CFG1_TERM_POL 0x2000
150 #define ADW_SCSI_CFG1_SLEW_RATE 0x1000
151 #define ADW_SCSI_CFG1_FILTER_MASK 0x0C00
152 #define ADW_SCSI_CFG1_FLTR_DISABLE 0x0000
153 #define ADW_SCSI_CFG1_FLTR_11_TO_20NS 0x0800
154 #define ADW_SCSI_CFG1_FLTR_21_TO_39NS 0x0C00
155 #define ADW_SCSI_CFG1_DIS_ACTIVE_NEG 0x0200
156 #define ADW_SCSI_CFG1_DIFF_MODE 0x0100
157 #define ADW_SCSI_CFG1_DIFF_SENSE 0x0080
158 #define ADW_SCSI_CFG1_TERM_CTL_MANUAL 0x0040 /* Global Term Switch */
159 #define ADW_SCSI_CFG1_TERM_CTL_MASK 0x0030
160 #define ADW_SCSI_CFG1_TERM_CTL_H 0x0020 /* Enable SCSI-H */
161 #define ADW_SCSI_CFG1_TERM_CTL_L 0x0010 /* Enable SCSI-L */
162 #define ADW_SCSI_CFG1_CABLE_DETECT 0x000F
163 #define ADW_SCSI_CFG1_EXT16_MASK 0x0008 /* Ext16 cable pres */
164 #define ADW_SCSI_CFG1_EXT8_MASK 0x0004 /* Ext8 cable pres */
165 #define ADW_SCSI_CFG1_INT8_MASK 0x0002 /* Int8 cable pres */
166 #define ADW_SCSI_CFG1_INT16_MASK 0x0001 /* Int16 cable pres */
167 #define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK \
168 (ADW_SCSI_CFG1_EXT16_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
169 #define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \
170 (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
171
172 /*
173 * Addendum for ASC-38C0800 Chip
174 */
175 #define ADW2_SCSI_CFG1_DIS_TERM_DRV 0x4000 /*
176 * The Terminators
177 * must be disabled
178 * in order to detect
179 * cable presence
180 */
181
182 #define ADW2_SCSI_CFG1_DEV_DETECT 0x1C00
183 #define ADW2_SCSI_CFG1_DEV_DETECT_HVD 0x1000
184 #define ADW2_SCSI_CFG1_DEV_DETECT_LVD 0x0800
185 #define ADW2_SCSI_CFG1_DEV_DETECT_SE 0x0400
186
187 #define ADW2_SCSI_CFG1_TERM_CTL_LVD 0x00C0 /* Ultra2 Only */
188 #define ADW2_SCSI_CFG1_TERM_LVD_HI 0x0080
189 #define ADW2_SCSI_CFG1_TERM_LVD_LO 0x0040
190 #define ADW2_SCSI_CFG1_EXTLVD_MASK 0x0008 /* ExtLVD cable pres */
191 #define ADW2_SCSI_CFG1_INTLVD_MASK 0x0004 /* IntLVD cable pres */
192
193 #define ADW_MEM_CFG 0x0010
194 #define ADW_MEM_CFG_BIOS_EN 0x40
195 #define ADW_MEM_CFG_FAST_EE_CLK 0x20 /* Diagnostic Bit */
196 #define ADW_MEM_CFG_RAM_SZ_MASK 0x1C /* RISC RAM Size */
197 #define ADW_MEM_CFG_RAM_SZ_2KB 0x00
198 #define ADW_MEM_CFG_RAM_SZ_4KB 0x04
199 #define ADW_MEM_CFG_RAM_SZ_8KB 0x08
200 #define ADW_MEM_CFG_RAM_SZ_16KB 0x0C
201 #define ADW_MEM_CFG_RAM_SZ_32KB 0x10
202 #define ADW_MEM_CFG_RAM_SZ_64KB 0x14
203
204 #define ADW_GPIO_CNTL 0x0011
205 #define ADW_GPIO_DATA 0x0012
206
207 #define ADW_COMMA 0x0014
208 #define ADW_COMMB 0x0018
209
210 #define ADW_EEP_CMD 0x001A
211 #define ADW_EEP_CMD_READ 0x0080 /* or in address */
212 #define ADW_EEP_CMD_WRITE 0x0040 /* or in address */
213 #define ADW_EEP_CMD_WRITE_ABLE 0x0030
214 #define ADW_EEP_CMD_WRITE_DISABLE 0x0000
215 #define ADW_EEP_CMD_DONE 0x0200
216 #define ADW_EEP_CMD_DONE_ERR 0x0001
217 #define ADW_EEP_DELAY_MS 100
218
219 #define ADW_EEP_DATA 0x001C
220
221 #define ADW_DMA_CFG0 0x0020
222 #define ADW_DMA_CFG0_BC_THRESH_ENB 0x80
223 #define ADW_DMA_CFG0_FIFO_THRESH 0x70
224 #define ADW_DMA_CFG0_FIFO_THRESH_16B 0x00
225 #define ADW_DMA_CFG0_FIFO_THRESH_32B 0x20
226 #define ADW_DMA_CFG0_FIFO_THRESH_48B 0x30
227 #define ADW_DMA_CFG0_FIFO_THRESH_64B 0x40
228 #define ADW_DMA_CFG0_FIFO_THRESH_80B 0x50
229 #define ADW_DMA_CFG0_FIFO_THRESH_96B 0x60
230 #define ADW_DMA_CFG0_FIFO_THRESH_112B 0x70
231 #define ADW_DMA_CFG0_START_CTL_MASK 0x0C
232 #define ADW_DMA_CFG0_START_CTL_TH 0x00 /* Start on thresh */
233 #define ADW_DMA_CFG0_START_CTL_IDLE 0x04 /* Start when idle */
234 #define ADW_DMA_CFG0_START_CTL_TH_IDLE 0x08 /* Either */
235 #define ADW_DMA_CFG0_START_CTL_EM_FU 0x0C /* Start on full/empty */
236 #define ADW_DMA_CFG0_READ_CMD_MASK 0x03
237 #define ADW_DMA_CFG0_READ_CMD_MR 0x00
238 #define ADW_DMA_CFG0_READ_CMD_MRL 0x02
239 #define ADW_DMA_CFG0_READ_CMD_MRM 0x03
240
241 #define ADW_TICKLE 0x0022
242 #define ADW_TICKLE_NOP 0x00
243 #define ADW_TICKLE_A 0x01
244 #define ADW_TICKLE_B 0x02
245 #define ADW_TICKLE_C 0x03
246
247 /* Program Counter */
248 #define ADW_PC 0x2A
249
250 #define ADW_SCSI_CTRL 0x0034
251 #define ADW_SCSI_CTRL_RSTOUT 0x2000
252
253 /*
254 * ASC-38C0800 RAM BIST Register bit definitions
255 */
256 #define ADW_RAM_BIST 0x0038
257 #define ADW_RAM_BIST_RAM_TEST_MODE 0x80
258 #define ADW_RAM_BIST_PRE_TEST_MODE 0x40
259 #define ADW_RAM_BIST_NORMAL_MODE 0x00
260 #define ADW_RAM_BIST_RAM_TEST_DONE 0x10
261 #define ADW_RAM_BIST_RAM_TEST_STATUS 0x0F
262 #define ADW_RAM_BIST_RAM_TEST_HOST_ERR 0x08
263 #define ADW_RAM_BIST_RAM_TEST_RAM_ERR 0x04
264 #define ADW_RAM_BIST_RAM_TEST_RISC_ERR 0x02
265 #define ADW_RAM_BIST_RAM_TEST_SCSI_ERR 0x01
266 #define ADW_RAM_BIST_RAM_TEST_SUCCESS 0x00
267 #define ADW_RAM_BIST_PRE_TEST_VALUE 0x05
268 #define ADW_RAM_BIST_NORMAL_VALUE 0x00
269 #define ADW_PLL_TEST 0x0039
270
271 #define ADW_SCSI_RESET_HOLD_TIME_US 60
272
273 /* LRAM Constants */
274 #define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
275 #define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */
276
277 #define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
278 #define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
279
280 #define ADW_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
281 #define ADW_38C1600_IOLEN 0x100 /* I/O Port Range in bytes */
282 #define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB */
283
284 #define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
285 #define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
286
287 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
288 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
289 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
290 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
291 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
292
293 /* ====================== SCSI Request Structures =========================== */
294
295 #define ADW_NO_OF_SG_PER_BLOCK 15
296
297 /*
298 * Although the adapter can deal with S/G lists of indefinite size,
299 * we limit the list to 30 to conserve space as the kernel can only send
300 * us buffers of at most 64KB currently.
301 */
302 #define ADW_SG_BLOCKCNT 2
303 #define ADW_SGSIZE (ADW_NO_OF_SG_PER_BLOCK * ADW_SG_BLOCKCNT)
304
305 struct adw_sg_elm {
306 u_int32_t sg_addr;
307 u_int32_t sg_count;
308 };
309
310 /* sg block structure used by the microcode */
311 struct adw_sg_block {
312 u_int8_t reserved1;
313 u_int8_t reserved2;
314 u_int8_t reserved3;
315 u_int8_t sg_cnt; /* Valid entries in this block */
316 u_int32_t sg_busaddr_next; /* link to the next sg block */
317 struct adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
318 };
319
320 /* Structure representing a single allocation block of adw sg blocks */
321 struct sg_map_node {
322 bus_dmamap_t sg_dmamap;
323 bus_addr_t sg_physaddr;
324 struct adw_sg_block* sg_vaddr;
325 SLIST_ENTRY(sg_map_node) links;
326 };
327
328 typedef enum {
329 QHSTA_NO_ERROR = 0x00,
330 QHSTA_M_SEL_TIMEOUT = 0x11,
331 QHSTA_M_DATA_OVER_RUN = 0x12,
332 QHSTA_M_UNEXPECTED_BUS_FREE = 0x13,
333 QHSTA_M_QUEUE_ABORTED = 0x15,
334 QHSTA_M_SXFR_SDMA_ERR = 0x16, /* SCSI DMA Error */
335 QHSTA_M_SXFR_SXFR_PERR = 0x17, /* SCSI Bus Parity Error */
336 QHSTA_M_RDMA_PERR = 0x18, /* RISC PCI DMA parity error */
337 QHSTA_M_SXFR_OFF_UFLW = 0x19, /* Offset Underflow */
338 QHSTA_M_SXFR_OFF_OFLW = 0x20, /* Offset Overflow */
339 QHSTA_M_SXFR_WD_TMO = 0x21, /* Watchdog Timeout */
340 QHSTA_M_SXFR_DESELECTED = 0x22, /* Deselected */
341 QHSTA_M_SXFR_XFR_PH_ERR = 0x24, /* Transfer Phase Error */
342 QHSTA_M_SXFR_UNKNOWN_ERROR = 0x25, /* SXFR_STATUS Unknown Error */
343 QHSTA_M_SCSI_BUS_RESET = 0x30, /* Request aborted from SBR */
344 QHSTA_M_SCSI_BUS_RESET_UNSOL= 0x31, /* Request aborted from unsol. SBR*/
345 QHSTA_M_BUS_DEVICE_RESET = 0x32, /* Request aborted from BDR */
346 QHSTA_M_DIRECTION_ERR = 0x35, /* Data Phase mismatch */
347 QHSTA_M_DIRECTION_ERR_HUNG = 0x36, /* Data Phase mismatch - bus hang */
348 QHSTA_M_WTM_TIMEOUT = 0x41,
349 QHSTA_M_BAD_CMPL_STATUS_IN = 0x42,
350 QHSTA_M_NO_AUTO_REQ_SENSE = 0x43,
351 QHSTA_M_AUTO_REQ_SENSE_FAIL = 0x44,
352 QHSTA_M_INVALID_DEVICE = 0x45, /* Bad target ID */
353 QHSTA_M_FROZEN_TIDQ = 0x46, /* TID Queue frozen. */
354 QHSTA_M_SGBACKUP_ERROR = 0x47 /* Scatter-Gather backup error */
355 } host_status_t;
356
357 typedef enum {
358 QD_NO_STATUS = 0x00, /* Request not completed yet. */
359 QD_NO_ERROR = 0x01,
360 QD_ABORTED_BY_HOST = 0x02,
361 QD_WITH_ERROR = 0x04
362 } done_status_t;
363
364 /*
365 * Microcode request structure
366 *
367 * All fields in this structure are used by the microcode so their
368 * size and ordering cannot be changed.
369 */
370 struct adw_scsi_req_q {
371 u_int8_t cntl; /* Ucode flags and state. */
372 u_int8_t target_cmd;
373 u_int8_t target_id; /* Device target identifier. */
374 u_int8_t target_lun; /* Device target logical unit number. */
375 u_int32_t data_addr; /* Data buffer physical address. */
376 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
377 u_int32_t sense_baddr; /* Sense buffer bus address. */
378 u_int32_t carrier_baddr; /* Carrier bus address. */
379 u_int8_t mflag; /* microcode flag field. */
380 u_int8_t sense_len; /* Auto-sense length. Residual on complete. */
381 u_int8_t cdb_len; /* SCSI CDB length. */
382 u_int8_t scsi_cntl; /* SCSI command control flags (tags, nego) */
383 #define ADW_QSC_NO_DISC 0x01
384 #define ADW_QSC_NO_TAGMSG 0x02
385 #define ADW_QSC_NO_SYNC 0x04
386 #define ADW_QSC_NO_WIDE 0x08
387 #define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR */
388 #define ADW_QSC_SIMPLE_Q_TAG 0x00
389 #define ADW_QSC_HEAD_OF_Q_TAG 0x40
390 #define ADW_QSC_ORDERED_Q_TAG 0x80
391 u_int8_t done_status; /* Completion status. */
392 u_int8_t scsi_status; /* SCSI status byte. */
393 u_int8_t host_status; /* Ucode host status. */
394 u_int8_t sg_wk_ix; /* Microcode working SG index. */
395 u_int8_t cdb[12]; /* SCSI command block. */
396 u_int32_t sg_real_addr; /* SG list physical address. */
397 u_int32_t scsi_req_baddr; /* Bus address of this structure. */
398 u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */
399 /*
400 * The 'tokens' placed in these two fields are
401 * used to identify the scsi request and the next
402 * carrier in the response queue, *not* physical
403 * addresses. This driver uses byte offsets for
404 * portability and speed of mapping back to either
405 * a virtual or physical address.
406 */
407 u_int32_t scsi_req_bo; /* byte offset of this structure */
408 u_int32_t carrier_bo; /* byte offst of our carrier. */
409 };
410
411 typedef enum {
412 ACB_FREE = 0x00,
413 ACB_ACTIVE = 0x01,
414 ACB_RELEASE_SIMQ = 0x02,
415 ACB_RECOVERY_ACB = 0x04
416 } acb_state;
417
418 struct acb {
419 struct adw_scsi_req_q queue;
420 bus_dmamap_t dmamap;
421 acb_state state;
422 union ccb *ccb;
423 struct adw_sg_block* sg_blocks;
424 bus_addr_t sg_busaddr;
425 struct scsi_sense_data sense_data;
426 SLIST_ENTRY(acb) links;
427 };
428
429 /*
430 * EEPROM configuration format
431 *
432 * Field naming convention:
433 *
434 * *_enable indicates the field enables or disables the feature. The
435 * value is never reset.
436 *
437 * *_able indicates both whether a feature should be enabled or disabled
438 * and whether a device is capable of the feature. At initialization
439 * this field may be set, but later if a device is found to be incapable
440 * of the feature, the field is cleared.
441 *
442 * Default values are maintained in a_init.c in the structure
443 * Default_EEPROM_Config.
444 */
445 struct adw_eeprom
446 {
447 u_int16_t cfg_lsw; /* 00 power up initialization */
448 #define ADW_EEPROM_BIG_ENDIAN 0x8000
449 #define ADW_EEPROM_BIOS_ENABLE 0x4000
450 #define ADW_EEPROM_TERM_POL 0x2000
451 #define ADW_EEPROM_CIS_LD 0x1000
452
453 /* bit 13 set - Term Polarity Control */
454 /* bit 14 set - BIOS Enable */
455 /* bit 15 set - Big Endian Mode */
456 u_int16_t cfg_msw; /* unused */
457 u_int16_t disc_enable;
458 u_int16_t wdtr_able;
459 union {
460 /*
461 * sync enable bits for UW cards,
462 * actual sync rate for TID 0-3
463 * on U2W and U160 cards.
464 */
465 u_int16_t sync_enable;
466 u_int16_t sdtr1;
467 } sync1;
468 u_int16_t start_motor;
469 u_int16_t tagqng_able;
470 u_int16_t bios_scan;
471 u_int16_t scam_tolerant;
472
473 u_int8_t adapter_scsi_id;
474 u_int8_t bios_boot_delay;
475
476 u_int8_t scsi_reset_delay;
477 u_int8_t bios_id_lun; /* high nibble is lun */
478 /* low nibble is scsi id */
479
480 u_int8_t termination_se; /* 0 - automatic */
481 #define ADW_EEPROM_TERM_AUTO 0
482 #define ADW_EEPROM_TERM_OFF 1
483 #define ADW_EEPROM_TERM_HIGH_ON 2
484 #define ADW_EEPROM_TERM_BOTH_ON 3
485
486 u_int8_t termination_lvd;
487 u_int16_t bios_ctrl;
488 #define ADW_BIOS_INIT_DIS 0x0001 /* Don't act as initiator */
489 #define ADW_BIOS_EXT_TRANS 0x0002 /* > 1 GB support */
490 #define ADW_BIOS_MORE_2DISK 0x0004 /* > 1 GB support */
491 #define ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */
492 #define ADW_BIOS_CD_BOOT 0x0010 /* support bootable CD */
493 #define ADW_BIOS_SCAN_EN 0x0020 /* BIOS SCAN enabled */
494 #define ADW_BIOS_MULTI_LUN 0x0040 /* probe luns */
495 #define ADW_BIOS_MESSAGE 0x0080 /* display BIOS message */
496 #define ADW_BIOS_RESET_BUS 0x0200 /* reset SCSI bus durint init */
497 #define ADW_BIOS_QUIET 0x0800 /* No verbose initialization */
498 #define ADW_BIOS_SCSI_PAR_EN 0x1000 /* SCSI parity enabled */
499
500 union {
501 /* 13
502 * ultra enable bits for UW cards,
503 * actual sync rate for TID 4-7
504 * on U2W and U160 cards.
505 */
506 u_int16_t ultra_enable;
507 u_int16_t sdtr2;
508 } sync2;
509 union {
510 /* 14
511 * reserved for UW cards,
512 * actual sync rate for TID 8-11
513 * on U2W and U160 cards.
514 */
515 u_int16_t reserved;
516 u_int16_t sdtr3;
517 } sync3;
518 u_int8_t max_host_qng; /* 15 maximum host queuing */
519 u_int8_t max_dvc_qng; /* maximum per device queuing */
520 u_int16_t dvc_cntl; /* 16 control bit for driver */
521 union {
522 /* 17
523 * reserved for UW cards,
524 * actual sync rate for TID 12-15
525 * on U2W and U160 cards.
526 */
527 u_int16_t reserved;
528 u_int16_t sdtr4;
529 } sync4;
530 u_int16_t serial_number[3]; /* 18-20 */
531 u_int16_t checksum; /* 21 */
532 u_int8_t oem_name[16]; /* 22 - 29 */
533 u_int16_t dvc_err_code; /* 30 */
534 u_int16_t adv_err_code; /* 31 */
535 u_int16_t adv_err_addr; /* 32 */
536 u_int16_t saved_dvc_err_code; /* 33 */
537 u_int16_t saved_adv_err_code; /* 34 */
538 u_int16_t saved_adv_err_addr; /* 35 */
539 u_int16_t reserved[20]; /* 36 - 55 */
540 u_int16_t cisptr_lsw; /* 56 CIS data */
541 u_int16_t cisptr_msw; /* 57 CIS data */
542 u_int32_t subid; /* 58-59 SubSystem Vendor/Dev ID */
543 u_int16_t reserved2[4];
544 };
545
546 /* EEProm Addresses */
547 #define ADW_EEP_DVC_CFG_BEGIN 0x00
548 #define ADW_EEP_DVC_CFG_END (offsetof(struct adw_eeprom, checksum)/2)
549 #define ADW_EEP_DVC_CTL_BEGIN (offsetof(struct adw_eeprom, oem_name)/2)
550 #define ADW_EEP_MAX_WORD_ADDR (sizeof(struct adw_eeprom)/2)
551
552 #define ADW_BUS_RESET_HOLD_DELAY_US 100
553
554 typedef enum {
555 ADW_CHIP_NONE,
556 ADW_CHIP_ASC3550, /* Ultra-Wide IC */
557 ADW_CHIP_ASC38C0800, /* Ultra2-Wide/LVD IC */
558 ADW_CHIP_ASC38C1600 /* Ultra3-Wide/LVD2 IC */
559 } adw_chip;
560
561 typedef enum {
562 ADW_FENONE = 0x0000,
563 ADW_ULTRA = 0x0001, /* Supports 20MHz Transfers */
564 ADW_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
565 ADW_DT = 0x0004, /* Supports Double Transistion REQ/ACK*/
566 ADW_WIDE = 0x0008, /* Wide Channel */
567 ADW_ASC3550_FE = ADW_ULTRA,
568 ADW_ASC38C0800_FE = ADW_ULTRA2,
569 ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT
570 } adw_feature;
571
572 typedef enum {
573 ADW_FNONE = 0x0000,
574 ADW_EEPROM_FAILED = 0x0001
575 } adw_flag;
576
577 typedef enum {
578 ADW_STATE_NORMAL = 0x00,
579 ADW_RESOURCE_SHORTAGE = 0x01
580 } adw_state;
581
582 typedef enum {
583 ADW_MC_SDTR_ASYNC,
584 ADW_MC_SDTR_5,
585 ADW_MC_SDTR_10,
586 ADW_MC_SDTR_20,
587 ADW_MC_SDTR_40,
588 ADW_MC_SDTR_80
589 } adw_mc_sdtr;
590
591 struct adw_syncrate
592 {
593 adw_mc_sdtr mc_sdtr;
594 u_int8_t period;
595 char *rate;
596 };
597
598 /* We have an input and output queue for our carrier structures */
599 #define ADW_OUTPUT_QUEUE 0 /* Offset into carriers member */
600 #define ADW_INPUT_QUEUE 1 /* Offset into carriers member */
601 #define ADW_NUM_CARRIER_QUEUES 2
602 struct adw_softc
603 {
604 bus_space_tag_t tag;
605 bus_space_handle_t bsh;
606 adw_state state;
607 bus_dma_tag_t buffer_dmat;
608 struct acb *acbs;
609 struct adw_carrier *carriers;
610 struct adw_carrier *free_carriers;
611 struct adw_carrier *commandq;
612 struct adw_carrier *responseq;
613 LIST_HEAD(, ccb_hdr) pending_ccbs;
614 SLIST_HEAD(, acb) free_acb_list;
615 bus_dma_tag_t parent_dmat;
616 bus_dma_tag_t carrier_dmat; /* dmat for our acb carriers*/
617 bus_dmamap_t carrier_dmamap;
618 bus_dma_tag_t acb_dmat; /* dmat for our ccb array */
619 bus_dmamap_t acb_dmamap;
620 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
621 SLIST_HEAD(, sg_map_node) sg_maps;
622 bus_addr_t acb_busbase;
623 bus_addr_t carrier_busbase;
624 adw_chip chip;
625 adw_feature features;
626 adw_flag flags;
627 u_int memsize;
628 char channel;
629 struct cam_path *path;
630 struct cam_sim *sim;
631 struct resource *regs;
632 struct resource *irq;
633 void *ih;
634 const struct adw_mcode *mcode_data;
635 const struct adw_eeprom *default_eeprom;
636 device_t device;
637 int regs_res_type;
638 int regs_res_id;
639 int irq_res_type;
640 u_int max_acbs;
641 u_int num_acbs;
642 u_int initiator_id;
643 u_int init_level;
644 u_int unit;
645 char* name;
646 cam_status last_reset; /* Last reset type */
647 u_int16_t bios_ctrl;
648 u_int16_t user_wdtr;
649 u_int16_t user_sdtr[4]; /* A nibble per-device */
650 u_int16_t user_tagenb;
651 u_int16_t tagenb;
652 u_int16_t user_discenb;
653 u_int16_t serial_number[3];
654 };
655
656 extern const struct adw_eeprom adw_asc3550_default_eeprom;
657 extern const struct adw_eeprom adw_asc38C0800_default_eeprom;
658 extern const struct adw_syncrate adw_syncrates[];
659 extern const int adw_num_syncrates;
660
661 #define adw_inb(adw, port) \
662 bus_space_read_1((adw)->tag, (adw)->bsh, port)
663 #define adw_inw(adw, port) \
664 bus_space_read_2((adw)->tag, (adw)->bsh, port)
665 #define adw_inl(adw, port) \
666 bus_space_read_4((adw)->tag, (adw)->bsh, port)
667
668 #define adw_outb(adw, port, value) \
669 bus_space_write_1((adw)->tag, (adw)->bsh, port, value)
670 #define adw_outw(adw, port, value) \
671 bus_space_write_2((adw)->tag, (adw)->bsh, port, value)
672 #define adw_outl(adw, port, value) \
673 bus_space_write_4((adw)->tag, (adw)->bsh, port, value)
674
675 #define adw_set_multi_2(adw, port, value, count) \
676 bus_space_set_multi_2((adw)->tag, (adw)->bsh, port, value, count)
677
678 static __inline const char* adw_name(struct adw_softc *adw);
679 static __inline u_int adw_lram_read_8(struct adw_softc *adw, u_int addr);
680 static __inline u_int adw_lram_read_16(struct adw_softc *adw, u_int addr);
681 static __inline u_int adw_lram_read_32(struct adw_softc *adw, u_int addr);
682 static __inline void adw_lram_write_8(struct adw_softc *adw, u_int addr,
683 u_int value);
684 static __inline void adw_lram_write_16(struct adw_softc *adw, u_int addr,
685 u_int value);
686 static __inline void adw_lram_write_32(struct adw_softc *adw, u_int addr,
687 u_int value);
688
689 static __inline u_int32_t acbvtobo(struct adw_softc *adw,
690 struct acb *acb);
691 static __inline u_int32_t acbvtob(struct adw_softc *adw,
692 struct acb *acb);
693 static __inline struct acb * acbbotov(struct adw_softc *adw,
694 u_int32_t busaddr);
695 static __inline struct acb * acbbtov(struct adw_softc *adw,
696 u_int32_t busaddr);
697 static __inline u_int32_t carriervtobo(struct adw_softc *adw,
698 struct adw_carrier *carrier);
699 static __inline u_int32_t carriervtob(struct adw_softc *adw,
700 struct adw_carrier *carrier);
701 static __inline struct adw_carrier *
702 carrierbotov(struct adw_softc *adw,
703 u_int32_t byte_offset);
704 static __inline struct adw_carrier *
705 carrierbtov(struct adw_softc *adw,
706 u_int32_t baddr);
707
708 static __inline const char*
adw_name(struct adw_softc * adw)709 adw_name(struct adw_softc *adw)
710 {
711 return (adw->name);
712 }
713
714 static __inline u_int
adw_lram_read_8(struct adw_softc * adw,u_int addr)715 adw_lram_read_8(struct adw_softc *adw, u_int addr)
716 {
717 adw_outw(adw, ADW_RAM_ADDR, addr);
718 return (adw_inb(adw, ADW_RAM_DATA));
719 }
720
721 static __inline u_int
adw_lram_read_16(struct adw_softc * adw,u_int addr)722 adw_lram_read_16(struct adw_softc *adw, u_int addr)
723 {
724 adw_outw(adw, ADW_RAM_ADDR, addr);
725 return (adw_inw(adw, ADW_RAM_DATA));
726 }
727
728 static __inline u_int
adw_lram_read_32(struct adw_softc * adw,u_int addr)729 adw_lram_read_32(struct adw_softc *adw, u_int addr)
730 {
731 u_int retval;
732
733 adw_outw(adw, ADW_RAM_ADDR, addr);
734 retval = adw_inw(adw, ADW_RAM_DATA);
735 retval |= (adw_inw(adw, ADW_RAM_DATA) << 16);
736 return (retval);
737 }
738
739 static __inline void
adw_lram_write_8(struct adw_softc * adw,u_int addr,u_int value)740 adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value)
741 {
742 adw_outw(adw, ADW_RAM_ADDR, addr);
743 adw_outb(adw, ADW_RAM_DATA, value);
744 }
745
746 static __inline void
adw_lram_write_16(struct adw_softc * adw,u_int addr,u_int value)747 adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value)
748 {
749 adw_outw(adw, ADW_RAM_ADDR, addr);
750 adw_outw(adw, ADW_RAM_DATA, value);
751 }
752
753 static __inline void
adw_lram_write_32(struct adw_softc * adw,u_int addr,u_int value)754 adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
755 {
756 adw_outw(adw, ADW_RAM_ADDR, addr);
757 adw_outw(adw, ADW_RAM_DATA, value);
758 adw_outw(adw, ADW_RAM_DATA, value >> 16);
759 }
760
761 static __inline u_int32_t
acbvtobo(struct adw_softc * adw,struct acb * acb)762 acbvtobo(struct adw_softc *adw, struct acb *acb)
763 {
764 return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
765 }
766
767 static __inline u_int32_t
acbvtob(struct adw_softc * adw,struct acb * acb)768 acbvtob(struct adw_softc *adw, struct acb *acb)
769 {
770 return (adw->acb_busbase + acbvtobo(adw, acb));
771 }
772
773 static __inline struct acb *
acbbotov(struct adw_softc * adw,u_int32_t byteoffset)774 acbbotov(struct adw_softc *adw, u_int32_t byteoffset)
775 {
776 return ((struct acb *)((caddr_t)adw->acbs + byteoffset));
777 }
778
779 static __inline struct acb *
acbbtov(struct adw_softc * adw,u_int32_t busaddr)780 acbbtov(struct adw_softc *adw, u_int32_t busaddr)
781 {
782 return (acbbotov(adw, busaddr - adw->acb_busbase));
783 }
784
785 /*
786 * Return the byte offset for a carrier relative to our array of carriers.
787 */
788 static __inline u_int32_t
carriervtobo(struct adw_softc * adw,struct adw_carrier * carrier)789 carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier)
790 {
791 return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers));
792 }
793
794 static __inline u_int32_t
carriervtob(struct adw_softc * adw,struct adw_carrier * carrier)795 carriervtob(struct adw_softc *adw, struct adw_carrier *carrier)
796 {
797 return (adw->carrier_busbase + carriervtobo(adw, carrier));
798 }
799
800 static __inline struct adw_carrier *
carrierbotov(struct adw_softc * adw,u_int32_t byte_offset)801 carrierbotov(struct adw_softc *adw, u_int32_t byte_offset)
802 {
803 return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset));
804 }
805
806 static __inline struct adw_carrier *
carrierbtov(struct adw_softc * adw,u_int32_t baddr)807 carrierbtov(struct adw_softc *adw, u_int32_t baddr)
808 {
809 return (carrierbotov(adw, baddr - adw->carrier_busbase));
810 }
811
812 /* Intialization */
813 int adw_find_signature(struct adw_softc *adw);
814 void adw_reset_chip(struct adw_softc *adw);
815 int adw_reset_bus(struct adw_softc *adw);
816 u_int16_t adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
817 void adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
818 int adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
819 void adw_set_user_sdtr(struct adw_softc *adw,
820 u_int tid, u_int mc_sdtr);
821 u_int adw_get_user_sdtr(struct adw_softc *adw, u_int tid);
822 void adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr);
823 u_int adw_get_chip_sdtr(struct adw_softc *adw, u_int tid);
824 u_int adw_find_sdtr(struct adw_softc *adw, u_int period);
825 u_int adw_find_period(struct adw_softc *adw, u_int mc_sdtr);
826 u_int adw_hshk_cfg_period_factor(u_int tinfo);
827
828 /* Idle Commands */
829 adw_idle_cmd_status_t adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
830 u_int parameter);
831
832 /* SCSI Transaction Processing */
833 static __inline void adw_send_acb(struct adw_softc *adw, struct acb *acb,
834 u_int32_t acb_baddr);
835
adw_tickle_risc(struct adw_softc * adw,u_int value)836 static __inline void adw_tickle_risc(struct adw_softc *adw, u_int value)
837 {
838 /*
839 * Tickle the RISC to tell it to read its Command Queue Head pointer.
840 */
841 adw_outb(adw, ADW_TICKLE, value);
842 if (adw->chip == ADW_CHIP_ASC3550) {
843 /*
844 * Clear the tickle value. In the ASC-3550 the RISC flag
845 * command 'clr_tickle_a' does not work unless the host
846 * value is cleared.
847 */
848 adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP);
849 }
850 }
851
852 static __inline void
adw_send_acb(struct adw_softc * adw,struct acb * acb,u_int32_t acb_baddr)853 adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
854 {
855 struct adw_carrier *new_cq;
856
857 new_cq = adw->free_carriers;
858 adw->free_carriers = carrierbotov(adw, new_cq->next_ba);
859 new_cq->next_ba = ADW_CQ_STOPPER;
860
861 acb->queue.carrier_baddr = adw->commandq->carr_ba;
862 acb->queue.carrier_bo = adw->commandq->carr_offset;
863 adw->commandq->areq_ba = acbvtob(adw, acb);
864 adw->commandq->next_ba = new_cq->carr_ba;
865 #if 0
866 kprintf("EnQ 0x%x 0x%x 0x%x 0x%x\n",
867 adw->commandq->carr_offset,
868 adw->commandq->carr_ba,
869 adw->commandq->areq_ba,
870 adw->commandq->next_ba);
871 #endif
872 adw->commandq = new_cq;
873
874
875 adw_tickle_risc(adw, ADW_TICKLE_A);
876 }
877
878 #endif /* _ADWLIB_H_ */
879