| /NextBSD/contrib/llvm/lib/Target/X86/Disassembler/ |
| HD | X86Disassembler.cpp | 343 unsigned NewOpc; in translateImmediate() local 377 unsigned NewOpc; in translateImmediate() local 408 unsigned NewOpc; in translateImmediate() local
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMExpandPseudoInsts.cpp | 802 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local 841 unsigned NewOpc; in ExpandMI() local 1085 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local 1116 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
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| HD | ARMLoadStoreOptimizer.cpp | 1210 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local 1308 unsigned NewOpc = 0; in MergeBaseUpdateLoadStore() local 1470 DebugLoc DL, unsigned NewOpc, in InsertLDR_STR() 1535 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1557 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local 1776 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local 1931 DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord() 2096 unsigned NewOpc = 0; in RescheduleOps() local
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| HD | Thumb2InstrInfo.cpp | 501 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local 535 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
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| HD | ThumbRegisterInfo.cpp | 398 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
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| HD | ARMConstantIslandPass.cpp | 1811 unsigned NewOpc = 0; in optimizeThumb2Instructions() local 1870 unsigned NewOpc = 0; in optimizeThumb2Branches() local
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| HD | ARMISelLowering.cpp | 2768 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local 6169 unsigned NewOpc = 0; in LowerMUL() local 7602 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? in EmitInstrWithCustomInserter() local 7626 unsigned NewOpc; in EmitInstrWithCustomInserter() local 7841 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); in AdjustInstrPostInstrSelection() local 9065 unsigned NewOpc = 0; in CombineBaseUpdate() local 9267 unsigned NewOpc = 0; in CombineVLDDUP() local
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| HD | ARMISelDAGToDAG.cpp | 3073 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD) in Select() local 3155 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD) in Select() local
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64LoadStoreOptimizer.cpp | 347 unsigned NewOpc = getMatchingPairOpcode(Opc); in mergePairedInsns() local 687 unsigned NewOpc = getPreIndexedOpcode(I->getOpcode()); in mergePreIdxUpdateInsn() local 730 unsigned NewOpc = getPostIndexedOpcode(I->getOpcode()); in mergePostIdxUpdateInsn() local
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| HD | AArch64AdvSIMDScalarPass.cpp | 290 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
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| HD | AArch64InstrInfo.cpp | 827 unsigned NewOpc = convertFlagSettingOpcode(CmpInstr); in optimizeCompareInstr() local 860 unsigned NewOpc = MI->getOpcode(); in optimizeCompareInstr() local 2472 unsigned NewOpc = convertFlagSettingOpcode(&Root); in getMachineCombinerPatterns() local
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsInstrInfo.cpp | 278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc()
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| HD | MipsLongBranch.cpp | 219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch() local
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| HD | MipsSEISelLowering.cpp | 1267 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, in lowerMulDiv()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86MCInstLower.cpp | 478 unsigned NewOpc; in Lower() local 502 unsigned NewOpc; in Lower() local
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| HD | X86InstrInfo.cpp | 4578 unsigned NewOpc; in optimizeCompareInstr() local 5251 unsigned NewOpc = 0; in foldMemoryOperandImpl() local 5375 unsigned NewOpc = 0; in foldMemoryOperandImpl() local 5613 unsigned NewOpc; in unfoldMemoryOperand() local
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonGenPredicate.cpp | 370 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
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| HD | HexagonFrameLowering.cpp | 625 unsigned NewOpc = Hexagon::L4_return; in insertEpilogueInBlock() local
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeVectorOps.cpp | 465 unsigned NewOpc; in PromoteFP_TO_INT() local
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| HD | LegalizeIntegerTypes.cpp | 399 unsigned NewOpc = N->getOpcode(); in PromoteIntRes_FP_TO_XINT() local
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| /NextBSD/contrib/llvm/lib/Target/X86/AsmParser/ |
| HD | X86AsmParser.cpp | 2457 unsigned NewOpc; in processInstruction() local 2481 unsigned NewOpc; in processInstruction() local
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | MachineLICM.cpp | 1246 unsigned NewOpc = in ExtractHoistableLoad() local
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| HD | TwoAddressInstructionPass.cpp | 1274 unsigned NewOpc = in tryInstructionTransform() local
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| /NextBSD/contrib/llvm/lib/Target/ARM/AsmParser/ |
| HD | ARMAsmParser.cpp | 7919 unsigned NewOpc; in processInstruction() local 8401 unsigned NewOpc; in processInstruction() local 8516 unsigned NewOpc; in processInstruction() local 8556 unsigned NewOpc; in processInstruction() local
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | SIInstrInfo.cpp | 445 int NewOpc; in commuteOpcode() local
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