1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H 14 #define LLVM_LIB_TARGET_R600_SIDEFINES_H 15 16 namespace SIInstrFlags { 17 // This needs to be kept in sync with the field bits in InstSI. 18 enum { 19 SALU = 1 << 3, 20 VALU = 1 << 4, 21 22 SOP1 = 1 << 5, 23 SOP2 = 1 << 6, 24 SOPC = 1 << 7, 25 SOPK = 1 << 8, 26 SOPP = 1 << 9, 27 28 VOP1 = 1 << 10, 29 VOP2 = 1 << 11, 30 VOP3 = 1 << 12, 31 VOPC = 1 << 13, 32 33 MUBUF = 1 << 14, 34 MTBUF = 1 << 15, 35 SMRD = 1 << 16, 36 DS = 1 << 17, 37 MIMG = 1 << 18, 38 FLAT = 1 << 19, 39 WQM = 1 << 20, 40 VGPRSpill = 1 << 21 41 }; 42 } 43 44 namespace llvm { 45 namespace AMDGPU { 46 enum OperandType { 47 /// Operand with register or 32-bit immediate 48 OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET, 49 /// Operand with register or inline constant 50 OPERAND_REG_INLINE_C 51 }; 52 } 53 } 54 55 namespace SIInstrFlags { 56 enum Flags { 57 // First 4 bits are the instruction encoding 58 VM_CNT = 1 << 0, 59 EXP_CNT = 1 << 1, 60 LGKM_CNT = 1 << 2 61 }; 62 63 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 64 // The result is true if any of these tests are true. 65 enum ClassFlags { 66 S_NAN = 1 << 0, // Signaling NaN 67 Q_NAN = 1 << 1, // Quiet NaN 68 N_INFINITY = 1 << 2, // Negative infinity 69 N_NORMAL = 1 << 3, // Negative normal 70 N_SUBNORMAL = 1 << 4, // Negative subnormal 71 N_ZERO = 1 << 5, // Negative zero 72 P_ZERO = 1 << 6, // Positive zero 73 P_SUBNORMAL = 1 << 7, // Positive subnormal 74 P_NORMAL = 1 << 8, // Positive normal 75 P_INFINITY = 1 << 9 // Positive infinity 76 }; 77 } 78 79 namespace SISrcMods { 80 enum { 81 NEG = 1 << 0, 82 ABS = 1 << 1 83 }; 84 } 85 86 namespace SIOutMods { 87 enum { 88 NONE = 0, 89 MUL2 = 1, 90 MUL4 = 2, 91 DIV2 = 3 92 }; 93 } 94 95 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 96 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 97 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 98 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 99 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 100 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 101 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 102 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 103 104 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 105 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 106 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 107 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 108 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 109 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 110 #define C_00B84C_USER_SGPR 0xFFFFFFC1 111 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 112 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 113 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 114 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 115 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 116 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 117 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 118 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 119 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 120 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 121 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 122 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 123 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 124 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 125 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 126 /* CIK */ 127 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 128 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 129 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 130 /* */ 131 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 132 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 133 #define C_00B84C_LDS_SIZE 0xFF007FFF 134 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 135 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 136 #define C_00B84C_EXCP_EN 137 138 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 139 140 141 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 142 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 143 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 144 #define C_00B848_VGPRS 0xFFFFFFC0 145 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 146 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 147 #define C_00B848_SGPRS 0xFFFFFC3F 148 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 149 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 150 #define C_00B848_PRIORITY 0xFFFFF3FF 151 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 152 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 153 #define C_00B848_FLOAT_MODE 0xFFF00FFF 154 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 155 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 156 #define C_00B848_PRIV 0xFFEFFFFF 157 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 158 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 159 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 160 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 161 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 162 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 163 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 164 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 165 #define C_00B848_IEEE_MODE 0xFF7FFFFF 166 167 168 // Helpers for setting FLOAT_MODE 169 #define FP_ROUND_ROUND_TO_NEAREST 0 170 #define FP_ROUND_ROUND_TO_INF 1 171 #define FP_ROUND_ROUND_TO_NEGINF 2 172 #define FP_ROUND_ROUND_TO_ZERO 3 173 174 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 175 // precision. 176 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 177 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 178 179 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 180 #define FP_DENORM_FLUSH_OUT 1 181 #define FP_DENORM_FLUSH_IN 2 182 #define FP_DENORM_FLUSH_NONE 3 183 184 185 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 186 // precision. 187 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 188 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 189 190 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 191 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 192 193 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 194 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 195 196 197 #endif 198