| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
223 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
465 unsigned PredReg; in rewriteT2FrameIndex() local
635 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getITInstrPredicate()
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| HD | ARMLoadStoreOptimizer.cpp | 432 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses()
567 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, in CreateLoadStoreMulti()
759 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, in CreateLoadStoreDouble()
824 unsigned PredReg = 0; in MergeOpsUpdate() local
1000 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingDecrement()
1035 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingIncrement()
1155 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1304 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1474 ARMCC::CondCodes Pred, unsigned PredReg, in InsertLDR_STR()
1529 unsigned PredReg = 0; in FixInvalidRegPairOp() local
[all …]
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| HD | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| HD | Thumb2SizeReduction.cpp | 582 unsigned PredReg = 0; in ReduceSpecial() local
686 unsigned PredReg = 0; in ReduceTo2Addr() local
783 unsigned PredReg = 0; in ReduceToNarrow() local
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| HD | ARMFrameLowering.cpp | 128 unsigned PredReg = 0) { in emitRegPlusImmediate()
142 unsigned PredReg = 0) { in emitSPUpdate()
1802 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1807 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
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| HD | Thumb2ITBlockPass.cpp | 184 unsigned PredReg = 0; in InsertITInstructions() local
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| HD | ARMBaseRegisterInfo.cpp | 397 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| HD | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| HD | ARMBaseInstrInfo.cpp | 1668 unsigned PredReg = 0; in isProfitableToIfCvt() local
1724 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate()
1754 unsigned PredReg = 0; in commuteInstruction() local
1945 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
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| HD | ARMISelDAGToDAG.cpp | 2532 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2802 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2822 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2841 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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| HD | ARMExpandPseudoInsts.cpp | 656 unsigned PredReg = 0; in ExpandMOV32BitImm() local
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| HD | ARMConstantIslandPass.cpp | 1455 unsigned PredReg = 0; in createNewWater() local
1911 unsigned PredReg = 0; in optimizeThumb2Branches() local
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HD | HexagonMCDuplexInfo.cpp | 182 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| HD | HexagonMCCompound.cpp | 183 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonGenPredicate.cpp | 304 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred()
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| HD | HexagonInstrInfo.cpp | 1043 unsigned PredReg, PredRegPos, PredRegFlags; in PredicateInstruction() local
1997 unsigned &PredReg, unsigned &PredRegPos, in getPredReg()
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| HD | HexagonHardwareLoops.cpp | 613 unsigned PredReg, PredPos, PredRegFlags; in getLoopTripCount() local
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