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Searched defs:RW (Results 1 – 13 of 13) sorted by relevance

/NextBSD/contrib/compiler-rt/lib/tsan/tests/rtl/
HDtsan_test_util.h34 enum Type { Normal, Spin, RW }; enumerator
/NextBSD/usr.bin/uuencode/
HDuuencode.c110 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) in main() macro
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonBitTracker.cpp84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask() local
209 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
210 -> BT::RegisterCell { in evaluate()
273 uint16_t RW = W0; in evaluate() local
/NextBSD/contrib/ntp/include/
HDntpd.h95 #define RW (CAN_READ|CAN_WRITE) macro
/NextBSD/libexec/getty/
HDgettytab.h158 #define RW gettyflags[11].value macro
/NextBSD/sys/dev/aic7xxx/aicasm/
HDaicasm_symbol.h67 RW = 0x03 enumerator
/NextBSD/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM64/
HDEmulateInstructionARM64.h249 RW:1, // Current register width – 0 is AArch64, 1 is AArch32 member
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenSchedule.cpp301 CodeGenSchedRW &RW = getSchedRW(MatchDef); in collectSchedRW() local
991 static bool hasAliasedVariants(const CodeGenSchedRW &RW, in hasAliasedVariants()
/NextBSD/contrib/llvm/tools/clang/lib/CodeGen/
HDCGBuiltin.cpp526 Value *Locality, *RW, *Address = EmitScalarExpr(E->getArg(0)); in EmitBuiltinExpr() local
3412 Value *RW = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
4200 Value *RW = EmitScalarExpr(E->getArg(1)); in EmitAArch64BuiltinExpr() local
6179 Value *RW = ConstantInt::get(Int32Ty, 0); in EmitX86BuiltinExpr() local
/NextBSD/sys/dev/usb/wlan/
HDif_rsureg.h157 #define RW(var, field, val) \ macro
HDif_urtwnreg.h872 #define RW(var, field, val) \ macro
/NextBSD/sys/dev/rtwn/
HDif_rtwnreg.h914 #define RW(var, field, val) \ macro
/NextBSD/contrib/llvm/tools/clang/lib/Sema/
HDSemaOverload.cpp7134 RW = S.Context.getIntWidth(RT); in getUsualArithmeticConversions() local