| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
184 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
194 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
232 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
251 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
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| D | MipsMCCodeEmitter.cpp | 96 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ExpandPseudo.cpp | 466 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
500 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
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| D | X86InstrInfo.cpp | 6223 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2168 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2303 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2476 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
3017 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
3371 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3419 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3441 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3462 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3812 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
3831 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
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| D | Thumb2SizeReduction.cpp | 754 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
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| D | ARMAsmPrinter.cpp | 320 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
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| D | HexagonBitTracker.cpp | 314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 230 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 462 unsigned Reg0 = in emitPrologue() local
480 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 1436 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1449 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1504 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1551 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 991 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1004 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1042 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1053 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
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| /openbsd/src/gnu/llvm/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 755 uint16_t Reg0 = 0; variable
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 1243 Register Reg0 = MO0.getReg(); in allocateInstruction() local
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| D | TargetInstrInfo.cpp | 183 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
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| D | RegisterCoalescer.cpp | 2639 Register Reg0; in valuesIdentical() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 799 Register Reg0 = UseMI->getOperand(0).getReg(); in foldOperand() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 1972 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1166 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1196 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
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