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Searched defs:RegClass (Results 1 – 25 of 36) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
HDRDFRegisters.h183 const TargetRegisterClass *RegClass = nullptr; member
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
HDWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
641 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUMachineCFGStructurizer.cpp1883 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1950 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2010 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2124 const TargetRegisterClass *RegClass = in createEntryPHI() local
2262 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2396 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
HDGCNDPPCombine.cpp197 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; in getOperandSize() local
HDAMDGPUISelDAGToDAG.cpp371 int RegClass = Desc.operands()[OpIdx].RegClass; in getOperandRegClass() local
446 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
HDMachineRegisterInfo.cpp159 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
HDTargetInstrInfo.cpp54 short RegClass = MCID.operands()[OpNum].RegClass; in getRegClass() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/CSKY/
HDCSKYISelDAGToDAG.cpp385 SDValue RegClass = in createGPRPairNode() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64LoadStoreOptimizer.cpp1425 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameMOP() local
1628 auto *RegClass = TRI->getMinimalPhysRegClass(Reg); in tryToFindRegisterToRename() local
1656 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in findRenameRegForSameLdStRegPair() local
HDAArch64AsmPrinter.cpp1110 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDThumb2InstrInfo.cpp562 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
HDARMISelDAGToDAG.cpp1855 SDValue RegClass = in createGPRPairNode() local
1866 SDValue RegClass = in createSRegPairNode() local
1877 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1888 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1900 SDValue RegClass = in createQuadSRegsNode() local
1915 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1930 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
HDMVETPAndVPTOptimisationsPass.cpp617 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); in IsWritingToVCCR() local
HDARMBaseRegisterInfo.cpp855 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDInlineAsm.h309 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCompressInstEmitter.cpp151 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
HDAMDGPUDisassembler.cpp162 #define DECODE_OPERAND_REG_8(RegClass) \ argument
197 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ argument
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/Common/
HDCodeGenRegisters.cpp1675 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1736 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDUtils.cpp49 const TargetRegisterClass &RegClass) { in constrainRegToClass()
60 const TargetRegisterClass &RegClass, MachineOperand &RegMO) { in constrainOperandRegClass()
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86FrameLowering.cpp953 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInlineWindowsCoreCLR64() local
3680 auto &RegClass = in adjustStackWithPops() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.cpp590 const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg); in getRegAllocationHints() local
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVInstrInfo.cpp385 uint16_t Encoding) { in copyPhysRegVector()
549 for (const auto &RegClass : RVVRegClasses) { in copyPhysReg() local

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