| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 194 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef() local
217 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef() local
248 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse() local
271 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegUse() local
287 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastRefOrPartRef() local
336 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegKill() local
367 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegKill() local
445 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegDef() local
449 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegDef() local
471 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegDef() local
[all …]
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| D | CriticalAntiDepBreaker.cpp | 216 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
241 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
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| D | AggressiveAntiDepBreaker.cpp | 249 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs() local
325 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandleLastUse() local
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| D | MachineInstrBundle.cpp | 202 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in finalizeBundle() local
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| D | IfConversion.cpp | 1961 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1969 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
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| D | BranchFolding.cpp | 1879 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findHoistingInsertPosAndDeps() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 439 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findPotentialNewifiableTFRs() local
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| D | HexagonInstrInfo.cpp | 2223 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2228 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
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| D | HexagonFrameLowering.cpp | 255 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) { in getMax32BitSubRegister() local
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| /openbsd/src/gnu/llvm/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 107 uint32_t SubRegs; // Sub-register set, described above member
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| /openbsd/src/gnu/llvm/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 278 SubRegMap SubRegs; member
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| D | CodeGenRegisters.cpp | 616 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); in expand() local
2122 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1432 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1441 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1451 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZTuple() local
1459 const unsigned SubRegs[]) { in createTuple()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 598 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
643 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
2912 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex() local
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| D | SIInstrInfo.cpp | 5390 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 642 const unsigned SubRegs[], MachineIRBuilder &MIB) { in createTuple()
663 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
672 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 935 unsigned SubRegs = 0; in copyPhysReg() local
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| D | ARMISelDAGToDAG.cpp | 2937 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD() local
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3536 for (MCSubRegIterator SubRegs(VA.getLocReg(), TRI, /*IncludeSelf=*/true); in LowerCallResult() local
4896 for (MCSubRegIterator SubRegs(RegPair.first, TRI, /*IncludeSelf=*/true); in LowerCall() local
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