1 /* Definitions of target machine for GNU compiler. 2 Motorola 68HC11 and 68HC12. 3 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 4 Contributed by Stephane Carrez (stcarrez@nerim.fr) 5 6 This file is part of GNU CC. 7 8 GNU CC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GNU CC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GNU CC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. 22 23 Note: 24 A first 68HC11 port was made by Otto Lind (otto@coactive.com) 25 on gcc 2.6.3. I have used it as a starting point for this port. 26 However, this new port is a complete re-write. Its internal 27 design is completely different. The generated code is not 28 compatible with the gcc 2.6.3 port. 29 30 The gcc 2.6.3 port is available at: 31 32 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz 33 34 */ 35 36 /***************************************************************************** 37 ** 38 ** Controlling the Compilation Driver, `gcc' 39 ** 40 *****************************************************************************/ 41 42 #undef ENDFILE_SPEC 43 44 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */ 45 #ifndef ASM_SPEC 46 #define ASM_SPEC \ 47 "%{m68hc12:-m68hc12}" \ 48 "%{m68hcs12:-m68hcs12}" \ 49 "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \ 50 "%{mshort:-mshort}%{!mshort:-mlong} " \ 51 "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}" 52 #endif 53 54 /* We need to tell the linker the target elf format. Just pass an 55 emulation option. This can be overriden by -Wl option of gcc. */ 56 #ifndef LINK_SPEC 57 #define LINK_SPEC \ 58 "%{m68hc12:-m m68hc12elf}" \ 59 "%{m68hcs12:-m m68hc12elf}" \ 60 "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \ 61 "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}" 62 #endif 63 64 #ifndef LIB_SPEC 65 #define LIB_SPEC "" 66 #endif 67 68 #ifndef CC1_SPEC 69 #define CC1_SPEC "" 70 #endif 71 72 #ifndef CPP_SPEC 73 #define CPP_SPEC \ 74 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\ 75 %{!mshort:-D__INT__=32}\ 76 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\ 77 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\ 78 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\ 79 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\ 80 %{mlong-calls:-D__USE_RTC__}" 81 #endif 82 83 #undef STARTFILE_SPEC 84 #define STARTFILE_SPEC "crt1%O%s" 85 86 /* Names to predefine in the preprocessor for this target machine. */ 87 #define CPP_PREDEFINES "-Dmc68hc1x" 88 89 /* As an embedded target, we have no libc. */ 90 #define inhibit_libc 91 92 /* Forward type declaration for prototypes definitions. 93 rtx_ptr is equivalent to rtx. Can't use the same name. */ 94 struct rtx_def; 95 typedef struct rtx_def *rtx_ptr; 96 97 union tree_node; 98 typedef union tree_node *tree_ptr; 99 100 /* We can't declare enum machine_mode forward nor include 'machmode.h' here. 101 Prototypes defined here will use an int instead. It's better than no 102 prototype at all. */ 103 typedef int enum_machine_mode; 104 105 /***************************************************************************** 106 ** 107 ** Run-time Target Specification 108 ** 109 *****************************************************************************/ 110 111 /* Run-time compilation parameters selecting different hardware subsets. */ 112 113 extern int target_flags; 114 115 extern short *reg_renumber; /* def in local_alloc.c */ 116 117 /* Macros used in the machine description to test the flags. */ 118 119 /* 6811 specific options 120 * 121 * For 68HC12, the auto inc/dec mode is disabled by default. The reason 122 * is that for most programs, the reload pass will fail because it needs 123 * more registers to save the value of the indexed register after the 124 * memory access. For simple programs, you can enable this 125 * with -mauto-incdec. 126 */ 127 128 #define MASK_SHORT 0002 /* Compile with 16-bit `int' */ 129 #define MASK_AUTO_INC_DEC 0004 130 #define MASK_M6811 0010 131 #define MASK_M6812 0020 132 #define MASK_M68S12 0040 133 #define MASK_NO_DIRECT_MODE 0100 134 #define MASK_MIN_MAX 0200 135 #define MASK_LONG_CALLS 0400 136 137 #define TARGET_OP_TIME (optimize && optimize_size == 0) 138 #define TARGET_SHORT (target_flags & MASK_SHORT) 139 #define TARGET_M6811 (target_flags & MASK_M6811) 140 #define TARGET_M6812 (target_flags & MASK_M6812) 141 #define TARGET_M68S12 (target_flags & MASK_M68S12) 142 #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC) 143 #define TARGET_MIN_MAX (target_flags & MASK_MIN_MAX) 144 #define TARGET_NO_DIRECT_MODE (target_flags & MASK_NO_DIRECT_MODE) 145 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE) 146 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS) 147 148 /* Default target_flags if no switches specified. */ 149 #ifndef TARGET_DEFAULT 150 # define TARGET_DEFAULT (MASK_M6811) 151 #endif 152 153 /* Define this macro as a C expression for the initializer of an 154 array of string to tell the driver program which options are 155 defaults for this target and thus do not need to be handled 156 specially when using `MULTILIB_OPTIONS'. */ 157 #ifndef MULTILIB_DEFAULTS 158 # if TARGET_DEFAULT & MASK_M6811 159 # define MULTILIB_DEFAULTS { "m68hc11" } 160 # else 161 # define MULTILIB_DEFAULTS { "m68hc12" } 162 # endif 163 #endif 164 165 /* Macro to define tables used to set the flags. This is a list in braces of 166 pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits 167 to set or minus the bits to clear. An empty string NAME is used to 168 identify the default VALUE. */ 169 170 #define TARGET_SWITCHES \ 171 { { "short", MASK_SHORT, \ 172 N_("Compile with 16-bit integer mode")}, \ 173 { "noshort", - MASK_SHORT, \ 174 N_("Compile with 32-bit integer mode")}, \ 175 { "auto-incdec", MASK_AUTO_INC_DEC, \ 176 N_("Auto pre/post decrement increment allowed")}, \ 177 { "noauto-incdec", - MASK_AUTO_INC_DEC, \ 178 N_("Auto pre/post decrement increment not allowed")}, \ 179 { "inmax", MASK_MIN_MAX, \ 180 N_("Min/max instructions allowed")}, \ 181 { "nominmax", - MASK_MIN_MAX, \ 182 N_("Min/max instructions not allowed")}, \ 183 { "long-calls", MASK_LONG_CALLS, \ 184 N_("Use call and rtc for function calls and returns")}, \ 185 { "nolong-calls", - MASK_LONG_CALLS, \ 186 N_("Use jsr and rts for function calls and returns")}, \ 187 { "relax", MASK_NO_DIRECT_MODE, \ 188 N_("Do not use direct addressing mode for soft registers")},\ 189 { "norelax", -MASK_NO_DIRECT_MODE, \ 190 N_("Use direct addressing mode for soft registers")}, \ 191 { "68hc11", MASK_M6811, \ 192 N_("Compile for a 68HC11")}, \ 193 { "68hc12", MASK_M6812, \ 194 N_("Compile for a 68HC12")}, \ 195 { "68hcs12", MASK_M6812 | MASK_M68S12, \ 196 N_("Compile for a 68HCS12")}, \ 197 { "6811", MASK_M6811, \ 198 N_("Compile for a 68HC11")}, \ 199 { "6812", MASK_M6812, \ 200 N_("Compile for a 68HC12")}, \ 201 { "68S12", MASK_M6812 | MASK_M68S12, \ 202 N_("Compile for a 68HCS12")}, \ 203 { "", TARGET_DEFAULT, 0 }} 204 205 /* This macro is similar to `TARGET_SWITCHES' but defines names of 206 command options that have values. Its definition is an 207 initializer with a subgrouping for each command option. 208 209 Each subgrouping contains a string constant, that defines the 210 fixed part of the option name, and the address of a variable. The 211 variable, type `char *', is set to the variable part of the given 212 option if the fixed part matches. The actual option name is made 213 by appending `-m' to the specified name. */ 214 #define TARGET_OPTIONS \ 215 { { "reg-alloc=", &m68hc11_reg_alloc_order, \ 216 N_("Specify the register allocation order")}, \ 217 { "soft-reg-count=", &m68hc11_soft_reg_count, \ 218 N_("Indicate the number of soft registers available") }, \ 219 SUBTARGET_OPTIONS \ 220 } 221 222 /* These are meant to be redefined in the host dependent files */ 223 #define SUBTARGET_SWITCHES 224 #define SUBTARGET_OPTIONS 225 226 extern const char *m68hc11_regparm_string; 227 extern const char *m68hc11_reg_alloc_order; 228 extern const char *m68hc11_soft_reg_count; 229 230 #ifndef TARGET_M68HC12 231 # define TARGET_M68HC11 1 232 #endif 233 234 /* Print subsidiary information on the compiler version in use. */ 235 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)") 236 237 /* Sometimes certain combinations of command options do not make 238 sense on a particular target machine. You can define a macro 239 `OVERRIDE_OPTIONS' to take account of this. This macro, if 240 defined, is executed once just after all the command options have 241 been parsed. 242 243 Don't use this macro to turn on various extra optimizations for 244 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 245 246 #define OVERRIDE_OPTIONS m68hc11_override_options (); 247 248 249 /* Define cost parameters for a given processor variant. */ 250 struct processor_costs { 251 const int add; /* cost of an add instruction */ 252 const int logical; /* cost of a logical instruction */ 253 const int shift_var; 254 const int shiftQI_const[8]; 255 const int shiftHI_const[16]; 256 const int multQI; 257 const int multHI; 258 const int multSI; 259 const int divQI; 260 const int divHI; 261 const int divSI; 262 }; 263 264 /* Costs for the current processor. */ 265 extern const struct processor_costs *m68hc11_cost; 266 267 268 /* target machine storage layout */ 269 270 /* Define this if most significant byte of a word is the lowest numbered. */ 271 #define BYTES_BIG_ENDIAN 1 272 273 /* Define this if most significant bit is lowest numbered 274 in instructions that operate on numbered bit-fields. */ 275 #define BITS_BIG_ENDIAN 0 276 277 /* Define this if most significant word of a multiword number is numbered. */ 278 #define WORDS_BIG_ENDIAN 1 279 280 /* Width of a word, in units (bytes). */ 281 #define UNITS_PER_WORD 2 282 283 /* Definition of size_t. This is really an unsigned short as the 284 68hc11 only handles a 64K address space. */ 285 #define SIZE_TYPE "short unsigned int" 286 287 /* A C expression for a string describing the name of the data type 288 to use for the result of subtracting two pointers. The typedef 289 name `ptrdiff_t' is defined using the contents of the string. 290 The 68hc11 only has a 64K address space. */ 291 #define PTRDIFF_TYPE "short int" 292 293 /* Allocation boundary (bits) for storing pointers in memory. */ 294 #define POINTER_BOUNDARY 8 295 296 /* Normal alignment required for function parameters on the stack, in bits. 297 This can't be less than BITS_PER_WORD */ 298 #define PARM_BOUNDARY (BITS_PER_WORD) 299 300 /* Boundary (bits) on which stack pointer should be aligned. */ 301 #define STACK_BOUNDARY 8 302 303 /* Allocation boundary (bits) for the code of a function. */ 304 #define FUNCTION_BOUNDARY 8 305 306 #define BIGGEST_ALIGNMENT 8 307 308 /* Alignment of field after `int : 0' in a structure. */ 309 #define EMPTY_FIELD_BOUNDARY 8 310 311 /* Every structure's size must be a multiple of this. */ 312 #define STRUCTURE_SIZE_BOUNDARY 8 313 314 /* Define this if instructions will fail to work if given data not 315 on the nominal alignment. If instructions will merely go slower 316 in that case, do not define this macro. */ 317 #define STRICT_ALIGNMENT 0 318 319 /* An integer expression for the size in bits of the largest integer 320 machine mode that should actually be used. All integer machine modes of 321 this size or smaller can be used for structures and unions with the 322 appropriate sizes. */ 323 #define MAX_FIXED_MODE_SIZE 64 324 325 /* target machine storage layout */ 326 327 /* Size (bits) of the type "int" on target machine 328 (If undefined, default is BITS_PER_WORD). */ 329 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 330 331 /* Size (bits) of the type "short" on target machine */ 332 #define SHORT_TYPE_SIZE 16 333 334 /* Size (bits) of the type "long" on target machine */ 335 #define LONG_TYPE_SIZE 32 336 337 /* Size (bits) of the type "long long" on target machine */ 338 #define LONG_LONG_TYPE_SIZE 64 339 340 /* A C expression for the size in bits of the type `float' on the 341 target machine. If you don't define this, the default is one word. 342 Don't use default: a word is only 16. */ 343 #define FLOAT_TYPE_SIZE 32 344 345 /* A C expression for the size in bits of the type double on the target 346 machine. If you don't define this, the default is two words. 347 Be IEEE compliant. */ 348 #define DOUBLE_TYPE_SIZE 64 349 350 #define LONG_DOUBLE_TYPE_SIZE 64 351 352 /* Define this as 1 if `char' should by default be signed; else as 0. */ 353 #define DEFAULT_SIGNED_CHAR 0 354 355 /* Define these to avoid dependence on meaning of `int'. 356 Note that WCHAR_TYPE_SIZE is used in cexp.y, 357 where TARGET_SHORT is not available. */ 358 #define WCHAR_TYPE "short int" 359 #define WCHAR_TYPE_SIZE 16 360 361 362 /* Standard register usage. */ 363 364 #define HARD_REG_SIZE (UNITS_PER_WORD) 365 366 /* Assign names to real MC68HC11 registers. 367 A and B registers are not really used (A+B = D) 368 X register is first so that GCC allocates X+D for 32-bit integers and 369 the lowpart of that integer will be D. Having the lower part in D is 370 better for 32<->16bit conversions and for many arithmetic operations. */ 371 #define HARD_X_REGNUM 0 372 #define HARD_D_REGNUM 1 373 #define HARD_Y_REGNUM 2 374 #define HARD_SP_REGNUM 3 375 #define HARD_PC_REGNUM 4 376 #define HARD_A_REGNUM 5 377 #define HARD_B_REGNUM 6 378 #define HARD_CCR_REGNUM 7 379 380 /* The Z register does not really exist in the 68HC11. This a fake register 381 for GCC. It is treated exactly as an index register (X or Y). It is only 382 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this 383 register helps the reload pass of GCC. Otherwise, the reload often aborts 384 with register spill failures. 385 386 The Z register is replaced by either X or Y during the machine specific 387 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register 388 when this is necessary. 389 390 It's possible to tell GCC not to use this register with -ffixed-z. */ 391 #define HARD_Z_REGNUM 8 392 393 /* The frame pointer is a soft-register. It's treated as such by GCC: 394 it is not and must not be part of the BASE_REG_CLASS. */ 395 #define DEFAULT_HARD_FP_REGNUM (9) 396 #define HARD_FP_REGNUM (9) 397 #define HARD_AP_REGNUM (HARD_FP_REGNUM) 398 399 /* Temporary soft-register used in some cases when an operand came 400 up into a bad register class (D, X, Y, SP) and gcc failed to 401 recognize this. This register is never allocated by GCC. */ 402 #define SOFT_TMP_REGNUM 10 403 404 /* The soft-register which is used to save the Z register 405 (see Z register replacement notes in m68hc11.c). */ 406 #define SOFT_Z_REGNUM 11 407 408 /* The soft-register which is used to save either X or Y. */ 409 #define SOFT_SAVED_XY_REGNUM 12 410 411 /* A fake clobber register for 68HC12 patterns. */ 412 #define FAKE_CLOBBER_REGNUM (13) 413 414 /* Define 32 soft-registers of 16-bit each. By default, 415 only 12 of them are enabled and can be used by GCC. The 416 -msoft-reg-count=<n> option allows to control the number of valid 417 soft-registers. GCC can put 32-bit values in them 418 by allocating consecutive registers. The first 3 soft-registers 419 are never allocated by GCC. They are used in case the insn template needs 420 a temporary register, or for the Z register replacement. */ 421 422 #define MAX_SOFT_REG_COUNT (32) 423 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \ 424 0, 0, 0, 0, 1, 1, 1, 1, \ 425 1, 1, 1, 1, 1, 1, 1, 1, \ 426 1, 1, 1, 1, 1, 1, 1, 1 427 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \ 428 0, 0, 0, 0, 1, 1, 1, 1, \ 429 1, 1, 1, 1, 1, 1, 1, 1, \ 430 1, 1, 1, 1, 1, 1, 1, 1 431 #define SOFT_REG_ORDER \ 432 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\ 433 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\ 434 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\ 435 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\ 436 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\ 437 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\ 438 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\ 439 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31 440 441 #define SOFT_REG_NAMES \ 442 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \ 443 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \ 444 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \ 445 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \ 446 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \ 447 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \ 448 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \ 449 "*_.d29", "*_.d30", "*_.d31", "*_.d32" 450 451 /* First available soft-register for GCC. */ 452 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2) 453 454 /* Last available soft-register for GCC. */ 455 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT) 456 #define SOFT_FP_REGNUM (SOFT_REG_LAST) 457 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1) 458 459 /* Number of actual hardware registers. The hardware registers are assigned 460 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. 461 All registers that the compiler knows about must be given numbers, even 462 those that are not normally considered general registers. */ 463 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2) 464 465 /* 1 for registers that have pervasive standard uses and are not available 466 for the register allocator. */ 467 #define FIXED_REGISTERS \ 468 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1} 469 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */ 470 471 /* 1 for registers not available across function calls. For our pseudo 472 registers, all are available. */ 473 #define CALL_USED_REGISTERS \ 474 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1} 475 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */ 476 477 478 /* Define this macro to change register usage conditional on target flags. 479 480 The soft-registers are disabled or enabled according to the 481 -msoft-reg-count=<n> option. */ 482 483 484 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ()) 485 486 /* List the order in which to allocate registers. Each register must be 487 listed once, even those in FIXED_REGISTERS. */ 488 #define REG_ALLOC_ORDER \ 489 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \ 490 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \ 491 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \ 492 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \ 493 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM } 494 495 /* A C expression for the number of consecutive hard registers, 496 starting at register number REGNO, required to hold a value of 497 mode MODE. */ 498 #define HARD_REGNO_NREGS(REGNO, MODE) \ 499 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \ 500 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE)) 501 502 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 503 - 8 bit values are stored anywhere (except the SP register). 504 - 16 bit values can be stored in any register whose mode is 16 505 - 32 bit values can be stored in D, X registers or in a soft register 506 (except the last one because we need 2 soft registers) 507 - Values whose size is > 32 bit are not stored in real hard 508 registers. They may be stored in soft registers if there are 509 enough of them. */ 510 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 511 hard_regno_mode_ok (REGNO,MODE) 512 513 /* Value is 1 if it is a good idea to tie two pseudo registers when one has 514 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce 515 different values for MODE1 and MODE2, for any hard reg, then this must be 516 0 for correct output. 517 518 All modes are tieable except QImode. */ 519 #define MODES_TIEABLE_P(MODE1, MODE2) \ 520 (((MODE1) == (MODE2)) \ 521 || ((MODE1) != QImode && (MODE2) != QImode)) 522 523 524 /* Define the classes of registers for register constraints in the 525 machine description. Also define ranges of constants. 526 527 One of the classes must always be named ALL_REGS and include all hard regs. 528 If there is more than one class, another class must be named NO_REGS 529 and contain no registers. 530 531 The name GENERAL_REGS must be the name of a class (or an alias for 532 another name such as ALL_REGS). This is the class of registers 533 that is allowed by "g" or "r" in a register constraint. 534 Also, registers outside this class are allocated only when 535 instructions express preferences for them. 536 537 The classes must be numbered in nondecreasing order; that is, 538 a larger-numbered class must never be contained completely 539 in a smaller-numbered class. 540 541 For any two classes, it is very desirable that there be another 542 class that represents their union. */ 543 544 /* The M68hc11 has so fiew registers that it's not possible for GCC to 545 do any register allocation without breaking. We extend the processor 546 registers by having soft registers. These registers are treated as 547 hard registers by GCC but they are located in memory and accessed by page0 548 accesses (IND mode). */ 549 enum reg_class 550 { 551 NO_REGS, 552 D_REGS, /* 16-bit data register */ 553 X_REGS, /* 16-bit X register */ 554 Y_REGS, /* 16-bit Y register */ 555 SP_REGS, /* 16 bit stack pointer */ 556 DA_REGS, /* 8-bit A reg. */ 557 DB_REGS, /* 8-bit B reg. */ 558 Z_REGS, /* 16-bit fake Z register */ 559 D8_REGS, /* 8-bit A or B reg. */ 560 Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */ 561 D_OR_X_REGS, /* D or X register */ 562 D_OR_Y_REGS, /* D or Y register */ 563 D_OR_SP_REGS, /* D or SP register */ 564 X_OR_Y_REGS, /* IX or Y register */ 565 A_REGS, /* 16-bit address register (X, Y, Z) */ 566 X_OR_SP_REGS, /* X or SP register */ 567 Y_OR_SP_REGS, /* Y or SP register */ 568 X_OR_Y_OR_D_REGS, /* X, Y or D */ 569 A_OR_D_REGS, /* X, Y, Z or D */ 570 A_OR_SP_REGS, /* X, Y, Z or SP */ 571 H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */ 572 S_REGS, /* 16-bit soft register */ 573 D_OR_S_REGS, /* 16-bit soft register or D register */ 574 X_OR_S_REGS, /* 16-bit soft register or X register */ 575 Y_OR_S_REGS, /* 16-bit soft register or Y register */ 576 Z_OR_S_REGS, /* 16-bit soft register or Z register */ 577 SP_OR_S_REGS, /* 16-bit soft register or SP register */ 578 D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */ 579 D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */ 580 D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */ 581 A_OR_S_REGS, /* 16-bit soft register or X, Y registers */ 582 D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */ 583 TMP_REGS, /* 16 bit fake scratch register */ 584 D_OR_A_OR_TMP_REGS, /* General scratch register */ 585 G_REGS, /* 16-bit general register 586 (H_REGS + soft registers) */ 587 ALL_REGS, 588 LIM_REG_CLASSES 589 }; 590 591 /* alias GENERAL_REGS to G_REGS. */ 592 #define GENERAL_REGS G_REGS 593 594 #define N_REG_CLASSES (int) LIM_REG_CLASSES 595 596 /* Give names of register classes as strings for dump file. */ 597 #define REG_CLASS_NAMES \ 598 { "NO_REGS", \ 599 "D_REGS", \ 600 "X_REGS", \ 601 "Y_REGS", \ 602 "SP_REGS", \ 603 "DA_REGS", \ 604 "DB_REGS", \ 605 "D8_REGS", \ 606 "Z_REGS", \ 607 "Q_REGS", \ 608 "D_OR_X_REGS", \ 609 "D_OR_Y_REGS", \ 610 "D_OR_SP_REGS", \ 611 "X_OR_Y_REGS", \ 612 "A_REGS", \ 613 "X_OR_SP_REGS", \ 614 "Y_OR_SP_REGS", \ 615 "X_OR_Y_OR_D_REGS", \ 616 "A_OR_D_REGS", \ 617 "A_OR_SP_REGS", \ 618 "H_REGS", \ 619 "S_REGS", \ 620 "D_OR_S_REGS", \ 621 "X_OR_S_REGS", \ 622 "Y_OR_S_REGS", \ 623 "Z_OR_S_REGS", \ 624 "SP_OR_S_REGS", \ 625 "D_OR_X_OR_S_REGS", \ 626 "D_OR_Y_OR_S_REGS", \ 627 "D_OR_SP_OR_S_REGS", \ 628 "A_OR_S_REGS", \ 629 "D_OR_A_OR_S_REGS", \ 630 "TMP_REGS", \ 631 "D_OR_A_OR_TMP_REGS", \ 632 "G_REGS", \ 633 "ALL_REGS" } 634 635 /* An initializer containing the contents of the register classes, 636 as integers which are bit masks. The Nth integer specifies the 637 contents of class N. The way the integer MASK is interpreted is 638 that register R is in the class if `MASK & (1 << R)' is 1. */ 639 640 /*-------------------------------------------------------------- 641 X 0x00000001 642 D 0x00000002 643 Y 0x00000004 644 SP 0x00000008 645 PC 0x00000010 646 A 0x00000020 647 B 0x00000040 648 CCR 0x00000080 649 Z 0x00000100 650 FRAME 0x00000200 651 ZTMP 0x00000400 652 ZREG 0x00000800 653 XYREG 0x00001000 654 FAKE 0x00002000 655 Di 0xFFFFc000, 0x03FFF 656 SFRAME 0x00000000, 0x04000 657 AP 0x00000000, 0x08000 658 659 D_OR_X_REGS represents D+X. It is used for 32-bits numbers. 660 A_REGS represents a valid base register for indexing. It represents 661 X,Y and the Z register. 662 S_REGS represents the soft-registers. This includes the hard frame 663 and soft frame registers. 664 --------------------------------------------------------------*/ 665 666 #define REG_CLASS_CONTENTS \ 667 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \ 668 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \ 669 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \ 670 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \ 671 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \ 672 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \ 673 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \ 674 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \ 675 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \ 676 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \ 677 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \ 678 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \ 679 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \ 680 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \ 681 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \ 682 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \ 683 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \ 684 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \ 685 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \ 686 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \ 687 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \ 688 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \ 689 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \ 690 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \ 691 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \ 692 /* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \ 693 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \ 694 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \ 695 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \ 696 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \ 697 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \ 698 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \ 699 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \ 700 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \ 701 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \ 702 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }} 703 704 705 /* set up a C expression whose value is a register class containing hard 706 register REGNO */ 707 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \ 708 || (REGNO) == HARD_B_REGNUM) 709 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X))) 710 711 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM) 712 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 713 714 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM) 715 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X))) 716 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM) 717 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X))) 718 719 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM) 720 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X))) 721 722 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM) 723 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X))) 724 725 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) 726 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) 727 728 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM) 729 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X))) 730 731 /* Address register. */ 732 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \ 733 || (REGNO) == HARD_Y_REGNUM \ 734 || (REGNO) == HARD_Z_REGNUM) 735 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) 736 737 /* M68hc11 hard registers. */ 738 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \ 739 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO)) 740 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X))) 741 742 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM) 743 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X))) 744 745 /* Soft registers (or register emulation for gcc). The temporary register 746 used by insn template must be part of the S_REGS class so that it 747 matches the 'u' constraint. */ 748 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \ 749 && (REGNO) <= SOFT_REG_LAST \ 750 && (REGNO) != FAKE_CLOBBER_REGNUM) 751 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) 752 753 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) 754 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) 755 756 /* General register. */ 757 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \ 758 || ((REGNO) == HARD_PC_REGNUM) \ 759 || ((REGNO) == HARD_FP_REGNUM) \ 760 || ((REGNO) == SOFT_FP_REGNUM) \ 761 || ((REGNO) == FAKE_CLOBBER_REGNUM) \ 762 || ((REGNO) == SOFT_AP_REGNUM)) 763 764 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X))) 765 766 #define REGNO_REG_CLASS(REGNO) \ 767 (D_REGNO_P (REGNO) ? D_REGS : \ 768 (X_REGNO_P (REGNO) ? X_REGS : \ 769 (Y_REGNO_P (REGNO) ? Y_REGS : \ 770 (SP_REGNO_P (REGNO) ? SP_REGS : \ 771 (Z_REGNO_P (REGNO) ? Z_REGS : \ 772 (H_REGNO_P (REGNO) ? H_REGS : \ 773 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \ 774 (S_REGNO_P (REGNO) ? S_REGS : \ 775 (DA_REGNO_P (REGNO) ? DA_REGS: \ 776 (DB_REGNO_P (REGNO) ? DB_REGS: \ 777 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))) 778 779 780 /* Get reg_class from a letter in the machine description. */ 781 782 extern enum reg_class m68hc11_tmp_regs_class; 783 #define REG_CLASS_FROM_LETTER(C) \ 784 ((C) == 'a' ? DA_REGS : \ 785 (C) == 'A' ? A_REGS : \ 786 (C) == 'b' ? DB_REGS : \ 787 (C) == 'B' ? X_OR_Y_REGS : \ 788 (C) == 'd' ? D_REGS : \ 789 (C) == 'D' ? D_OR_X_REGS : \ 790 (C) == 'q' ? Q_REGS : \ 791 (C) == 'h' ? H_REGS : \ 792 (C) == 't' ? TMP_REGS : \ 793 (C) == 'u' ? S_REGS : \ 794 (C) == 'v' ? m68hc11_tmp_regs_class : \ 795 (C) == 'w' ? SP_REGS : \ 796 (C) == 'x' ? X_REGS : \ 797 (C) == 'y' ? Y_REGS : \ 798 (C) == 'z' ? Z_REGS : NO_REGS) 799 800 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS) 801 802 #define SMALL_REGISTER_CLASSES 1 803 804 /* A C expression that is nonzero if hard register number REGNO2 can be 805 considered for use as a rename register for REGNO1 */ 806 807 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 808 m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2)) 809 810 /* A C expression whose value is nonzero if pseudos that have been 811 assigned to registers of class CLASS would likely be spilled 812 because registers of CLASS are needed for spill registers. 813 814 The default value of this macro returns 1 if CLASS has exactly one 815 register and zero otherwise. On most machines, this default 816 should be used. Only define this macro to some other expression 817 if pseudo allocated by `local-alloc.c' end up in memory because 818 their hard registers were needed for spill registers. If this 819 macro returns nonzero for those classes, those pseudos will only 820 be allocated by `global.c', which knows how to reallocate the 821 pseudo to another register. If there would not be another 822 register available for reallocation, you should not change the 823 definition of this macro since the only effect of such a 824 definition would be to slow down register allocation. */ 825 826 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 827 (((CLASS) == D_REGS) \ 828 || ((CLASS) == X_REGS) \ 829 || ((CLASS) == Y_REGS) \ 830 || ((CLASS) == A_REGS) \ 831 || ((CLASS) == SP_REGS) \ 832 || ((CLASS) == D_OR_X_REGS) \ 833 || ((CLASS) == D_OR_Y_REGS) \ 834 || ((CLASS) == X_OR_SP_REGS) \ 835 || ((CLASS) == Y_OR_SP_REGS) \ 836 || ((CLASS) == D_OR_SP_REGS)) 837 838 /* Return the maximum number of consecutive registers needed to represent 839 mode MODE in a register of class CLASS. */ 840 #define CLASS_MAX_NREGS(CLASS, MODE) \ 841 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \ 842 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \ 843 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 844 845 /* The letters I, J, K, L and M in a register constraint string 846 can be used to stand for particular ranges of immediate operands. 847 This macro defines what the ranges are. 848 C is the letter, and VALUE is a constant value. 849 Return 1 if VALUE is in the range specified by C. 850 851 `K' is for 0. 852 `L' is for range -65536 to 65536 853 `M' is for values whose 16-bit low part is 0 854 'N' is for +1 or -1. 855 'O' is for 16 (for rotate using swap). 856 'P' is for range -8 to 2 (used by addhi_sp) 857 858 'I', 'J' are not used. */ 859 860 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 861 ((C) == 'K' ? (VALUE) == 0 : \ 862 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \ 863 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \ 864 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \ 865 (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \ 866 (C) == 'O' ? (VALUE) == 16 : \ 867 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0) 868 869 /* Similar, but for floating constants, and defining letters G and H. 870 871 `G' is for 0.0. */ 872 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 873 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ 874 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) 875 876 /* 'U' represents certain kind of memory indexed operand for 68HC12. 877 and any memory operand for 68HC11. */ 878 #define EXTRA_CONSTRAINT(OP, C) \ 879 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \ 880 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \ 881 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \ 882 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \ 883 && non_push_operand (OP, GET_MODE (OP))) : 0) 884 885 886 /* Stack layout; function entry, exit and calling. */ 887 888 /* Define this if pushing a word on the stack 889 makes the stack pointer a smaller address. */ 890 #define STACK_GROWS_DOWNWARD 891 892 /* Define this if the nominal address of the stack frame 893 is at the high-address end of the local variables; 894 that is, each additional local variable allocated 895 goes at a more negative offset in the frame. 896 897 Don't define for 68HC11, the frame pointer is the bottom 898 of local variables. */ 899 /* #define FRAME_GROWS_DOWNWARD */ 900 901 /* Define this if successive arguments to a function occupy decreasing 902 addresses in the stack. */ 903 /* #define ARGS_GROW_DOWNWARD */ 904 905 /* Offset within stack frame to start allocating local variables at. 906 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 907 first local allocated. Otherwise, it is the offset to the BEGINNING 908 of the first local allocated. */ 909 #define STARTING_FRAME_OFFSET 0 910 911 /* Offset of first parameter from the argument pointer register value. */ 912 913 #define FIRST_PARM_OFFSET(FNDECL) 2 914 915 /* After the prologue, RA is at 0(AP) in the current frame. */ 916 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 917 ((COUNT) == 0 \ 918 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ 919 : 0) 920 921 /* Before the prologue, the top of the frame is at 2(sp). */ 922 #define INCOMING_FRAME_SP_OFFSET 2 923 924 /* Define this if functions should assume that stack space has been 925 allocated for arguments even when their values are passed in 926 registers. 927 928 The value of this macro is the size, in bytes, of the area reserved for 929 arguments passed in registers. 930 931 This space can either be allocated by the caller or be a part of the 932 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 933 says which. */ 934 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */ 935 936 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack 937 parameters don't skip the area specified by REG_PARM_STACK_SPACE. 938 Normally, when a parameter is not passed in registers, it is placed on 939 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro 940 suppresses this behavior and causes the parameter to be passed on the 941 stack in its natural location. */ 942 /* #define STACK_PARMS_IN_REG_PARM_AREA */ 943 944 /* Register to use for pushing function arguments. */ 945 #define STACK_POINTER_REGNUM HARD_SP_REGNUM 946 947 /* Base register for access to local variables of the function. */ 948 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM 949 950 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM 951 952 /* Base register for access to arguments of the function. */ 953 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM 954 955 /* Register in which static-chain is passed to a function. */ 956 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM 957 958 959 /* Definitions for register eliminations. 960 961 This is an array of structures. Each structure initializes one pair 962 of eliminable registers. The "from" register number is given first, 963 followed by "to". Eliminations of the same "from" register are listed 964 in order of preference. 965 966 We have two registers that are eliminated on the 6811. The psuedo arg 967 pointer and pseudo frame pointer registers can always be eliminated; 968 they are replaced with either the stack or the real frame pointer. */ 969 970 #define ELIMINABLE_REGS \ 971 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 972 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 973 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 974 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 975 976 /* Value should be nonzero if functions must have frame pointers. 977 Zero means the frame pointer need not be set up (and parms may be 978 accessed via the stack pointer) in functions that seem suitable. 979 This is computed in `reload', in reload1.c. */ 980 #define FRAME_POINTER_REQUIRED 0 981 982 /* Given FROM and TO register numbers, say whether this elimination is allowed. 983 Frame pointer elimination is automatically handled. 984 985 All other eliminations are valid. */ 986 987 #define CAN_ELIMINATE(FROM, TO) \ 988 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 989 ? ! frame_pointer_needed \ 990 : 1) 991 992 993 /* Define the offset between two registers, one to be eliminated, and the other 994 its replacement, at the start of a routine. */ 995 996 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 997 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); } 998 999 1000 /* Passing Function Arguments on the Stack. */ 1001 1002 /* When a prototype says `char' or `short', really pass an `int'. */ 1003 /* #define PROMOTE_PROTOTYPES */ 1004 1005 /* If we generate an insn to push BYTES bytes, this says how many the 1006 stack pointer really advances by. No rounding or alignment needed 1007 for MC6811. */ 1008 #define PUSH_ROUNDING(BYTES) (BYTES) 1009 1010 /* Value is 1 if returning from a function call automatically pops the 1011 arguments described by the number-of-args field in the call. FUNTYPE is 1012 the data type of the function (as a tree), or for a library call it is 1013 an identifier node for the subroutine name. 1014 1015 The standard MC6811 call, with arg count word, includes popping the 1016 args as part of the call template. */ 1017 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1018 1019 /* Nonzero if type TYPE should be returned in memory. 1020 Blocks and data types largers than 4 bytes cannot be returned 1021 in the register (D + X = 4). */ 1022 #define RETURN_IN_MEMORY(TYPE) \ 1023 ((TYPE_MODE (TYPE) == BLKmode) \ 1024 ? (int_size_in_bytes (TYPE) > 4) \ 1025 : (GET_MODE_SIZE (TYPE_MODE (TYPE)) > 4)) 1026 1027 1028 /* Passing Arguments in Registers. */ 1029 1030 /* Define a data type for recording info about an argument list 1031 during the scan of that argument list. This data type should 1032 hold all necessary information about the function itself 1033 and about the args processed so far, enough to enable macros 1034 such as FUNCTION_ARG to determine where the next arg should go. */ 1035 1036 typedef struct m68hc11_args 1037 { 1038 int words; 1039 int nregs; 1040 } CUMULATIVE_ARGS; 1041 1042 /* A C expression that indicates when an argument must be passed by reference. 1043 If nonzero for an argument, a copy of that argument is made in memory and a 1044 pointer to the argument is passed instead of the argument itself. 1045 The pointer is passed in whatever way is appropriate for passing a pointer 1046 to that type. 1047 1048 64-bit numbers are passed by reference. */ 1049 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1050 m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) 1051 1052 1053 /* If defined, a C expression which determines whether, and in which direction, 1054 to pad out an argument with extra space. The value should be of type 1055 `enum direction': either `upward' to pad above the argument, 1056 `downward' to pad below, or `none' to inhibit padding. 1057 1058 Structures are stored left shifted in their argument slot. */ 1059 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1060 m68hc11_function_arg_padding ((MODE), (TYPE)) 1061 1062 #undef PAD_VARARGS_DOWN 1063 #define PAD_VARARGS_DOWN \ 1064 (m68hc11_function_arg_padding (TYPE_MODE (type), type) == downward) 1065 1066 /* A C expression that indicates when it is the called function's 1067 responsibility to make a copy of arguments passed by invisible 1068 reference. Normally, the caller makes a copy and passes the 1069 address of the copy to the routine being called. When 1070 FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller 1071 does not make a copy. Instead, it passes a pointer to the "live" 1072 value. The called function must not modify this value. If it can 1073 be determined that the value won't be modified, it need not make a 1074 copy; otherwise a copy must be made. */ 1075 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ 1076 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED)) 1077 1078 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a 1079 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ 1080 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ 1081 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 1082 1083 /* Update the data in CUM to advance over an argument of mode MODE and data 1084 type TYPE. (TYPE is null for libcalls where that information may not be 1085 available.) */ 1086 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1087 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED)) 1088 1089 /* Define where to put the arguments to a function. 1090 Value is zero to push the argument on the stack, 1091 or a hard register in which to store the argument. 1092 1093 MODE is the argument's machine mode. 1094 TYPE is the data type of the argument (as a tree). 1095 This is null for libcalls where that information may 1096 not be available. 1097 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1098 the preceding args and about the function being called. 1099 NAMED is nonzero if this argument is a named parameter 1100 (otherwise it is an extra parameter matching an ellipsis). */ 1101 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1102 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED)) 1103 1104 /* Define the profitability of saving registers around calls. 1105 1106 Disable this because the saving instructions generated by 1107 caller-save need a reload and the way it is implemented, 1108 it forbids all spill registers at that point. Enabling 1109 caller saving results in spill failure. */ 1110 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 1111 1112 /* For an arg passed partly in registers and partly in memory, 1113 this is the number of registers used. 1114 For args passed entirely in registers or entirely in memory, zero. 1115 1116 Passing an arg partly in register and memory does not work at all. 1117 Don't do that. */ 1118 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) 1119 1120 /* 1 if N is a possible register number for function argument passing. 1121 D is for 16-bit values, X is for 32-bit (X+D). */ 1122 #define FUNCTION_ARG_REGNO_P(N) \ 1123 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) 1124 1125 /* All return values are in the D or X+D registers: 1126 - 8 and 16-bit values are returned in D. 1127 BLKmode are passed in D as pointer. 1128 - 32-bit values are returned in X + D. 1129 The high part is passed in X and the low part in D. 1130 For GCC, the register number must be HARD_X_REGNUM. */ 1131 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1132 gen_rtx (REG, TYPE_MODE (VALTYPE), \ 1133 ((TYPE_MODE (VALTYPE) == BLKmode \ 1134 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \ 1135 ? HARD_D_REGNUM : HARD_X_REGNUM)) 1136 1137 #define LIBCALL_VALUE(MODE) \ 1138 gen_rtx (REG, MODE, \ 1139 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \ 1140 ? HARD_D_REGNUM : HARD_X_REGNUM)) 1141 1142 /* 1 if N is a possible register number for a function value. */ 1143 #define FUNCTION_VALUE_REGNO_P(N) \ 1144 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM) 1145 1146 /* Register in which address to store a structure value is passed to a 1147 function. */ 1148 #define STRUCT_VALUE_REGNUM HARD_D_REGNUM 1149 1150 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1151 the stack pointer does not matter. The value is tested only in functions 1152 that have frame pointers. No definition is equivalent to always zero. */ 1153 #define EXIT_IGNORE_STACK 0 1154 1155 1156 /* Generating Code for Profiling. */ 1157 1158 /* Output assembler code to FILE to increment profiler label # LABELNO 1159 for profiling a function entry. */ 1160 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1161 fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO)) 1162 /* Length in units of the trampoline for entering a nested function. */ 1163 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9) 1164 1165 /* A C statement to initialize the variable parts of a trampoline. 1166 ADDR is an RTX for the address of the trampoline; FNADDR is an 1167 RTX for the address of the nested function; STATIC_CHAIN is an 1168 RTX for the static chain value that should be passed to the 1169 function when it is called. */ 1170 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1171 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1172 1173 1174 /* `INIT_TARGET_OPTABS' 1175 Define this macro as a C statement that declares additional library 1176 routines renames existing ones. `init_optabs' calls this macro 1177 after initializing all the normal library routines. 1178 1179 Overrides the memcpy */ 1180 1181 #define INIT_TARGET_OPTABS \ 1182 do \ 1183 { \ 1184 memcpy_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcpy"); \ 1185 memcmp_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memcmp"); \ 1186 memset_libfunc = gen_rtx_SYMBOL_REF (Pmode, "__memset"); \ 1187 } \ 1188 while (0) 1189 1190 1191 /* Addressing modes, and classification of registers for them. */ 1192 1193 /* The 68HC12 has all the post/pre increment/decrement modes. */ 1194 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1195 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1196 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1197 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1198 1199 /* The class value for base registers. This depends on the target: 1200 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value 1201 is stored at init time. */ 1202 extern enum reg_class m68hc11_base_reg_class; 1203 #define BASE_REG_CLASS m68hc11_base_reg_class 1204 1205 /* The class value for index registers. This is NO_REGS for 68HC11. */ 1206 1207 extern enum reg_class m68hc11_index_reg_class; 1208 #define INDEX_REG_CLASS m68hc11_index_reg_class 1209 1210 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero 1211 only if REGNO is a hard reg of the suitable class or a pseudo reg currently 1212 allocated to a suitable hard reg. Since they use reg_renumber, they are 1213 safe only once reg_renumber has been allocated, which happens in 1214 local-alloc.c. */ 1215 1216 1217 /* Internal macro, return 1 if REGNO is a valid base register. */ 1218 #define REG_VALID_P(REGNO) (1) /* ? */ 1219 1220 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER]; 1221 #define REG_VALID_FOR_BASE_P(REGNO) \ 1222 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \ 1223 && m68hc11_reg_valid_for_base[REGNO]) 1224 1225 /* Internal macro, return 1 if REGNO is a valid index register. */ 1226 extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER]; 1227 #define REG_VALID_FOR_INDEX_P(REGNO) \ 1228 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \ 1229 && m68hc11_reg_valid_for_index[REGNO]) 1230 1231 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */ 1232 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ 1233 ((REGNO) >= FIRST_PSEUDO_REGISTER \ 1234 || REG_VALID_FOR_BASE_P (REGNO) \ 1235 || (REGNO) == FRAME_POINTER_REGNUM \ 1236 || (REGNO) == HARD_FRAME_POINTER_REGNUM \ 1237 || (REGNO) == ARG_POINTER_REGNUM \ 1238 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) 1239 1240 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */ 1241 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ 1242 (TARGET_M6812 \ 1243 && ((REGNO) >= FIRST_PSEUDO_REGISTER \ 1244 || REG_VALID_FOR_INDEX_P (REGNO) \ 1245 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) 1246 1247 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */ 1248 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \ 1249 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \ 1250 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) 1251 1252 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */ 1253 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \ 1254 (TARGET_M6812 \ 1255 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \ 1256 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) 1257 1258 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \ 1259 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \ 1260 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO))) 1261 1262 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \ 1263 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \ 1264 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO))) 1265 1266 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO) 1267 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO) 1268 1269 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X)) 1270 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X)) 1271 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X)) 1272 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X)) 1273 1274 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */ 1275 #define IS_STACK_PUSH(operand) \ 1276 ((GET_CODE (operand) == MEM) \ 1277 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \ 1278 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) 1279 1280 #define IS_STACK_POP(operand) \ 1281 ((GET_CODE (operand) == MEM) \ 1282 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \ 1283 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) 1284 1285 /* 1 if X is an rtx for a constant that is a valid address. */ 1286 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) 1287 1288 /* Maximum number of registers that can appear in a valid memory address */ 1289 #define MAX_REGS_PER_ADDRESS 2 1290 1291 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a 1292 valid memory address for an instruction. The MODE argument is the 1293 machine mode for the MEM expression that wants to use this address. */ 1294 1295 /*-------------------------------------------------------------- 1296 Valid addresses are either direct or indirect (MEM) versions 1297 of the following forms: 1298 constant N 1299 register ,X 1300 indexed N,X 1301 --------------------------------------------------------------*/ 1302 1303 /* The range of index that is allowed by indirect addressing. */ 1304 1305 #define VALID_MIN_OFFSET m68hc11_min_offset 1306 #define VALID_MAX_OFFSET m68hc11_max_offset 1307 1308 /* The offset values which are allowed by the n,x and n,y addressing modes. 1309 Take into account the size of the mode because we may have to add 1310 a mode offset to access the lowest part of the data. 1311 (For example, for an SImode, the last valid offset is 252.) */ 1312 #define VALID_CONSTANT_OFFSET_P(X,MODE) \ 1313 (((GET_CODE (X) == CONST_INT) && \ 1314 ((INTVAL (X) >= VALID_MIN_OFFSET) \ 1315 && ((INTVAL (X) <= VALID_MAX_OFFSET \ 1316 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \ 1317 || (TARGET_M6812 \ 1318 && ((GET_CODE (X) == SYMBOL_REF) \ 1319 || GET_CODE (X) == LABEL_REF \ 1320 || GET_CODE (X) == CONST))) 1321 1322 /* This is included to allow stack push/pop operations. Special hacks in the 1323 md and m6811.c files exist to support this. */ 1324 #define PUSH_POP_ADDRESS_P(X) \ 1325 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \ 1326 && SP_REG_P (XEXP (X, 0))) 1327 1328 /* Go to ADDR if X is a valid address. */ 1329 #ifndef REG_OK_STRICT 1330 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1331 { \ 1332 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \ 1333 } 1334 #else 1335 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1336 { \ 1337 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \ 1338 } 1339 #endif 1340 1341 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its 1342 validity for a certain class. We have two alternate definitions for each 1343 of them. The usual definition accepts all pseudo regs; the other rejects 1344 them unless they have been allocated suitable hard regs. The symbol 1345 REG_OK_STRICT causes the latter definition to be used. 1346 1347 Most source files want to accept pseudo regs in the hope that they will 1348 get allocated to the class that the insn wants them to be in. Source files 1349 for reload pass need to be strict. After reload, it makes no difference, 1350 since pseudo regs have been eliminated by then. */ 1351 1352 #ifndef REG_OK_STRICT 1353 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1354 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) 1355 1356 /* Nonzero if X is a hard reg that can be used as an index. */ 1357 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) 1358 #else 1359 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) 1360 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) 1361 #endif 1362 1363 1364 /* Try machine-dependent ways of modifying an illegitimate address 1365 to be legitimate. If we find one, return the new, valid address. 1366 This macro is used in only one place: `memory_address' in explow.c. 1367 1368 OLDX is the address as it was before break_out_memory_refs was called. 1369 In some cases it is useful to look at this to decide what needs to be done. 1370 1371 MODE and WIN are passed so that this macro can use 1372 GO_IF_LEGITIMATE_ADDRESS. 1373 1374 It is always safe for this macro to do nothing. 1375 It exists to recognize opportunities to optimize the output. */ 1376 1377 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1378 { rtx operand = (X); \ 1379 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \ 1380 { \ 1381 (X) = operand; \ 1382 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \ 1383 } \ 1384 } 1385 1386 /* Go to LABEL if ADDR (a legitimate address expression) 1387 has an effect that depends on the machine mode it is used for. */ 1388 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1389 { \ 1390 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 1391 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 1392 goto LABEL; \ 1393 } 1394 1395 /* Nonzero if the constant value X is a legitimate general operand. 1396 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1397 1398 #define LEGITIMATE_CONSTANT_P(X) 1 1399 1400 1401 /* Tell final.c how to eliminate redundant test instructions. */ 1402 1403 #define NOTICE_UPDATE_CC(EXP, INSN) \ 1404 m68hc11_notice_update_cc ((EXP), (INSN)) 1405 1406 /* Compute the cost of computing a constant rtl expression RTX whose rtx-code 1407 is CODE. The body of this macro is a portion of a switch statement. If 1408 the code is computed here, return it with a return statement. Otherwise, 1409 break from the switch. 1410 1411 Constants are cheap. Moving them in registers must be avoided 1412 because most instructions do not handle two register operands. */ 1413 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 1414 case CONST_INT: \ 1415 /* Logical and arithmetic operations with a constant */ \ 1416 /* operand are better because they are not supported */ \ 1417 /* with two registers. */ \ 1418 /* 'clr' is slow */ \ 1419 if ((OUTER_CODE) == SET && (RTX) == const0_rtx) \ 1420 /* After reload, the reload_cse pass checks the cost */ \ 1421 /* to change a SET into a PLUS. Make const0 cheap. */ \ 1422 return 1 - reload_completed; \ 1423 else \ 1424 return 0; \ 1425 case CONST: \ 1426 case LABEL_REF: \ 1427 case SYMBOL_REF: \ 1428 if ((OUTER_CODE) == SET) \ 1429 return 1 - reload_completed; \ 1430 return 0; \ 1431 case CONST_DOUBLE: \ 1432 return 0; 1433 1434 #define RTX_COSTS(X,CODE,OUTER_CODE) \ 1435 case ROTATE: \ 1436 case ROTATERT: \ 1437 case ASHIFT: \ 1438 case LSHIFTRT: \ 1439 case ASHIFTRT: \ 1440 case MINUS: \ 1441 case PLUS: \ 1442 case AND: \ 1443 case XOR: \ 1444 case IOR: \ 1445 case UDIV: \ 1446 case DIV: \ 1447 case MOD: \ 1448 case MULT: \ 1449 case NEG: \ 1450 case SIGN_EXTEND: \ 1451 case NOT: \ 1452 case COMPARE: \ 1453 case ZERO_EXTEND: \ 1454 case IF_THEN_ELSE: \ 1455 return m68hc11_rtx_costs (X, CODE, OUTER_CODE); 1456 1457 /* An expression giving the cost of an addressing mode that contains 1458 ADDRESS. If not defined, the cost is computed from the ADDRESS 1459 expression and the `CONST_COSTS' values. */ 1460 1461 #define ADDRESS_COST(RTX) m68hc11_address_cost (RTX) 1462 1463 /* Move costs between classes of registers */ 1464 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1465 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2)) 1466 1467 /* Move cost between register and memory. 1468 - Move to a 16-bit register is reasonable, 1469 - Move to a soft register can be expensive. */ 1470 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 1471 m68hc11_memory_move_cost ((MODE),(CLASS),(IN)) 1472 1473 /* A C expression for the cost of a branch instruction. A value of 1 1474 is the default; other values are interpreted relative to that. 1475 1476 Pretend branches are cheap because GCC generates sub-optimal code 1477 for the default value. */ 1478 #define BRANCH_COST 0 1479 1480 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1481 #define SLOW_BYTE_ACCESS 0 1482 1483 /* It is as good to call a constant function address as to call an address 1484 kept in a register. */ 1485 #define NO_FUNCTION_CSE 1486 1487 /* Try a machine-dependent way of reloading an illegitimate address 1488 operand. If we find one, push the reload and jump to WIN. This 1489 macro is used in only one place: `find_reloads_address' in reload.c. 1490 1491 For M68HC11, we handle large displacements of a base register 1492 by splitting the addend accors an addhi3 insn. 1493 1494 For M68HC12, the 64K offset range is available. 1495 */ 1496 1497 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1498 do { \ 1499 /* We must recognize output that we have already generated ourselves. */ \ 1500 if (GET_CODE (X) == PLUS \ 1501 && GET_CODE (XEXP (X, 0)) == PLUS \ 1502 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1503 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 1504 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1505 { \ 1506 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1507 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1508 OPNUM, TYPE); \ 1509 goto WIN; \ 1510 } \ 1511 if (GET_CODE (X) == PLUS \ 1512 && GET_CODE (XEXP (X, 0)) == REG \ 1513 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1514 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \ 1515 { \ 1516 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1517 HOST_WIDE_INT low, high; \ 1518 high = val & (~0x0FF); \ 1519 low = val & 0x00FF; \ 1520 if (low >= 256-15) { high += 16; low -= 16; } \ 1521 /* Reload the high part into a base reg; leave the low part \ 1522 in the mem directly. */ \ 1523 \ 1524 X = gen_rtx_PLUS (Pmode, \ 1525 gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 1526 GEN_INT (high)), \ 1527 GEN_INT (low)); \ 1528 \ 1529 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1530 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1531 OPNUM, TYPE); \ 1532 goto WIN; \ 1533 } \ 1534 } while (0) 1535 1536 1537 /* Defining the Output Assembler Language. */ 1538 1539 /* A default list of other sections which we might be "in" at any given 1540 time. For targets that use additional sections (e.g. .tdesc) you 1541 should override this definition in the target-specific file which 1542 includes this file. */ 1543 1544 /* Output before read-only data. */ 1545 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text") 1546 1547 /* Output before writable data. */ 1548 #define DATA_SECTION_ASM_OP ("\t.sect\t.data") 1549 1550 /* Output before uninitialized data. */ 1551 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss") 1552 1553 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. 1554 1555 Same as config/elfos.h but don't mark these section SHF_WRITE since 1556 there is no shared library problem. */ 1557 #undef CTORS_SECTION_ASM_OP 1558 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" 1559 1560 #undef DTORS_SECTION_ASM_OP 1561 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" 1562 1563 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor 1564 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor 1565 1566 /* This is how to begin an assembly language file. Most svr4 assemblers want 1567 at least a .file directive to come first, and some want to see a .version 1568 directive come right after that. Here we just establish a default 1569 which generates only the .file directive. If you need a .version 1570 directive for any specific target, you should override this definition 1571 in the target-specific file which includes this one. */ 1572 1573 #undef ASM_FILE_START 1574 #define ASM_FILE_START(FILE) \ 1575 m68hc11_asm_file_start ((FILE), main_input_filename) 1576 1577 /* Comment character */ 1578 #define ASM_COMMENT_START ";" 1579 1580 /* Output to assembler file text saying following lines 1581 may contain character constants, extra white space, comments, etc. */ 1582 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n" 1583 1584 /* Output to assembler file text saying following lines 1585 no longer contain unusual constructs. */ 1586 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n" 1587 1588 /* Write the extra assembler code needed to declare a function properly. 1589 Some svr4 assemblers need to also have something extra said about the 1590 function's return value. We allow for that here. 1591 1592 For 68HC12 we mark functions that return with 'rtc'. The linker 1593 will ensure that a 'call' is really made (instead of 'jsr'). 1594 The debugger needs this information to correctly compute the stack frame. 1595 1596 For 68HC11/68HC12 we also mark interrupt handlers for gdb to 1597 compute the correct stack frame. */ 1598 1599 #undef ASM_DECLARE_FUNCTION_NAME 1600 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 1601 do \ 1602 { \ 1603 fprintf (FILE, "%s", TYPE_ASM_OP); \ 1604 assemble_name (FILE, NAME); \ 1605 putc (',', FILE); \ 1606 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ 1607 putc ('\n', FILE); \ 1608 \ 1609 if (current_function_far) \ 1610 { \ 1611 fprintf (FILE, "\t.far\t"); \ 1612 assemble_name (FILE, NAME); \ 1613 putc ('\n', FILE); \ 1614 } \ 1615 else if (current_function_interrupt \ 1616 || current_function_trap) \ 1617 { \ 1618 fprintf (FILE, "\t.interrupt\t"); \ 1619 assemble_name (FILE, NAME); \ 1620 putc ('\n', FILE); \ 1621 } \ 1622 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 1623 ASM_OUTPUT_LABEL(FILE, NAME); \ 1624 } \ 1625 while (0) 1626 1627 /* Output #ident as a .ident. */ 1628 1629 /* output external reference */ 1630 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ 1631 {fputs ("\t; extern\t", FILE); \ 1632 assemble_name (FILE, NAME); \ 1633 fputs ("\n", FILE);} 1634 1635 1636 1637 /* Store in OUTPUT a string (made with alloca) containing 1638 an assembler-name for a local static variable named NAME. 1639 LABELNO is an integer which is different for each call. */ 1640 1641 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1642 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1643 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1644 1645 /* How to refer to registers in assembler output. This sequence is indexed 1646 by compiler's hard-register-number (see above). */ 1647 #define REGISTER_NAMES \ 1648 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \ 1649 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \ 1650 SOFT_REG_NAMES, "*sframe", "*ap"} 1651 1652 /* Print an instruction operand X on file FILE. CODE is the code from the 1653 %-spec for printing this operand. If `%z3' was used to print operand 1654 3, then CODE is 'z'. */ 1655 1656 #define PRINT_OPERAND(FILE, X, CODE) \ 1657 print_operand (FILE, X, CODE) 1658 1659 /* Print a memory operand whose address is X, on file FILE. */ 1660 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1661 print_operand_address (FILE, ADDR) 1662 1663 /* This is how to output an insn to push/pop a register on the stack. 1664 It need not be very fast code. 1665 1666 Don't define because we don't know how to handle that with 1667 the STATIC_CHAIN_REGNUM (soft register). Saving the static 1668 chain must be made inside FUNCTION_PROFILER. */ 1669 1670 #undef ASM_OUTPUT_REG_PUSH 1671 #undef ASM_OUTPUT_REG_POP 1672 1673 /* This is how to output an element of a case-vector that is relative. */ 1674 1675 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1676 fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL) 1677 1678 /* This is how to output an element of a case-vector that is absolute. */ 1679 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1680 fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE) 1681 1682 /* This is how to output an assembler line that says to advance the 1683 location counter to a multiple of 2**LOG bytes. */ 1684 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1685 do { \ 1686 if ((LOG) > 1) \ 1687 fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \ 1688 } while (0) 1689 1690 1691 /* Assembler Commands for Exception Regions. */ 1692 1693 /* Default values provided by GCC should be ok. Assumming that DWARF-2 1694 frame unwind info is ok for this platform. */ 1695 1696 #undef PREFERRED_DEBUGGING_TYPE 1697 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1698 1699 /* For the support of memory banks we need addresses that indicate 1700 the page number. */ 1701 #define DWARF2_ADDR_SIZE 4 1702 1703 /* SCz 2003-07-08: Don't use as dwarf2 .file/.loc directives because 1704 the linker is doing relaxation and it does not adjust the debug_line 1705 sections when it shrinks the code. This results in invalid addresses 1706 when debugging. This does not bless too much the HC11/HC12 as most 1707 applications are embedded and small, hence a reasonable debug info. 1708 This problem is known for binutils 2.13, 2.14 and mainline. */ 1709 #undef HAVE_AS_DWARF2_DEBUG_LINE 1710 1711 /* The prefix for local labels. You should be able to define this as 1712 an empty string, or any arbitrary string (such as ".", ".L%", etc) 1713 without having to make any other changes to account for the specific 1714 definition. Note it is a string literal, not interpreted by printf 1715 and friends. */ 1716 #define LOCAL_LABEL_PREFIX "." 1717 1718 /* The prefix for immediate operands. */ 1719 #define IMMEDIATE_PREFIX "#" 1720 #define GLOBAL_ASM_OP "\t.globl\t" 1721 1722 1723 /* Miscellaneous Parameters. */ 1724 1725 /* Define the codes that are matched by predicates in m68hc11.c. */ 1726 #define PREDICATE_CODES \ 1727 {"stack_register_operand", {SUBREG, REG}}, \ 1728 {"d_register_operand", {SUBREG, REG}}, \ 1729 {"hard_addr_reg_operand", {SUBREG, REG}}, \ 1730 {"hard_reg_operand", {SUBREG, REG}}, \ 1731 {"m68hc11_logical_operator", {AND, IOR, XOR}}, \ 1732 {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \ 1733 ASHIFT, ASHIFTRT, LSHIFTRT, \ 1734 ROTATE, ROTATERT }}, \ 1735 {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \ 1736 {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \ 1737 {"m68hc11_shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT}},\ 1738 {"m68hc11_eq_compare_operator", {EQ, NE}}, \ 1739 {"non_push_operand", {SUBREG, REG, MEM}}, \ 1740 {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \ 1741 {"tst_operand", {SUBREG, REG, MEM}}, \ 1742 {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \ 1743 CONST_INT, CONST_DOUBLE}}, 1744 1745 /* Specify the machine mode that this machine uses 1746 for the index in the tablejump instruction. */ 1747 #define CASE_VECTOR_MODE Pmode 1748 1749 /* This flag, if defined, says the same insns that convert to a signed fixnum 1750 also convert validly to an unsigned one. */ 1751 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC 1752 1753 /* Max number of bytes we can move from memory to memory in one 1754 reasonably fast instruction. */ 1755 #define MOVE_MAX 2 1756 1757 /* MOVE_RATIO is the number of move instructions that is better than a 1758 block move. Make this small on 6811, since the code size grows very 1759 large with each move. */ 1760 #define MOVE_RATIO 3 1761 1762 /* Define if shifts truncate the shift count which implies one can omit 1763 a sign-extension or zero-extension of a shift count. */ 1764 #define SHIFT_COUNT_TRUNCATED 1 1765 1766 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1767 is done just by pretending it is already truncated. */ 1768 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1769 1770 /* Specify the machine mode that pointers have. After generation of rtl, the 1771 compiler makes no further distinction between pointers and any other 1772 objects of this machine mode. */ 1773 #define Pmode HImode 1774 1775 /* A function address in a call instruction is a byte address (for indexing 1776 purposes) so give the MEM rtx a byte's mode. */ 1777 #define FUNCTION_MODE QImode 1778 1779 /* Allow $ in identifiers */ 1780 #define DOLLARS_IN_IDENTIFIERS 1 1781 1782 /* Machine-dependent reorg pass. 1783 Specific optimizations are defined here: 1784 - this pass changes the Z register into either X or Y 1785 (it preserves X/Y previous values in a memory slot in page0). 1786 1787 When this pass is finished, the global variable 1788 'z_replacement_completed' is set to 2. */ 1789 #define MACHINE_DEPENDENT_REORG(X) m68hc11_reorg (X) 1790 1791 extern int debug_m6811; 1792 extern int z_replacement_completed; 1793 extern int current_function_interrupt; 1794 extern int current_function_trap; 1795 extern int current_function_far; 1796 1797 extern GTY(()) rtx m68hc11_compare_op0; 1798 extern GTY(()) rtx m68hc11_compare_op1; 1799 extern GTY(()) rtx m68hc11_soft_tmp_reg; 1800 extern GTY(()) rtx ix_reg; 1801 extern GTY(()) rtx iy_reg; 1802 extern GTY(()) rtx d_reg; 1803