1 /*- 2 * Copyright (c) 1993 The Regents of the University of California. 3 * Copyright (c) 2008 The DragonFly Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp 31 * $FreeBSD: src/sys/i386/isa/timerreg.h,v 1.6 1999/08/28 00:45:04 peter Exp $ 32 * $DragonFly: src/sys/platform/pc64/isa/timerreg.h,v 1.1 2008/08/29 17:07:20 dillon Exp $ 33 */ 34 35 /* 36 * 37 * Register definitions for the Intel 8253 Programmable Interval Timer. 38 * 39 * This chip has three independent 16-bit down counters that can be 40 * read on the fly. There are three mode registers and three countdown 41 * registers. The countdown registers are addressed directly, via the 42 * first three I/O ports. The three mode registers are accessed via 43 * the fourth I/O port, with two bits in the mode byte indicating the 44 * register. (Why are hardware interfaces always so braindead?). 45 * 46 * To write a value into the countdown register, the mode register 47 * is first programmed with a command indicating the which byte of 48 * the two byte register is to be modified. The three possibilities 49 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then 50 * msb (TMR_MR_BOTH). 51 * 52 * To read the current value ("on the fly") from the countdown register, 53 * you write a "latch" command into the mode register, then read the stable 54 * value from the corresponding I/O port. For example, you write 55 * TMR_MR_LATCH into the corresponding mode register. Presumably, 56 * after doing this, a write operation to the I/O port would result 57 * in undefined behavior (but hopefully not fry the chip). 58 * Reading in this manner has no side effects. 59 * 60 * [IBM-PC] 61 * The outputs of the three timers are connected as follows: 62 * 63 * timer 0 -> irq 0 64 * timer 1 -> dma chan 0 (for dram refresh) 65 * timer 2 -> speaker (via keyboard controller) 66 * 67 * Timer 0 is used to call hardclock. 68 * Timer 2 is used to generate console beeps. 69 * 70 * [PC-9801] 71 * The outputs of the three timers are connected as follows: 72 * 73 * timer 0 -> irq 0 74 * timer 1 -> speaker (via keyboard controller) 75 * timer 2 -> RS232C 76 * 77 * Timer 0 is used to call hardclock. 78 * Timer 1 is used to generate console beeps. 79 * 80 * TIMER_INTTC: Interrupt on Terminal Count. OUT initially low, 81 * goes high on terminal count and remains 82 * high until a new count or a mode 0 control 83 * word is written. 84 * 85 * TIMER_ONESHOT: Hardware Retriggerable One Shot. Out initially high, 86 * out goes low following the trigger and remains low 87 * until terminal count, then goes high and remains 88 * high until the next trigger. 89 * 90 * TIMER_RATEGEN: Rate Generator. OUT is initially high. When the 91 * count has decremented to 1 OUT goes low for one CLK 92 * pulse, then goes high again. Counter reloads and 93 * the sequence is repeated. 94 * 95 * TIMER_SQWAVE: Square Wave Generator. OUT is initially high. When 96 * half the count is expired, OUT goes low. Counter 97 * reloads, OUT goes high, and the sequence repepats. 98 * 99 * TIMER_SWSTROBE: S/W Triggered Strobe. OUT initially high. On 100 * terminal count OUT goes low for one CLK pulse 101 * and then goes high again. Counting stops. 102 * The counting sequence is 'triggered' by writing 103 * the initial count. Writing a control word and 104 * initial count resets and reloads the counter. 105 * 106 * TIMER_HWSTROBE: H/W Triggered Strobe. OUT initially high. A rising 107 * edge on GATE loads the counter and counting begins. 108 * On terminal count OUT goes low for one CLK and then 109 * high again. 110 * 111 * NOTE: the largest possible initial count is 0x0000. This is equivalent 112 * to 2^16 binary and 10^4 BCD counts. The counter does not stop when it 113 * reaches zero. In Modes INTTC, ONESHOT, SWSTROBE, and HWSTROBE the 114 * counter wraps aroudn to the highest count (0xFFFF or 9999bcd) and 115 * continues counting. In MODES RATEGEN and SQWAVE (which are periodic) 116 * the counter reloads itself with the initial count and continues counting 117 * from there. 118 */ 119 120 /* 121 * Macros for specifying values to be written into a mode register. 122 */ 123 #define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ 124 #define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ 125 #define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ 126 #define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ 127 #define TIMER_SEL0 0x00 /* select counter 0 */ 128 #define TIMER_SEL1 0x40 /* select counter 1 */ 129 #define TIMER_SEL2 0x80 /* select counter 2 */ 130 #define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 131 #define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 132 #define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 133 #define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 134 #define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 135 #define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 136 #define TIMER_LATCH 0x00 /* latch counter for reading */ 137 #define TIMER_LSB 0x10 /* r/w counter LSB */ 138 #define TIMER_MSB 0x20 /* r/w counter MSB */ 139 #define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 140 #define TIMER_BCD 0x01 /* count in BCD */ 141 142