1 /* $NetBSD: aic7xxx.c,v 1.148 2024/02/02 22:39:10 andvar Exp $ */
2
3 /*
4 * Core routines and tables shareable across OS platforms.
5 *
6 * Copyright (c) 1994-2002 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: aic7xxx.c,v 1.148 2024/02/02 22:39:10 andvar Exp $
43 *
44 * //depot/aic7xxx/aic7xxx/aic7xxx.c#112 $
45 *
46 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.c,v 1.88 2003/01/20 20:44:55 gibbs Exp $
47 */
48 /*
49 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: aic7xxx.c,v 1.148 2024/02/02 22:39:10 andvar Exp $");
54
55 #include <dev/ic/aic7xxx_osm.h>
56 #include <dev/ic/aic7xxx_inline.h>
57 #include <dev/ic/aic7xxx_cam.h>
58
59 /****************************** Softc Data ************************************/
60 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
61
62 /***************************** Lookup Tables **********************************/
63 const char * const ahc_chip_names[] =
64 {
65 "NONE",
66 "aic7770",
67 "aic7850",
68 "aic7855",
69 "aic7859",
70 "aic7860",
71 "aic7870",
72 "aic7880",
73 "aic7895",
74 "aic7895C",
75 "aic7890/91",
76 "aic7896/97",
77 "aic7892",
78 "aic7899"
79 };
80
81 /*
82 * Hardware error codes.
83 */
84 struct ahc_hard_error_entry {
85 uint8_t errno;
86 const char *errmesg;
87 };
88
89 static struct ahc_hard_error_entry ahc_hard_errors[] = {
90 { ILLHADDR, "Illegal Host Access" },
91 { ILLSADDR, "Illegal Sequencer Address referenced" },
92 { ILLOPCODE, "Illegal Opcode in sequencer program" },
93 { SQPARERR, "Sequencer Parity Error" },
94 { DPARERR, "Data-path Parity Error" },
95 { MPARERR, "Scratch or SCB Memory Parity Error" },
96 { PCIERRSTAT, "PCI Error detected" },
97 { CIOPARERR, "CIOBUS Parity Error" },
98 };
99 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
100
101 static struct ahc_phase_table_entry ahc_phase_table[] =
102 {
103 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
104 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
105 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
106 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
107 { P_COMMAND, MSG_NOOP, "in Command phase" },
108 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
109 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
110 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
111 { P_BUSFREE, MSG_NOOP, "while idle" },
112 { 0, MSG_NOOP, "in unknown phase" }
113 };
114
115 /*
116 * In most cases we only wish to iterate over real phases, so
117 * exclude the last element from the count.
118 */
119 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
120
121 /*
122 * Valid SCSIRATE values. (p. 3-17)
123 * Provides a mapping of transfer periods in ns to the proper value to
124 * stick in the scsixfer reg.
125 */
126 static struct ahc_syncrate ahc_syncrates[] =
127 {
128 /* ultra2 fast/ultra period rate */
129 { 0x42, 0x000, 9, "80.0" },
130 { 0x03, 0x000, 10, "40.0" },
131 { 0x04, 0x000, 11, "33.0" },
132 { 0x05, 0x100, 12, "20.0" },
133 { 0x06, 0x110, 15, "16.0" },
134 { 0x07, 0x120, 18, "13.4" },
135 { 0x08, 0x000, 25, "10.0" },
136 { 0x19, 0x010, 31, "8.0" },
137 { 0x1a, 0x020, 37, "6.67" },
138 { 0x1b, 0x030, 43, "5.7" },
139 { 0x1c, 0x040, 50, "5.0" },
140 { 0x00, 0x050, 56, "4.4" },
141 { 0x00, 0x060, 62, "4.0" },
142 { 0x00, 0x070, 68, "3.6" },
143 { 0x00, 0x000, 0, NULL }
144 };
145
146 /* Our Sequencer Program */
147 #include <dev/microcode/aic7xxx/aic7xxx_seq.h>
148
149 /**************************** Function Declarations ***************************/
150 static void ahc_force_renegotiation(struct ahc_softc *ahc);
151 static struct ahc_tmode_tstate*
152 ahc_alloc_tstate(struct ahc_softc *ahc,
153 u_int scsi_id, char channel);
154 #ifdef AHC_TARGET_MODE
155 static void ahc_free_tstate(struct ahc_softc *ahc,
156 u_int scsi_id, char channel, int force);
157 #endif
158 static struct ahc_syncrate*
159 ahc_devlimited_syncrate(struct ahc_softc *ahc,
160 struct ahc_initiator_tinfo *,
161 u_int *period,
162 u_int *ppr_options,
163 role_t role);
164 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
165 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
166 struct ahc_devinfo *devinfo);
167 static void ahc_scb_devinfo(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo,
169 struct scb *scb);
170 static void ahc_assert_atn(struct ahc_softc *ahc);
171 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
172 struct ahc_devinfo *devinfo,
173 struct scb *scb);
174 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
175 struct ahc_devinfo *devinfo);
176 static void ahc_construct_sdtr(struct ahc_softc *ahc,
177 struct ahc_devinfo *devinfo,
178 u_int period, u_int offset);
179 static void ahc_construct_wdtr(struct ahc_softc *ahc,
180 struct ahc_devinfo *devinfo,
181 u_int bus_width);
182 static void ahc_construct_ppr(struct ahc_softc *ahc,
183 struct ahc_devinfo *devinfo,
184 u_int period, u_int offset,
185 u_int bus_width, u_int ppr_options);
186 static void ahc_clear_msg_state(struct ahc_softc *ahc);
187 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
188 static void ahc_handle_message_phase(struct ahc_softc *ahc);
189 typedef enum {
190 AHCMSG_1B,
191 AHCMSG_2B,
192 AHCMSG_EXT
193 } ahc_msgtype;
194 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
195 u_int msgval, int full);
196 static int ahc_parse_msg(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo);
198 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
199 struct ahc_devinfo *devinfo);
200 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
201 struct ahc_devinfo *devinfo);
202 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
203 static void ahc_handle_devreset(struct ahc_softc *ahc,
204 struct ahc_devinfo *devinfo,
205 cam_status status,
206 const char *message,
207 int verbose_level);
208 #if AHC_TARGET_MODE
209 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
210 struct ahc_devinfo *devinfo,
211 struct scb *scb);
212 #endif
213
214 #if 0
215 static bus_dmamap_callback_t ahc_dmamap_cb;
216 #endif
217 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
218 static int ahc_init_scbdata(struct ahc_softc *ahc);
219 static void ahc_fini_scbdata(struct ahc_softc *ahc);
220 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
221 struct scb *prev_scb,
222 struct scb *scb);
223 static int ahc_qinfifo_count(struct ahc_softc *ahc);
224 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
225 u_int prev, u_int scbptr);
226 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
227 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
228 u_int scbpos, u_int prev);
229 static void ahc_reset_current_bus(struct ahc_softc *ahc);
230 #ifdef AHC_DUMP_SEQ
231 static void ahc_dumpseq(struct ahc_softc *ahc);
232 #endif
233 static void ahc_loadseq(struct ahc_softc *ahc);
234 static int ahc_check_patch(struct ahc_softc *ahc,
235 const struct patch **start_patch,
236 u_int start_instr, u_int *skip_addr);
237 static void ahc_download_instr(struct ahc_softc *ahc,
238 u_int instrptr, uint8_t *dconsts);
239 #ifdef AHC_TARGET_MODE
240 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
241 struct ahc_tmode_lstate *lstate,
242 u_int initiator_id,
243 u_int event_type,
244 u_int event_arg);
245 static void ahc_update_scsiid(struct ahc_softc *ahc,
246 u_int targid_mask);
247 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
248 struct target_cmd *cmd);
249 #endif
250
251 /************************** Added for porting to NetBSD ***********************/
252 static int ahc_createdmamem(bus_dma_tag_t tag,
253 int size,
254 int flags,
255 bus_dmamap_t *mapp,
256 void **vaddr,
257 bus_addr_t *baddr,
258 bus_dma_segment_t *seg,
259 int *nseg,
260 const char *myname, const char *what);
261 static void ahc_freedmamem(bus_dma_tag_t tag,
262 int size,
263 bus_dmamap_t map,
264 void *vaddr,
265 bus_dma_segment_t *seg,
266 int nseg);
267
268 /************************* Sequencer Execution Control ************************/
269 /*
270 * Restart the sequencer program from address zero
271 */
272 void
ahc_restart(struct ahc_softc * ahc)273 ahc_restart(struct ahc_softc *ahc)
274 {
275
276 ahc_pause(ahc);
277
278 /* No more pending messages. */
279 ahc_clear_msg_state(ahc);
280
281 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
282 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
283 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
284 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
285 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
286 ahc_outb(ahc, SAVED_LUN, 0xFF);
287
288 /*
289 * Ensure that the sequencer's idea of TQINPOS
290 * matches our own. The sequencer increments TQINPOS
291 * only after it sees a DMA complete and a reset could
292 * occur before the increment leaving the kernel to believe
293 * the command arrived but the sequencer to not.
294 */
295 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
296
297 /* Always allow reselection */
298 ahc_outb(ahc, SCSISEQ,
299 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
300 if ((ahc->features & AHC_CMD_CHAN) != 0) {
301 /* Ensure that no DMA operations are in progress */
302 ahc_outb(ahc, CCSCBCNT, 0);
303 ahc_outb(ahc, CCSGCTL, 0);
304 ahc_outb(ahc, CCSCBCTL, 0);
305 }
306 /*
307 * If we were in the process of DMA'ing SCB data into
308 * an SCB, replace that SCB on the free list. This prevents
309 * an SCB leak.
310 */
311 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
312 ahc_add_curscb_to_free_list(ahc);
313 ahc_outb(ahc, SEQ_FLAGS2,
314 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
315 }
316 ahc_outb(ahc, MWI_RESIDUAL, 0);
317 ahc_outb(ahc, SEQCTL, FASTMODE);
318 ahc_outb(ahc, SEQADDR0, 0);
319 ahc_outb(ahc, SEQADDR1, 0);
320 ahc_unpause(ahc);
321 }
322
323 /************************* Input/Output Queues ********************************/
324 void
ahc_run_qoutfifo(struct ahc_softc * ahc)325 ahc_run_qoutfifo(struct ahc_softc *ahc)
326 {
327 struct scb *scb;
328 u_int scb_index;
329
330 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
331 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
332
333 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
334 if ((ahc->qoutfifonext & 0x03) == 0x03) {
335 u_int modnext;
336
337 /*
338 * Clear 32bits of QOUTFIFO at a time
339 * so that we don't clobber an incoming
340 * byte DMA to the array on architectures
341 * that only support 32bit load and store
342 * operations.
343 */
344 modnext = ahc->qoutfifonext & ~0x3;
345 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
346 ahc_dmamap_sync(ahc,
347 ahc->parent_dmat /*shared_data_dmat*/,
348 ahc->shared_data_dmamap,
349 /*offset*/modnext, /*len*/4,
350 BUS_DMASYNC_PREREAD);
351 }
352 ahc->qoutfifonext++;
353
354 scb = ahc_lookup_scb(ahc, scb_index);
355 if (scb == NULL) {
356 printf("%s: WARNING no command for scb %d "
357 "(cmdcmplt)\nQOUTPOS = %d\n",
358 ahc_name(ahc), scb_index,
359 (ahc->qoutfifonext - 1) & 0xFF);
360 continue;
361 }
362
363 /*
364 * Save off the residual
365 * if there is one.
366 */
367 ahc_update_residual(ahc, scb);
368 ahc_done(ahc, scb);
369 }
370 }
371
372 void
ahc_run_untagged_queues(struct ahc_softc * ahc)373 ahc_run_untagged_queues(struct ahc_softc *ahc)
374 {
375 int i;
376
377 for (i = 0; i < 16; i++)
378 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
379 }
380
381 void
ahc_run_untagged_queue(struct ahc_softc * ahc,struct scb_tailq * queue)382 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
383 {
384 struct scb *scb;
385
386 if (ahc->untagged_queue_lock != 0)
387 return;
388
389 if ((scb = TAILQ_FIRST(queue)) != NULL
390 && (scb->flags & SCB_ACTIVE) == 0) {
391 scb->flags |= SCB_ACTIVE;
392 ahc_queue_scb(ahc, scb);
393 }
394 }
395
396 /************************* Interrupt Handling *********************************/
397 void
ahc_handle_brkadrint(struct ahc_softc * ahc)398 ahc_handle_brkadrint(struct ahc_softc *ahc)
399 {
400 /*
401 * We upset the sequencer :-(
402 * Lookup the error message
403 */
404 int i;
405 int error;
406
407 error = ahc_inb(ahc, ERROR);
408 for (i = 0; error != 1 && i < num_errors; i++)
409 error >>= 1;
410 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
411 ahc_name(ahc), ahc_hard_errors[i].errmesg,
412 ahc_inb(ahc, SEQADDR0) |
413 (ahc_inb(ahc, SEQADDR1) << 8));
414
415 ahc_dump_card_state(ahc);
416
417 /* Tell everyone that this HBA is no longer available */
418 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
419 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
420 CAM_NO_HBA);
421
422 /* Disable all interrupt sources by resetting the controller */
423 ahc_shutdown(ahc);
424 }
425
426 void
ahc_handle_seqint(struct ahc_softc * ahc,u_int intstat)427 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
428 {
429 struct scb *scb;
430 struct ahc_devinfo devinfo;
431
432 ahc_fetch_devinfo(ahc, &devinfo);
433
434 /*
435 * Clear the upper byte that holds SEQINT status
436 * codes and clear the SEQINT bit. We will unpause
437 * the sequencer, if appropriate, after servicing
438 * the request.
439 */
440 ahc_outb(ahc, CLRINT, CLRSEQINT);
441 switch (intstat & SEQINT_MASK) {
442 case BAD_STATUS:
443 {
444 u_int scb_index;
445 struct hardware_scb *hscb;
446
447 /*
448 * Set the default return value to 0 (don't
449 * send sense). The sense code will change
450 * this if needed.
451 */
452 ahc_outb(ahc, RETURN_1, 0);
453
454 /*
455 * The sequencer will notify us when a command
456 * has an error that would be of interest to
457 * the kernel. This allows us to leave the sequencer
458 * running in the common case of command completes
459 * without error. The sequencer will already have
460 * DMA'd the SCB back up to us, so we can reference
461 * the in kernel copy directly.
462 */
463 scb_index = ahc_inb(ahc, SCB_TAG);
464 scb = ahc_lookup_scb(ahc, scb_index);
465 if (scb == NULL) {
466 ahc_print_devinfo(ahc, &devinfo);
467 printf("ahc_intr - referenced scb "
468 "not valid during seqint 0x%x scb(%d)\n",
469 intstat, scb_index);
470 ahc_dump_card_state(ahc);
471 panic("for safety");
472 goto unpause;
473 }
474
475 hscb = scb->hscb;
476
477 /* Don't want to clobber the original sense code */
478 if ((scb->flags & SCB_SENSE) != 0) {
479 /*
480 * Clear the SCB_SENSE Flag and have
481 * the sequencer do a normal command
482 * complete.
483 */
484 scb->flags &= ~SCB_SENSE;
485 break;
486 }
487 /* Freeze the queue until the client sees the error. */
488 ahc_freeze_devq(ahc, scb);
489 ahc_freeze_scb(scb);
490 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
491 switch (hscb->shared_data.status.scsi_status) {
492 case SCSI_STATUS_OK:
493 printf("%s: Interrupted for status of 0 (?)\n",
494 ahc_name(ahc));
495 break;
496 case SCSI_STATUS_CMD_TERMINATED:
497 case SCSI_STATUS_CHECK_COND:
498 {
499 struct ahc_dma_seg *sg;
500 struct scsi_request_sense *sc;
501 struct ahc_initiator_tinfo *targ_info;
502 struct ahc_tmode_tstate *tstate;
503 struct ahc_transinfo *tinfo;
504 uint32_t len;
505 #ifdef AHC_DEBUG
506 if (ahc_debug & AHC_SHOW_SENSE) {
507 ahc_print_path(ahc, scb);
508 printf("SCB %d: requests Check Status\n",
509 scb->hscb->tag);
510 }
511 #endif
512
513 if (ahc_perform_autosense(scb) == 0)
514 break;
515
516 targ_info = ahc_fetch_transinfo(ahc,
517 devinfo.channel,
518 devinfo.our_scsiid,
519 devinfo.target,
520 &tstate);
521 tinfo = &targ_info->curr;
522 sg = scb->sg_list;
523 sc = (struct scsi_request_sense *)
524 (&hscb->shared_data.cdb);
525 /*
526 * Save off the residual if there is one.
527 */
528 ahc_update_residual(ahc, scb);
529 #ifdef AHC_DEBUG
530 if (ahc_debug & AHC_SHOW_SENSE) {
531 ahc_print_path(ahc, scb);
532 printf("Sending Sense\n");
533 }
534 #endif
535 sg->addr = ahc_htole32(ahc_get_sense_bufaddr(ahc, scb));
536 len = ahc_get_sense_bufsize(ahc, scb);
537 sg->len = ahc_htole32(len | AHC_DMA_LAST_SEG);
538
539 memset(sc, 0, sizeof(*sc));
540 sc->opcode = SCSI_REQUEST_SENSE;
541 if (tinfo->protocol_version <= SCSI_REV_2
542 && SCB_GET_LUN(scb) < 8)
543 sc->byte2 = SCB_GET_LUN(scb) << 5;
544 sc->length = len;
545
546 /*
547 * We can't allow the target to disconnect.
548 * This will be an untagged transaction and
549 * having the target disconnect will make this
550 * transaction indistinguishable from outstanding
551 * tagged transactions.
552 */
553 hscb->control = 0;
554
555 /*
556 * This request sense could be because the
557 * the device lost power or in some other
558 * way has lost our transfer negotiations.
559 * Renegotiate if appropriate. Unit attention
560 * errors will be reported before any data
561 * phases occur.
562 */
563 if (ahc_get_residual(scb)
564 == ahc_get_transfer_length(scb)) {
565 ahc_update_neg_request(ahc, &devinfo,
566 tstate, targ_info,
567 AHC_NEG_IF_NON_ASYNC);
568 }
569 if (tstate->auto_negotiate & devinfo.target_mask) {
570 hscb->control |= MK_MESSAGE;
571 scb->flags &= ~SCB_NEGOTIATE;
572 scb->flags |= SCB_AUTO_NEGOTIATE;
573 }
574 hscb->cdb_len = sizeof(*sc);
575 hscb->dataptr = sg->addr;
576 hscb->datacnt = sg->len;
577 hscb->sgptr =
578 ahc_htole32(scb->sg_list_phys | SG_FULL_RESID);
579 scb->sg_count = 1;
580 scb->flags |= SCB_SENSE;
581 ahc_qinfifo_requeue_tail(ahc, scb);
582 ahc_outb(ahc, RETURN_1, SEND_SENSE);
583 /*
584 * Ensure we have enough time to actually
585 * retrieve the sense.
586 */
587 ahc_scb_timer_reset(scb, 5 * 1000000);
588 break;
589 }
590 default:
591 break;
592 }
593 break;
594 }
595 case NO_MATCH:
596 {
597 /* Ensure we don't leave the selection hardware on */
598 ahc_outb(ahc, SCSISEQ,
599 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
600
601 printf("%s:%c:%d: no active SCB for reconnecting "
602 "target - issuing BUS DEVICE RESET\n",
603 ahc_name(ahc), devinfo.channel, devinfo.target);
604 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
605 "ARG_1 == 0x%x ACCUM = 0x%x\n",
606 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
607 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
608 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
609 "SINDEX == 0x%x\n",
610 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
611 ahc_index_busy_tcl(ahc,
612 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
613 ahc_inb(ahc, SAVED_LUN))),
614 ahc_inb(ahc, SINDEX));
615 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
616 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
617 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
618 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
619 ahc_inb(ahc, SCB_CONTROL));
620 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
621 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
622 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
623 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
624 ahc_dump_card_state(ahc);
625 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
626 ahc->msgout_len = 1;
627 ahc->msgout_index = 0;
628 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
629 ahc_outb(ahc, MSG_OUT, HOST_MSG);
630 ahc_assert_atn(ahc);
631 break;
632 }
633 case SEND_REJECT:
634 {
635 u_int rejbyte = ahc_inb(ahc, ACCUM);
636 printf("%s:%c:%d: Warning - unknown message received from "
637 "target (0x%x). Rejecting\n",
638 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
639 break;
640 }
641 case PROTO_VIOLATION:
642 {
643 ahc_handle_proto_violation(ahc);
644 break;
645 }
646 case IGN_WIDE_RES:
647 ahc_handle_ign_wide_residue(ahc, &devinfo);
648 break;
649 case PDATA_REINIT:
650 ahc_reinitialize_dataptrs(ahc);
651 break;
652 case BAD_PHASE:
653 {
654 u_int lastphase;
655
656 lastphase = ahc_inb(ahc, LASTPHASE);
657 printf("%s:%c:%d: unknown scsi bus phase %x, "
658 "lastphase = 0x%x. Attempting to continue\n",
659 ahc_name(ahc), devinfo.channel, devinfo.target,
660 lastphase, ahc_inb(ahc, SCSISIGI));
661 break;
662 }
663 case MISSED_BUSFREE:
664 {
665 u_int lastphase;
666
667 lastphase = ahc_inb(ahc, LASTPHASE);
668 printf("%s:%c:%d: Missed busfree. "
669 "Lastphase = 0x%x, Curphase = 0x%x\n",
670 ahc_name(ahc), devinfo.channel, devinfo.target,
671 lastphase, ahc_inb(ahc, SCSISIGI));
672 ahc_restart(ahc);
673 return;
674 }
675 case HOST_MSG_LOOP:
676 {
677 /*
678 * The sequencer has encountered a message phase
679 * that requires host assistance for completion.
680 * While handling the message phase(s), we will be
681 * notified by the sequencer after each byte is
682 * transferred so we can track bus phase changes.
683 *
684 * If this is the first time we've seen a HOST_MSG_LOOP
685 * interrupt, initialize the state of the host message
686 * loop.
687 */
688 if (ahc->msg_type == MSG_TYPE_NONE) {
689 struct scb *scb1;
690 u_int scb_index;
691 u_int bus_phase;
692
693 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
694 if (bus_phase != P_MESGIN
695 && bus_phase != P_MESGOUT) {
696 printf("ahc_intr: HOST_MSG_LOOP bad "
697 "phase 0x%x\n",
698 bus_phase);
699 /*
700 * Probably transitioned to bus free before
701 * we got here. Just punt the message.
702 */
703 ahc_clear_intstat(ahc);
704 ahc_restart(ahc);
705 return;
706 }
707
708 scb_index = ahc_inb(ahc, SCB_TAG);
709 scb1 = ahc_lookup_scb(ahc, scb_index);
710 if (devinfo.role == ROLE_INITIATOR) {
711 if (scb1 == NULL)
712 panic("HOST_MSG_LOOP with "
713 "invalid SCB %x\n", scb_index);
714
715 if (bus_phase == P_MESGOUT)
716 ahc_setup_initiator_msgout(ahc,
717 &devinfo,
718 scb1);
719 else {
720 ahc->msg_type =
721 MSG_TYPE_INITIATOR_MSGIN;
722 ahc->msgin_index = 0;
723 }
724 }
725 #if AHC_TARGET_MODE
726 else {
727 if (bus_phase == P_MESGOUT) {
728 ahc->msg_type =
729 MSG_TYPE_TARGET_MSGOUT;
730 ahc->msgin_index = 0;
731 }
732 else
733 ahc_setup_target_msgin(ahc,
734 &devinfo,
735 scb1);
736 }
737 #endif
738 }
739
740 ahc_handle_message_phase(ahc);
741 break;
742 }
743 case PERR_DETECTED:
744 {
745 /*
746 * If we've cleared the parity error interrupt
747 * but the sequencer still believes that SCSIPERR
748 * is true, it must be that the parity error is
749 * for the currently presented byte on the bus,
750 * and we are not in a phase (data-in) where we will
751 * eventually ack this byte. Ack the byte and
752 * throw it away in the hope that the target will
753 * take us to message out to deliver the appropriate
754 * error message.
755 */
756 if ((intstat & SCSIINT) == 0
757 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
758
759 if ((ahc->features & AHC_DT) == 0) {
760 u_int curphase;
761
762 /*
763 * The hardware will only let you ack bytes
764 * if the expected phase in SCSISIGO matches
765 * the current phase. Make sure this is
766 * currently the case.
767 */
768 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
769 ahc_outb(ahc, LASTPHASE, curphase);
770 ahc_outb(ahc, SCSISIGO, curphase);
771 }
772 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
773 int wait;
774
775 /*
776 * In a data phase. Faster to bitbucket
777 * the data than to individually ack each
778 * byte. This is also the only strategy
779 * that will work with AUTOACK enabled.
780 */
781 ahc_outb(ahc, SXFRCTL1,
782 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
783 wait = 5000;
784 while (--wait != 0) {
785 if ((ahc_inb(ahc, SCSISIGI)
786 & (CDI|MSGI)) != 0)
787 break;
788 ahc_delay(100);
789 }
790 ahc_outb(ahc, SXFRCTL1,
791 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
792 if (wait == 0) {
793 struct scb *scb1;
794 u_int scb_index;
795
796 ahc_print_devinfo(ahc, &devinfo);
797 printf("Unable to clear parity error. "
798 "Resetting bus.\n");
799 scb_index = ahc_inb(ahc, SCB_TAG);
800 scb1 = ahc_lookup_scb(ahc, scb_index);
801 if (scb1 != NULL)
802 ahc_set_transaction_status(scb1,
803 CAM_UNCOR_PARITY);
804 ahc_reset_channel(ahc, devinfo.channel,
805 /*init reset*/TRUE);
806 }
807 } else {
808 (void)ahc_inb(ahc, SCSIDATL);
809 }
810 }
811 break;
812 }
813 case DATA_OVERRUN:
814 {
815 /*
816 * When the sequencer detects an overrun, it
817 * places the controller in "BITBUCKET" mode
818 * and allows the target to complete its transfer.
819 * Unfortunately, none of the counters get updated
820 * when the controller is in this mode, so we have
821 * no way of knowing how large the overrun was.
822 */
823 u_int scbindex = ahc_inb(ahc, SCB_TAG);
824 u_int lastphase = ahc_inb(ahc, LASTPHASE);
825 u_int i;
826
827 scb = ahc_lookup_scb(ahc, scbindex);
828 for (i = 0; i < num_phases; i++) {
829 if (lastphase == ahc_phase_table[i].phase)
830 break;
831 }
832 ahc_print_path(ahc, scb);
833 printf("data overrun detected %s."
834 " Tag == 0x%x.\n",
835 ahc_phase_table[i].phasemsg,
836 scb->hscb->tag);
837 ahc_print_path(ahc, scb);
838 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
839 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
840 ahc_get_transfer_length(scb), scb->sg_count);
841 if (scb->sg_count > 0) {
842 for (i = 0; i < scb->sg_count; i++) {
843
844 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
845 i,
846 (ahc_le32toh(scb->sg_list[i].len) >> 24
847 & SG_HIGH_ADDR_BITS),
848 ahc_le32toh(scb->sg_list[i].addr),
849 ahc_le32toh(scb->sg_list[i].len)
850 & AHC_SG_LEN_MASK);
851 }
852 }
853 /*
854 * Set this and it will take effect when the
855 * target does a command complete.
856 */
857 ahc_freeze_devq(ahc, scb);
858 if ((scb->flags & SCB_SENSE) == 0) {
859 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
860 } else {
861 scb->flags &= ~SCB_SENSE;
862 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
863 }
864 ahc_freeze_scb(scb);
865
866 if ((ahc->features & AHC_ULTRA2) != 0) {
867 /*
868 * Clear the channel in case we return
869 * to data phase later.
870 */
871 ahc_outb(ahc, SXFRCTL0,
872 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
873 ahc_outb(ahc, SXFRCTL0,
874 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
875 }
876 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
877 u_int dscommand1;
878
879 /* Ensure HHADDR is 0 for future DMA operations. */
880 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
881 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
882 ahc_outb(ahc, HADDR, 0);
883 ahc_outb(ahc, DSCOMMAND1, dscommand1);
884 }
885 break;
886 }
887 case MKMSG_FAILED:
888 {
889 u_int scbindex;
890
891 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
892 ahc_name(ahc), devinfo.channel, devinfo.target,
893 devinfo.lun);
894 scbindex = ahc_inb(ahc, SCB_TAG);
895 scb = ahc_lookup_scb(ahc, scbindex);
896 if (scb != NULL
897 && (scb->flags & SCB_RECOVERY_SCB) != 0)
898 /*
899 * Ensure that we didn't put a second instance of this
900 * SCB into the QINFIFO.
901 */
902 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
903 SCB_GET_CHANNEL(ahc, scb),
904 SCB_GET_LUN(scb), scb->hscb->tag,
905 ROLE_INITIATOR, /*status*/0,
906 SEARCH_REMOVE);
907 break;
908 }
909 case NO_FREE_SCB:
910 {
911 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
912 ahc_dump_card_state(ahc);
913 panic("for safety");
914 break;
915 }
916 case SCB_MISMATCH:
917 {
918 u_int scbptr;
919
920 scbptr = ahc_inb(ahc, SCBPTR);
921 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
922 scbptr, ahc_inb(ahc, ARG_1),
923 ahc->scb_data->hscbs[scbptr].tag);
924 ahc_dump_card_state(ahc);
925 panic("for safety");
926 break;
927 }
928 case OUT_OF_RANGE:
929 {
930 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
931 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
932 "ARG_1 == 0x%x ACCUM = 0x%x\n",
933 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
934 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
935 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
936 "SINDEX == 0x%x\n, A == 0x%x\n",
937 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
938 ahc_index_busy_tcl(ahc,
939 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
940 ahc_inb(ahc, SAVED_LUN))),
941 ahc_inb(ahc, SINDEX),
942 ahc_inb(ahc, ACCUM));
943 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
944 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
945 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
946 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
947 ahc_inb(ahc, SCB_CONTROL));
948 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
949 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
950 ahc_dump_card_state(ahc);
951 panic("for safety");
952 break;
953 }
954 default:
955 printf("ahc_intr: seqint, "
956 "intstat == 0x%x, scsisigi = 0x%x\n",
957 intstat, ahc_inb(ahc, SCSISIGI));
958 break;
959 }
960 unpause:
961 /*
962 * The sequencer is paused immediately on
963 * a SEQINT, so we should restart it when
964 * we're done.
965 */
966 ahc_unpause(ahc);
967 }
968
969 void
ahc_handle_scsiint(struct ahc_softc * ahc,u_int intstat)970 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
971 {
972 u_int scb_index;
973 u_int status0;
974 u_int status;
975 struct scb *scb;
976 char cur_channel;
977 char intr_channel;
978
979 if ((ahc->features & AHC_TWIN) != 0
980 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
981 cur_channel = 'B';
982 else
983 cur_channel = 'A';
984 intr_channel = cur_channel;
985
986 if ((ahc->features & AHC_ULTRA2) != 0)
987 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
988 else
989 status0 = 0;
990 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
991 if (status == 0 && status0 == 0) {
992 if ((ahc->features & AHC_TWIN) != 0) {
993 /* Try the other channel */
994 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
995 status = ahc_inb(ahc, SSTAT1)
996 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
997 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
998 }
999 if (status == 0) {
1000 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1001 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1002 ahc_unpause(ahc);
1003 return;
1004 }
1005 }
1006
1007 /* Make sure the sequencer is in a safe location. */
1008 ahc_clear_critical_section(ahc);
1009
1010 scb_index = ahc_inb(ahc, SCB_TAG);
1011 scb = ahc_lookup_scb(ahc, scb_index);
1012 if (scb != NULL
1013 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1014 scb = NULL;
1015
1016 if ((ahc->features & AHC_ULTRA2) != 0
1017 && (status0 & IOERR) != 0) {
1018 int now_lvd;
1019
1020 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1021 printf("%s: Transceiver State Has Changed to %s mode\n",
1022 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1023 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1024 /*
1025 * When transitioning to SE mode, the reset line
1026 * glitches, triggering an arbitration bug in some
1027 * Ultra2 controllers. This bug is cleared when we
1028 * assert the reset line. Since a reset glitch has
1029 * already occurred with this transition and a
1030 * transceiver state change is handled just like
1031 * a bus reset anyway, asserting the reset line
1032 * ourselves is safe.
1033 */
1034 ahc_reset_channel(ahc, intr_channel,
1035 /*Initiate Reset*/now_lvd == 0);
1036 } else if ((status & SCSIRSTI) != 0) {
1037 printf("%s: Someone reset channel %c\n",
1038 ahc_name(ahc), intr_channel);
1039 if (intr_channel != cur_channel)
1040 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1041 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1042 } else if ((status & SCSIPERR) != 0) {
1043 /*
1044 * Determine the bus phase and queue an appropriate message.
1045 * SCSIPERR is latched true as soon as a parity error
1046 * occurs. If the sequencer acked the transfer that
1047 * caused the parity error and the currently presented
1048 * transfer on the bus has correct parity, SCSIPERR will
1049 * be cleared by CLRSCSIPERR. Use this to determine if
1050 * we should look at the last phase the sequencer recorded,
1051 * or the current phase presented on the bus.
1052 */
1053 u_int mesg_out;
1054 u_int curphase;
1055 u_int errorphase;
1056 u_int lastphase;
1057 u_int scsirate;
1058 u_int i;
1059 u_int sstat2;
1060 int silent;
1061
1062 lastphase = ahc_inb(ahc, LASTPHASE);
1063 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1064 sstat2 = ahc_inb(ahc, SSTAT2);
1065 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1066 /*
1067 * For all phases save DATA, the sequencer won't
1068 * automatically ack a byte that has a parity error
1069 * in it. So the only way that the current phase
1070 * could be 'data-in' is if the parity error is for
1071 * an already acked byte in the data phase. During
1072 * synchronous data-in transfers, we may actually
1073 * ack bytes before latching the current phase in
1074 * LASTPHASE, leading to the discrepancy between
1075 * curphase and lastphase.
1076 */
1077 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1078 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1079 errorphase = curphase;
1080 else
1081 errorphase = lastphase;
1082
1083 for (i = 0; i < num_phases; i++) {
1084 if (errorphase == ahc_phase_table[i].phase)
1085 break;
1086 }
1087 mesg_out = ahc_phase_table[i].mesg_out;
1088 silent = FALSE;
1089 if (scb != NULL) {
1090 if (SCB_IS_SILENT(scb))
1091 silent = TRUE;
1092 else
1093 ahc_print_path(ahc, scb);
1094 scb->flags |= SCB_TRANSMISSION_ERROR;
1095 } else
1096 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1097 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1098 scsirate = ahc_inb(ahc, SCSIRATE);
1099 if (silent == FALSE) {
1100 printf("parity error detected %s. "
1101 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1102 ahc_phase_table[i].phasemsg,
1103 ahc_inw(ahc, SEQADDR0),
1104 scsirate);
1105 if ((ahc->features & AHC_DT) != 0) {
1106 if ((sstat2 & CRCVALERR) != 0)
1107 printf("\tCRC Value Mismatch\n");
1108 if ((sstat2 & CRCENDERR) != 0)
1109 printf("\tNo terminal CRC packet "
1110 "received\n");
1111 if ((sstat2 & CRCREQERR) != 0)
1112 printf("\tIllegal CRC packet "
1113 "request\n");
1114 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1115 printf("\tUnexpected %sDT Data Phase\n",
1116 (scsirate & SINGLE_EDGE)
1117 ? "" : "non-");
1118 }
1119 }
1120
1121 if ((ahc->features & AHC_DT) != 0
1122 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1123 /*
1124 * This error applies regardless of
1125 * data direction, so ignore the value
1126 * in the phase table.
1127 */
1128 mesg_out = MSG_INITIATOR_DET_ERR;
1129 }
1130
1131 /*
1132 * We've set the hardware to assert ATN if we
1133 * get a parity error on "in" phases, so all we
1134 * need to do is stuff the message buffer with
1135 * the appropriate message. "In" phases have set
1136 * mesg_out to something other than MSG_NOP.
1137 */
1138 if (mesg_out != MSG_NOOP) {
1139 if (ahc->msg_type != MSG_TYPE_NONE)
1140 ahc->send_msg_perror = TRUE;
1141 else
1142 ahc_outb(ahc, MSG_OUT, mesg_out);
1143 }
1144 /*
1145 * Force a renegotiation with this target just in
1146 * case we are out of sync for some external reason
1147 * unknown (or unreported) by the target.
1148 */
1149 ahc_force_renegotiation(ahc);
1150 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1151 ahc_unpause(ahc);
1152 } else if ((status & SELTO) != 0) {
1153 u_int scbptr;
1154
1155 /* Stop the selection */
1156 ahc_outb(ahc, SCSISEQ, 0);
1157
1158 /* No more pending messages */
1159 ahc_clear_msg_state(ahc);
1160
1161 /* Clear interrupt state */
1162 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1163 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1164
1165 /*
1166 * Although the driver does not care about the
1167 * 'Selection in Progress' status bit, the busy
1168 * LED does. SELINGO is only cleared by a successful
1169 * selection, so we must manually clear it to insure
1170 * the LED turns off just incase no future successful
1171 * selections occur (e.g. no devices on the bus).
1172 */
1173 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1174
1175 scbptr = ahc_inb(ahc, WAITING_SCBH);
1176 ahc_outb(ahc, SCBPTR, scbptr);
1177 scb_index = ahc_inb(ahc, SCB_TAG);
1178
1179 scb = ahc_lookup_scb(ahc, scb_index);
1180 if (scb == NULL) {
1181 printf("%s: ahc_intr - referenced scb not "
1182 "valid during SELTO scb(%d, %d)\n",
1183 ahc_name(ahc), scbptr, scb_index);
1184 ahc_dump_card_state(ahc);
1185 } else {
1186 #ifdef AHC_DEBUG
1187 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1188 ahc_print_path(ahc, scb);
1189 printf("Saw Selection Timeout for SCB 0x%x\n",
1190 scb_index);
1191 }
1192 #endif
1193 /*
1194 * Force a renegotiation with this target just in
1195 * case the cable was pulled and will later be
1196 * re-attached. The target may forget its negotiation
1197 * settings with us should it attempt to reselect
1198 * during the interruption. The target will not issue
1199 * a unit attention in this case, so we must always
1200 * renegotiate.
1201 */
1202 ahc_force_renegotiation(ahc);
1203 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1204 ahc_freeze_devq(ahc, scb);
1205 }
1206 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1207 ahc_restart(ahc);
1208 } else if ((status & BUSFREE) != 0
1209 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1210 u_int lastphase;
1211 u_int saved_scsiid;
1212 u_int saved_lun;
1213 u_int target;
1214 u_int initiator_role_id;
1215 char channel;
1216 int printerror;
1217
1218 /*
1219 * Clear our selection hardware as soon as possible.
1220 * We may have an entry in the waiting Q for this target,
1221 * that is affected by this busfree and we don't want to
1222 * go about selecting the target while we handle the event.
1223 */
1224 ahc_outb(ahc, SCSISEQ,
1225 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1226
1227 /*
1228 * Disable busfree interrupts and clear the busfree
1229 * interrupt status. We do this here so that several
1230 * bus transactions occur prior to clearing the SCSIINT
1231 * latch. It can take a bit for the clearing to take effect.
1232 */
1233 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1234 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1235
1236 /*
1237 * Look at what phase we were last in.
1238 * If its message out, chances are pretty good
1239 * that the busfree was in response to one of
1240 * our abort requests.
1241 */
1242 lastphase = ahc_inb(ahc, LASTPHASE);
1243 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1244 saved_lun = ahc_inb(ahc, SAVED_LUN);
1245 target = SCSIID_TARGET(ahc, saved_scsiid);
1246 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1247 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1248 printerror = 1;
1249
1250 if (lastphase == P_MESGOUT) {
1251 struct ahc_devinfo devinfo;
1252 u_int tag;
1253
1254 ahc_fetch_devinfo(ahc, &devinfo);
1255 tag = SCB_LIST_NULL;
1256 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1257 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1258 if (ahc->msgout_buf[ahc->msgout_index - 1]
1259 == MSG_ABORT_TAG)
1260 tag = scb->hscb->tag;
1261 ahc_print_path(ahc, scb);
1262 printf("SCB %d - Abort%s Completed.\n",
1263 scb->hscb->tag, tag == SCB_LIST_NULL ?
1264 "" : " Tag");
1265 ahc_abort_scbs(ahc, target, channel,
1266 saved_lun, tag,
1267 ROLE_INITIATOR,
1268 CAM_REQ_ABORTED);
1269 printerror = 0;
1270 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1271 MSG_BUS_DEV_RESET, TRUE)) {
1272 #ifdef __FreeBSD__
1273 /*
1274 * Don't mark the user's request for this BDR
1275 * as completing with CAM_BDR_SENT. CAM3
1276 * specifies CAM_REQ_CMP.
1277 */
1278 if (scb != NULL
1279 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1280 && ahc_match_scb(ahc, scb, target, channel,
1281 CAM_LUN_WILDCARD,
1282 SCB_LIST_NULL,
1283 ROLE_INITIATOR)) {
1284 ahc_set_transaction_status(scb,
1285 CAM_REQ_CMP);
1286 }
1287 #endif
1288 ahc_compile_devinfo(&devinfo,
1289 initiator_role_id,
1290 target,
1291 CAM_LUN_WILDCARD,
1292 channel,
1293 ROLE_INITIATOR);
1294 ahc_handle_devreset(ahc, &devinfo,
1295 CAM_BDR_SENT,
1296 "Bus Device Reset",
1297 /*verbose_level*/0);
1298 printerror = 0;
1299 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1300 MSG_EXT_PPR, FALSE)) {
1301 struct ahc_initiator_tinfo *tinfo;
1302 struct ahc_tmode_tstate *tstate;
1303
1304 /*
1305 * PPR Rejected. Try non-ppr negotiation
1306 * and retry command.
1307 */
1308 tinfo = ahc_fetch_transinfo(ahc,
1309 devinfo.channel,
1310 devinfo.our_scsiid,
1311 devinfo.target,
1312 &tstate);
1313 tinfo->curr.transport_version = 2;
1314 tinfo->goal.transport_version = 2;
1315 tinfo->goal.ppr_options = 0;
1316 ahc_qinfifo_requeue_tail(ahc, scb);
1317 printerror = 0;
1318 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1319 MSG_EXT_WDTR, FALSE)
1320 || ahc_sent_msg(ahc, AHCMSG_EXT,
1321 MSG_EXT_SDTR, FALSE)) {
1322 /*
1323 * Negotiation Rejected. Go-async and
1324 * retry command.
1325 */
1326 ahc_set_width(ahc, &devinfo,
1327 MSG_EXT_WDTR_BUS_8_BIT,
1328 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1329 /*paused*/TRUE);
1330 ahc_set_syncrate(ahc, &devinfo,
1331 /*syncrate*/NULL,
1332 /*period*/0, /*offset*/0,
1333 /*ppr_options*/0,
1334 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1335 /*paused*/TRUE);
1336 ahc_qinfifo_requeue_tail(ahc, scb);
1337 printerror = 0;
1338 }
1339 }
1340 if (printerror != 0) {
1341 u_int i;
1342
1343 if (scb != NULL) {
1344 u_int tag;
1345
1346 if ((scb->hscb->control & TAG_ENB) != 0)
1347 tag = scb->hscb->tag;
1348 else
1349 tag = SCB_LIST_NULL;
1350 ahc_print_path(ahc, scb);
1351 ahc_abort_scbs(ahc, target, channel,
1352 SCB_GET_LUN(scb), tag,
1353 ROLE_INITIATOR,
1354 CAM_UNEXP_BUSFREE);
1355 } else {
1356 /*
1357 * We had not fully identified this connection,
1358 * so we cannot abort anything.
1359 */
1360 printf("%s: ", ahc_name(ahc));
1361 }
1362 for (i = 0; i < num_phases; i++) {
1363 if (lastphase == ahc_phase_table[i].phase)
1364 break;
1365 }
1366 /*
1367 * Renegotiate with this device at the
1368 * next opportunity just in case this busfree
1369 * is due to a negotiation mismatch with the
1370 * device.
1371 */
1372 ahc_force_renegotiation(ahc);
1373 printf("Unexpected busfree %s\n"
1374 "SEQADDR == 0x%x\n",
1375 ahc_phase_table[i].phasemsg,
1376 ahc_inb(ahc, SEQADDR0)
1377 | (ahc_inb(ahc, SEQADDR1) << 8));
1378 }
1379 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1380 ahc_restart(ahc);
1381 } else {
1382 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1383 ahc_name(ahc), status);
1384 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1385 }
1386 }
1387
1388 /*
1389 * Force renegotiation to occur the next time we initiate
1390 * a command to the current device.
1391 */
1392 static void
ahc_force_renegotiation(struct ahc_softc * ahc)1393 ahc_force_renegotiation(struct ahc_softc *ahc)
1394 {
1395 struct ahc_devinfo devinfo;
1396 struct ahc_initiator_tinfo *targ_info;
1397 struct ahc_tmode_tstate *tstate;
1398
1399 ahc_fetch_devinfo(ahc, &devinfo);
1400 targ_info = ahc_fetch_transinfo(ahc,
1401 devinfo.channel,
1402 devinfo.our_scsiid,
1403 devinfo.target,
1404 &tstate);
1405 ahc_update_neg_request(ahc, &devinfo, tstate,
1406 targ_info, AHC_NEG_IF_NON_ASYNC);
1407 }
1408
1409 #define AHC_MAX_STEPS 2000
1410 void
ahc_clear_critical_section(struct ahc_softc * ahc)1411 ahc_clear_critical_section(struct ahc_softc *ahc)
1412 {
1413 int stepping;
1414 int steps;
1415 u_int simode0;
1416 u_int simode1;
1417
1418 if (ahc->num_critical_sections == 0)
1419 return;
1420
1421 stepping = FALSE;
1422 steps = 0;
1423 simode0 = 0;
1424 simode1 = 0;
1425 for (;;) {
1426 struct cs *cs;
1427 u_int seqaddr;
1428 u_int i;
1429
1430 seqaddr = ahc_inb(ahc, SEQADDR0)
1431 | (ahc_inb(ahc, SEQADDR1) << 8);
1432
1433 /*
1434 * Seqaddr represents the next instruction to execute,
1435 * so we are really executing the instruction just
1436 * before it.
1437 */
1438 if (seqaddr != 0)
1439 seqaddr -= 1;
1440 cs = ahc->critical_sections;
1441 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1442
1443 if (cs->begin < seqaddr && cs->end >= seqaddr)
1444 break;
1445 }
1446
1447 if (i == ahc->num_critical_sections)
1448 break;
1449
1450 if (steps > AHC_MAX_STEPS) {
1451 printf("%s: Infinite loop in critical section\n",
1452 ahc_name(ahc));
1453 ahc_dump_card_state(ahc);
1454 panic("critical section loop");
1455 }
1456
1457 steps++;
1458 if (stepping == FALSE) {
1459
1460 /*
1461 * Disable all interrupt sources so that the
1462 * sequencer will not be stuck by a pausing
1463 * interrupt condition while we attempt to
1464 * leave a critical section.
1465 */
1466 simode0 = ahc_inb(ahc, SIMODE0);
1467 ahc_outb(ahc, SIMODE0, 0);
1468 simode1 = ahc_inb(ahc, SIMODE1);
1469 if ((ahc->features & AHC_DT) != 0)
1470 /*
1471 * On DT class controllers, we
1472 * use the enhanced busfree logic.
1473 * Unfortunately we cannot re-enable
1474 * busfree detection within the
1475 * current connection, so we must
1476 * leave it on while single stepping.
1477 */
1478 ahc_outb(ahc, SIMODE1, ENBUSFREE);
1479 else
1480 ahc_outb(ahc, SIMODE1, 0);
1481 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1482 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP);
1483 stepping = TRUE;
1484 }
1485 if ((ahc->features & AHC_DT) != 0) {
1486 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1487 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1488 }
1489 ahc_outb(ahc, HCNTRL, ahc->unpause);
1490 while (!ahc_is_paused(ahc))
1491 ahc_delay(200);
1492 }
1493 if (stepping) {
1494 ahc_outb(ahc, SIMODE0, simode0);
1495 ahc_outb(ahc, SIMODE1, simode1);
1496 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP);
1497 }
1498 }
1499
1500 /*
1501 * Clear any pending interrupt status.
1502 */
1503 void
ahc_clear_intstat(struct ahc_softc * ahc)1504 ahc_clear_intstat(struct ahc_softc *ahc)
1505 {
1506 /* Clear any interrupt conditions this may have caused */
1507 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1508 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1509 CLRREQINIT);
1510 ahc_flush_device_writes(ahc);
1511 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1512 ahc_flush_device_writes(ahc);
1513 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1514 ahc_flush_device_writes(ahc);
1515 }
1516
1517 /**************************** Debugging Routines ******************************/
1518 #ifdef AHC_DEBUG
1519 uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/
1520 #endif
1521
1522 void
ahc_print_scb(struct scb * scb)1523 ahc_print_scb(struct scb *scb)
1524 {
1525 int i;
1526
1527 struct hardware_scb *hscb = scb->hscb;
1528
1529 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1530 (void *)scb,
1531 hscb->control,
1532 hscb->scsiid,
1533 hscb->lun,
1534 hscb->cdb_len);
1535 printf("Shared Data: ");
1536 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1537 printf("%#02x", hscb->shared_data.cdb[i]);
1538 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1539 ahc_le32toh(hscb->dataptr),
1540 ahc_le32toh(hscb->datacnt),
1541 ahc_le32toh(hscb->sgptr),
1542 hscb->tag);
1543 if (scb->sg_count > 0) {
1544 for (i = 0; i < scb->sg_count; i++) {
1545 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1546 i,
1547 (ahc_le32toh(scb->sg_list[i].len) >> 24
1548 & SG_HIGH_ADDR_BITS),
1549 ahc_le32toh(scb->sg_list[i].addr),
1550 ahc_le32toh(scb->sg_list[i].len));
1551 }
1552 }
1553 }
1554
1555 /************************* Transfer Negotiation *******************************/
1556 /*
1557 * Allocate per target mode instance (ID we respond to as a target)
1558 * transfer negotiation data structures.
1559 */
1560 static struct ahc_tmode_tstate *
ahc_alloc_tstate(struct ahc_softc * ahc,u_int scsi_id,char channel)1561 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1562 {
1563 struct ahc_tmode_tstate *master_tstate;
1564 struct ahc_tmode_tstate *tstate;
1565 int i;
1566
1567 master_tstate = ahc->enabled_targets[ahc->our_id];
1568 if (channel == 'B') {
1569 scsi_id += 8;
1570 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1571 }
1572 if (ahc->enabled_targets[scsi_id] != NULL
1573 && ahc->enabled_targets[scsi_id] != master_tstate)
1574 panic("%s: ahc_alloc_tstate - Target already allocated",
1575 ahc_name(ahc));
1576 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_WAITOK);
1577
1578 /*
1579 * If we have allocated a master tstate, copy user settings from
1580 * the master tstate (taken from SRAM or the EEPROM) for this
1581 * channel, but reset our current and goal settings to async/narrow
1582 * until an initiator talks to us.
1583 */
1584 if (master_tstate != NULL) {
1585 memcpy(tstate, master_tstate, sizeof(*tstate));
1586 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1587 tstate->ultraenb = 0;
1588 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1589 memset(&tstate->transinfo[i].curr, 0,
1590 sizeof(tstate->transinfo[i].curr));
1591 memset(&tstate->transinfo[i].goal, 0,
1592 sizeof(tstate->transinfo[i].goal));
1593 }
1594 } else
1595 memset(tstate, 0, sizeof(*tstate));
1596 ahc->enabled_targets[scsi_id] = tstate;
1597 return (tstate);
1598 }
1599
1600 #ifdef AHC_TARGET_MODE
1601 /*
1602 * Free per target mode instance (ID we respond to as a target)
1603 * transfer negotiation data structures.
1604 */
1605 static void
ahc_free_tstate(struct ahc_softc * ahc,u_int scsi_id,char channel,int force)1606 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1607 {
1608 struct ahc_tmode_tstate *tstate;
1609
1610 /*
1611 * Don't clean up our "master" tstate.
1612 * It has our default user settings.
1613 */
1614 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1615 || (channel == 'A' && scsi_id == ahc->our_id))
1616 && force == FALSE)
1617 return;
1618
1619 if (channel == 'B')
1620 scsi_id += 8;
1621 tstate = ahc->enabled_targets[scsi_id];
1622 if (tstate != NULL)
1623 free(tstate, M_DEVBUF);
1624 ahc->enabled_targets[scsi_id] = NULL;
1625 }
1626 #endif
1627
1628 /*
1629 * Called when we have an active connection to a target on the bus,
1630 * this function finds the nearest syncrate to the input period limited
1631 * by the capabilities of the bus connectivity of and sync settings for
1632 * the target.
1633 */
1634 struct ahc_syncrate *
ahc_devlimited_syncrate(struct ahc_softc * ahc,struct ahc_initiator_tinfo * tinfo,u_int * period,u_int * ppr_options,role_t role)1635 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1636 struct ahc_initiator_tinfo *tinfo,
1637 u_int *period, u_int *ppr_options, role_t role)
1638 {
1639 struct ahc_transinfo *transinfo;
1640 u_int maxsync;
1641
1642 if ((ahc->features & AHC_ULTRA2) != 0) {
1643 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1644 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1645 maxsync = AHC_SYNCRATE_DT;
1646 } else {
1647 maxsync = AHC_SYNCRATE_ULTRA;
1648 /* Can't do DT on an SE bus */
1649 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1650 }
1651 } else if ((ahc->features & AHC_ULTRA) != 0) {
1652 maxsync = AHC_SYNCRATE_ULTRA;
1653 } else {
1654 maxsync = AHC_SYNCRATE_FAST;
1655 }
1656 /*
1657 * Never allow a value higher than our current goal
1658 * period otherwise we may allow a target initiated
1659 * negotiation to go above the limit as set by the
1660 * user. In the case of an initiator initiated
1661 * sync negotiation, we limit based on the user
1662 * setting. This allows the system to still accept
1663 * incoming negotiations even if target initiated
1664 * negotiation is not performed.
1665 */
1666 if (role == ROLE_TARGET)
1667 transinfo = &tinfo->user;
1668 else
1669 transinfo = &tinfo->goal;
1670 *ppr_options &= transinfo->ppr_options;
1671 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1672 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1673 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1674 }
1675 if (transinfo->period == 0) {
1676 *period = 0;
1677 *ppr_options = 0;
1678 return (NULL);
1679 }
1680 *period = MAX(*period, transinfo->period);
1681 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1682 }
1683
1684 /*
1685 * Look up the valid period to SCSIRATE conversion in our table.
1686 * Return the period and offset that should be sent to the target
1687 * if this was the beginning of an SDTR.
1688 */
1689 struct ahc_syncrate *
ahc_find_syncrate(struct ahc_softc * ahc,u_int * period,u_int * ppr_options,u_int maxsync)1690 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1691 u_int *ppr_options, u_int maxsync)
1692 {
1693 struct ahc_syncrate *syncrate;
1694
1695 if ((ahc->features & AHC_DT) == 0)
1696 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1697
1698 /* Skip all DT only entries if DT is not available */
1699 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1700 && maxsync < AHC_SYNCRATE_ULTRA2)
1701 maxsync = AHC_SYNCRATE_ULTRA2;
1702
1703 for (syncrate = &ahc_syncrates[maxsync];
1704 syncrate->rate != NULL;
1705 syncrate++) {
1706
1707 /*
1708 * The Ultra2 table doesn't go as low
1709 * as for the Fast/Ultra cards.
1710 */
1711 if ((ahc->features & AHC_ULTRA2) != 0
1712 && (syncrate->sxfr_u2 == 0))
1713 break;
1714
1715 if (*period <= syncrate->period) {
1716 /*
1717 * When responding to a target that requests
1718 * sync, the requested rate may fall between
1719 * two rates that we can output, but still be
1720 * a rate that we can receive. Because of this,
1721 * we want to respond to the target with
1722 * the same rate that it sent to us even
1723 * if the period we use to send data to it
1724 * is lower. Only lower the response period
1725 * if we must.
1726 */
1727 if (syncrate == &ahc_syncrates[maxsync])
1728 *period = syncrate->period;
1729
1730 /*
1731 * At some speeds, we only support
1732 * ST transfers.
1733 */
1734 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1735 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1736 break;
1737 }
1738 }
1739
1740 if ((*period == 0)
1741 || (syncrate->rate == NULL)
1742 || ((ahc->features & AHC_ULTRA2) != 0
1743 && (syncrate->sxfr_u2 == 0))) {
1744 /* Use asynchronous transfers. */
1745 *period = 0;
1746 syncrate = NULL;
1747 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1748 }
1749 return (syncrate);
1750 }
1751
1752 /*
1753 * Convert from an entry in our syncrate table to the SCSI equivalent
1754 * sync "period" factor.
1755 */
1756 u_int
ahc_find_period(struct ahc_softc * ahc,u_int scsirate,u_int maxsync)1757 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1758 {
1759 struct ahc_syncrate *syncrate;
1760
1761 if ((ahc->features & AHC_ULTRA2) != 0)
1762 scsirate &= SXFR_ULTRA2;
1763 else
1764 scsirate &= SXFR;
1765
1766 syncrate = &ahc_syncrates[maxsync];
1767 while (syncrate->rate != NULL) {
1768
1769 if ((ahc->features & AHC_ULTRA2) != 0) {
1770 if (syncrate->sxfr_u2 == 0)
1771 break;
1772 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1773 return (syncrate->period);
1774 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1775 return (syncrate->period);
1776 }
1777 syncrate++;
1778 }
1779 return (0); /* async */
1780 }
1781
1782 /*
1783 * Truncate the given synchronous offset to a value the
1784 * current adapter type and syncrate are capable of.
1785 */
1786 void
ahc_validate_offset(struct ahc_softc * ahc,struct ahc_initiator_tinfo * tinfo,struct ahc_syncrate * syncrate,u_int * offset,int wide,role_t role)1787 ahc_validate_offset(struct ahc_softc *ahc,
1788 struct ahc_initiator_tinfo *tinfo,
1789 struct ahc_syncrate *syncrate,
1790 u_int *offset, int wide, role_t role)
1791 {
1792 u_int maxoffset;
1793
1794 /* Limit offset to what we can do */
1795 if (syncrate == NULL) {
1796 maxoffset = 0;
1797 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1798 maxoffset = MAX_OFFSET_ULTRA2;
1799 } else {
1800 if (wide)
1801 maxoffset = MAX_OFFSET_16BIT;
1802 else
1803 maxoffset = MAX_OFFSET_8BIT;
1804 }
1805 *offset = MIN(*offset, maxoffset);
1806 if (tinfo != NULL) {
1807 if (role == ROLE_TARGET)
1808 *offset = MIN(*offset, tinfo->user.offset);
1809 else
1810 *offset = MIN(*offset, tinfo->goal.offset);
1811 }
1812 }
1813
1814 /*
1815 * Truncate the given transfer width parameter to a value the
1816 * current adapter type is capable of.
1817 */
1818 void
ahc_validate_width(struct ahc_softc * ahc,struct ahc_initiator_tinfo * tinfo,u_int * bus_width,role_t role)1819 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1820 u_int *bus_width, role_t role)
1821 {
1822 switch (*bus_width) {
1823 default:
1824 if (ahc->features & AHC_WIDE) {
1825 /* Respond Wide */
1826 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1827 break;
1828 }
1829 /* FALLTHROUGH */
1830 case MSG_EXT_WDTR_BUS_8_BIT:
1831 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1832 break;
1833 }
1834 if (tinfo != NULL) {
1835 if (role == ROLE_TARGET)
1836 *bus_width = MIN(tinfo->user.width, *bus_width);
1837 else
1838 *bus_width = MIN(tinfo->goal.width, *bus_width);
1839 }
1840 }
1841
1842 /*
1843 * Update the bitmask of targets for which the controller should
1844 * negotiate with at the next convenient opportunity. This currently
1845 * means the next time we send the initial identify messages for
1846 * a new transaction.
1847 */
1848 int
ahc_update_neg_request(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct ahc_tmode_tstate * tstate,struct ahc_initiator_tinfo * tinfo,ahc_neg_type neg_type)1849 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1850 struct ahc_tmode_tstate *tstate,
1851 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1852 {
1853 u_int auto_negotiate_orig;
1854
1855 auto_negotiate_orig = tstate->auto_negotiate;
1856 if (neg_type == AHC_NEG_ALWAYS) {
1857 /*
1858 * Force our "current" settings to be
1859 * unknown so that unless a bus reset
1860 * occurs the need to renegotiate is
1861 * recorded persistently.
1862 */
1863 if ((ahc->features & AHC_WIDE) != 0)
1864 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1865 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1866 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1867 }
1868 if (tinfo->curr.period != tinfo->goal.period
1869 || tinfo->curr.width != tinfo->goal.width
1870 || tinfo->curr.offset != tinfo->goal.offset
1871 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1872 || (neg_type == AHC_NEG_IF_NON_ASYNC
1873 && (tinfo->goal.offset != 0
1874 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1875 || tinfo->goal.ppr_options != 0)))
1876 tstate->auto_negotiate |= devinfo->target_mask;
1877 else
1878 tstate->auto_negotiate &= ~devinfo->target_mask;
1879
1880 return (auto_negotiate_orig != tstate->auto_negotiate);
1881 }
1882
1883 /*
1884 * Update the user/goal/curr tables of synchronous negotiation
1885 * parameters as well as, in the case of a current or active update,
1886 * any data structures on the host controller. In the case of an
1887 * active update, the specified target is currently talking to us on
1888 * the bus, so the transfer parameter update must take effect
1889 * immediately.
1890 */
1891 void
ahc_set_syncrate(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct ahc_syncrate * syncrate,u_int period,u_int offset,u_int ppr_options,u_int type,int paused)1892 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1893 struct ahc_syncrate *syncrate, u_int period,
1894 u_int offset, u_int ppr_options, u_int type, int paused)
1895 {
1896 struct ahc_initiator_tinfo *tinfo;
1897 struct ahc_tmode_tstate *tstate;
1898 u_int old_period;
1899 u_int old_offset;
1900 u_int old_ppr;
1901 int active;
1902 int update_needed;
1903
1904 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1905 update_needed = 0;
1906
1907 if (syncrate == NULL) {
1908 period = 0;
1909 offset = 0;
1910 }
1911
1912 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1913 devinfo->target, &tstate);
1914
1915 if ((type & AHC_TRANS_USER) != 0) {
1916 tinfo->user.period = period;
1917 tinfo->user.offset = offset;
1918 tinfo->user.ppr_options = ppr_options;
1919 }
1920
1921 if ((type & AHC_TRANS_GOAL) != 0) {
1922 tinfo->goal.period = period;
1923 tinfo->goal.offset = offset;
1924 tinfo->goal.ppr_options = ppr_options;
1925 }
1926
1927 old_period = tinfo->curr.period;
1928 old_offset = tinfo->curr.offset;
1929 old_ppr = tinfo->curr.ppr_options;
1930
1931 if ((type & AHC_TRANS_CUR) != 0
1932 && (old_period != period
1933 || old_offset != offset
1934 || old_ppr != ppr_options)) {
1935 u_int scsirate;
1936
1937 update_needed++;
1938 scsirate = tinfo->scsirate;
1939 if ((ahc->features & AHC_ULTRA2) != 0) {
1940
1941 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1942 if (syncrate != NULL) {
1943 scsirate |= syncrate->sxfr_u2;
1944 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1945 scsirate |= ENABLE_CRC;
1946 else
1947 scsirate |= SINGLE_EDGE;
1948 }
1949 } else {
1950
1951 scsirate &= ~(SXFR|SOFS);
1952 /*
1953 * Ensure Ultra mode is set properly for
1954 * this target.
1955 */
1956 tstate->ultraenb &= ~devinfo->target_mask;
1957 if (syncrate != NULL) {
1958 if (syncrate->sxfr & ULTRA_SXFR) {
1959 tstate->ultraenb |=
1960 devinfo->target_mask;
1961 }
1962 scsirate |= syncrate->sxfr & SXFR;
1963 scsirate |= offset & SOFS;
1964 }
1965 if (active) {
1966 u_int sxfrctl0;
1967
1968 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1969 sxfrctl0 &= ~FAST20;
1970 if (tstate->ultraenb & devinfo->target_mask)
1971 sxfrctl0 |= FAST20;
1972 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1973 }
1974 }
1975 if (active) {
1976 ahc_outb(ahc, SCSIRATE, scsirate);
1977 if ((ahc->features & AHC_ULTRA2) != 0)
1978 ahc_outb(ahc, SCSIOFFSET, offset);
1979 }
1980
1981 tinfo->scsirate = scsirate;
1982 tinfo->curr.period = period;
1983 tinfo->curr.offset = offset;
1984 tinfo->curr.ppr_options = ppr_options;
1985
1986 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1987 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1988 if (bootverbose) {
1989 if (offset != 0) {
1990 printf("%s: target %d synchronous at %sMHz%s, "
1991 "offset = 0x%x\n", ahc_name(ahc),
1992 devinfo->target, syncrate->rate,
1993 (ppr_options & MSG_EXT_PPR_DT_REQ)
1994 ? " DT" : "", offset);
1995 } else {
1996 printf("%s: target %d using "
1997 "asynchronous transfers\n",
1998 ahc_name(ahc), devinfo->target);
1999 }
2000 }
2001 }
2002
2003 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2004 tinfo, AHC_NEG_TO_GOAL);
2005
2006 if (update_needed)
2007 ahc_update_pending_scbs(ahc);
2008 }
2009
2010 /*
2011 * Update the user/goal/curr tables of wide negotiation
2012 * parameters as well as, in the case of a current or active update,
2013 * any data structures on the host controller. In the case of an
2014 * active update, the specified target is currently talking to us on
2015 * the bus, so the transfer parameter update must take effect
2016 * immediately.
2017 */
2018 void
ahc_set_width(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int width,u_int type,int paused)2019 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2020 u_int width, u_int type, int paused)
2021 {
2022 struct ahc_initiator_tinfo *tinfo;
2023 struct ahc_tmode_tstate *tstate;
2024 u_int oldwidth;
2025 int active;
2026 int update_needed;
2027
2028 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2029 update_needed = 0;
2030 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2031 devinfo->target, &tstate);
2032
2033 if ((type & AHC_TRANS_USER) != 0)
2034 tinfo->user.width = width;
2035
2036 if ((type & AHC_TRANS_GOAL) != 0)
2037 tinfo->goal.width = width;
2038
2039 oldwidth = tinfo->curr.width;
2040 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2041 u_int scsirate;
2042
2043 update_needed++;
2044 scsirate = tinfo->scsirate;
2045 scsirate &= ~WIDEXFER;
2046 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2047 scsirate |= WIDEXFER;
2048
2049 tinfo->scsirate = scsirate;
2050
2051 if (active)
2052 ahc_outb(ahc, SCSIRATE, scsirate);
2053
2054 tinfo->curr.width = width;
2055
2056 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2057 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2058 if (bootverbose) {
2059 printf("%s: target %d using %dbit transfers\n",
2060 ahc_name(ahc), devinfo->target,
2061 8 * (0x01 << width));
2062 }
2063 }
2064
2065 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2066 tinfo, AHC_NEG_TO_GOAL);
2067 if (update_needed)
2068 ahc_update_pending_scbs(ahc);
2069 }
2070
2071 /*
2072 * Update the current state of tagged queuing for a given target.
2073 */
2074 void
ahc_set_tags(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,ahc_queue_alg alg)2075 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2076 ahc_queue_alg alg)
2077 {
2078 ahc_platform_set_tags(ahc, devinfo, alg);
2079 }
2080
2081 /*
2082 * When the transfer settings for a connection change, update any
2083 * in-transit SCBs to contain the new data so the hardware will
2084 * be set correctly during future (re)selections.
2085 */
2086 static void
ahc_update_pending_scbs(struct ahc_softc * ahc)2087 ahc_update_pending_scbs(struct ahc_softc *ahc)
2088 {
2089 struct scb *pending_scb;
2090 int pending_scb_count;
2091 int i;
2092 int paused;
2093 u_int saved_scbptr;
2094
2095 /*
2096 * Traverse the pending SCB list and ensure that all of the
2097 * SCBs there have the proper settings.
2098 */
2099 pending_scb_count = 0;
2100 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2101 struct ahc_devinfo devinfo;
2102 struct hardware_scb *pending_hscb;
2103 struct ahc_initiator_tinfo *tinfo;
2104 struct ahc_tmode_tstate *tstate;
2105
2106 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2107 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2108 devinfo.our_scsiid,
2109 devinfo.target, &tstate);
2110 pending_hscb = pending_scb->hscb;
2111 pending_hscb->control &= ~ULTRAENB;
2112 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2113 pending_hscb->control |= ULTRAENB;
2114 pending_hscb->scsirate = tinfo->scsirate;
2115 pending_hscb->scsioffset = tinfo->curr.offset;
2116 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2117 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2118 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2119 pending_hscb->control &= ~MK_MESSAGE;
2120 }
2121 ahc_sync_scb(ahc, pending_scb,
2122 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2123 pending_scb_count++;
2124 }
2125
2126 if (pending_scb_count == 0)
2127 return;
2128
2129 if (ahc_is_paused(ahc)) {
2130 paused = 1;
2131 } else {
2132 paused = 0;
2133 ahc_pause(ahc);
2134 }
2135
2136 saved_scbptr = ahc_inb(ahc, SCBPTR);
2137 /* Ensure that the hscbs down on the card match the new information */
2138 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2139 struct hardware_scb *pending_hscb;
2140 u_int control;
2141 u_int scb_tag;
2142
2143 ahc_outb(ahc, SCBPTR, i);
2144 scb_tag = ahc_inb(ahc, SCB_TAG);
2145 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2146 if (pending_scb == NULL)
2147 continue;
2148
2149 pending_hscb = pending_scb->hscb;
2150 control = ahc_inb(ahc, SCB_CONTROL);
2151 control &= ~(ULTRAENB|MK_MESSAGE);
2152 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2153 ahc_outb(ahc, SCB_CONTROL, control);
2154 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2155 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2156 }
2157 ahc_outb(ahc, SCBPTR, saved_scbptr);
2158
2159 if (paused == 0)
2160 ahc_unpause(ahc);
2161 }
2162
2163 /**************************** Pathing Information *****************************/
2164 static void
ahc_fetch_devinfo(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2165 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2166 {
2167 u_int saved_scsiid;
2168 role_t role;
2169 int our_id;
2170
2171 if (ahc_inb(ahc, SSTAT0) & TARGET)
2172 role = ROLE_TARGET;
2173 else
2174 role = ROLE_INITIATOR;
2175
2176 if (role == ROLE_TARGET
2177 && (ahc->features & AHC_MULTI_TID) != 0
2178 && (ahc_inb(ahc, SEQ_FLAGS)
2179 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2180 /* We were selected, so pull our id from TARGIDIN */
2181 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2182 } else if ((ahc->features & AHC_ULTRA2) != 0)
2183 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2184 else
2185 our_id = ahc_inb(ahc, SCSIID) & OID;
2186
2187 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2188 ahc_compile_devinfo(devinfo,
2189 our_id,
2190 SCSIID_TARGET(ahc, saved_scsiid),
2191 ahc_inb(ahc, SAVED_LUN),
2192 SCSIID_CHANNEL(ahc, saved_scsiid),
2193 role);
2194 }
2195
2196 struct ahc_phase_table_entry*
ahc_lookup_phase_entry(int phase)2197 ahc_lookup_phase_entry(int phase)
2198 {
2199 struct ahc_phase_table_entry *entry;
2200 struct ahc_phase_table_entry *last_entry;
2201
2202 /*
2203 * num_phases doesn't include the default entry which
2204 * will be returned if the phase doesn't match.
2205 */
2206 last_entry = &ahc_phase_table[num_phases];
2207 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2208 if (phase == entry->phase)
2209 break;
2210 }
2211 return (entry);
2212 }
2213
2214 void
ahc_compile_devinfo(struct ahc_devinfo * devinfo,u_int our_id,u_int target,u_int lun,char channel,role_t role)2215 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2216 u_int lun, char channel, role_t role)
2217 {
2218 devinfo->our_scsiid = our_id;
2219 devinfo->target = target;
2220 devinfo->lun = lun;
2221 devinfo->target_offset = target;
2222 devinfo->channel = channel;
2223 devinfo->role = role;
2224 if (channel == 'B')
2225 devinfo->target_offset += 8;
2226 devinfo->target_mask = (0x01 << devinfo->target_offset);
2227 }
2228
2229 void
ahc_print_devinfo(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2230 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2231 {
2232 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2233 devinfo->target, devinfo->lun);
2234 }
2235
2236 static void
ahc_scb_devinfo(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct scb * scb)2237 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2238 struct scb *scb)
2239 {
2240 role_t role;
2241 int our_id;
2242
2243 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2244 role = ROLE_INITIATOR;
2245 if ((scb->flags & SCB_TARGET_SCB) != 0)
2246 role = ROLE_TARGET;
2247 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2248 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2249 }
2250
2251
2252 /************************ Message Phase Processing ****************************/
2253 static void
ahc_assert_atn(struct ahc_softc * ahc)2254 ahc_assert_atn(struct ahc_softc *ahc)
2255 {
2256 u_int scsisigo;
2257
2258 scsisigo = ATNO;
2259 if ((ahc->features & AHC_DT) == 0)
2260 scsisigo |= ahc_inb(ahc, SCSISIGI);
2261 ahc_outb(ahc, SCSISIGO, scsisigo);
2262 }
2263
2264 /*
2265 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2266 * or enters the initial message out phase, we are interrupted. Fill our
2267 * outgoing message buffer with the appropriate message and begin handing
2268 * the message phase(s) manually.
2269 */
2270 static void
ahc_setup_initiator_msgout(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct scb * scb)2271 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2272 struct scb *scb)
2273 {
2274 /*
2275 * To facilitate adding multiple messages together,
2276 * each routine should increment the index and len
2277 * variables instead of setting them explicitly.
2278 */
2279 ahc->msgout_index = 0;
2280 ahc->msgout_len = 0;
2281
2282 if ((scb->flags & SCB_DEVICE_RESET) == 0
2283 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2284 u_int identify_msg;
2285
2286 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2287 if ((scb->hscb->control & DISCENB) != 0)
2288 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2289 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2290 ahc->msgout_len++;
2291
2292 if ((scb->hscb->control & TAG_ENB) != 0) {
2293 ahc->msgout_buf[ahc->msgout_index++] =
2294 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2295 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2296 ahc->msgout_len += 2;
2297 }
2298 }
2299
2300 if (scb->flags & SCB_DEVICE_RESET) {
2301 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2302 ahc->msgout_len++;
2303 ahc_print_path(ahc, scb);
2304 printf("Bus Device Reset Message Sent\n");
2305 /*
2306 * Clear our selection hardware in advance of
2307 * the busfree. We may have an entry in the waiting
2308 * Q for this target, and we don't want to go about
2309 * selecting while we handle the busfree and blow it
2310 * away.
2311 */
2312 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2313 } else if ((scb->flags & SCB_ABORT) != 0) {
2314 if ((scb->hscb->control & TAG_ENB) != 0)
2315 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2316 else
2317 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2318 ahc->msgout_len++;
2319 ahc_print_path(ahc, scb);
2320 printf("Abort%s Message Sent\n",
2321 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2322 /*
2323 * Clear our selection hardware in advance of
2324 * the busfree. We may have an entry in the waiting
2325 * Q for this target, and we don't want to go about
2326 * selecting while we handle the busfree and blow it
2327 * away.
2328 */
2329 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2330 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2331 ahc_build_transfer_msg(ahc, devinfo);
2332 } else {
2333 printf("ahc_intr: AWAITING_MSG for an SCB that "
2334 "does not have a waiting message\n");
2335 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2336 devinfo->target_mask);
2337 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2338 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2339 ahc_inb(ahc, MSG_OUT), scb->flags);
2340 }
2341
2342 /*
2343 * Clear the MK_MESSAGE flag from the SCB so we aren't
2344 * asked to send this message again.
2345 */
2346 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2347 scb->hscb->control &= ~MK_MESSAGE;
2348 ahc->msgout_index = 0;
2349 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2350 }
2351
2352 /*
2353 * Build an appropriate transfer negotiation message for the
2354 * currently active target.
2355 */
2356 static void
ahc_build_transfer_msg(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2357 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2358 {
2359 /*
2360 * We need to initiate transfer negotiations.
2361 * If our current and goal settings are identical,
2362 * we want to renegotiate due to a check condition.
2363 */
2364 struct ahc_initiator_tinfo *tinfo;
2365 struct ahc_tmode_tstate *tstate;
2366 struct ahc_syncrate *rate;
2367 int dowide;
2368 int dosync;
2369 int doppr;
2370 u_int period;
2371 u_int ppr_options;
2372 u_int offset;
2373
2374 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2375 devinfo->target, &tstate);
2376 /*
2377 * Filter our period based on the current connection.
2378 * If we can't perform DT transfers on this segment (not in LVD
2379 * mode for instance), then our decision to issue a PPR message
2380 * may change.
2381 */
2382 period = tinfo->goal.period;
2383 ppr_options = tinfo->goal.ppr_options;
2384 /* Target initiated PPR is not allowed in the SCSI spec */
2385 if (devinfo->role == ROLE_TARGET)
2386 ppr_options = 0;
2387 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2388 &ppr_options, devinfo->role);
2389 dowide = tinfo->curr.width != tinfo->goal.width;
2390 dosync = tinfo->curr.period != period;
2391 /*
2392 * Only use PPR if we have options that need it, even if the device
2393 * claims to support it. There might be an expander in the way
2394 * that doesn't.
2395 */
2396 doppr = ppr_options != 0;
2397
2398 if (!dowide && !dosync && !doppr) {
2399 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2400 dosync = tinfo->goal.offset != 0;
2401 }
2402
2403 if (!dowide && !dosync && !doppr) {
2404 /*
2405 * Force async with a WDTR message if we have a wide bus,
2406 * or just issue an SDTR with a 0 offset.
2407 */
2408 if ((ahc->features & AHC_WIDE) != 0)
2409 dowide = 1;
2410 else
2411 dosync = 1;
2412
2413 if (bootverbose) {
2414 ahc_print_devinfo(ahc, devinfo);
2415 printf("Ensuring async\n");
2416 }
2417 }
2418
2419 /* Target initiated PPR is not allowed in the SCSI spec */
2420 if (devinfo->role == ROLE_TARGET)
2421 doppr = 0;
2422
2423 /*
2424 * Both the PPR message and SDTR message require the
2425 * goal syncrate to be limited to what the target device
2426 * is capable of handling (based on whether an LVD->SE
2427 * expander is on the bus), so combine these two cases.
2428 * Regardless, guarantee that if we are using WDTR and SDTR
2429 * messages that WDTR comes first.
2430 */
2431 if (doppr || (dosync && !dowide)) {
2432
2433 offset = tinfo->goal.offset;
2434 ahc_validate_offset(ahc, tinfo, rate, &offset,
2435 doppr ? tinfo->goal.width
2436 : tinfo->curr.width,
2437 devinfo->role);
2438 if (doppr) {
2439 ahc_construct_ppr(ahc, devinfo, period, offset,
2440 tinfo->goal.width, ppr_options);
2441 } else {
2442 ahc_construct_sdtr(ahc, devinfo, period, offset);
2443 }
2444 } else {
2445 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2446 }
2447 }
2448
2449 /*
2450 * Build a synchronous negotiation message in our message
2451 * buffer based on the input parameters.
2452 */
2453 static void
ahc_construct_sdtr(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int period,u_int offset)2454 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2455 u_int period, u_int offset)
2456 {
2457 if (offset == 0)
2458 period = AHC_ASYNC_XFER_PERIOD;
2459 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2460 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2461 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2462 ahc->msgout_buf[ahc->msgout_index++] = period;
2463 ahc->msgout_buf[ahc->msgout_index++] = offset;
2464 ahc->msgout_len += 5;
2465 if (bootverbose) {
2466 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2467 ahc_name(ahc), devinfo->channel, devinfo->target,
2468 devinfo->lun, period, offset);
2469 }
2470 }
2471
2472 /*
2473 * Build a wide negotiation message in our message
2474 * buffer based on the input parameters.
2475 */
2476 static void
ahc_construct_wdtr(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int bus_width)2477 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2478 u_int bus_width)
2479 {
2480 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2481 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2482 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2483 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2484 ahc->msgout_len += 4;
2485 if (bootverbose) {
2486 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2487 ahc_name(ahc), devinfo->channel, devinfo->target,
2488 devinfo->lun, bus_width);
2489 }
2490 }
2491
2492 /*
2493 * Build a parallel protocol request message in our message
2494 * buffer based on the input parameters.
2495 */
2496 static void
ahc_construct_ppr(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int period,u_int offset,u_int bus_width,u_int ppr_options)2497 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2498 u_int period, u_int offset, u_int bus_width,
2499 u_int ppr_options)
2500 {
2501 if (offset == 0)
2502 period = AHC_ASYNC_XFER_PERIOD;
2503 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2504 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2505 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2506 ahc->msgout_buf[ahc->msgout_index++] = period;
2507 ahc->msgout_buf[ahc->msgout_index++] = 0;
2508 ahc->msgout_buf[ahc->msgout_index++] = offset;
2509 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2510 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2511 ahc->msgout_len += 8;
2512 if (bootverbose) {
2513 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2514 "offset %x, ppr_options %x\n", ahc_name(ahc),
2515 devinfo->channel, devinfo->target, devinfo->lun,
2516 bus_width, period, offset, ppr_options);
2517 }
2518 }
2519
2520 /*
2521 * Clear any active message state.
2522 */
2523 static void
ahc_clear_msg_state(struct ahc_softc * ahc)2524 ahc_clear_msg_state(struct ahc_softc *ahc)
2525 {
2526 ahc->msgout_len = 0;
2527 ahc->msgin_index = 0;
2528 ahc->msg_type = MSG_TYPE_NONE;
2529 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2530 /*
2531 * The target didn't care to respond to our
2532 * message request, so clear ATN.
2533 */
2534 ahc_outb(ahc, CLRSINT1, CLRATNO);
2535 }
2536 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2537 ahc_outb(ahc, SEQ_FLAGS2,
2538 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2539 }
2540
2541 static void
ahc_handle_proto_violation(struct ahc_softc * ahc)2542 ahc_handle_proto_violation(struct ahc_softc *ahc)
2543 {
2544 struct ahc_devinfo devinfo;
2545 struct scb *scb;
2546 u_int scbid;
2547 u_int seq_flags;
2548 u_int curphase;
2549 u_int lastphase;
2550 int found;
2551
2552 ahc_fetch_devinfo(ahc, &devinfo);
2553 scbid = ahc_inb(ahc, SCB_TAG);
2554 scb = ahc_lookup_scb(ahc, scbid);
2555 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2556 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2557 lastphase = ahc_inb(ahc, LASTPHASE);
2558 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2559
2560 /*
2561 * The reconnecting target either did not send an
2562 * identify message, or did, but we didn't find an SCB
2563 * to match.
2564 */
2565 ahc_print_devinfo(ahc, &devinfo);
2566 printf("Target did not send an IDENTIFY message. "
2567 "LASTPHASE = 0x%x.\n", lastphase);
2568 scb = NULL;
2569 } else if (scb == NULL) {
2570 /*
2571 * We don't seem to have an SCB active for this
2572 * transaction. Print an error and reset the bus.
2573 */
2574 ahc_print_devinfo(ahc, &devinfo);
2575 printf("No SCB found during protocol violation\n");
2576 goto proto_violation_reset;
2577 } else {
2578 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2579 if ((seq_flags & NO_CDB_SENT) != 0) {
2580 ahc_print_path(ahc, scb);
2581 printf("No or incomplete CDB sent to device.\n");
2582 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2583 /*
2584 * The target never bothered to provide status to
2585 * us prior to completing the command. Since we don't
2586 * know the disposition of this command, we must attempt
2587 * to abort it. Assert ATN and prepare to send an abort
2588 * message.
2589 */
2590 ahc_print_path(ahc, scb);
2591 printf("Completed command without status.\n");
2592 } else {
2593 ahc_print_path(ahc, scb);
2594 printf("Unknown protocol violation.\n");
2595 ahc_dump_card_state(ahc);
2596 }
2597 }
2598 if ((lastphase & ~P_DATAIN_DT) == 0
2599 || lastphase == P_COMMAND) {
2600 proto_violation_reset:
2601 /*
2602 * Target either went directly to data/command
2603 * phase or didn't respond to our ATN.
2604 * The only safe thing to do is to blow
2605 * it away with a bus reset.
2606 */
2607 found = ahc_reset_channel(ahc, 'A', TRUE);
2608 printf("%s: Issued Channel %c Bus Reset. "
2609 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2610 } else {
2611 /*
2612 * Leave the selection hardware off in case
2613 * this abort attempt will affect yet to
2614 * be sent commands.
2615 */
2616 ahc_outb(ahc, SCSISEQ,
2617 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2618 ahc_assert_atn(ahc);
2619 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2620 if (scb == NULL) {
2621 ahc_print_devinfo(ahc, &devinfo);
2622 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2623 ahc->msgout_len = 1;
2624 ahc->msgout_index = 0;
2625 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2626 } else {
2627 ahc_print_path(ahc, scb);
2628 scb->flags |= SCB_ABORT;
2629 }
2630 printf("Protocol violation %s. Attempting to abort.\n",
2631 ahc_lookup_phase_entry(curphase)->phasemsg);
2632 }
2633 }
2634
2635 /*
2636 * Manual message loop handler.
2637 */
2638 static void
ahc_handle_message_phase(struct ahc_softc * ahc)2639 ahc_handle_message_phase(struct ahc_softc *ahc)
2640 {
2641 struct ahc_devinfo devinfo;
2642 u_int bus_phase;
2643 int end_session;
2644
2645 ahc_fetch_devinfo(ahc, &devinfo);
2646 end_session = FALSE;
2647 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2648
2649 reswitch:
2650 switch (ahc->msg_type) {
2651 case MSG_TYPE_INITIATOR_MSGOUT:
2652 {
2653 int lastbyte;
2654 int phasemis;
2655 int msgdone;
2656
2657 if (ahc->msgout_len == 0)
2658 panic("HOST_MSG_LOOP interrupt with no active message");
2659
2660 #ifdef AHC_DEBUG
2661 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2662 ahc_print_devinfo(ahc, &devinfo);
2663 printf("INITIATOR_MSG_OUT");
2664 }
2665 #endif
2666 phasemis = bus_phase != P_MESGOUT;
2667 if (phasemis) {
2668 #ifdef AHC_DEBUG
2669 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2670 printf(" PHASEMIS %s\n",
2671 ahc_lookup_phase_entry(bus_phase)
2672 ->phasemsg);
2673 }
2674 #endif
2675 if (bus_phase == P_MESGIN) {
2676 /*
2677 * Change gears and see if
2678 * this messages is of interest to
2679 * us or should be passed back to
2680 * the sequencer.
2681 */
2682 ahc_outb(ahc, CLRSINT1, CLRATNO);
2683 ahc->send_msg_perror = FALSE;
2684 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2685 ahc->msgin_index = 0;
2686 goto reswitch;
2687 }
2688 end_session = TRUE;
2689 break;
2690 }
2691
2692 if (ahc->send_msg_perror) {
2693 ahc_outb(ahc, CLRSINT1, CLRATNO);
2694 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2695 #ifdef AHC_DEBUG
2696 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2697 printf(" byte 0x%x\n", ahc->send_msg_perror);
2698 #endif
2699 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2700 break;
2701 }
2702
2703 msgdone = ahc->msgout_index == ahc->msgout_len;
2704 if (msgdone) {
2705 /*
2706 * The target has requested a retry.
2707 * Re-assert ATN, reset our message index to
2708 * 0, and try again.
2709 */
2710 ahc->msgout_index = 0;
2711 ahc_assert_atn(ahc);
2712 }
2713
2714 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2715 if (lastbyte) {
2716 /* Last byte is signified by dropping ATN */
2717 ahc_outb(ahc, CLRSINT1, CLRATNO);
2718 }
2719
2720 /*
2721 * Clear our interrupt status and present
2722 * the next byte on the bus.
2723 */
2724 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2725 #ifdef AHC_DEBUG
2726 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2727 printf(" byte 0x%x\n",
2728 ahc->msgout_buf[ahc->msgout_index]);
2729 #endif
2730 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2731 break;
2732 }
2733 case MSG_TYPE_INITIATOR_MSGIN:
2734 {
2735 int phasemis;
2736 int message_done;
2737
2738 #ifdef AHC_DEBUG
2739 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2740 ahc_print_devinfo(ahc, &devinfo);
2741 printf("INITIATOR_MSG_IN");
2742 }
2743 #endif
2744 phasemis = bus_phase != P_MESGIN;
2745 if (phasemis) {
2746 #ifdef AHC_DEBUG
2747 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2748 printf(" PHASEMIS %s\n",
2749 ahc_lookup_phase_entry(bus_phase)
2750 ->phasemsg);
2751 }
2752 #endif
2753 ahc->msgin_index = 0;
2754 if (bus_phase == P_MESGOUT
2755 && (ahc->send_msg_perror == TRUE
2756 || (ahc->msgout_len != 0
2757 && ahc->msgout_index == 0))) {
2758 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2759 goto reswitch;
2760 }
2761 end_session = TRUE;
2762 break;
2763 }
2764
2765 /* Pull the byte in without acking it */
2766 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2767 #ifdef AHC_DEBUG
2768 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2769 printf(" byte 0x%x\n",
2770 ahc->msgin_buf[ahc->msgin_index]);
2771 #endif
2772
2773 message_done = ahc_parse_msg(ahc, &devinfo);
2774
2775 if (message_done) {
2776 /*
2777 * Clear our incoming message buffer in case there
2778 * is another message following this one.
2779 */
2780 ahc->msgin_index = 0;
2781
2782 /*
2783 * If this message illicited a response,
2784 * assert ATN so the target takes us to the
2785 * message out phase.
2786 */
2787 if (ahc->msgout_len != 0) {
2788 #ifdef AHC_DEBUG
2789 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2790 ahc_print_devinfo(ahc, &devinfo);
2791 printf("Asserting ATN for response\n");
2792 }
2793 #endif
2794 ahc_assert_atn(ahc);
2795 }
2796 } else
2797 ahc->msgin_index++;
2798
2799 if (message_done == MSGLOOP_TERMINATED) {
2800 end_session = TRUE;
2801 } else {
2802 /* Ack the byte */
2803 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2804 (void)ahc_inb(ahc, SCSIDATL);
2805 }
2806 break;
2807 }
2808 case MSG_TYPE_TARGET_MSGIN:
2809 {
2810 int msgdone;
2811 int msgout_request;
2812
2813 if (ahc->msgout_len == 0)
2814 panic("Target MSGIN with no active message");
2815
2816 /*
2817 * If we interrupted a mesgout session, the initiator
2818 * will not know this until our first REQ. So, we
2819 * only honor mesgout requests after we've sent our
2820 * first byte.
2821 */
2822 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2823 && ahc->msgout_index > 0)
2824 msgout_request = TRUE;
2825 else
2826 msgout_request = FALSE;
2827
2828 if (msgout_request) {
2829
2830 /*
2831 * Change gears and see if
2832 * this messages is of interest to
2833 * us or should be passed back to
2834 * the sequencer.
2835 */
2836 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2837 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2838 ahc->msgin_index = 0;
2839 /* Dummy read to REQ for first byte */
2840 (void)ahc_inb(ahc, SCSIDATL);
2841 ahc_outb(ahc, SXFRCTL0,
2842 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2843 break;
2844 }
2845
2846 msgdone = ahc->msgout_index == ahc->msgout_len;
2847 if (msgdone) {
2848 ahc_outb(ahc, SXFRCTL0,
2849 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2850 end_session = TRUE;
2851 break;
2852 }
2853
2854 /*
2855 * Present the next byte on the bus.
2856 */
2857 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2858 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2859 break;
2860 }
2861 case MSG_TYPE_TARGET_MSGOUT:
2862 {
2863 int lastbyte;
2864 int msgdone;
2865
2866 /*
2867 * The initiator signals that this is
2868 * the last byte by dropping ATN.
2869 */
2870 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2871
2872 /*
2873 * Read the latched byte, but turn off SPIOEN first
2874 * so that we don't inadvertently cause a REQ for the
2875 * next byte.
2876 */
2877 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2878 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2879 msgdone = ahc_parse_msg(ahc, &devinfo);
2880 if (msgdone == MSGLOOP_TERMINATED) {
2881 /*
2882 * The message is *really* done in that it caused
2883 * us to go to bus free. The sequencer has already
2884 * been reset at this point, so pull the ejection
2885 * handle.
2886 */
2887 return;
2888 }
2889
2890 ahc->msgin_index++;
2891
2892 /*
2893 * XXX Read spec about initiator dropping ATN too soon
2894 * and use msgdone to detect it.
2895 */
2896 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2897 ahc->msgin_index = 0;
2898
2899 /*
2900 * If this message illicited a response, transition
2901 * to the Message in phase and send it.
2902 */
2903 if (ahc->msgout_len != 0) {
2904 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2905 ahc_outb(ahc, SXFRCTL0,
2906 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2907 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2908 ahc->msgin_index = 0;
2909 break;
2910 }
2911 }
2912
2913 if (lastbyte)
2914 end_session = TRUE;
2915 else {
2916 /* Ask for the next byte. */
2917 ahc_outb(ahc, SXFRCTL0,
2918 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2919 }
2920
2921 break;
2922 }
2923 default:
2924 panic("Unknown REQINIT message type");
2925 }
2926
2927 if (end_session) {
2928 ahc_clear_msg_state(ahc);
2929 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2930 } else
2931 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2932 }
2933
2934 /*
2935 * See if we sent a particular extended message to the target.
2936 * If "full" is true, return true only if the target saw the full
2937 * message. If "full" is false, return true if the target saw at
2938 * least the first byte of the message.
2939 */
2940 static int
ahc_sent_msg(struct ahc_softc * ahc,ahc_msgtype type,u_int msgval,int full)2941 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2942 {
2943 int found;
2944 u_int index;
2945
2946 found = FALSE;
2947 index = 0;
2948
2949 while (index < ahc->msgout_len) {
2950 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2951 u_int end_index;
2952
2953 end_index = index + 1 + ahc->msgout_buf[index + 1];
2954 if (ahc->msgout_buf[index+2] == msgval
2955 && type == AHCMSG_EXT) {
2956
2957 if (full) {
2958 if (ahc->msgout_index > end_index)
2959 found = TRUE;
2960 } else if (ahc->msgout_index > index)
2961 found = TRUE;
2962 }
2963 index = end_index;
2964 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2965 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2966
2967 /* Skip tag type and tag id or residue param*/
2968 index += 2;
2969 } else {
2970 /* Single byte message */
2971 if (type == AHCMSG_1B
2972 && ahc->msgout_buf[index] == msgval
2973 && ahc->msgout_index > index)
2974 found = TRUE;
2975 index++;
2976 }
2977
2978 if (found)
2979 break;
2980 }
2981 return (found);
2982 }
2983
2984 /*
2985 * Wait for a complete incoming message, parse it, and respond accordingly.
2986 */
2987 static int
ahc_parse_msg(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2988 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2989 {
2990 struct ahc_initiator_tinfo *tinfo;
2991 struct ahc_tmode_tstate *tstate;
2992 int reject;
2993 int done;
2994 int response;
2995 u_int targ_scsirate;
2996
2997 done = MSGLOOP_IN_PROG;
2998 response = FALSE;
2999 reject = FALSE;
3000 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3001 devinfo->target, &tstate);
3002 targ_scsirate = tinfo->scsirate;
3003
3004 /*
3005 * Parse as much of the message as is available,
3006 * rejecting it if we don't support it. When
3007 * the entire message is available and has been
3008 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3009 * that we have parsed an entire message.
3010 *
3011 * In the case of extended messages, we accept the length
3012 * byte outright and perform more checking once we know the
3013 * extended message type.
3014 */
3015 switch (ahc->msgin_buf[0]) {
3016 case MSG_DISCONNECT:
3017 case MSG_SAVEDATAPOINTER:
3018 case MSG_CMDCOMPLETE:
3019 case MSG_RESTOREPOINTERS:
3020 case MSG_IGN_WIDE_RESIDUE:
3021 /*
3022 * End our message loop as these are messages
3023 * the sequencer handles on its own.
3024 */
3025 done = MSGLOOP_TERMINATED;
3026 break;
3027 case MSG_MESSAGE_REJECT:
3028 response = ahc_handle_msg_reject(ahc, devinfo);
3029 /* FALLTHROUGH */
3030 case MSG_NOOP:
3031 done = MSGLOOP_MSGCOMPLETE;
3032 break;
3033 case MSG_EXTENDED:
3034 {
3035 /* Wait for enough of the message to begin validation */
3036 if (ahc->msgin_index < 2)
3037 break;
3038 switch (ahc->msgin_buf[2]) {
3039 case MSG_EXT_SDTR:
3040 {
3041 struct ahc_syncrate *syncrate;
3042 u_int period;
3043 u_int ppr_options;
3044 u_int offset;
3045 u_int saved_offset;
3046
3047 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3048 reject = TRUE;
3049 break;
3050 }
3051
3052 /*
3053 * Wait until we have both args before validating
3054 * and acting on this message.
3055 *
3056 * Add one to MSG_EXT_SDTR_LEN to account for
3057 * the extended message preamble.
3058 */
3059 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3060 break;
3061
3062 period = ahc->msgin_buf[3];
3063 ppr_options = 0;
3064 saved_offset = offset = ahc->msgin_buf[4];
3065 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3066 &ppr_options,
3067 devinfo->role);
3068 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3069 targ_scsirate & WIDEXFER,
3070 devinfo->role);
3071 if (bootverbose) {
3072 printf("(%s:%c:%d:%d): Received "
3073 "SDTR period %x, offset %x\n\t"
3074 "Filtered to period %x, offset %x\n",
3075 ahc_name(ahc), devinfo->channel,
3076 devinfo->target, devinfo->lun,
3077 ahc->msgin_buf[3], saved_offset,
3078 period, offset);
3079 }
3080 ahc_set_syncrate(ahc, devinfo,
3081 syncrate, period,
3082 offset, ppr_options,
3083 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3084 /*paused*/TRUE);
3085
3086 /*
3087 * See if we initiated Sync Negotiation
3088 * and didn't have to fall down to async
3089 * transfers.
3090 */
3091 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3092 /* We started it */
3093 if (saved_offset != offset) {
3094 /* Went too low - force async */
3095 reject = TRUE;
3096 }
3097 } else {
3098 /*
3099 * Send our own SDTR in reply
3100 */
3101 if (bootverbose
3102 && devinfo->role == ROLE_INITIATOR) {
3103 printf("(%s:%c:%d:%d): Target "
3104 "Initiated SDTR\n",
3105 ahc_name(ahc), devinfo->channel,
3106 devinfo->target, devinfo->lun);
3107 }
3108 ahc->msgout_index = 0;
3109 ahc->msgout_len = 0;
3110 ahc_construct_sdtr(ahc, devinfo,
3111 period, offset);
3112 ahc->msgout_index = 0;
3113 response = TRUE;
3114 }
3115 done = MSGLOOP_MSGCOMPLETE;
3116 break;
3117 }
3118 case MSG_EXT_WDTR:
3119 {
3120 u_int bus_width;
3121 u_int saved_width;
3122 u_int sending_reply;
3123
3124 sending_reply = FALSE;
3125 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3126 reject = TRUE;
3127 break;
3128 }
3129
3130 /*
3131 * Wait until we have our arg before validating
3132 * and acting on this message.
3133 *
3134 * Add one to MSG_EXT_WDTR_LEN to account for
3135 * the extended message preamble.
3136 */
3137 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3138 break;
3139
3140 bus_width = ahc->msgin_buf[3];
3141 saved_width = bus_width;
3142 ahc_validate_width(ahc, tinfo, &bus_width,
3143 devinfo->role);
3144 if (bootverbose) {
3145 printf("(%s:%c:%d:%d): Received WDTR "
3146 "%x filtered to %x\n",
3147 ahc_name(ahc), devinfo->channel,
3148 devinfo->target, devinfo->lun,
3149 saved_width, bus_width);
3150 }
3151
3152 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3153 /*
3154 * Don't send a WDTR back to the
3155 * target, since we asked first.
3156 * If the width went higher than our
3157 * request, reject it.
3158 */
3159 if (saved_width > bus_width) {
3160 reject = TRUE;
3161 printf("(%s:%c:%d:%d): requested %dBit "
3162 "transfers. Rejecting...\n",
3163 ahc_name(ahc), devinfo->channel,
3164 devinfo->target, devinfo->lun,
3165 8 * (0x01 << bus_width));
3166 bus_width = 0;
3167 }
3168 } else {
3169 /*
3170 * Send our own WDTR in reply
3171 */
3172 if (bootverbose
3173 && devinfo->role == ROLE_INITIATOR) {
3174 printf("(%s:%c:%d:%d): Target "
3175 "Initiated WDTR\n",
3176 ahc_name(ahc), devinfo->channel,
3177 devinfo->target, devinfo->lun);
3178 }
3179 ahc->msgout_index = 0;
3180 ahc->msgout_len = 0;
3181 ahc_construct_wdtr(ahc, devinfo, bus_width);
3182 ahc->msgout_index = 0;
3183 response = TRUE;
3184 sending_reply = TRUE;
3185 }
3186 ahc_set_width(ahc, devinfo, bus_width,
3187 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3188 /*paused*/TRUE);
3189 /* After a wide message, we are async */
3190 ahc_set_syncrate(ahc, devinfo,
3191 /*syncrate*/NULL, /*period*/0,
3192 /*offset*/0, /*ppr_options*/0,
3193 AHC_TRANS_ACTIVE, /*paused*/TRUE);
3194 if (sending_reply == FALSE && reject == FALSE) {
3195
3196 if (tinfo->goal.offset) {
3197 ahc->msgout_index = 0;
3198 ahc->msgout_len = 0;
3199 ahc_build_transfer_msg(ahc, devinfo);
3200 ahc->msgout_index = 0;
3201 response = TRUE;
3202 }
3203 }
3204 done = MSGLOOP_MSGCOMPLETE;
3205 break;
3206 }
3207 case MSG_EXT_PPR:
3208 {
3209 struct ahc_syncrate *syncrate;
3210 u_int period;
3211 u_int offset;
3212 u_int bus_width;
3213 u_int ppr_options;
3214 u_int saved_width;
3215 u_int saved_offset;
3216 u_int saved_ppr_options;
3217
3218 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3219 reject = TRUE;
3220 break;
3221 }
3222
3223 /*
3224 * Wait until we have all args before validating
3225 * and acting on this message.
3226 *
3227 * Add one to MSG_EXT_PPR_LEN to account for
3228 * the extended message preamble.
3229 */
3230 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3231 break;
3232
3233 period = ahc->msgin_buf[3];
3234 offset = ahc->msgin_buf[5];
3235 bus_width = ahc->msgin_buf[6];
3236 saved_width = bus_width;
3237 ppr_options = ahc->msgin_buf[7];
3238 /*
3239 * According to the spec, a DT only
3240 * period factor with no DT option
3241 * set implies async.
3242 */
3243 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3244 && period == 9)
3245 offset = 0;
3246 saved_ppr_options = ppr_options;
3247 saved_offset = offset;
3248
3249 /*
3250 * Mask out any options we don't support
3251 * on any controller. Transfer options are
3252 * only available if we are negotiating wide.
3253 */
3254 ppr_options &= MSG_EXT_PPR_DT_REQ;
3255 if (bus_width == 0)
3256 ppr_options = 0;
3257
3258 ahc_validate_width(ahc, tinfo, &bus_width,
3259 devinfo->role);
3260 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3261 &ppr_options,
3262 devinfo->role);
3263 ahc_validate_offset(ahc, tinfo, syncrate,
3264 &offset, bus_width,
3265 devinfo->role);
3266
3267 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3268 /*
3269 * If we are unable to do any of the
3270 * requested options (we went too low),
3271 * then we'll have to reject the message.
3272 */
3273 if (saved_width > bus_width
3274 || saved_offset != offset
3275 || saved_ppr_options != ppr_options) {
3276 reject = TRUE;
3277 period = 0;
3278 offset = 0;
3279 bus_width = 0;
3280 ppr_options = 0;
3281 syncrate = NULL;
3282 }
3283 } else {
3284 if (devinfo->role != ROLE_TARGET)
3285 printf("(%s:%c:%d:%d): Target "
3286 "Initiated PPR\n",
3287 ahc_name(ahc), devinfo->channel,
3288 devinfo->target, devinfo->lun);
3289 else
3290 printf("(%s:%c:%d:%d): Initiator "
3291 "Initiated PPR\n",
3292 ahc_name(ahc), devinfo->channel,
3293 devinfo->target, devinfo->lun);
3294 ahc->msgout_index = 0;
3295 ahc->msgout_len = 0;
3296 ahc_construct_ppr(ahc, devinfo, period, offset,
3297 bus_width, ppr_options);
3298 ahc->msgout_index = 0;
3299 response = TRUE;
3300 }
3301 if (bootverbose) {
3302 printf("(%s:%c:%d:%d): Received PPR width %x, "
3303 "period %x, offset %x,options %x\n"
3304 "\tFiltered to width %x, period %x, "
3305 "offset %x, options %x\n",
3306 ahc_name(ahc), devinfo->channel,
3307 devinfo->target, devinfo->lun,
3308 saved_width, ahc->msgin_buf[3],
3309 saved_offset, saved_ppr_options,
3310 bus_width, period, offset, ppr_options);
3311 }
3312 ahc_set_width(ahc, devinfo, bus_width,
3313 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3314 /*paused*/TRUE);
3315 ahc_set_syncrate(ahc, devinfo,
3316 syncrate, period,
3317 offset, ppr_options,
3318 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3319 /*paused*/TRUE);
3320 done = MSGLOOP_MSGCOMPLETE;
3321 break;
3322 }
3323 default:
3324 /* Unknown extended message. Reject it. */
3325 reject = TRUE;
3326 break;
3327 }
3328 break;
3329 }
3330 #ifdef AHC_TARGET_MODE
3331 case MSG_BUS_DEV_RESET:
3332 ahc_handle_devreset(ahc, devinfo,
3333 CAM_BDR_SENT,
3334 "Bus Device Reset Received",
3335 /*verbose_level*/0);
3336 ahc_restart(ahc);
3337 done = MSGLOOP_TERMINATED;
3338 break;
3339 case MSG_ABORT_TAG:
3340 case MSG_ABORT:
3341 case MSG_CLEAR_QUEUE:
3342 {
3343 int tag;
3344
3345 /* Target mode messages */
3346 if (devinfo->role != ROLE_TARGET) {
3347 reject = TRUE;
3348 break;
3349 }
3350 tag = SCB_LIST_NULL;
3351 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3352 tag = ahc_inb(ahc, INITIATOR_TAG);
3353 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3354 devinfo->lun, tag, ROLE_TARGET,
3355 CAM_REQ_ABORTED);
3356
3357 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3358 if (tstate != NULL) {
3359 struct ahc_tmode_lstate* lstate;
3360
3361 lstate = tstate->enabled_luns[devinfo->lun];
3362 if (lstate != NULL) {
3363 ahc_queue_lstate_event(ahc, lstate,
3364 devinfo->our_scsiid,
3365 ahc->msgin_buf[0],
3366 /*arg*/tag);
3367 ahc_send_lstate_events(ahc, lstate);
3368 }
3369 }
3370 ahc_restart(ahc);
3371 done = MSGLOOP_TERMINATED;
3372 break;
3373 }
3374 #endif
3375 case MSG_TERM_IO_PROC:
3376 default:
3377 reject = TRUE;
3378 break;
3379 }
3380
3381 if (reject) {
3382 /*
3383 * Setup to reject the message.
3384 */
3385 ahc->msgout_index = 0;
3386 ahc->msgout_len = 1;
3387 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3388 done = MSGLOOP_MSGCOMPLETE;
3389 response = TRUE;
3390 }
3391
3392 if (done != MSGLOOP_IN_PROG && !response)
3393 /* Clear the outgoing message buffer */
3394 ahc->msgout_len = 0;
3395
3396 return (done);
3397 }
3398
3399 /*
3400 * Process a message reject message.
3401 */
3402 static int
ahc_handle_msg_reject(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)3403 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3404 {
3405 /*
3406 * What we care about here is if we had an
3407 * outstanding SDTR or WDTR message for this
3408 * target. If we did, this is a signal that
3409 * the target is refusing negotiation.
3410 */
3411 struct scb *scb;
3412 struct ahc_initiator_tinfo *tinfo;
3413 struct ahc_tmode_tstate *tstate;
3414 u_int scb_index;
3415 u_int last_msg;
3416 int response = 0;
3417
3418 scb_index = ahc_inb(ahc, SCB_TAG);
3419 scb = ahc_lookup_scb(ahc, scb_index);
3420 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3421 devinfo->our_scsiid,
3422 devinfo->target, &tstate);
3423 /* Might be necessary */
3424 last_msg = ahc_inb(ahc, LAST_MSG);
3425
3426 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3427 /*
3428 * Target does not support the PPR message.
3429 * Attempt to negotiate SPI-2 style.
3430 */
3431 if (bootverbose) {
3432 printf("(%s:%c:%d:%d): PPR Rejected. "
3433 "Trying WDTR/SDTR\n",
3434 ahc_name(ahc), devinfo->channel,
3435 devinfo->target, devinfo->lun);
3436 }
3437 tinfo->goal.ppr_options = 0;
3438 tinfo->curr.transport_version = 2;
3439 tinfo->goal.transport_version = 2;
3440 ahc->msgout_index = 0;
3441 ahc->msgout_len = 0;
3442 ahc_build_transfer_msg(ahc, devinfo);
3443 ahc->msgout_index = 0;
3444 response = 1;
3445 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3446
3447 /* note 8bit xfers */
3448 if (bootverbose)
3449 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3450 "8bit transfers\n", ahc_name(ahc),
3451 devinfo->channel, devinfo->target, devinfo->lun);
3452 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3453 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3454 /*paused*/TRUE);
3455 /*
3456 * No need to clear the sync rate. If the target
3457 * did not accept the command, our syncrate is
3458 * unaffected. If the target started the negotiation,
3459 * but rejected our response, we already cleared the
3460 * sync rate before sending our WDTR.
3461 */
3462 if (tinfo->goal.offset != tinfo->curr.offset) {
3463
3464 /* Start the sync negotiation */
3465 ahc->msgout_index = 0;
3466 ahc->msgout_len = 0;
3467 ahc_build_transfer_msg(ahc, devinfo);
3468 ahc->msgout_index = 0;
3469 response = 1;
3470 }
3471 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3472 /* note asynch xfers and clear flag */
3473 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3474 /*offset*/0, /*ppr_options*/0,
3475 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3476 /*paused*/TRUE);
3477 if (bootverbose)
3478 printf("(%s:%c:%d:%d): refuses synchronous negotiation."
3479 " Using asynchronous transfers\n",
3480 ahc_name(ahc), devinfo->channel,
3481 devinfo->target, devinfo->lun);
3482 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3483 int tag_type;
3484 int mask;
3485
3486 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3487
3488 if (tag_type == MSG_SIMPLE_TASK) {
3489 if (bootverbose)
3490 printf("(%s:%c:%d:%d): refuses tagged commands."
3491 " Performing non-tagged I/O\n",
3492 ahc_name(ahc), devinfo->channel,
3493 devinfo->target, devinfo->lun);
3494 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3495 mask = ~0x23;
3496 } else {
3497 if (bootverbose)
3498 printf("(%s:%c:%d:%d): refuses %s tagged "
3499 "commands. Performing simple queue "
3500 "tagged I/O only\n",
3501 ahc_name(ahc), devinfo->channel,
3502 devinfo->target, devinfo->lun,
3503 tag_type == MSG_ORDERED_TASK
3504 ? "ordered" : "head of queue");
3505 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3506 mask = ~0x03;
3507 }
3508
3509 /*
3510 * Resend the identify for this CCB as the target
3511 * may believe that the selection is invalid otherwise.
3512 */
3513 ahc_outb(ahc, SCB_CONTROL,
3514 ahc_inb(ahc, SCB_CONTROL) & mask);
3515 scb->hscb->control &= mask;
3516 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3517 /*type*/MSG_SIMPLE_TASK);
3518 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3519 ahc_assert_atn(ahc);
3520
3521 /*
3522 * This transaction is now at the head of
3523 * the untagged queue for this target.
3524 */
3525 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3526 struct scb_tailq *untagged_q;
3527
3528 untagged_q =
3529 &(ahc->untagged_queues[devinfo->target_offset]);
3530 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3531 scb->flags |= SCB_UNTAGGEDQ;
3532 }
3533 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3534 scb->hscb->tag);
3535
3536 /*
3537 * Requeue all tagged commands for this target
3538 * currently in our possession so they can be
3539 * converted to untagged commands.
3540 */
3541 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3542 SCB_GET_CHANNEL(ahc, scb),
3543 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3544 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3545 SEARCH_COMPLETE);
3546 } else {
3547 /*
3548 * Otherwise, we ignore it.
3549 */
3550 if (bootverbose)
3551 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3552 ahc_name(ahc), devinfo->channel, devinfo->target,
3553 last_msg);
3554 }
3555 return (response);
3556 }
3557
3558 /*
3559 * Process an ignore wide residue message.
3560 */
3561 static void
ahc_handle_ign_wide_residue(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)3562 ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
3563 struct ahc_devinfo *devinfo)
3564 {
3565 u_int scb_index;
3566 struct scb *scb;
3567
3568 scb_index = ahc_inb(ahc, SCB_TAG);
3569 scb = ahc_lookup_scb(ahc, scb_index);
3570 /*
3571 * XXX Actually check data direction in the sequencer?
3572 * Perhaps add datadir to some spare bits in the hscb?
3573 */
3574 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3575 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3576 /*
3577 * Ignore the message if we haven't
3578 * seen an appropriate data phase yet.
3579 */
3580 } else {
3581 /*
3582 * If the residual occurred on the last
3583 * transfer and the transfer request was
3584 * expected to end on an odd count, do
3585 * nothing. Otherwise, subtract a byte
3586 * and update the residual count accordingly.
3587 */
3588 uint32_t sgptr;
3589
3590 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3591 if ((sgptr & SG_LIST_NULL) != 0
3592 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) {
3593 /*
3594 * If the residual occurred on the last
3595 * transfer and the transfer request was
3596 * expected to end on an odd count, do
3597 * nothing.
3598 */
3599 } else {
3600 struct ahc_dma_seg *sg;
3601 uint32_t data_cnt;
3602 uint32_t data_addr;
3603 uint32_t sglen;
3604
3605 /* Pull in the rest of the sgptr */
3606 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3607 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3608 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8);
3609 sgptr &= SG_PTR_MASK;
3610 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24)
3611 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16)
3612 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8)
3613 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT));
3614
3615 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24)
3616 | (ahc_inb(ahc, SHADDR + 2) << 16)
3617 | (ahc_inb(ahc, SHADDR + 1) << 8)
3618 | (ahc_inb(ahc, SHADDR));
3619
3620 data_cnt += 1;
3621 data_addr -= 1;
3622
3623 sg = ahc_sg_bus_to_virt(scb, sgptr);
3624 /*
3625 * The residual sg ptr points to the next S/G
3626 * to load so we must go back one.
3627 */
3628 sg--;
3629 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3630 if (sg != scb->sg_list
3631 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3632
3633 sg--;
3634 sglen = ahc_le32toh(sg->len);
3635 /*
3636 * Preserve High Address and SG_LIST bits
3637 * while setting the count to 1.
3638 */
3639 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3640 data_addr = ahc_le32toh(sg->addr)
3641 + (sglen & AHC_SG_LEN_MASK) - 1;
3642
3643 /*
3644 * Increment sg so it points to the
3645 * "next" sg.
3646 */
3647 sg++;
3648 sgptr = ahc_sg_virt_to_bus(scb, sg);
3649 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3,
3650 sgptr >> 24);
3651 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2,
3652 sgptr >> 16);
3653 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1,
3654 sgptr >> 8);
3655 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3656 }
3657
3658 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24);
3659 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16);
3660 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8);
3661 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3662 }
3663 }
3664 }
3665
3666
3667 /*
3668 * Reinitialize the data pointers for the active transfer
3669 * based on its current residual.
3670 */
3671 static void
ahc_reinitialize_dataptrs(struct ahc_softc * ahc)3672 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3673 {
3674 struct scb *scb;
3675 struct ahc_dma_seg *sg;
3676 u_int scb_index;
3677 uint32_t sgptr;
3678 uint32_t resid;
3679 uint32_t dataptr;
3680
3681 scb_index = ahc_inb(ahc, SCB_TAG);
3682 scb = ahc_lookup_scb(ahc, scb_index);
3683 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3684 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3685 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3686 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3687
3688 sgptr &= SG_PTR_MASK;
3689 sg = ahc_sg_bus_to_virt(scb, sgptr);
3690
3691 /* The residual sg_ptr always points to the next sg */
3692 sg--;
3693
3694 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3695 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3696 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3697
3698 dataptr = ahc_le32toh(sg->addr)
3699 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3700 - resid;
3701 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3702 u_int dscommand1;
3703
3704 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3705 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3706 ahc_outb(ahc, HADDR,
3707 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3708 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3709 }
3710 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3711 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3712 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3713 ahc_outb(ahc, HADDR, dataptr);
3714 ahc_outb(ahc, HCNT + 2, resid >> 16);
3715 ahc_outb(ahc, HCNT + 1, resid >> 8);
3716 ahc_outb(ahc, HCNT, resid);
3717 if ((ahc->features & AHC_ULTRA2) == 0) {
3718 ahc_outb(ahc, STCNT + 2, resid >> 16);
3719 ahc_outb(ahc, STCNT + 1, resid >> 8);
3720 ahc_outb(ahc, STCNT, resid);
3721 }
3722 }
3723
3724 /*
3725 * Handle the effects of issuing a bus device reset message.
3726 */
3727 static void
ahc_handle_devreset(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,cam_status status,const char * message,int verbose_level)3728 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3729 cam_status status, const char *message, int verbose_level)
3730 {
3731 #ifdef AHC_TARGET_MODE
3732 struct ahc_tmode_tstate* tstate;
3733 u_int lun;
3734 #endif
3735 int found;
3736
3737 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3738 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3739 status);
3740
3741 #ifdef AHC_TARGET_MODE
3742 /*
3743 * Send an immediate notify ccb to all target mord peripheral
3744 * drivers affected by this action.
3745 */
3746 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3747 if (tstate != NULL) {
3748 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3749 struct ahc_tmode_lstate* lstate;
3750
3751 lstate = tstate->enabled_luns[lun];
3752 if (lstate == NULL)
3753 continue;
3754
3755 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3756 MSG_BUS_DEV_RESET, /*arg*/0);
3757 ahc_send_lstate_events(ahc, lstate);
3758 }
3759 }
3760 #endif
3761
3762 /*
3763 * Go back to async/narrow transfers and renegotiate.
3764 */
3765 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3766 AHC_TRANS_CUR, /*paused*/TRUE);
3767 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3768 /*period*/0, /*offset*/0, /*ppr_options*/0,
3769 AHC_TRANS_CUR, /*paused*/TRUE);
3770
3771 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3772 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3773
3774 if (message != NULL
3775 && (verbose_level <= bootverbose))
3776 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3777 message, devinfo->channel, devinfo->target, found);
3778 }
3779
3780 #ifdef AHC_TARGET_MODE
3781 static void
ahc_setup_target_msgin(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct scb * scb)3782 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3783 struct scb *scb)
3784 {
3785
3786 /*
3787 * To facilitate adding multiple messages together,
3788 * each routine should increment the index and len
3789 * variables instead of setting them explicitly.
3790 */
3791 ahc->msgout_index = 0;
3792 ahc->msgout_len = 0;
3793
3794 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3795 ahc_build_transfer_msg(ahc, devinfo);
3796 else
3797 panic("ahc_intr: AWAITING target message with no message");
3798
3799 ahc->msgout_index = 0;
3800 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3801 }
3802 #endif
3803
3804 int
ahc_softc_init(struct ahc_softc * ahc)3805 ahc_softc_init(struct ahc_softc *ahc)
3806 {
3807
3808 /* The IRQMS bit is only valid on VL and EISA chips */
3809 if ((ahc->chip & AHC_PCI) == 0)
3810 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3811 else
3812 ahc->unpause = 0;
3813 ahc->pause = ahc->unpause | PAUSE;
3814 /* XXX The shared scb data stuff should be deprecated */
3815 if (ahc->scb_data == NULL) {
3816 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3817 M_DEVBUF, M_WAITOK | M_ZERO);
3818 }
3819
3820 return (0);
3821 }
3822
3823 void
ahc_softc_insert(struct ahc_softc * ahc)3824 ahc_softc_insert(struct ahc_softc *ahc)
3825 {
3826 struct ahc_softc *list_ahc;
3827
3828 #if AHC_PCI_CONFIG > 0
3829 /*
3830 * Second Function PCI devices need to inherit some
3831 * settings from function 0.
3832 */
3833 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3834 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3835 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3836 ahc_dev_softc_t list_pci;
3837 ahc_dev_softc_t pci;
3838
3839 list_pci = list_ahc->dev_softc;
3840 pci = ahc->dev_softc;
3841 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3842 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
3843 struct ahc_softc *master;
3844 struct ahc_softc *slave;
3845
3846 if (ahc_get_pci_function(list_pci) == 0) {
3847 master = list_ahc;
3848 slave = ahc;
3849 } else {
3850 master = ahc;
3851 slave = list_ahc;
3852 }
3853 slave->flags &= ~AHC_BIOS_ENABLED;
3854 slave->flags |=
3855 master->flags & AHC_BIOS_ENABLED;
3856 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3857 slave->flags |=
3858 master->flags & AHC_PRIMARY_CHANNEL;
3859 break;
3860 }
3861 }
3862 }
3863 #endif
3864
3865 /*
3866 * Insertion sort into our list of softcs.
3867 */
3868 list_ahc = TAILQ_FIRST(&ahc_tailq);
3869 while (list_ahc != NULL
3870 && ahc_softc_comp(list_ahc, ahc) <= 0)
3871 list_ahc = TAILQ_NEXT(list_ahc, links);
3872 if (list_ahc != NULL)
3873 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
3874 else
3875 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
3876 ahc->init_level++;
3877 }
3878
3879 /*
3880 * Verify that the passed in softc pointer is for a
3881 * controller that is still configured.
3882 */
3883 struct ahc_softc *
ahc_find_softc(struct ahc_softc * ahc)3884 ahc_find_softc(struct ahc_softc *ahc)
3885 {
3886 struct ahc_softc *list_ahc;
3887
3888 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3889 if (list_ahc == ahc)
3890 return (ahc);
3891 }
3892 return (NULL);
3893 }
3894
3895 void
ahc_set_unit(struct ahc_softc * ahc,int unit)3896 ahc_set_unit(struct ahc_softc *ahc, int unit)
3897 {
3898 ahc->unit = unit;
3899 }
3900
3901 void
ahc_set_name(struct ahc_softc * ahc,const char * name)3902 ahc_set_name(struct ahc_softc *ahc, const char *name)
3903 {
3904 ahc->name = name;
3905 }
3906
3907 void
ahc_free(struct ahc_softc * ahc)3908 ahc_free(struct ahc_softc *ahc)
3909 {
3910 int i;
3911
3912 ahc_fini_scbdata(ahc);
3913 switch (ahc->init_level) {
3914 default:
3915 case 2:
3916 ahc_shutdown(ahc);
3917 /* TAILQ_REMOVE(&ahc_tailq, ahc, links); XXX */
3918 /* FALLTHROUGH */
3919 case 1:
3920 ahc_freedmamem(ahc->parent_dmat, ahc->shared_data_size,
3921 ahc->shared_data_dmamap, (void *)ahc->qoutfifo,
3922 &ahc->shared_data_seg, ahc->shared_data_nseg);
3923 break;
3924 case 0:
3925 break;
3926 }
3927
3928 ahc_platform_free(ahc);
3929 for (i = 0; i < AHC_NUM_TARGETS; i++) {
3930 struct ahc_tmode_tstate *tstate;
3931
3932 tstate = ahc->enabled_targets[i];
3933 if (tstate != NULL) {
3934 #if AHC_TARGET_MODE
3935 int j;
3936
3937 for (j = 0; j < AHC_NUM_LUNS; j++) {
3938 struct ahc_tmode_lstate *lstate;
3939
3940 lstate = tstate->enabled_luns[j];
3941 if (lstate != NULL) {
3942 /*xpt_free_path(lstate->path);*/
3943 free(lstate, M_DEVBUF);
3944 }
3945 }
3946 #endif
3947 free(tstate, M_DEVBUF);
3948 }
3949 }
3950 #if AHC_TARGET_MODE
3951 if (ahc->black_hole != NULL) {
3952 /*xpt_free_path(ahc->black_hole->path);*/
3953 free(ahc->black_hole, M_DEVBUF);
3954 }
3955 #endif
3956 #ifndef __NetBSD__
3957 if (ahc->name != NULL)
3958 free(ahc->name, M_DEVBUF);
3959 #endif
3960 if (ahc->seep_config != NULL)
3961 free(ahc->seep_config, M_DEVBUF);
3962 #if !defined(__FreeBSD__) && !defined(__NetBSD__)
3963 free(ahc, M_DEVBUF);
3964 #endif
3965 return;
3966 }
3967
3968 void
ahc_shutdown(void * arg)3969 ahc_shutdown(void *arg)
3970 {
3971 struct ahc_softc *ahc;
3972 int i;
3973
3974 ahc = arg;
3975
3976 /* This will reset most registers to 0, but not all */
3977 ahc_reset(ahc);
3978 ahc_outb(ahc, SCSISEQ, 0);
3979 ahc_outb(ahc, SXFRCTL0, 0);
3980 ahc_outb(ahc, DSPCISTATUS, 0);
3981
3982 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
3983 ahc_outb(ahc, i, 0);
3984 }
3985
3986 /*
3987 * Reset the controller and record some information about it
3988 * that is only available just after a reset.
3989 */
3990 int
ahc_reset(struct ahc_softc * ahc)3991 ahc_reset(struct ahc_softc *ahc)
3992 {
3993 u_int sblkctl;
3994 u_int sxfrctl1_a, sxfrctl1_b;
3995 int wait;
3996
3997 /*
3998 * Preserve the value of the SXFRCTL1 register for all channels.
3999 * It contains settings that affect termination and we don't want
4000 * to disturb the integrity of the bus.
4001 */
4002 ahc_pause(ahc);
4003 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) {
4004 /*
4005 * The chip has not been initialized since
4006 * PCI/EISA/VLB bus reset. Don't trust
4007 * "left over BIOS data".
4008 */
4009 ahc->flags |= AHC_NO_BIOS_INIT;
4010 }
4011 sxfrctl1_b = 0;
4012 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4013 u_int sblkctl1;
4014
4015 /*
4016 * Save channel B's settings in case this chip
4017 * is setup for TWIN channel operation.
4018 */
4019 sblkctl1 = ahc_inb(ahc, SBLKCTL);
4020 ahc_outb(ahc, SBLKCTL, sblkctl1 | SELBUSB);
4021 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4022 ahc_outb(ahc, SBLKCTL, sblkctl1 & ~SELBUSB);
4023 }
4024 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4025
4026 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4027
4028 /*
4029 * Ensure that the reset has finished. We delay 1000us
4030 * prior to reading the register to make sure the chip
4031 * has sufficiently completed its reset to handle register
4032 * accesses.
4033 */
4034 wait = 1000;
4035 do {
4036 ahc_delay(1000);
4037 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4038
4039 if (wait == 0) {
4040 printf("%s: WARNING - Failed chip reset! "
4041 "Trying to initialize anyway.\n", ahc_name(ahc));
4042 }
4043 ahc_outb(ahc, HCNTRL, ahc->pause);
4044
4045 /* Determine channel configuration */
4046 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4047 /* No Twin Channel PCI cards */
4048 if ((ahc->chip & AHC_PCI) != 0)
4049 sblkctl &= ~SELBUSB;
4050 switch (sblkctl) {
4051 case 0:
4052 /* Single Narrow Channel */
4053 break;
4054 case 2:
4055 /* Wide Channel */
4056 ahc->features |= AHC_WIDE;
4057 break;
4058 case 8:
4059 /* Twin Channel */
4060 ahc->features |= AHC_TWIN;
4061 break;
4062 default:
4063 printf(" Unsupported adapter type (0x%x). Ignoring\n",
4064 sblkctl);
4065 return(-1);
4066 }
4067
4068 /*
4069 * Reload sxfrctl1.
4070 *
4071 * We must always initialize STPWEN to 1 before we
4072 * restore the saved values. STPWEN is initialized
4073 * to a tri-state condition which can only be cleared
4074 * by turning it on.
4075 */
4076 if ((ahc->features & AHC_TWIN) != 0) {
4077 u_int sblkctl1;
4078
4079 sblkctl1 = ahc_inb(ahc, SBLKCTL);
4080 ahc_outb(ahc, SBLKCTL, sblkctl1 | SELBUSB);
4081 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4082 ahc_outb(ahc, SBLKCTL, sblkctl1 & ~SELBUSB);
4083 }
4084 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4085
4086 #ifdef AHC_DUMP_SEQ
4087 if (ahc->init_level == 0)
4088 ahc_dumpseq(ahc);
4089 #endif
4090
4091 return (0);
4092 }
4093
4094 /*
4095 * Determine the number of SCBs available on the controller
4096 */
4097 int
ahc_probe_scbs(struct ahc_softc * ahc)4098 ahc_probe_scbs(struct ahc_softc *ahc) {
4099 int i;
4100
4101 for (i = 0; i < AHC_SCB_MAX; i++) {
4102
4103 ahc_outb(ahc, SCBPTR, i);
4104 ahc_outb(ahc, SCB_BASE, i);
4105 if (ahc_inb(ahc, SCB_BASE) != i)
4106 break;
4107 ahc_outb(ahc, SCBPTR, 0);
4108 if (ahc_inb(ahc, SCB_BASE) != 0)
4109 break;
4110 }
4111 return (i);
4112 }
4113
4114 #if 0
4115 static void
4116 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4117 {
4118 bus_addr_t *baddr;
4119
4120 baddr = (bus_addr_t *)arg;
4121 *baddr = segs->ds_addr;
4122 }
4123 #endif
4124
4125 static void
ahc_build_free_scb_list(struct ahc_softc * ahc)4126 ahc_build_free_scb_list(struct ahc_softc *ahc)
4127 {
4128 int scbsize;
4129 int i;
4130
4131 scbsize = 32;
4132 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4133 scbsize = 64;
4134
4135 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4136 int j;
4137
4138 ahc_outb(ahc, SCBPTR, i);
4139
4140 /*
4141 * Touch all SCB bytes to avoid parity errors
4142 * should one of our debugging routines read
4143 * an otherwise uninitialized byte.
4144 */
4145 for (j = 0; j < scbsize; j++)
4146 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4147
4148 /* Clear the control byte. */
4149 ahc_outb(ahc, SCB_CONTROL, 0);
4150
4151 /* Set the next pointer */
4152 if ((ahc->flags & AHC_PAGESCBS) != 0)
4153 ahc_outb(ahc, SCB_NEXT, i+1);
4154 else
4155 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4156
4157 /* Make the tag number, SCSIID, and lun invalid */
4158 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4159 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4160 ahc_outb(ahc, SCB_LUN, 0xFF);
4161 }
4162
4163 /* Make sure that the last SCB terminates the free list */
4164 ahc_outb(ahc, SCBPTR, i-1);
4165 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4166 }
4167
4168 static int
ahc_init_scbdata(struct ahc_softc * ahc)4169 ahc_init_scbdata(struct ahc_softc *ahc)
4170 {
4171 struct scb_data *scb_data;
4172
4173 scb_data = ahc->scb_data;
4174 SLIST_INIT(&scb_data->free_scbs);
4175 SLIST_INIT(&scb_data->sg_maps);
4176
4177 /* Allocate SCB resources */
4178 scb_data->scbarray = malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4179 M_DEVBUF, M_WAITOK | M_ZERO);
4180
4181 /* Determine the number of hardware SCBs and initialize them */
4182
4183 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4184 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4185 /* SCB 0 heads the free list */
4186 ahc_outb(ahc, FREE_SCBH, 0);
4187 } else {
4188 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4189 }
4190
4191 if (ahc->scb_data->maxhscbs == 0) {
4192 printf("%s: No SCB space found\n", ahc_name(ahc));
4193 return (ENXIO);
4194 }
4195
4196 ahc_build_free_scb_list(ahc);
4197
4198 /*
4199 * Create our DMA tags. These tags define the kinds of device
4200 * accessible memory allocations and memory mappings we will
4201 * need to perform during normal operation.
4202 *
4203 * Unless we need to further restrict the allocation, we rely
4204 * on the restrictions of the parent dmat, hence the common
4205 * use of MAXADDR and MAXSIZE.
4206 */
4207
4208 if (ahc_createdmamem(ahc->parent_dmat,
4209 AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags,
4210 &scb_data->hscb_dmamap,
4211 (void **)&scb_data->hscbs, &scb_data->hscb_busaddr,
4212 &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc),
4213 "hardware SCB structures") < 0)
4214 goto error_exit;
4215
4216 scb_data->init_level++;
4217
4218 if (ahc_createdmamem(ahc->parent_dmat,
4219 AHC_SCB_MAX * sizeof(struct scsi_sense_data), ahc->sc_dmaflags,
4220 &scb_data->sense_dmamap, (void **)&scb_data->sense,
4221 &scb_data->sense_busaddr, &scb_data->sense_seg,
4222 &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0)
4223 goto error_exit;
4224
4225 scb_data->init_level++;
4226
4227 /* Perform initial CCB allocation */
4228 memset(scb_data->hscbs, 0,
4229 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4230 ahc_alloc_scbs(ahc);
4231 scb_data->init_level++;
4232
4233 if (scb_data->numscbs == 0) {
4234 printf("%s: ahc_init_scbdata - "
4235 "Unable to allocate initial scbs\n",
4236 ahc_name(ahc));
4237 goto error_exit;
4238 }
4239
4240 /*
4241 * Tell the sequencer which SCB will be the next one it receives.
4242 */
4243 ahc->next_queued_scb = ahc_get_scb(ahc);
4244 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4245
4246 /*
4247 * Note that we were successful
4248 */
4249 return (0);
4250
4251 error_exit:
4252
4253 return (ENOMEM);
4254 }
4255
4256 static void
ahc_fini_scbdata(struct ahc_softc * ahc)4257 ahc_fini_scbdata(struct ahc_softc *ahc)
4258 {
4259 struct scb_data *scb_data;
4260
4261 scb_data = ahc->scb_data;
4262 if (scb_data == NULL)
4263 return;
4264
4265 switch (scb_data->init_level) {
4266 default:
4267 case 5:
4268 {
4269 struct sg_map_node *sg_map;
4270
4271 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4272 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4273 ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE,
4274 sg_map->sg_dmamap, (void *)sg_map->sg_vaddr,
4275 &sg_map->sg_dmasegs, sg_map->sg_nseg);
4276 free(sg_map, M_DEVBUF);
4277 }
4278 }
4279 /*FALLTHROUGH*/
4280 case 4:
4281 ahc_freedmamem(ahc->parent_dmat,
4282 AHC_SCB_MAX * sizeof(struct scsi_sense_data),
4283 scb_data->sense_dmamap, (void *)scb_data->sense,
4284 &scb_data->sense_seg, scb_data->sense_nseg);
4285 /*FALLTHROUGH*/
4286 case 3:
4287 ahc_freedmamem(ahc->parent_dmat,
4288 AHC_SCB_MAX * sizeof(struct hardware_scb),
4289 scb_data->hscb_dmamap, (void *)scb_data->hscbs,
4290 &scb_data->hscb_seg, scb_data->hscb_nseg);
4291 /*FALLTHROUGH*/
4292 case 2:
4293 case 1:
4294 case 0:
4295 break;
4296 }
4297 if (scb_data->scbarray != NULL)
4298 free(scb_data->scbarray, M_DEVBUF);
4299 }
4300
4301 int
ahc_alloc_scbs(struct ahc_softc * ahc)4302 ahc_alloc_scbs(struct ahc_softc *ahc)
4303 {
4304 struct scb_data *scb_data;
4305 struct scb *next_scb;
4306 struct sg_map_node *sg_map;
4307 bus_addr_t physaddr;
4308 struct ahc_dma_seg *segs;
4309 int newcount;
4310 int i;
4311
4312 scb_data = ahc->scb_data;
4313 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4314 /* Can't allocate any more */
4315 return (0);
4316
4317 next_scb = &scb_data->scbarray[scb_data->numscbs];
4318
4319 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_WAITOK);
4320
4321 if (sg_map == NULL)
4322 return (0);
4323
4324 /* Allocate S/G space for the next batch of SCBS */
4325 if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags,
4326 &sg_map->sg_dmamap,
4327 (void **)&sg_map->sg_vaddr, &sg_map->sg_physaddr,
4328 &sg_map->sg_dmasegs, &sg_map->sg_nseg,
4329 ahc_name(ahc),
4330 "SG space") < 0) {
4331 free(sg_map, M_DEVBUF);
4332 return (0);
4333 }
4334
4335 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4336
4337 segs = sg_map->sg_vaddr;
4338 physaddr = sg_map->sg_physaddr;
4339
4340 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4341 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4342 for (i = 0; i < newcount; i++) {
4343 struct scb_platform_data *pdata;
4344 int error;
4345
4346 pdata = malloc(sizeof(*pdata), M_DEVBUF, M_WAITOK);
4347 if (pdata == NULL)
4348 break;
4349 next_scb->platform_data = pdata;
4350 next_scb->sg_map = sg_map;
4351 next_scb->sg_list = segs;
4352 /*
4353 * The sequencer always starts with the second entry.
4354 * The first entry is embedded in the scb.
4355 */
4356 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4357 next_scb->ahc_softc = ahc;
4358 next_scb->flags = SCB_FREE;
4359
4360 error = bus_dmamap_create(ahc->parent_dmat,
4361 AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0,
4362 BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags,
4363 &next_scb->dmamap);
4364 if (error != 0) {
4365 free(pdata, M_DEVBUF);
4366 break;
4367 }
4368
4369 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4370 next_scb->hscb->tag = ahc->scb_data->numscbs;
4371 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4372 next_scb, links.sle);
4373 segs += AHC_NSEG;
4374 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4375 next_scb++;
4376 ahc->scb_data->numscbs++;
4377 }
4378 return (newcount);
4379 }
4380
4381 void
ahc_controller_info(struct ahc_softc * ahc,char * tbuf,size_t l)4382 ahc_controller_info(struct ahc_softc *ahc, char *tbuf, size_t l)
4383 {
4384 size_t len;
4385
4386 len = snprintf(tbuf, l, "%s: ",
4387 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4388 if (len > l)
4389 return;
4390 if ((ahc->features & AHC_TWIN) != 0)
4391 len += snprintf(tbuf + len, l - len,
4392 "Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ",
4393 ahc->our_id, ahc->our_id_b,
4394 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4395 else {
4396 const char *speed;
4397 const char *type;
4398
4399 speed = "";
4400 if ((ahc->features & AHC_ULTRA) != 0) {
4401 speed = "Ultra ";
4402 } else if ((ahc->features & AHC_DT) != 0) {
4403 speed = "Ultra160 ";
4404 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4405 speed = "Ultra2 ";
4406 }
4407 if ((ahc->features & AHC_WIDE) != 0) {
4408 type = "Wide";
4409 } else {
4410 type = "Single";
4411 }
4412 len += snprintf(tbuf + len, l - len, "%s%s Channel %c, SCSI Id=%d, ",
4413 speed, type, ahc->channel, ahc->our_id);
4414 }
4415 if (len > l)
4416 return;
4417
4418 if ((ahc->flags & AHC_PAGESCBS) != 0)
4419 snprintf(tbuf + len, l - len, "%d/%d SCBs",
4420 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4421 else
4422 snprintf(tbuf + len, l - len, "%d SCBs", ahc->scb_data->maxhscbs);
4423 }
4424
4425 /*
4426 * Start the board, ready for normal operation
4427 */
4428 int
ahc_init(struct ahc_softc * ahc)4429 ahc_init(struct ahc_softc *ahc)
4430 {
4431 int max_targ;
4432 int i;
4433 int term;
4434 u_int scsi_conf;
4435 u_int scsiseq_template;
4436 u_int ultraenb;
4437 u_int discenable;
4438 u_int tagenable;
4439 size_t driver_data_size;
4440 uint32_t physaddr;
4441
4442 #ifdef AHC_DEBUG
4443 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4444 ahc->flags |= AHC_SEQUENCER_DEBUG;
4445 #endif
4446
4447 #ifdef AHC_PRINT_SRAM
4448 printf("Scratch Ram:");
4449 for (i = 0x20; i < 0x5f; i++) {
4450 if (((i % 8) == 0) && (i != 0)) {
4451 printf ("\n ");
4452 }
4453 printf (" 0x%x", ahc_inb(ahc, i));
4454 }
4455 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4456 for (i = 0x70; i < 0x7f; i++) {
4457 if (((i % 8) == 0) && (i != 0)) {
4458 printf ("\n ");
4459 }
4460 printf (" 0x%x", ahc_inb(ahc, i));
4461 }
4462 }
4463 printf ("\n");
4464 /*
4465 * Reading uninitialized scratch ram may
4466 * generate parity errors.
4467 */
4468 ahc_outb(ahc, CLRINT, CLRPARERR);
4469 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4470 #endif
4471 max_targ = 15;
4472
4473 /*
4474 * Assume we have a board at this stage and it has been reset.
4475 */
4476 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4477 ahc->our_id = ahc->our_id_b = 7;
4478
4479 /*
4480 * Default to allowing initiator operations.
4481 */
4482 ahc->flags |= AHC_INITIATORROLE;
4483
4484 /*
4485 * Only allow target mode features if this unit has them enabled.
4486 */
4487 //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4488 ahc->features &= ~AHC_TARGETMODE;
4489
4490 /*
4491 * DMA tag for our command fifos and other data in system memory
4492 * the card's sequencer must be able to access. For initiator
4493 * roles, we need to allocate space for the qinfifo and qoutfifo.
4494 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4495 * When providing for the target mode role, we must additionally
4496 * provide space for the incoming target command fifo and an extra
4497 * byte to deal with a DMA bug in some chip versions.
4498 */
4499 driver_data_size = 2 * 256 * sizeof(uint8_t);
4500 if ((ahc->features & AHC_TARGETMODE) != 0)
4501 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4502 + /*DMA WideOdd Bug Buffer*/1;
4503 ahc->shared_data_size = driver_data_size;
4504
4505 if (ahc_createdmamem(ahc->parent_dmat, ahc->shared_data_size,
4506 ahc->sc_dmaflags,
4507 &ahc->shared_data_dmamap, (void **)&ahc->qoutfifo,
4508 &ahc->shared_data_busaddr, &ahc->shared_data_seg,
4509 &ahc->shared_data_nseg, ahc_name(ahc),
4510 "shared data") < 0)
4511 return (ENOMEM);
4512
4513 ahc->init_level++;
4514
4515 if ((ahc->features & AHC_TARGETMODE) != 0) {
4516 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4517 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4518 ahc->dma_bug_buf = ahc->shared_data_busaddr
4519 + ahc->shared_data_size - 1;
4520 /* All target command blocks start out invalid. */
4521 for (i = 0; i < AHC_TMODE_CMDS; i++)
4522 ahc->targetcmds[i].cmd_valid = 0;
4523 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4524 ahc->tqinfifonext = 1;
4525 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4526 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4527 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4528 }
4529 ahc->qinfifo = &ahc->qoutfifo[256];
4530
4531 ahc->init_level++;
4532
4533 /* Allocate SCB data now that buffer_dmat is initialized */
4534 if (ahc->scb_data->maxhscbs == 0)
4535 if (ahc_init_scbdata(ahc) != 0)
4536 return (ENOMEM);
4537
4538 if (bootverbose)
4539 printf("%s: found %d SCBs\n", ahc_name(ahc),
4540 ahc->scb_data->maxhscbs);
4541
4542 /*
4543 * Allocate a tstate to house information for our
4544 * initiator presence on the bus as well as the user
4545 * data for any target mode initiator.
4546 */
4547 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4548 printf("%s: unable to allocate ahc_tmode_tstate. "
4549 "Failing attach\n", ahc_name(ahc));
4550 return (ENOMEM);
4551 }
4552
4553 if ((ahc->features & AHC_TWIN) != 0) {
4554 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4555 printf("%s: unable to allocate ahc_tmode_tstate. "
4556 "Failing attach\n", ahc_name(ahc));
4557 return (ENOMEM);
4558 }
4559 }
4560
4561 ahc_outb(ahc, SEQ_FLAGS, 0);
4562 ahc_outb(ahc, SEQ_FLAGS2, 0);
4563
4564 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4565 ahc->flags |= AHC_PAGESCBS;
4566 } else {
4567 ahc->flags &= ~AHC_PAGESCBS;
4568 }
4569
4570 #ifdef AHC_DEBUG
4571 if (ahc_debug & AHC_SHOW_MISC) {
4572 printf("%s: hardware scb %lu bytes; kernel scb %lu bytes; "
4573 "ahc_dma %lu bytes\n",
4574 ahc_name(ahc),
4575 (u_long)sizeof(struct hardware_scb),
4576 (u_long)sizeof(struct scb),
4577 (u_long)sizeof(struct ahc_dma_seg));
4578 }
4579 #endif /* AHC_DEBUG */
4580
4581 /*
4582 * Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels
4583 */
4584 if (ahc->features & AHC_TWIN) {
4585
4586 /*
4587 * The device is gated to channel B after a chip reset,
4588 * so set those values first
4589 */
4590 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4591 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4592 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4593 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4594 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4595 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4596 if ((ahc->features & AHC_ULTRA2) != 0)
4597 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4598 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4599 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4600
4601 if ((scsi_conf & RESET_SCSI) != 0
4602 && (ahc->flags & AHC_INITIATORROLE) != 0)
4603 ahc->flags |= AHC_RESET_BUS_B;
4604
4605 /* Select Channel A */
4606 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4607 }
4608
4609 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4610 if ((ahc->features & AHC_ULTRA2) != 0)
4611 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4612 else
4613 ahc_outb(ahc, SCSIID, ahc->our_id);
4614 scsi_conf = ahc_inb(ahc, SCSICONF);
4615 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4616 |term|ahc->seltime
4617 |ENSTIMER|ACTNEGEN);
4618 if ((ahc->features & AHC_ULTRA2) != 0)
4619 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4620 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4621 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4622
4623 if ((scsi_conf & RESET_SCSI) != 0
4624 && (ahc->flags & AHC_INITIATORROLE) != 0)
4625 ahc->flags |= AHC_RESET_BUS_A;
4626
4627 /*
4628 * Look at the information that board initialization or
4629 * the board bios has left us.
4630 */
4631 ultraenb = 0;
4632 tagenable = ALL_TARGETS_MASK;
4633
4634 /* Grab the disconnection disable table and invert it for our needs */
4635 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4636 printf("%s: Host Adapter BIOS disabled. Using default SCSI "
4637 "host and target device parameters\n", ahc_name(ahc));
4638 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4639 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4640 discenable = ALL_TARGETS_MASK;
4641 if ((ahc->features & AHC_ULTRA) != 0)
4642 ultraenb = ALL_TARGETS_MASK;
4643 } else if ((ahc->flags & AHC_USETARGETDEFAULTS) != 0) {
4644 printf("%s: Host Adapter has no SEEPROM. Using default SCSI"
4645 " target parameters\n", ahc_name(ahc));
4646 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B;
4647 discenable = ALL_TARGETS_MASK;
4648 if ((ahc->features & AHC_ULTRA) != 0)
4649 ultraenb = ALL_TARGETS_MASK;
4650 } else {
4651 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4652 | ahc_inb(ahc, DISC_DSB));
4653 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4654 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4655 | ahc_inb(ahc, ULTRA_ENB);
4656 }
4657
4658 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4659 max_targ = 7;
4660
4661 for (i = 0; i <= max_targ; i++) {
4662 struct ahc_initiator_tinfo *tinfo;
4663 struct ahc_tmode_tstate *tstate;
4664 u_int our_id;
4665 u_int target_id;
4666 char channel;
4667
4668 channel = 'A';
4669 our_id = ahc->our_id;
4670 target_id = i;
4671 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4672 channel = 'B';
4673 our_id = ahc->our_id_b;
4674 target_id = i % 8;
4675 }
4676 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4677 target_id, &tstate);
4678 /* Default to async narrow across the board */
4679 memset(tinfo, 0, sizeof(*tinfo));
4680 if (ahc->flags & (AHC_USEDEFAULTS | AHC_USETARGETDEFAULTS)) {
4681 if ((ahc->features & AHC_WIDE) != 0)
4682 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4683
4684 /*
4685 * These will be truncated when we determine the
4686 * connection type we have with the target.
4687 */
4688 tinfo->user.period = ahc_syncrates->period;
4689 tinfo->user.offset = ~0;
4690 } else {
4691 u_int scsirate;
4692 uint16_t mask;
4693
4694 /* Take the settings leftover in scratch RAM. */
4695 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4696 mask = (0x01 << i);
4697 if ((ahc->features & AHC_ULTRA2) != 0) {
4698 u_int offset;
4699 u_int maxsync;
4700
4701 if ((scsirate & SOFS) == 0x0F) {
4702 /*
4703 * Haven't negotiated yet,
4704 * so the format is different.
4705 */
4706 scsirate = (scsirate & SXFR) >> 4
4707 | (ultraenb & mask)
4708 ? 0x08 : 0x0
4709 | (scsirate & WIDEXFER);
4710 offset = MAX_OFFSET_ULTRA2;
4711 } else
4712 offset = ahc_inb(ahc, TARG_OFFSET + i);
4713 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4714 /* Set to the lowest sync rate, 5MHz */
4715 scsirate |= 0x1c;
4716 maxsync = AHC_SYNCRATE_ULTRA2;
4717 if ((ahc->features & AHC_DT) != 0)
4718 maxsync = AHC_SYNCRATE_DT;
4719 tinfo->user.period =
4720 ahc_find_period(ahc, scsirate, maxsync);
4721 if (offset == 0)
4722 tinfo->user.period = 0;
4723 else
4724 tinfo->user.offset = ~0;
4725 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4726 && (ahc->features & AHC_DT) != 0)
4727 tinfo->user.ppr_options =
4728 MSG_EXT_PPR_DT_REQ;
4729 } else if ((scsirate & SOFS) != 0) {
4730 if ((scsirate & SXFR) == 0x40
4731 && (ultraenb & mask) != 0) {
4732 /* Treat 10MHz as a non-ultra speed */
4733 scsirate &= ~SXFR;
4734 ultraenb &= ~mask;
4735 }
4736 tinfo->user.period =
4737 ahc_find_period(ahc, scsirate,
4738 (ultraenb & mask)
4739 ? AHC_SYNCRATE_ULTRA
4740 : AHC_SYNCRATE_FAST);
4741 if (tinfo->user.period != 0)
4742 tinfo->user.offset = ~0;
4743 }
4744 if (tinfo->user.period == 0)
4745 tinfo->user.offset = 0;
4746 if ((scsirate & WIDEXFER) != 0
4747 && (ahc->features & AHC_WIDE) != 0)
4748 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4749 tinfo->user.protocol_version = 4;
4750 if ((ahc->features & AHC_DT) != 0)
4751 tinfo->user.transport_version = 3;
4752 else
4753 tinfo->user.transport_version = 2;
4754 tinfo->goal.protocol_version = 2;
4755 tinfo->goal.transport_version = 2;
4756 tinfo->curr.protocol_version = 2;
4757 tinfo->curr.transport_version = 2;
4758 }
4759 tstate->ultraenb = 0;
4760 tstate->discenable = discenable;
4761 }
4762 ahc->user_discenable = discenable;
4763 ahc->user_tagenable = tagenable;
4764
4765 /* There are no untagged SCBs active yet. */
4766 for (i = 0; i < 16; i++) {
4767 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4768 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4769 int lun;
4770
4771 /*
4772 * The SCB based BTT allows an entry per
4773 * target and lun pair.
4774 */
4775 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4776 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4777 }
4778 }
4779
4780 /* All of our queues are empty */
4781 for (i = 0; i < 256; i++)
4782 ahc->qoutfifo[i] = SCB_LIST_NULL;
4783
4784 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4785
4786 for (i = 0; i < 256; i++)
4787 ahc->qinfifo[i] = SCB_LIST_NULL;
4788
4789 if ((ahc->features & AHC_MULTI_TID) != 0) {
4790 ahc_outb(ahc, TARGID, 0);
4791 ahc_outb(ahc, TARGID + 1, 0);
4792 }
4793
4794 /*
4795 * Tell the sequencer where it can find our arrays in memory.
4796 */
4797 physaddr = ahc->scb_data->hscb_busaddr;
4798 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4799 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4800 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4801 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4802
4803 physaddr = ahc->shared_data_busaddr;
4804 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4805 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4806 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4807 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4808
4809 /*
4810 * Initialize the group code to command length table.
4811 * This overrides the values in TARG_SCSIRATE, so only
4812 * setup the table after we have processed that information.
4813 */
4814 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4815 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4816 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4817 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4818 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4819 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4820 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4821 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4822
4823 /* Tell the sequencer of our initial queue positions */
4824 ahc_outb(ahc, KERNEL_QINPOS, 0);
4825 ahc_outb(ahc, QINPOS, 0);
4826 ahc_outb(ahc, QOUTPOS, 0);
4827
4828 /*
4829 * Use the built in queue management registers
4830 * if they are available.
4831 */
4832 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4833 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4834 ahc_outb(ahc, SDSCB_QOFF, 0);
4835 ahc_outb(ahc, SNSCB_QOFF, 0);
4836 ahc_outb(ahc, HNSCB_QOFF, 0);
4837 }
4838
4839
4840 /* We don't have any waiting selections */
4841 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4842
4843 /* Our disconnection list is empty too */
4844 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4845
4846 /* Message out buffer starts empty */
4847 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4848
4849 /*
4850 * Setup the allowed SCSI Sequences based on operational mode.
4851 * If we are a target, we'll enable select in operations once
4852 * we've had a lun enabled.
4853 */
4854 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4855 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4856 scsiseq_template |= ENRSELI;
4857 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4858
4859 /*
4860 * Load the Sequencer program and Enable the adapter
4861 * in "fast" mode.
4862 */
4863 if (bootverbose)
4864 printf("%s: Downloading Sequencer Program...",
4865 ahc_name(ahc));
4866
4867 ahc_loadseq(ahc);
4868
4869 if ((ahc->features & AHC_ULTRA2) != 0) {
4870 int wait;
4871
4872 /*
4873 * Wait for up to 500ms for our transceivers
4874 * to settle. If the adapter does not have
4875 * a cable attached, the transceivers may
4876 * never settle, so don't complain if we
4877 * fail here.
4878 */
4879 ahc_pause(ahc);
4880 for (wait = 5000;
4881 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4882 wait--)
4883 ahc_delay(100);
4884 ahc_unpause(ahc);
4885 }
4886
4887 return (0);
4888 }
4889
4890 void
ahc_intr_enable(struct ahc_softc * ahc,int enable)4891 ahc_intr_enable(struct ahc_softc *ahc, int enable)
4892 {
4893 u_int hcntrl;
4894
4895 hcntrl = ahc_inb(ahc, HCNTRL);
4896 hcntrl &= ~INTEN;
4897 ahc->pause &= ~INTEN;
4898 ahc->unpause &= ~INTEN;
4899 if (enable) {
4900 hcntrl |= INTEN;
4901 ahc->pause |= INTEN;
4902 ahc->unpause |= INTEN;
4903 }
4904 ahc_outb(ahc, HCNTRL, hcntrl);
4905 }
4906
4907 /*
4908 * Ensure that the card is paused in a location
4909 * outside of all critical sections and that all
4910 * pending work is completed prior to returning.
4911 * This routine should only be called from outside
4912 * an interrupt context.
4913 */
4914 void
ahc_pause_and_flushwork(struct ahc_softc * ahc)4915 ahc_pause_and_flushwork(struct ahc_softc *ahc)
4916 {
4917 int intstat;
4918 int maxloops;
4919 int paused;
4920
4921 maxloops = 1000;
4922 ahc->flags |= AHC_ALL_INTERRUPTS;
4923 intstat = 0;
4924 paused = FALSE;
4925 do {
4926 if (paused)
4927 ahc_unpause(ahc);
4928 ahc_intr(ahc);
4929 ahc_pause(ahc);
4930 paused = TRUE;
4931 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
4932 ahc_clear_critical_section(ahc);
4933 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
4934 break;
4935 } while (--maxloops
4936 && (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) != 0
4937 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO))));
4938 if (maxloops == 0) {
4939 printf("Infinite interrupt loop, INTSTAT = %x",
4940 ahc_inb(ahc, INTSTAT));
4941 }
4942 ahc_platform_flushwork(ahc);
4943 ahc->flags &= ~AHC_ALL_INTERRUPTS;
4944 }
4945
4946 int
ahc_suspend(struct ahc_softc * ahc)4947 ahc_suspend(struct ahc_softc *ahc)
4948 {
4949 uint8_t *ptr;
4950 int i;
4951
4952 ahc_pause_and_flushwork(ahc);
4953
4954 if (LIST_FIRST(&ahc->pending_scbs) != NULL)
4955 return (EBUSY);
4956
4957 #if AHC_TARGET_MODE
4958 /*
4959 * XXX What about ATIOs that have not yet been serviced?
4960 * Perhaps we should just refuse to be suspended if we
4961 * are acting in a target role.
4962 */
4963 if (ahc->pending_device != NULL)
4964 return (EBUSY);
4965 #endif
4966
4967 /* Save volatile registers */
4968 if ((ahc->features & AHC_TWIN) != 0) {
4969 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4970 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ);
4971 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
4972 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1);
4973 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0);
4974 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1);
4975 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER);
4976 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL);
4977 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4978 }
4979 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ);
4980 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
4981 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1);
4982 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0);
4983 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1);
4984 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER);
4985 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL);
4986
4987 if ((ahc->chip & AHC_PCI) != 0) {
4988 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
4989 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
4990 }
4991
4992 if ((ahc->features & AHC_DT) != 0) {
4993 u_int sfunct;
4994
4995 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
4996 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
4997 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE);
4998 ahc_outb(ahc, SFUNCT, sfunct);
4999 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1);
5000 }
5001
5002 if ((ahc->features & AHC_MULTI_FUNC) != 0)
5003 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR);
5004
5005 if ((ahc->features & AHC_ULTRA2) != 0)
5006 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
5007
5008 ptr = ahc->suspend_state.scratch_ram;
5009 for (i = 0; i < 64; i++)
5010 *ptr++ = ahc_inb(ahc, SRAM_BASE + i);
5011
5012 if ((ahc->features & AHC_MORE_SRAM) != 0) {
5013 for (i = 0; i < 16; i++)
5014 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i);
5015 }
5016
5017 ptr = ahc->suspend_state.btt;
5018 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5019 for (i = 0;i < AHC_NUM_TARGETS; i++) {
5020 int j;
5021
5022 for (j = 0;j < AHC_NUM_LUNS; j++) {
5023 u_int tcl;
5024
5025 tcl = BUILD_TCL(i << 4, j);
5026 *ptr = ahc_index_busy_tcl(ahc, tcl);
5027 }
5028 }
5029 }
5030 ahc_shutdown(ahc);
5031 return (0);
5032 }
5033
5034 int
ahc_resume(struct ahc_softc * ahc)5035 ahc_resume(struct ahc_softc *ahc)
5036 {
5037 uint8_t *ptr;
5038 int i;
5039
5040 ahc_reset(ahc);
5041
5042 ahc_build_free_scb_list(ahc);
5043
5044 /* Restore volatile registers */
5045 if ((ahc->features & AHC_TWIN) != 0) {
5046 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
5047 ahc_outb(ahc, SCSIID, ahc->our_id);
5048 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq);
5049 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0);
5050 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1);
5051 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0);
5052 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1);
5053 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer);
5054 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl);
5055 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
5056 }
5057 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq);
5058 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0);
5059 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1);
5060 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0);
5061 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1);
5062 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer);
5063 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl);
5064 if ((ahc->features & AHC_ULTRA2) != 0)
5065 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
5066 else
5067 ahc_outb(ahc, SCSIID, ahc->our_id);
5068
5069 if ((ahc->chip & AHC_PCI) != 0) {
5070 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0);
5071 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus);
5072 }
5073
5074 if ((ahc->features & AHC_DT) != 0) {
5075 u_int sfunct;
5076
5077 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
5078 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
5079 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode);
5080 ahc_outb(ahc, SFUNCT, sfunct);
5081 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1);
5082 }
5083
5084 if ((ahc->features & AHC_MULTI_FUNC) != 0)
5085 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr);
5086
5087 if ((ahc->features & AHC_ULTRA2) != 0)
5088 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh);
5089
5090 ptr = ahc->suspend_state.scratch_ram;
5091 for (i = 0; i < 64; i++)
5092 ahc_outb(ahc, SRAM_BASE + i, *ptr++);
5093
5094 if ((ahc->features & AHC_MORE_SRAM) != 0) {
5095 for (i = 0; i < 16; i++)
5096 ahc_outb(ahc, TARG_OFFSET + i, *ptr++);
5097 }
5098
5099 ptr = ahc->suspend_state.btt;
5100 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5101 for (i = 0;i < AHC_NUM_TARGETS; i++) {
5102 int j;
5103
5104 for (j = 0;j < AHC_NUM_LUNS; j++) {
5105 u_int tcl;
5106
5107 tcl = BUILD_TCL(i << 4, j);
5108 ahc_busy_tcl(ahc, tcl, *ptr);
5109 }
5110 }
5111 }
5112 return (0);
5113 }
5114
5115 /************************** Busy Target Table *********************************/
5116 /*
5117 * Return the untagged transaction id for a given target/channel lun.
5118 * Optionally, clear the entry.
5119 */
5120 u_int
ahc_index_busy_tcl(struct ahc_softc * ahc,u_int tcl)5121 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5122 {
5123 u_int scbid;
5124 u_int target_offset;
5125
5126 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5127 u_int saved_scbptr;
5128
5129 saved_scbptr = ahc_inb(ahc, SCBPTR);
5130 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5131 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5132 ahc_outb(ahc, SCBPTR, saved_scbptr);
5133 } else {
5134 target_offset = TCL_TARGET_OFFSET(tcl);
5135 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5136 }
5137
5138 return (scbid);
5139 }
5140
5141 void
ahc_unbusy_tcl(struct ahc_softc * ahc,u_int tcl)5142 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5143 {
5144 u_int target_offset;
5145
5146 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5147 u_int saved_scbptr;
5148
5149 saved_scbptr = ahc_inb(ahc, SCBPTR);
5150 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5151 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5152 ahc_outb(ahc, SCBPTR, saved_scbptr);
5153 } else {
5154 target_offset = TCL_TARGET_OFFSET(tcl);
5155 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5156 }
5157 }
5158
5159 void
ahc_busy_tcl(struct ahc_softc * ahc,u_int tcl,u_int scbid)5160 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5161 {
5162 u_int target_offset;
5163
5164 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5165 u_int saved_scbptr;
5166
5167 saved_scbptr = ahc_inb(ahc, SCBPTR);
5168 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5169 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5170 ahc_outb(ahc, SCBPTR, saved_scbptr);
5171 } else {
5172 target_offset = TCL_TARGET_OFFSET(tcl);
5173 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5174 }
5175 }
5176
5177 /************************** SCB and SCB queue management **********************/
5178 int
ahc_match_scb(struct ahc_softc * ahc,struct scb * scb,int target,char channel,int lun,u_int tag,role_t role)5179 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5180 char channel, int lun, u_int tag, role_t role)
5181 {
5182 int targ = SCB_GET_TARGET(ahc, scb);
5183 char chan = SCB_GET_CHANNEL(ahc, scb);
5184 int slun = SCB_GET_LUN(scb);
5185 int match;
5186
5187 match = ((chan == channel) || (channel == ALL_CHANNELS));
5188 if (match != 0)
5189 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5190 if (match != 0)
5191 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5192 if (match != 0) {
5193 #if 0
5194 #if AHC_TARGET_MODE
5195 int group;
5196
5197 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5198 if (role == ROLE_INITIATOR) {
5199 match = (group != XPT_FC_GROUP_TMODE)
5200 && ((tag == scb->hscb->tag)
5201 || (tag == SCB_LIST_NULL));
5202 } else if (role == ROLE_TARGET) {
5203 match = (group == XPT_FC_GROUP_TMODE)
5204 && ((tag == scb->io_ctx->csio.tag_id)
5205 || (tag == SCB_LIST_NULL));
5206 }
5207 #else /* !AHC_TARGET_MODE */
5208 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5209 #endif /* AHC_TARGET_MODE */
5210 #endif
5211 }
5212
5213 return match;
5214 }
5215
5216 void
ahc_freeze_devq(struct ahc_softc * ahc,struct scb * scb)5217 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5218 {
5219 int target;
5220 char channel;
5221 int lun;
5222
5223 target = SCB_GET_TARGET(ahc, scb);
5224 lun = SCB_GET_LUN(scb);
5225 channel = SCB_GET_CHANNEL(ahc, scb);
5226
5227 ahc_search_qinfifo(ahc, target, channel, lun,
5228 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5229 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5230
5231 ahc_platform_freeze_devq(ahc, scb);
5232 }
5233
5234 void
ahc_qinfifo_requeue_tail(struct ahc_softc * ahc,struct scb * scb)5235 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5236 {
5237 struct scb *prev_scb;
5238
5239 prev_scb = NULL;
5240 if (ahc_qinfifo_count(ahc) != 0) {
5241 u_int prev_tag;
5242 uint8_t prev_pos;
5243
5244 prev_pos = ahc->qinfifonext - 1;
5245 prev_tag = ahc->qinfifo[prev_pos];
5246 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5247 }
5248 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5249 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5250 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5251 } else {
5252 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5253 }
5254 }
5255
5256 static void
ahc_qinfifo_requeue(struct ahc_softc * ahc,struct scb * prev_scb,struct scb * scb)5257 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5258 struct scb *scb)
5259 {
5260 if (prev_scb == NULL) {
5261 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5262 } else {
5263 prev_scb->hscb->next = scb->hscb->tag;
5264 ahc_sync_scb(ahc, prev_scb,
5265 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5266 }
5267 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5268 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5269 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5270 }
5271
5272 static int
ahc_qinfifo_count(struct ahc_softc * ahc)5273 ahc_qinfifo_count(struct ahc_softc *ahc)
5274 {
5275 uint8_t qinpos;
5276 uint8_t diff;
5277
5278 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5279 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5280 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5281 } else
5282 qinpos = ahc_inb(ahc, QINPOS);
5283 diff = ahc->qinfifonext - qinpos;
5284 return (diff);
5285 }
5286
5287 int
ahc_search_qinfifo(struct ahc_softc * ahc,int target,char channel,int lun,u_int tag,role_t role,uint32_t status,ahc_search_action action)5288 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5289 int lun, u_int tag, role_t role, uint32_t status,
5290 ahc_search_action action)
5291 {
5292 struct scb *scb;
5293 struct scb *prev_scb;
5294 uint8_t qinstart;
5295 uint8_t qinpos;
5296 uint8_t qintail;
5297 uint8_t next;
5298 uint8_t prev;
5299 uint8_t curscbptr;
5300 int found;
5301 int have_qregs;
5302
5303 qintail = ahc->qinfifonext;
5304 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5305 if (have_qregs) {
5306 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5307 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5308 } else
5309 qinstart = ahc_inb(ahc, QINPOS);
5310 qinpos = qinstart;
5311 found = 0;
5312 prev_scb = NULL;
5313
5314 if (action == SEARCH_COMPLETE) {
5315 /*
5316 * Don't attempt to run any queued untagged transactions
5317 * until we are done with the abort process.
5318 */
5319 ahc_freeze_untagged_queues(ahc);
5320 }
5321
5322 /*
5323 * Start with an empty queue. Entries that are not chosen
5324 * for removal will be re-added to the queue as we go.
5325 */
5326 ahc->qinfifonext = qinpos;
5327 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5328
5329 while (qinpos != qintail) {
5330 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5331 if (scb == NULL) {
5332 printf("qinpos = %d, SCB index = %d\n",
5333 qinpos, ahc->qinfifo[qinpos]);
5334 panic("Loop 1\n");
5335 }
5336
5337 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5338 /*
5339 * We found an scb that needs to be acted on.
5340 */
5341 found++;
5342 switch (action) {
5343 case SEARCH_COMPLETE:
5344 {
5345 cam_status ostat;
5346 cam_status cstat;
5347
5348 ostat = ahc_get_transaction_status(scb);
5349 if (ostat == CAM_REQ_INPROG)
5350 ahc_set_transaction_status(scb, status);
5351 cstat = ahc_get_transaction_status(scb);
5352 if (cstat != CAM_REQ_CMP)
5353 ahc_freeze_scb(scb);
5354 if ((scb->flags & SCB_ACTIVE) == 0)
5355 printf("Inactive SCB in qinfifo\n");
5356 ahc_done(ahc, scb);
5357
5358 /* FALLTHROUGH */
5359 }
5360 case SEARCH_REMOVE:
5361 break;
5362 case SEARCH_COUNT:
5363 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5364 prev_scb = scb;
5365 break;
5366 }
5367 } else {
5368 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5369 prev_scb = scb;
5370 }
5371 qinpos++;
5372 }
5373
5374 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5375 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5376 } else {
5377 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5378 }
5379
5380 if (action != SEARCH_COUNT
5381 && (found != 0)
5382 && (qinstart != ahc->qinfifonext)) {
5383 /*
5384 * The sequencer may be in the process of DMA'ing
5385 * down the SCB at the beginning of the queue.
5386 * This could be problematic if either the first,
5387 * or the second SCB is removed from the queue
5388 * (the first SCB includes a pointer to the "next"
5389 * SCB to DMA). If we have removed any entries, swap
5390 * the first element in the queue with the next HSCB
5391 * so the sequencer will notice that NEXT_QUEUED_SCB
5392 * has changed during its DMA attempt and will retry
5393 * the DMA.
5394 */
5395 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5396
5397 if (scb == NULL) {
5398 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5399 found, qinstart, ahc->qinfifonext);
5400 panic("First/Second Qinfifo fixup\n");
5401 }
5402 /*
5403 * ahc_swap_with_next_hscb forces our next pointer to
5404 * point to the reserved SCB for future commands. Save
5405 * and restore our original next pointer to maintain
5406 * queue integrity.
5407 */
5408 next = scb->hscb->next;
5409 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5410 ahc_swap_with_next_hscb(ahc, scb);
5411 scb->hscb->next = next;
5412 ahc->qinfifo[qinstart] = scb->hscb->tag;
5413
5414 /* Tell the card about the new head of the qinfifo. */
5415 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5416
5417 /* Fixup the tail "next" pointer. */
5418 qintail = ahc->qinfifonext - 1;
5419 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5420 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5421 }
5422
5423 /*
5424 * Search waiting for selection list.
5425 */
5426 curscbptr = ahc_inb(ahc, SCBPTR);
5427 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5428 prev = SCB_LIST_NULL;
5429
5430 while (next != SCB_LIST_NULL) {
5431 uint8_t scb_index;
5432
5433 ahc_outb(ahc, SCBPTR, next);
5434 scb_index = ahc_inb(ahc, SCB_TAG);
5435 if (scb_index >= ahc->scb_data->numscbs) {
5436 printf("Waiting List inconsistency. "
5437 "SCB index == %d, yet numscbs == %d.",
5438 scb_index, ahc->scb_data->numscbs);
5439 ahc_dump_card_state(ahc);
5440 panic("for safety");
5441 }
5442 scb = ahc_lookup_scb(ahc, scb_index);
5443 if (scb == NULL) {
5444 printf("scb_index = %d, next = %d\n",
5445 scb_index, next);
5446 panic("Waiting List traversal\n");
5447 }
5448 if (ahc_match_scb(ahc, scb, target, channel,
5449 lun, SCB_LIST_NULL, role)) {
5450 /*
5451 * We found an scb that needs to be acted on.
5452 */
5453 found++;
5454 switch (action) {
5455 case SEARCH_COMPLETE:
5456 {
5457 cam_status ostat;
5458 cam_status cstat;
5459
5460 ostat = ahc_get_transaction_status(scb);
5461 if (ostat == CAM_REQ_INPROG)
5462 ahc_set_transaction_status(scb, status);
5463 cstat = ahc_get_transaction_status(scb);
5464 if (cstat != CAM_REQ_CMP)
5465 ahc_freeze_scb(scb);
5466 if ((scb->flags & SCB_ACTIVE) == 0)
5467 printf("Inactive SCB in "
5468 "Waiting List\n");
5469 ahc_done(ahc, scb);
5470 }
5471 /* FALLTHROUGH */
5472 case SEARCH_REMOVE:
5473 next = ahc_rem_wscb(ahc, next, prev);
5474 break;
5475 case SEARCH_COUNT:
5476 prev = next;
5477 next = ahc_inb(ahc, SCB_NEXT);
5478 break;
5479 }
5480 } else {
5481
5482 prev = next;
5483 next = ahc_inb(ahc, SCB_NEXT);
5484 }
5485 }
5486 ahc_outb(ahc, SCBPTR, curscbptr);
5487
5488 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5489 channel, lun, status, action);
5490
5491 if (action == SEARCH_COMPLETE)
5492 ahc_release_untagged_queues(ahc);
5493 return (found);
5494 }
5495
5496 int
ahc_search_untagged_queues(struct ahc_softc * ahc,struct scsipi_xfer * xs,int target,char channel,int lun,uint32_t status,ahc_search_action action)5497 ahc_search_untagged_queues(struct ahc_softc *ahc,
5498 struct scsipi_xfer *xs, int target, char channel, int lun,
5499 uint32_t status, ahc_search_action action)
5500 {
5501 struct scb *scb;
5502 int maxtarget;
5503 int found;
5504 int i;
5505
5506 if (action == SEARCH_COMPLETE) {
5507 /*
5508 * Don't attempt to run any queued untagged transactions
5509 * until we are done with the abort process.
5510 */
5511 ahc_freeze_untagged_queues(ahc);
5512 }
5513
5514 found = 0;
5515 i = 0;
5516 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5517
5518 maxtarget = 16;
5519 if (target != CAM_TARGET_WILDCARD) {
5520
5521 i = target;
5522 if (channel == 'B')
5523 i += 8;
5524 maxtarget = i + 1;
5525 }
5526 } else {
5527 maxtarget = 0;
5528 }
5529
5530 for (; i < maxtarget; i++) {
5531 struct scb_tailq *untagged_q;
5532 struct scb *next_scb;
5533
5534 untagged_q = &(ahc->untagged_queues[i]);
5535 next_scb = TAILQ_FIRST(untagged_q);
5536 while (next_scb != NULL) {
5537
5538 scb = next_scb;
5539 next_scb = TAILQ_NEXT(scb, links.tqe);
5540
5541 /*
5542 * The head of the list may be the currently
5543 * active untagged command for a device.
5544 * We're only searching for commands that
5545 * have not been started. A transaction
5546 * marked active but still in the qinfifo
5547 * is removed by the qinfifo scanning code
5548 * above.
5549 */
5550 if ((scb->flags & SCB_ACTIVE) != 0)
5551 continue;
5552
5553 if (ahc_match_scb(ahc, scb, target, channel, lun,
5554 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5555 /*|| (ctx != NULL && ctx != scb->io_ctx)*/)
5556 continue;
5557
5558 /*
5559 * We found an scb that needs to be acted on.
5560 */
5561 found++;
5562 switch (action) {
5563 case SEARCH_COMPLETE:
5564 {
5565 cam_status ostat;
5566 cam_status cstat;
5567
5568 ostat = ahc_get_transaction_status(scb);
5569 if (ostat == CAM_REQ_INPROG)
5570 ahc_set_transaction_status(scb, status);
5571 cstat = ahc_get_transaction_status(scb);
5572 if (cstat != CAM_REQ_CMP)
5573 ahc_freeze_scb(scb);
5574 if ((scb->flags & SCB_ACTIVE) == 0)
5575 printf("Inactive SCB in untaggedQ\n");
5576 ahc_done(ahc, scb);
5577 break;
5578 }
5579 case SEARCH_REMOVE:
5580 scb->flags &= ~SCB_UNTAGGEDQ;
5581 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5582 break;
5583 case SEARCH_COUNT:
5584 break;
5585 }
5586 }
5587 }
5588
5589 if (action == SEARCH_COMPLETE)
5590 ahc_release_untagged_queues(ahc);
5591 return (found);
5592 }
5593
5594 int
ahc_search_disc_list(struct ahc_softc * ahc,int target,char channel,int lun,u_int tag,int stop_on_first,int remove,int save_state)5595 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5596 int lun, u_int tag, int stop_on_first, int remove,
5597 int save_state)
5598 {
5599 struct scb *scbp;
5600 u_int next;
5601 u_int prev;
5602 u_int count;
5603 u_int active_scb;
5604
5605 count = 0;
5606 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5607 prev = SCB_LIST_NULL;
5608
5609 if (save_state) {
5610 /* restore this when we're done */
5611 active_scb = ahc_inb(ahc, SCBPTR);
5612 } else
5613 /* Silence compiler */
5614 active_scb = SCB_LIST_NULL;
5615
5616 while (next != SCB_LIST_NULL) {
5617 u_int scb_index;
5618
5619 ahc_outb(ahc, SCBPTR, next);
5620 scb_index = ahc_inb(ahc, SCB_TAG);
5621 if (scb_index >= ahc->scb_data->numscbs) {
5622 printf("Disconnected List inconsistency. "
5623 "SCB index == %d, yet numscbs == %d.",
5624 scb_index, ahc->scb_data->numscbs);
5625 ahc_dump_card_state(ahc);
5626 panic("for safety");
5627 }
5628
5629 if (next == prev) {
5630 panic("Disconnected List Loop. "
5631 "cur SCBPTR == %x, prev SCBPTR == %x.",
5632 next, prev);
5633 }
5634 scbp = ahc_lookup_scb(ahc, scb_index);
5635 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5636 tag, ROLE_INITIATOR)) {
5637 count++;
5638 if (remove) {
5639 next =
5640 ahc_rem_scb_from_disc_list(ahc, prev, next);
5641 } else {
5642 prev = next;
5643 next = ahc_inb(ahc, SCB_NEXT);
5644 }
5645 if (stop_on_first)
5646 break;
5647 } else {
5648 prev = next;
5649 next = ahc_inb(ahc, SCB_NEXT);
5650 }
5651 }
5652 if (save_state)
5653 ahc_outb(ahc, SCBPTR, active_scb);
5654 return (count);
5655 }
5656
5657 /*
5658 * Remove an SCB from the on chip list of disconnected transactions.
5659 * This is empty/unused if we are not performing SCB paging.
5660 */
5661 static u_int
ahc_rem_scb_from_disc_list(struct ahc_softc * ahc,u_int prev,u_int scbptr)5662 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5663 {
5664 u_int next;
5665
5666 ahc_outb(ahc, SCBPTR, scbptr);
5667 next = ahc_inb(ahc, SCB_NEXT);
5668
5669 ahc_outb(ahc, SCB_CONTROL, 0);
5670
5671 ahc_add_curscb_to_free_list(ahc);
5672
5673 if (prev != SCB_LIST_NULL) {
5674 ahc_outb(ahc, SCBPTR, prev);
5675 ahc_outb(ahc, SCB_NEXT, next);
5676 } else
5677 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5678
5679 return (next);
5680 }
5681
5682 /*
5683 * Add the SCB as selected by SCBPTR onto the on chip list of
5684 * free hardware SCBs. This list is empty/unused if we are not
5685 * performing SCB paging.
5686 */
5687 static void
ahc_add_curscb_to_free_list(struct ahc_softc * ahc)5688 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5689 {
5690 /*
5691 * Invalidate the tag so that our abort
5692 * routines don't think it's active.
5693 */
5694 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5695
5696 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5697 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5698 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5699 }
5700 }
5701
5702 /*
5703 * Manipulate the waiting for selection list and return the
5704 * scb that follows the one that we remove.
5705 */
5706 static u_int
ahc_rem_wscb(struct ahc_softc * ahc,u_int scbpos,u_int prev)5707 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5708 {
5709 u_int curscb, next;
5710
5711 /*
5712 * Select the SCB we want to abort and
5713 * pull the next pointer out of it.
5714 */
5715 curscb = ahc_inb(ahc, SCBPTR);
5716 ahc_outb(ahc, SCBPTR, scbpos);
5717 next = ahc_inb(ahc, SCB_NEXT);
5718
5719 /* Clear the necessary fields */
5720 ahc_outb(ahc, SCB_CONTROL, 0);
5721
5722 ahc_add_curscb_to_free_list(ahc);
5723
5724 /* update the waiting list */
5725 if (prev == SCB_LIST_NULL) {
5726 /* First in the list */
5727 ahc_outb(ahc, WAITING_SCBH, next);
5728
5729 /*
5730 * Ensure we aren't attempting to perform
5731 * selection for this entry.
5732 */
5733 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5734 } else {
5735 /*
5736 * Select the scb that pointed to us
5737 * and update its next pointer.
5738 */
5739 ahc_outb(ahc, SCBPTR, prev);
5740 ahc_outb(ahc, SCB_NEXT, next);
5741 }
5742
5743 /*
5744 * Point us back at the original scb position.
5745 */
5746 ahc_outb(ahc, SCBPTR, curscb);
5747 return next;
5748 }
5749
5750 /******************************** Error Handling ******************************/
5751 /*
5752 * Abort all SCBs that match the given description (target/channel/lun/tag),
5753 * setting their status to the passed in status if the status has not already
5754 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5755 * is paused before it is called.
5756 */
5757 int
ahc_abort_scbs(struct ahc_softc * ahc,int target,char channel,int lun,u_int tag,role_t role,uint32_t status)5758 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5759 int lun, u_int tag, role_t role, uint32_t status)
5760 {
5761 struct scb *scbp;
5762 struct scb *scbp_next;
5763 u_int active_scb;
5764 int i, j;
5765 int maxtarget;
5766 int minlun;
5767 int maxlun;
5768
5769 int found;
5770
5771 /*
5772 * Don't attempt to run any queued untagged transactions
5773 * until we are done with the abort process.
5774 */
5775 ahc_freeze_untagged_queues(ahc);
5776
5777 /* restore this when we're done */
5778 active_scb = ahc_inb(ahc, SCBPTR);
5779
5780 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5781 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5782
5783 /*
5784 * Clean out the busy target table for any untagged commands.
5785 */
5786 i = 0;
5787 maxtarget = 16;
5788 if (target != CAM_TARGET_WILDCARD) {
5789 i = target;
5790 if (channel == 'B')
5791 i += 8;
5792 maxtarget = i + 1;
5793 }
5794
5795 if (lun == CAM_LUN_WILDCARD) {
5796
5797 /*
5798 * Unless we are using an SCB based
5799 * busy targets table, there is only
5800 * one table entry for all luns of
5801 * a target.
5802 */
5803 minlun = 0;
5804 maxlun = 1;
5805 if ((ahc->flags & AHC_SCB_BTT) != 0)
5806 maxlun = AHC_NUM_LUNS;
5807 } else {
5808 minlun = lun;
5809 maxlun = lun + 1;
5810 }
5811
5812 if (role != ROLE_TARGET) {
5813 for (;i < maxtarget; i++) {
5814 for (j = minlun;j < maxlun; j++) {
5815 u_int scbid;
5816 u_int tcl;
5817
5818 tcl = BUILD_TCL(i << 4, j);
5819 scbid = ahc_index_busy_tcl(ahc, tcl);
5820 scbp = ahc_lookup_scb(ahc, scbid);
5821 if (scbp == NULL
5822 || ahc_match_scb(ahc, scbp, target, channel,
5823 lun, tag, role) == 0)
5824 continue;
5825 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5826 }
5827 }
5828
5829 /*
5830 * Go through the disconnected list and remove any entries we
5831 * have queued for completion, 0'ing their control byte too.
5832 * We save the active SCB and restore it ourselves, so there
5833 * is no reason for this search to restore it too.
5834 */
5835 ahc_search_disc_list(ahc, target, channel, lun, tag,
5836 /*stop_on_first*/FALSE, /*remove*/TRUE,
5837 /*save_state*/FALSE);
5838 }
5839
5840 /*
5841 * Go through the hardware SCB array looking for commands that
5842 * were active but not on any list. In some cases, these remnants
5843 * might not still have mappings in the scbindex array (e.g. unexpected
5844 * bus free with the same scb queued for an abort). Don't hold this
5845 * against them.
5846 */
5847 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5848 u_int scbid;
5849
5850 ahc_outb(ahc, SCBPTR, i);
5851 scbid = ahc_inb(ahc, SCB_TAG);
5852 scbp = ahc_lookup_scb(ahc, scbid);
5853 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5854 || (scbp != NULL
5855 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5856 ahc_add_curscb_to_free_list(ahc);
5857 }
5858
5859 /*
5860 * Go through the pending CCB list and look for
5861 * commands for this target that are still active.
5862 * These are other tagged commands that were
5863 * disconnected when the reset occurred.
5864 */
5865 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5866 while (scbp_next != NULL) {
5867 scbp = scbp_next;
5868 scbp_next = LIST_NEXT(scbp, pending_links);
5869 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5870 cam_status ostat;
5871
5872 ostat = ahc_get_transaction_status(scbp);
5873 if (ostat == CAM_REQ_INPROG)
5874 ahc_set_transaction_status(scbp, status);
5875 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5876 ahc_freeze_scb(scbp);
5877 if ((scbp->flags & SCB_ACTIVE) == 0)
5878 printf("Inactive SCB on pending list\n");
5879 ahc_done(ahc, scbp);
5880 found++;
5881 }
5882 }
5883 ahc_outb(ahc, SCBPTR, active_scb);
5884 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5885 ahc_release_untagged_queues(ahc);
5886 return found;
5887 }
5888
5889 static void
ahc_reset_current_bus(struct ahc_softc * ahc)5890 ahc_reset_current_bus(struct ahc_softc *ahc)
5891 {
5892 uint8_t scsiseq;
5893
5894 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5895 scsiseq = ahc_inb(ahc, SCSISEQ);
5896 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5897 ahc_flush_device_writes(ahc);
5898 ahc_delay(AHC_BUSRESET_DELAY);
5899 /* Turn off the bus reset */
5900 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5901
5902 ahc_clear_intstat(ahc);
5903
5904 /* Re-enable reset interrupts */
5905 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5906 }
5907
5908 int
ahc_reset_channel(struct ahc_softc * ahc,char channel,int initiate_reset)5909 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5910 {
5911 struct ahc_devinfo dinfo;
5912 u_int initiator, target, max_scsiid;
5913 u_int sblkctl;
5914 u_int scsiseq;
5915 u_int simode1;
5916 int found;
5917 int restart_needed;
5918 char cur_channel;
5919
5920 ahc->pending_device = NULL;
5921
5922 ahc_compile_devinfo(&dinfo,
5923 CAM_TARGET_WILDCARD,
5924 CAM_TARGET_WILDCARD,
5925 CAM_LUN_WILDCARD,
5926 channel, ROLE_UNKNOWN);
5927 ahc_pause(ahc);
5928
5929 /* Make sure the sequencer is in a safe location. */
5930 ahc_clear_critical_section(ahc);
5931
5932 /*
5933 * Run our command complete fifos to ensure that we perform
5934 * completion processing on any commands that 'completed'
5935 * before the reset occurred.
5936 */
5937 ahc_run_qoutfifo(ahc);
5938 #if AHC_TARGET_MODE
5939 /*
5940 * XXX - In Twin mode, the tqinfifo may have commands
5941 * for an unaffected channel in it. However, if
5942 * we have run out of ATIO resources to drain that
5943 * queue, we may not get them all out here. Further,
5944 * the blocked transactions for the reset channel
5945 * should just be killed off, irrespective of whether
5946 * we are blocked on ATIO resources. Write a routine
5947 * to compact the tqinfifo appropriately.
5948 */
5949 if ((ahc->flags & AHC_TARGETROLE) != 0) {
5950 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5951 }
5952 #endif
5953
5954 /*
5955 * Reset the bus if we are initiating this reset
5956 */
5957 sblkctl = ahc_inb(ahc, SBLKCTL);
5958 cur_channel = 'A';
5959 if ((ahc->features & AHC_TWIN) != 0
5960 && ((sblkctl & SELBUSB) != 0))
5961 cur_channel = 'B';
5962 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5963 if (cur_channel != channel) {
5964 /* Case 1: Command for another bus is active
5965 * Stealthily reset the other bus without
5966 * upsetting the current bus.
5967 */
5968 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5969 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5970 #if AHC_TARGET_MODE
5971 /*
5972 * Bus resets clear ENSELI, so we cannot
5973 * defer re-enabling bus reset interrupts
5974 * if we are in target mode.
5975 */
5976 if ((ahc->flags & AHC_TARGETROLE) != 0)
5977 simode1 |= ENSCSIRST;
5978 #endif
5979 ahc_outb(ahc, SIMODE1, simode1);
5980 if (initiate_reset)
5981 ahc_reset_current_bus(ahc);
5982 ahc_clear_intstat(ahc);
5983 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5984 ahc_outb(ahc, SBLKCTL, sblkctl);
5985 restart_needed = FALSE;
5986 } else {
5987 /* Case 2: A command from this bus is active or we're idle */
5988 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5989 #if AHC_TARGET_MODE
5990 /*
5991 * Bus resets clear ENSELI, so we cannot
5992 * defer re-enabling bus reset interrupts
5993 * if we are in target mode.
5994 */
5995 if ((ahc->flags & AHC_TARGETROLE) != 0)
5996 simode1 |= ENSCSIRST;
5997 #endif
5998 ahc_outb(ahc, SIMODE1, simode1);
5999 if (initiate_reset)
6000 ahc_reset_current_bus(ahc);
6001 ahc_clear_intstat(ahc);
6002 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6003 restart_needed = TRUE;
6004 }
6005
6006 /*
6007 * Clean up all the state information for the
6008 * pending transactions on this bus.
6009 */
6010 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6011 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6012 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6013
6014 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6015
6016 #ifdef AHC_TARGET_MODE
6017 /*
6018 * Send an immediate notify ccb to all target more peripheral
6019 * drivers affected by this action.
6020 */
6021 for (target = 0; target <= max_scsiid; target++) {
6022 struct ahc_tmode_tstate* tstate;
6023 u_int lun;
6024
6025 tstate = ahc->enabled_targets[target];
6026 if (tstate == NULL)
6027 continue;
6028 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6029 struct ahc_tmode_lstate* lstate;
6030
6031 lstate = tstate->enabled_luns[lun];
6032 if (lstate == NULL)
6033 continue;
6034
6035 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6036 EVENT_TYPE_BUS_RESET, /*arg*/0);
6037 ahc_send_lstate_events(ahc, lstate);
6038 }
6039 }
6040 #endif
6041 /*
6042 * Revert to async/narrow transfers until we renegotiate.
6043 */
6044 for (target = 0; target <= max_scsiid; target++) {
6045
6046 if (ahc->enabled_targets[target] == NULL)
6047 continue;
6048 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6049 struct ahc_devinfo devinfo;
6050
6051 ahc_compile_devinfo(&devinfo, target, initiator,
6052 CAM_LUN_WILDCARD,
6053 channel, ROLE_UNKNOWN);
6054 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6055 AHC_TRANS_CUR, /*paused*/TRUE);
6056 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6057 /*period*/0, /*offset*/0,
6058 /*ppr_options*/0, AHC_TRANS_CUR,
6059 /*paused*/TRUE);
6060 }
6061 }
6062
6063 if (restart_needed)
6064 ahc_restart(ahc);
6065 else
6066 ahc_unpause(ahc);
6067 return found;
6068 }
6069
6070
6071 /***************************** Residual Processing ****************************/
6072 /*
6073 * Calculate the residual for a just completed SCB.
6074 */
6075 void
ahc_calc_residual(struct ahc_softc * ahc,struct scb * scb)6076 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6077 {
6078 struct hardware_scb *hscb;
6079 struct status_pkt *spkt;
6080 uint32_t sgptr;
6081 uint32_t resid_sgptr;
6082 uint32_t resid;
6083
6084 /*
6085 * 5 cases.
6086 * 1) No residual.
6087 * SG_RESID_VALID clear in sgptr.
6088 * 2) Transferless command
6089 * 3) Never performed any transfers.
6090 * sgptr has SG_FULL_RESID set.
6091 * 4) No residual but target did not
6092 * save data pointers after the
6093 * last transfer, so sgptr was
6094 * never updated.
6095 * 5) We have a partial residual.
6096 * Use residual_sgptr to determine
6097 * where we are.
6098 */
6099
6100 hscb = scb->hscb;
6101 sgptr = ahc_le32toh(hscb->sgptr);
6102 if ((sgptr & SG_RESID_VALID) == 0)
6103 /* Case 1 */
6104 return;
6105 sgptr &= ~SG_RESID_VALID;
6106
6107 if ((sgptr & SG_LIST_NULL) != 0)
6108 /* Case 2 */
6109 return;
6110
6111 spkt = &hscb->shared_data.status;
6112 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6113 if ((sgptr & SG_FULL_RESID) != 0) {
6114 /* Case 3 */
6115 resid = ahc_get_transfer_length(scb);
6116 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6117 /* Case 4 */
6118 return;
6119 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6120 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6121 } else {
6122 struct ahc_dma_seg *sg;
6123
6124 /*
6125 * Remainder of the SG where the transfer
6126 * stopped.
6127 */
6128 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6129 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6130
6131 /* The residual sg_ptr always points to the next sg */
6132 sg--;
6133
6134 /*
6135 * Add up the contents of all residual
6136 * SG segments that are after the SG where
6137 * the transfer stopped.
6138 */
6139 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6140 sg++;
6141 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6142 }
6143 }
6144 if ((scb->flags & SCB_SENSE) == 0)
6145 ahc_set_residual(scb, resid);
6146 else
6147 ahc_set_sense_residual(scb, resid);
6148
6149 #ifdef AHC_DEBUG
6150 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6151 ahc_print_path(ahc, scb);
6152 printf("Handled %sResidual of %d bytes\n",
6153 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6154 }
6155 #endif
6156 }
6157
6158 /******************************* Target Mode **********************************/
6159 #ifdef AHC_TARGET_MODE
6160 /*
6161 * Add a target mode event to this lun's queue
6162 */
6163 static void
ahc_queue_lstate_event(struct ahc_softc * ahc,struct ahc_tmode_lstate * lstate,u_int initiator_id,u_int event_type,u_int event_arg)6164 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6165 u_int initiator_id, u_int event_type, u_int event_arg)
6166 {
6167 struct ahc_tmode_event *event;
6168 int pending;
6169
6170 xpt_freeze_devq(lstate->path, /*count*/1);
6171 if (lstate->event_w_idx >= lstate->event_r_idx)
6172 pending = lstate->event_w_idx - lstate->event_r_idx;
6173 else
6174 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6175 - (lstate->event_r_idx - lstate->event_w_idx);
6176
6177 if (event_type == EVENT_TYPE_BUS_RESET
6178 || event_type == MSG_BUS_DEV_RESET) {
6179 /*
6180 * Any earlier events are irrelevant, so reset our buffer.
6181 * This has the effect of allowing us to deal with reset
6182 * floods (an external device holding down the reset line)
6183 * without losing the event that is really interesting.
6184 */
6185 lstate->event_r_idx = 0;
6186 lstate->event_w_idx = 0;
6187 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6188 }
6189
6190 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6191 xpt_print_path(lstate->path);
6192 printf("immediate event %x:%x lost\n",
6193 lstate->event_buffer[lstate->event_r_idx].event_type,
6194 lstate->event_buffer[lstate->event_r_idx].event_arg);
6195 lstate->event_r_idx++;
6196 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6197 lstate->event_r_idx = 0;
6198 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6199 }
6200
6201 event = &lstate->event_buffer[lstate->event_w_idx];
6202 event->initiator_id = initiator_id;
6203 event->event_type = event_type;
6204 event->event_arg = event_arg;
6205 lstate->event_w_idx++;
6206 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6207 lstate->event_w_idx = 0;
6208 }
6209
6210 /*
6211 * Send any target mode events queued up waiting
6212 * for immediate notify resources.
6213 */
6214 void
ahc_send_lstate_events(struct ahc_softc * ahc,struct ahc_tmode_lstate * lstate)6215 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6216 {
6217 struct ccb_hdr *ccbh;
6218 struct ccb_immed_notify *inot;
6219
6220 while (lstate->event_r_idx != lstate->event_w_idx
6221 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6222 struct ahc_tmode_event *event;
6223
6224 event = &lstate->event_buffer[lstate->event_r_idx];
6225 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6226 inot = (struct ccb_immed_notify *)ccbh;
6227 switch (event->event_type) {
6228 case EVENT_TYPE_BUS_RESET:
6229 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6230 break;
6231 default:
6232 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6233 inot->message_args[0] = event->event_type;
6234 inot->message_args[1] = event->event_arg;
6235 break;
6236 }
6237 inot->initiator_id = event->initiator_id;
6238 inot->sense_len = 0;
6239 xpt_done((union ccb *)inot);
6240 lstate->event_r_idx++;
6241 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6242 lstate->event_r_idx = 0;
6243 }
6244 }
6245 #endif
6246
6247 /******************** Sequencer Program Patching/Download *********************/
6248
6249 #ifdef AHC_DUMP_SEQ
6250 void
ahc_dumpseq(struct ahc_softc * ahc)6251 ahc_dumpseq(struct ahc_softc* ahc)
6252 {
6253 int i;
6254 int max_prog;
6255
6256 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI)
6257 max_prog = 448;
6258 else if ((ahc->features & AHC_ULTRA2) != 0)
6259 max_prog = 768;
6260 else
6261 max_prog = 512;
6262
6263 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6264 ahc_outb(ahc, SEQADDR0, 0);
6265 ahc_outb(ahc, SEQADDR1, 0);
6266 for (i = 0; i < max_prog; i++) {
6267 uint8_t ins_bytes[4];
6268
6269 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6270 printf("0x%08x\n", ins_bytes[0] << 24
6271 | ins_bytes[1] << 16
6272 | ins_bytes[2] << 8
6273 | ins_bytes[3]);
6274 }
6275 }
6276 #endif
6277
6278 static void __noinline
ahc_loadseq(struct ahc_softc * ahc)6279 ahc_loadseq(struct ahc_softc *ahc)
6280 {
6281 struct cs cs_table[NUM_CRITICAL_SECTIONS];
6282 u_int begin_set[NUM_CRITICAL_SECTIONS];
6283 u_int end_set[NUM_CRITICAL_SECTIONS];
6284 const struct patch *cur_patch;
6285 u_int cs_count;
6286 u_int cur_cs;
6287 u_int i;
6288 int downloaded;
6289 u_int skip_addr;
6290 u_int sg_prefetch_cnt;
6291 uint8_t download_consts[7];
6292
6293 /*
6294 * Start out with 0 critical sections
6295 * that apply to this firmware load.
6296 */
6297 cs_count = 0;
6298 cur_cs = 0;
6299 memset(begin_set, 0, sizeof(begin_set));
6300 memset(end_set, 0, sizeof(end_set));
6301
6302 /* Setup downloadable constant table */
6303 download_consts[QOUTFIFO_OFFSET] = 0;
6304 if (ahc->targetcmds != NULL)
6305 download_consts[QOUTFIFO_OFFSET] += 32;
6306 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6307 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6308 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6309 sg_prefetch_cnt = ahc->pci_cachesize;
6310 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6311 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6312 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6313 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6314 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6315
6316 cur_patch = patches;
6317 downloaded = 0;
6318 skip_addr = 0;
6319 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6320 ahc_outb(ahc, SEQADDR0, 0);
6321 ahc_outb(ahc, SEQADDR1, 0);
6322
6323 for (i = 0; i < sizeof(seqprog)/4; i++) {
6324 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6325 /*
6326 * Don't download this instruction as it
6327 * is in a patch that was removed.
6328 */
6329 continue;
6330 }
6331 /*
6332 * Move through the CS table until we find a CS
6333 * that might apply to this instruction.
6334 */
6335 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
6336 if (critical_sections[cur_cs].end <= i) {
6337 if (begin_set[cs_count] == TRUE
6338 && end_set[cs_count] == FALSE) {
6339 cs_table[cs_count].end = downloaded;
6340 end_set[cs_count] = TRUE;
6341 cs_count++;
6342 }
6343 continue;
6344 }
6345 if (critical_sections[cur_cs].begin <= i
6346 && begin_set[cs_count] == FALSE) {
6347 cs_table[cs_count].begin = downloaded;
6348 begin_set[cs_count] = TRUE;
6349 }
6350 break;
6351 }
6352 ahc_download_instr(ahc, i, download_consts);
6353 downloaded++;
6354 }
6355
6356 ahc->num_critical_sections = cs_count;
6357 if (cs_count != 0) {
6358
6359 cs_count *= sizeof(struct cs);
6360 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_WAITOK);
6361 memcpy(ahc->critical_sections, cs_table, cs_count);
6362 }
6363 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6364 ahc_restart(ahc);
6365
6366 if (bootverbose) {
6367 printf(" %d instructions downloaded\n", downloaded);
6368 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6369 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6370 }
6371 }
6372
6373 static int
ahc_check_patch(struct ahc_softc * ahc,const struct patch ** start_patch,u_int start_instr,u_int * skip_addr)6374 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
6375 u_int start_instr, u_int *skip_addr)
6376 {
6377 const struct patch *cur_patch;
6378 const struct patch *last_patch;
6379 u_int num_patches;
6380
6381 num_patches = sizeof(patches)/sizeof(struct patch);
6382 last_patch = &patches[num_patches];
6383 cur_patch = *start_patch;
6384
6385 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6386
6387 if (cur_patch->patch_func(ahc) == 0) {
6388
6389 /* Start rejecting code */
6390 *skip_addr = start_instr + cur_patch->skip_instr;
6391 cur_patch += cur_patch->skip_patch;
6392 } else {
6393 /* Accepted this patch. Advance to the next
6394 * one and wait for our instruction pointer to
6395 * hit this point.
6396 */
6397 cur_patch++;
6398 }
6399 }
6400
6401 *start_patch = cur_patch;
6402 if (start_instr < *skip_addr)
6403 /* Still skipping */
6404 return (0);
6405
6406 return (1);
6407 }
6408
6409 static void
ahc_download_instr(struct ahc_softc * ahc,u_int instrptr,uint8_t * dconsts)6410 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6411 {
6412 union ins_formats instr;
6413 struct ins_format1 *fmt1_ins;
6414 struct ins_format3 *fmt3_ins;
6415 u_int opcode;
6416
6417 /*
6418 * The firmware is always compiled into a little endian format.
6419 */
6420 instr.integer = ahc_le32toh(*(const uint32_t*)&seqprog[instrptr * 4]);
6421
6422 fmt1_ins = &instr.format1;
6423 fmt3_ins = NULL;
6424
6425 /* Pull the opcode */
6426 opcode = instr.format1.opcode;
6427 switch (opcode) {
6428 case AIC_OP_JMP:
6429 case AIC_OP_JC:
6430 case AIC_OP_JNC:
6431 case AIC_OP_CALL:
6432 case AIC_OP_JNE:
6433 case AIC_OP_JNZ:
6434 case AIC_OP_JE:
6435 case AIC_OP_JZ:
6436 {
6437 const struct patch *cur_patch;
6438 int address_offset;
6439 u_int address;
6440 u_int skip_addr;
6441 u_int i;
6442
6443 fmt3_ins = &instr.format3;
6444 address_offset = 0;
6445 address = fmt3_ins->address;
6446 cur_patch = patches;
6447 skip_addr = 0;
6448 for (i = 0; i < address;) {
6449 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6450
6451 if (skip_addr > i) {
6452 int end_addr;
6453
6454 end_addr = MIN(address, skip_addr);
6455 address_offset += end_addr - i;
6456 i = skip_addr;
6457 } else {
6458 i++;
6459 }
6460 }
6461 address -= address_offset;
6462 fmt3_ins->address = address;
6463 }
6464 /* FALLTHROUGH */
6465 case AIC_OP_OR:
6466 case AIC_OP_AND:
6467 case AIC_OP_XOR:
6468 case AIC_OP_ADD:
6469 case AIC_OP_ADC:
6470 case AIC_OP_BMOV:
6471 if (fmt1_ins->parity != 0) {
6472 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6473 }
6474 fmt1_ins->parity = 0;
6475 if ((ahc->features & AHC_CMD_CHAN) == 0
6476 && opcode == AIC_OP_BMOV) {
6477 /*
6478 * Block move was added at the same time
6479 * as the command channel. Verify that
6480 * this is only a move of a single element
6481 * and convert the BMOV to a MOV
6482 * (AND with an immediate of FF).
6483 */
6484 if (fmt1_ins->immediate != 1)
6485 panic("%s: BMOV not supported\n",
6486 ahc_name(ahc));
6487 fmt1_ins->opcode = AIC_OP_AND;
6488 fmt1_ins->immediate = 0xff;
6489 }
6490 /* FALLTHROUGH */
6491 case AIC_OP_ROL:
6492 if ((ahc->features & AHC_ULTRA2) != 0) {
6493 int i, count;
6494
6495 /* Calculate odd parity for the instruction */
6496 for (i = 0, count = 0; i < 31; i++) {
6497 uint32_t mask;
6498
6499 mask = 0x01 << i;
6500 if ((instr.integer & mask) != 0)
6501 count++;
6502 }
6503 if ((count & 0x01) == 0)
6504 instr.format1.parity = 1;
6505 } else {
6506 /* Compress the instruction for older sequencers */
6507 if (fmt3_ins != NULL) {
6508 instr.integer =
6509 fmt3_ins->immediate
6510 | (fmt3_ins->source << 8)
6511 | (fmt3_ins->address << 16)
6512 | (fmt3_ins->opcode << 25);
6513 } else {
6514 instr.integer =
6515 fmt1_ins->immediate
6516 | (fmt1_ins->source << 8)
6517 | (fmt1_ins->destination << 16)
6518 | (fmt1_ins->ret << 24)
6519 | (fmt1_ins->opcode << 25);
6520 }
6521 }
6522 /* The sequencer is a little endian CPU */
6523 instr.integer = ahc_htole32(instr.integer);
6524 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6525 break;
6526 default:
6527 panic("Unknown opcode encountered in seq program");
6528 break;
6529 }
6530 }
6531
6532 int
ahc_print_register(ahc_reg_parse_entry_t * table,u_int num_entries,const char * name,u_int address,u_int value,u_int * cur_column,u_int wrap_point)6533 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6534 const char *name, u_int address, u_int value,
6535 u_int *cur_column, u_int wrap_point)
6536 {
6537 size_t printed;
6538 u_int printed_mask;
6539 char line[1024];
6540
6541 line[0] = 0;
6542
6543 if (cur_column != NULL && *cur_column >= wrap_point) {
6544 printf("\n");
6545 *cur_column = 0;
6546 }
6547 printed = snprintf(line, sizeof(line), "%s[0x%x]", name, value);
6548 if (printed > sizeof(line))
6549 printed = sizeof(line);
6550 if (table == NULL) {
6551 printed += snprintf(&line[printed], (sizeof line) - printed,
6552 " ");
6553 if (printed > sizeof(line))
6554 printed = sizeof(line);
6555 printf("%s", line);
6556 if (cur_column != NULL)
6557 *cur_column += printed;
6558 return (printed);
6559 }
6560 printed_mask = 0;
6561 while (printed_mask != 0xFF) {
6562 int entry;
6563
6564 for (entry = 0; entry < num_entries; entry++) {
6565 if (((value & table[entry].mask)
6566 != table[entry].value)
6567 || ((printed_mask & table[entry].mask)
6568 == table[entry].mask))
6569 continue;
6570 if (printed > sizeof(line))
6571 printed = sizeof(line);
6572 printed += snprintf(&line[printed],
6573 (sizeof line) - printed, "%s%s",
6574 printed_mask == 0 ? ":(" : "|",
6575 table[entry].name);
6576 printed_mask |= table[entry].mask;
6577
6578 break;
6579 }
6580 if (entry >= num_entries)
6581 break;
6582 }
6583 if (printed > sizeof(line))
6584 printed = sizeof(line);
6585 if (printed_mask != 0)
6586 printed += snprintf(&line[printed],
6587 (sizeof line) - printed, ") ");
6588 else
6589 printed += snprintf(&line[printed],
6590 (sizeof line) - printed, " ");
6591 if (cur_column != NULL)
6592 *cur_column += printed;
6593 printf("%s", line);
6594
6595 return (printed);
6596 }
6597
6598 void
ahc_dump_card_state(struct ahc_softc * ahc)6599 ahc_dump_card_state(struct ahc_softc *ahc)
6600 {
6601 struct scb *scb;
6602 struct scb_tailq *untagged_q;
6603 u_int cur_col;
6604 int paused;
6605 int target;
6606 int maxtarget;
6607 int i;
6608 uint8_t last_phase;
6609 uint8_t qinpos;
6610 uint8_t qintail;
6611 uint8_t qoutpos;
6612 uint8_t scb_index;
6613 uint8_t saved_scbptr;
6614
6615 if (ahc_is_paused(ahc)) {
6616 paused = 1;
6617 } else {
6618 paused = 0;
6619 ahc_pause(ahc);
6620 }
6621
6622 saved_scbptr = ahc_inb(ahc, SCBPTR);
6623 last_phase = ahc_inb(ahc, LASTPHASE);
6624 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6625 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6626 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6627 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6628 if (paused)
6629 printf("Card was paused\n");
6630 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6631 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6632 ahc_inb(ahc, ARG_2));
6633 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6634 ahc_inb(ahc, SCBPTR));
6635 cur_col = 0;
6636 if ((ahc->features & AHC_DT) != 0)
6637 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6638 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6639 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6640 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6641 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6642 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6643 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6644 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6645 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6646 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6647 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6648 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6649 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6650 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6651 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6652 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6653 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6654 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6655 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6656 if (cur_col != 0)
6657 printf("\n");
6658 printf("STACK:");
6659 for (i = 0; i < STACK_SIZE; i++)
6660 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6661 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6662 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6663 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6664 /* QINFIFO */
6665 printf("QINFIFO entries: ");
6666 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6667 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6668 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6669 } else
6670 qinpos = ahc_inb(ahc, QINPOS);
6671 qintail = ahc->qinfifonext;
6672 while (qinpos != qintail) {
6673 printf("%d ", ahc->qinfifo[qinpos]);
6674 qinpos++;
6675 }
6676 printf("\n");
6677
6678 printf("Waiting Queue entries: ");
6679 scb_index = ahc_inb(ahc, WAITING_SCBH);
6680 i = 0;
6681 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6682 ahc_outb(ahc, SCBPTR, scb_index);
6683 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6684 scb_index = ahc_inb(ahc, SCB_NEXT);
6685 }
6686 printf("\n");
6687
6688 printf("Disconnected Queue entries: ");
6689 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6690 i = 0;
6691 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6692 ahc_outb(ahc, SCBPTR, scb_index);
6693 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6694 scb_index = ahc_inb(ahc, SCB_NEXT);
6695 }
6696 printf("\n");
6697
6698 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6699 printf("QOUTFIFO entries: ");
6700 qoutpos = ahc->qoutfifonext;
6701 i = 0;
6702 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6703 printf("%d ", ahc->qoutfifo[qoutpos]);
6704 qoutpos++;
6705 }
6706 printf("\n");
6707
6708 printf("Sequencer Free SCB List: ");
6709 scb_index = ahc_inb(ahc, FREE_SCBH);
6710 i = 0;
6711 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6712 ahc_outb(ahc, SCBPTR, scb_index);
6713 printf("%d ", scb_index);
6714 scb_index = ahc_inb(ahc, SCB_NEXT);
6715 }
6716 printf("\n");
6717
6718 printf("Sequencer SCB Info: ");
6719 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6720 ahc_outb(ahc, SCBPTR, i);
6721 /*cur_col =*/ printf("\n%3d ", i);
6722
6723 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6724 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6725 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6726 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6727 }
6728 printf("\n");
6729
6730 printf("Pending list: ");
6731 i = 0;
6732 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6733 if (i++ > 256)
6734 break;
6735 /*cur_col =*/ printf("\n%3d ", scb->hscb->tag);
6736 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6737 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6738 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6739 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6740 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6741 printf("(");
6742 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6743 &cur_col, 60);
6744 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6745 printf(")");
6746 }
6747 }
6748 printf("\n");
6749
6750 printf("Kernel Free SCB list: ");
6751 i = 0;
6752 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6753 if (i++ > 256)
6754 break;
6755 printf("%d ", scb->hscb->tag);
6756 }
6757 printf("\n");
6758
6759 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6760 for (target = 0; target <= maxtarget; target++) {
6761 untagged_q = &ahc->untagged_queues[target];
6762 if (TAILQ_FIRST(untagged_q) == NULL)
6763 continue;
6764 printf("Untagged Q(%d): ", target);
6765 i = 0;
6766 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6767 if (i++ > 256)
6768 break;
6769 printf("%d ", scb->hscb->tag);
6770 }
6771 printf("\n");
6772 }
6773
6774 ahc_platform_dump_card_state(ahc);
6775 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6776 ahc_outb(ahc, SCBPTR, saved_scbptr);
6777 if (paused == 0)
6778 ahc_unpause(ahc);
6779 }
6780
6781 /************************* Target Mode ****************************************/
6782 #ifdef AHC_TARGET_MODE
6783 cam_status
ahc_find_tmode_devs(struct ahc_softc * ahc,struct cam_sim * sim,union ccb * ccb,struct ahc_tmode_tstate ** tstate,struct ahc_tmode_lstate ** lstate,int notfound_failure)6784 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6785 struct ahc_tmode_tstate **tstate,
6786 struct ahc_tmode_lstate **lstate,
6787 int notfound_failure)
6788 {
6789
6790 if ((ahc->features & AHC_TARGETMODE) == 0)
6791 return (CAM_REQ_INVALID);
6792
6793 /*
6794 * Handle the 'black hole' device that sucks up
6795 * requests to unattached luns on enabled targets.
6796 */
6797 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6798 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6799 *tstate = NULL;
6800 *lstate = ahc->black_hole;
6801 } else {
6802 u_int max_id;
6803
6804 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
6805 if (ccb->ccb_h.target_id > max_id)
6806 return (CAM_TID_INVALID);
6807
6808 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6809 return (CAM_LUN_INVALID);
6810
6811 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6812 *lstate = NULL;
6813 if (*tstate != NULL)
6814 *lstate =
6815 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6816 }
6817
6818 if (notfound_failure != 0 && *lstate == NULL)
6819 return (CAM_PATH_INVALID);
6820
6821 return (CAM_REQ_CMP);
6822 }
6823
6824 void
ahc_handle_en_lun(struct ahc_softc * ahc,struct cam_sim * sim,union ccb * ccb)6825 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6826 {
6827 struct ahc_tmode_tstate *tstate;
6828 struct ahc_tmode_lstate *lstate;
6829 struct ccb_en_lun *cel;
6830 cam_status status;
6831 u_int target;
6832 u_int lun;
6833 u_int target_mask;
6834 u_int our_id;
6835 u_long s;
6836 char channel;
6837
6838 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6839 /*notfound_failure*/FALSE);
6840
6841 if (status != CAM_REQ_CMP) {
6842 ccb->ccb_h.status = status;
6843 return;
6844 }
6845
6846 if (cam_sim_bus(sim) == 0)
6847 our_id = ahc->our_id;
6848 else
6849 our_id = ahc->our_id_b;
6850
6851 if (ccb->ccb_h.target_id != our_id) {
6852 /*
6853 * our_id represents our initiator ID, or
6854 * the ID of the first target to have an
6855 * enabled lun in target mode. There are
6856 * two cases that may preclude enabling a
6857 * target id other than our_id.
6858 *
6859 * o our_id is for an active initiator role.
6860 * Since the hardware does not support
6861 * reselections to the initiator role at
6862 * anything other than our_id, and our_id
6863 * is used by the hardware to indicate the
6864 * ID to use for both select-out and
6865 * reselect-out operations, the only target
6866 * ID we can support in this mode is our_id.
6867 *
6868 * o The MULTARGID feature is not available and
6869 * a previous target mode ID has been enabled.
6870 */
6871 if ((ahc->features & AHC_MULTIROLE) != 0) {
6872
6873 if ((ahc->features & AHC_MULTI_TID) != 0
6874 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6875 /*
6876 * Only allow additional targets if
6877 * the initiator role is disabled.
6878 * The hardware cannot handle a re-select-in
6879 * on the initiator id during a re-select-out
6880 * on a different target id.
6881 */
6882 status = CAM_TID_INVALID;
6883 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6884 || ahc->enabled_luns > 0) {
6885 /*
6886 * Only allow our target id to change
6887 * if the initiator role is not configured
6888 * and there are no enabled luns which
6889 * are attached to the currently registered
6890 * scsi id.
6891 */
6892 status = CAM_TID_INVALID;
6893 }
6894 } else if ((ahc->features & AHC_MULTI_TID) == 0
6895 && ahc->enabled_luns > 0) {
6896
6897 status = CAM_TID_INVALID;
6898 }
6899 }
6900
6901 if (status != CAM_REQ_CMP) {
6902 ccb->ccb_h.status = status;
6903 return;
6904 }
6905
6906 /*
6907 * We now have an id that is valid.
6908 * If we aren't in target mode, switch modes.
6909 */
6910 if ((ahc->flags & AHC_TARGETROLE) == 0
6911 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6912 u_long s;
6913
6914 printf("Configuring Target Mode\n");
6915 ahc_lock(ahc, &s);
6916 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6917 ccb->ccb_h.status = CAM_BUSY;
6918 ahc_unlock(ahc, &s);
6919 return;
6920 }
6921 ahc->flags |= AHC_TARGETROLE;
6922 if ((ahc->features & AHC_MULTIROLE) == 0)
6923 ahc->flags &= ~AHC_INITIATORROLE;
6924 ahc_pause(ahc);
6925 ahc_loadseq(ahc);
6926 ahc_unlock(ahc, &s);
6927 }
6928 cel = &ccb->cel;
6929 target = ccb->ccb_h.target_id;
6930 lun = ccb->ccb_h.target_lun;
6931 channel = SIM_CHANNEL(ahc, sim);
6932 target_mask = 0x01 << target;
6933 if (channel == 'B')
6934 target_mask <<= 8;
6935
6936 if (cel->enable != 0) {
6937 u_int scsiseq;
6938
6939 /* Are we already enabled?? */
6940 if (lstate != NULL) {
6941 xpt_print_path(ccb->ccb_h.path);
6942 printf("Lun already enabled\n");
6943 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6944 return;
6945 }
6946
6947 if (cel->grp6_len != 0
6948 || cel->grp7_len != 0) {
6949 /*
6950 * Don't (yet?) support vendor
6951 * specific commands.
6952 */
6953 ccb->ccb_h.status = CAM_REQ_INVALID;
6954 printf("Non-zero Group Codes\n");
6955 return;
6956 }
6957
6958 /*
6959 * Seems to be okay.
6960 * Setup our data structures.
6961 */
6962 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6963 tstate = ahc_alloc_tstate(ahc, target, channel);
6964 if (tstate == NULL) {
6965 xpt_print_path(ccb->ccb_h.path);
6966 printf("Couldn't allocate tstate\n");
6967 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6968 return;
6969 }
6970 }
6971 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
6972 if (lstate == NULL) {
6973 xpt_print_path(ccb->ccb_h.path);
6974 printf("Couldn't allocate lstate\n");
6975 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6976 return;
6977 }
6978 memset(lstate, 0, sizeof(*lstate));
6979 status = xpt_create_path(&lstate->path, /*periph*/NULL,
6980 xpt_path_path_id(ccb->ccb_h.path),
6981 xpt_path_target_id(ccb->ccb_h.path),
6982 xpt_path_lun_id(ccb->ccb_h.path));
6983 if (status != CAM_REQ_CMP) {
6984 free(lstate, M_DEVBUF);
6985 xpt_print_path(ccb->ccb_h.path);
6986 printf("Couldn't allocate path\n");
6987 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6988 return;
6989 }
6990 SLIST_INIT(&lstate->accept_tios);
6991 SLIST_INIT(&lstate->immed_notifies);
6992 ahc_lock(ahc, &s);
6993 ahc_pause(ahc);
6994 if (target != CAM_TARGET_WILDCARD) {
6995 tstate->enabled_luns[lun] = lstate;
6996 ahc->enabled_luns++;
6997
6998 if ((ahc->features & AHC_MULTI_TID) != 0) {
6999 u_int targid_mask;
7000
7001 targid_mask = ahc_inb(ahc, TARGID)
7002 | (ahc_inb(ahc, TARGID + 1) << 8);
7003
7004 targid_mask |= target_mask;
7005 ahc_outb(ahc, TARGID, targid_mask);
7006 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7007
7008 ahc_update_scsiid(ahc, targid_mask);
7009 } else {
7010 u_int our_id;
7011 char channel;
7012
7013 channel = SIM_CHANNEL(ahc, sim);
7014 our_id = SIM_SCSI_ID(ahc, sim);
7015
7016 /*
7017 * This can only happen if selections
7018 * are not enabled
7019 */
7020 if (target != our_id) {
7021 u_int sblkctl;
7022 char cur_channel;
7023 int swap;
7024
7025 sblkctl = ahc_inb(ahc, SBLKCTL);
7026 cur_channel = (sblkctl & SELBUSB)
7027 ? 'B' : 'A';
7028 if ((ahc->features & AHC_TWIN) == 0)
7029 cur_channel = 'A';
7030 swap = cur_channel != channel;
7031 if (channel == 'A')
7032 ahc->our_id = target;
7033 else
7034 ahc->our_id_b = target;
7035
7036 if (swap)
7037 ahc_outb(ahc, SBLKCTL,
7038 sblkctl ^ SELBUSB);
7039
7040 ahc_outb(ahc, SCSIID, target);
7041
7042 if (swap)
7043 ahc_outb(ahc, SBLKCTL, sblkctl);
7044 }
7045 }
7046 } else
7047 ahc->black_hole = lstate;
7048 /* Allow select-in operations */
7049 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7050 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7051 scsiseq |= ENSELI;
7052 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7053 scsiseq = ahc_inb(ahc, SCSISEQ);
7054 scsiseq |= ENSELI;
7055 ahc_outb(ahc, SCSISEQ, scsiseq);
7056 }
7057 ahc_unpause(ahc);
7058 ahc_unlock(ahc, &s);
7059 ccb->ccb_h.status = CAM_REQ_CMP;
7060 xpt_print_path(ccb->ccb_h.path);
7061 printf("Lun now enabled for target mode\n");
7062 } else {
7063 struct scb *scb;
7064 int i, empty;
7065
7066 if (lstate == NULL) {
7067 ccb->ccb_h.status = CAM_LUN_INVALID;
7068 return;
7069 }
7070
7071 ahc_lock(ahc, &s);
7072
7073 ccb->ccb_h.status = CAM_REQ_CMP;
7074 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7075 struct ccb_hdr *ccbh;
7076
7077 ccbh = &scb->io_ctx->ccb_h;
7078 if (ccbh->func_code == XPT_CONT_TARGET_IO
7079 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7080 printf("CTIO pending\n");
7081 ccb->ccb_h.status = CAM_REQ_INVALID;
7082 ahc_unlock(ahc, &s);
7083 return;
7084 }
7085 }
7086
7087 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7088 printf("ATIOs pending\n");
7089 ccb->ccb_h.status = CAM_REQ_INVALID;
7090 }
7091
7092 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7093 printf("INOTs pending\n");
7094 ccb->ccb_h.status = CAM_REQ_INVALID;
7095 }
7096
7097 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7098 ahc_unlock(ahc, &s);
7099 return;
7100 }
7101
7102 xpt_print_path(ccb->ccb_h.path);
7103 printf("Target mode disabled\n");
7104 xpt_free_path(lstate->path);
7105 free(lstate, M_DEVBUF);
7106
7107 ahc_pause(ahc);
7108 /* Can we clean up the target too? */
7109 if (target != CAM_TARGET_WILDCARD) {
7110 tstate->enabled_luns[lun] = NULL;
7111 ahc->enabled_luns--;
7112 for (empty = 1, i = 0; i < 8; i++)
7113 if (tstate->enabled_luns[i] != NULL) {
7114 empty = 0;
7115 break;
7116 }
7117
7118 if (empty) {
7119 ahc_free_tstate(ahc, target, channel,
7120 /*force*/FALSE);
7121 if (ahc->features & AHC_MULTI_TID) {
7122 u_int targid_mask;
7123
7124 targid_mask = ahc_inb(ahc, TARGID)
7125 | (ahc_inb(ahc, TARGID + 1)
7126 << 8);
7127
7128 targid_mask &= ~target_mask;
7129 ahc_outb(ahc, TARGID, targid_mask);
7130 ahc_outb(ahc, TARGID+1,
7131 (targid_mask >> 8));
7132 ahc_update_scsiid(ahc, targid_mask);
7133 }
7134 }
7135 } else {
7136
7137 ahc->black_hole = NULL;
7138
7139 /*
7140 * We can't allow selections without
7141 * our black hole device.
7142 */
7143 empty = TRUE;
7144 }
7145 if (ahc->enabled_luns == 0) {
7146 /* Disallow select-in */
7147 u_int scsiseq;
7148
7149 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7150 scsiseq &= ~ENSELI;
7151 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7152 scsiseq = ahc_inb(ahc, SCSISEQ);
7153 scsiseq &= ~ENSELI;
7154 ahc_outb(ahc, SCSISEQ, scsiseq);
7155
7156 if ((ahc->features & AHC_MULTIROLE) == 0) {
7157 printf("Configuring Initiator Mode\n");
7158 ahc->flags &= ~AHC_TARGETROLE;
7159 ahc->flags |= AHC_INITIATORROLE;
7160 ahc_pause(ahc);
7161 ahc_loadseq(ahc);
7162 }
7163 }
7164 ahc_unpause(ahc);
7165 ahc_unlock(ahc, &s);
7166 }
7167 }
7168
7169 static void
ahc_update_scsiid(struct ahc_softc * ahc,u_int targid_mask)7170 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7171 {
7172 u_int scsiid_mask;
7173 u_int scsiid;
7174
7175 if ((ahc->features & AHC_MULTI_TID) == 0)
7176 panic("ahc_update_scsiid called on non-multitid unit\n");
7177
7178 /*
7179 * Since we will rely on the TARGID mask
7180 * for selection enables, ensure that OID
7181 * in SCSIID is not set to some other ID
7182 * that we don't want to allow selections on.
7183 */
7184 if ((ahc->features & AHC_ULTRA2) != 0)
7185 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7186 else
7187 scsiid = ahc_inb(ahc, SCSIID);
7188 scsiid_mask = 0x1 << (scsiid & OID);
7189 if ((targid_mask & scsiid_mask) == 0) {
7190 u_int our_id;
7191
7192 /* ffs counts from 1 */
7193 our_id = ffs(targid_mask);
7194 if (our_id == 0)
7195 our_id = ahc->our_id;
7196 else
7197 our_id--;
7198 scsiid &= TID;
7199 scsiid |= our_id;
7200 }
7201 if ((ahc->features & AHC_ULTRA2) != 0)
7202 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7203 else
7204 ahc_outb(ahc, SCSIID, scsiid);
7205 }
7206
7207 void
ahc_run_tqinfifo(struct ahc_softc * ahc,int paused)7208 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7209 {
7210 struct target_cmd *cmd;
7211
7212 /*
7213 * If the card supports auto-access pause,
7214 * we can access the card directly regardless
7215 * of whether it is paused or not.
7216 */
7217 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7218 paused = TRUE;
7219
7220 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7221 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7222
7223 /*
7224 * Only advance through the queue if we
7225 * have the resources to process the command.
7226 */
7227 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7228 break;
7229
7230 cmd->cmd_valid = 0;
7231 ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/,
7232 ahc->shared_data_dmamap,
7233 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7234 sizeof(struct target_cmd),
7235 BUS_DMASYNC_PREREAD);
7236 ahc->tqinfifonext++;
7237
7238 /*
7239 * Lazily update our position in the target mode incoming
7240 * command queue as seen by the sequencer.
7241 */
7242 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7243 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7244 u_int hs_mailbox;
7245
7246 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7247 hs_mailbox &= ~HOST_TQINPOS;
7248 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7249 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7250 } else {
7251 if (!paused)
7252 ahc_pause(ahc);
7253 ahc_outb(ahc, KERNEL_TQINPOS,
7254 ahc->tqinfifonext & HOST_TQINPOS);
7255 if (!paused)
7256 ahc_unpause(ahc);
7257 }
7258 }
7259 }
7260 }
7261
7262 static int
ahc_handle_target_cmd(struct ahc_softc * ahc,struct target_cmd * cmd)7263 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7264 {
7265 struct ahc_tmode_tstate *tstate;
7266 struct ahc_tmode_lstate *lstate;
7267 struct ccb_accept_tio *atio;
7268 uint8_t *byte;
7269 int initiator;
7270 int target;
7271 int lun;
7272
7273 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7274 target = SCSIID_OUR_ID(cmd->scsiid);
7275 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7276
7277 byte = cmd->bytes;
7278 tstate = ahc->enabled_targets[target];
7279 lstate = NULL;
7280 if (tstate != NULL)
7281 lstate = tstate->enabled_luns[lun];
7282
7283 /*
7284 * Commands for disabled luns go to the black hole driver.
7285 */
7286 if (lstate == NULL)
7287 lstate = ahc->black_hole;
7288
7289 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7290 if (atio == NULL) {
7291 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7292 /*
7293 * Wait for more ATIOs from the peripheral driver for this lun.
7294 */
7295 if (bootverbose)
7296 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7297 return (1);
7298 } else
7299 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7300 #if 0
7301 printf("Incoming command from %d for %d:%d%s\n",
7302 initiator, target, lun,
7303 lstate == ahc->black_hole ? "(Black Holed)" : "");
7304 #endif
7305 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7306
7307 if (lstate == ahc->black_hole) {
7308 /* Fill in the wildcards */
7309 atio->ccb_h.target_id = target;
7310 atio->ccb_h.target_lun = lun;
7311 }
7312
7313 /*
7314 * Package it up and send it off to
7315 * whomever has this lun enabled.
7316 */
7317 atio->sense_len = 0;
7318 atio->init_id = initiator;
7319 if (byte[0] != 0xFF) {
7320 /* Tag was included */
7321 atio->tag_action = *byte++;
7322 atio->tag_id = *byte++;
7323 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7324 } else {
7325 atio->ccb_h.flags = 0;
7326 }
7327 byte++;
7328
7329 /* Okay. Now determine the cdb size based on the command code */
7330 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7331 case 0:
7332 atio->cdb_len = 6;
7333 break;
7334 case 1:
7335 case 2:
7336 atio->cdb_len = 10;
7337 break;
7338 case 4:
7339 atio->cdb_len = 16;
7340 break;
7341 case 5:
7342 atio->cdb_len = 12;
7343 break;
7344 case 3:
7345 default:
7346 /* Only copy the opcode. */
7347 atio->cdb_len = 1;
7348 printf("Reserved or VU command code type encountered\n");
7349 break;
7350 }
7351
7352 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7353
7354 atio->ccb_h.status |= CAM_CDB_RECVD;
7355
7356 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7357 /*
7358 * We weren't allowed to disconnect.
7359 * We're hanging on the bus until a
7360 * continue target I/O comes in response
7361 * to this accept tio.
7362 */
7363 #if 0
7364 printf("Received Immediate Command %d:%d:%d - %p\n",
7365 initiator, target, lun, ahc->pending_device);
7366 #endif
7367 ahc->pending_device = lstate;
7368 ahc_freeze_ccb((union ccb *)atio);
7369 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7370 }
7371 xpt_done((union ccb*)atio);
7372 return (0);
7373 }
7374 #endif
7375
7376 static int
ahc_createdmamem(bus_dma_tag_t tag,int size,int flags,bus_dmamap_t * mapp,void ** vaddr,bus_addr_t * baddr,bus_dma_segment_t * seg,int * nseg,const char * myname,const char * what)7377 ahc_createdmamem(bus_dma_tag_t tag, int size, int flags, bus_dmamap_t *mapp,
7378 void **vaddr, bus_addr_t *baddr, bus_dma_segment_t *seg, int *nseg,
7379 const char *myname, const char *what)
7380 {
7381 int error, level = 0;
7382
7383 if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0,
7384 seg, 1, nseg, BUS_DMA_WAITOK)) != 0) {
7385 printf("%s: failed to allocate DMA mem for %s, error = %d\n",
7386 myname, what, error);
7387 goto out;
7388 }
7389 level++;
7390
7391 if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr,
7392 BUS_DMA_WAITOK|BUS_DMA_COHERENT)) != 0) {
7393 printf("%s: failed to map DMA mem for %s, error = %d\n",
7394 myname, what, error);
7395 goto out;
7396 }
7397 level++;
7398
7399 if ((error = bus_dmamap_create(tag, size, 1, size, 0,
7400 BUS_DMA_WAITOK | flags, mapp)) != 0) {
7401 printf("%s: failed to create DMA map for %s, error = %d\n",
7402 myname, what, error);
7403 goto out;
7404 }
7405 level++;
7406
7407
7408 if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL,
7409 BUS_DMA_WAITOK)) != 0) {
7410 printf("%s: failed to load DMA map for %s, error = %d\n",
7411 myname, what, error);
7412 goto out;
7413 }
7414
7415 *baddr = (*mapp)->dm_segs[0].ds_addr;
7416
7417 return 0;
7418 out:
7419 printf("ahc_createdmamem error (%d)\n", level);
7420 switch (level) {
7421 case 3:
7422 bus_dmamap_destroy(tag, *mapp);
7423 /* FALLTHROUGH */
7424 case 2:
7425 bus_dmamem_unmap(tag, *vaddr, size);
7426 /* FALLTHROUGH */
7427 case 1:
7428 bus_dmamem_free(tag, seg, *nseg);
7429 break;
7430 default:
7431 break;
7432 }
7433
7434 return -1;
7435 }
7436
7437 static void
ahc_freedmamem(bus_dma_tag_t tag,int size,bus_dmamap_t map,void * vaddr,bus_dma_segment_t * seg,int nseg)7438 ahc_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, void *vaddr,
7439 bus_dma_segment_t *seg, int nseg)
7440 {
7441
7442 bus_dmamap_unload(tag, map);
7443 bus_dmamap_destroy(tag, map);
7444 bus_dmamem_unmap(tag, vaddr, size);
7445 bus_dmamem_free(tag, seg, nseg);
7446 }
7447