1 /*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD$
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23
24 #include "ar5210/ar5210.h"
25 #include "ar5210/ar5210reg.h"
26 #include "ar5210/ar5210phy.h"
27
28 #include "ah_eeprom_v1.h"
29
30 typedef struct {
31 uint32_t Offset;
32 uint32_t Value;
33 } REGISTER_VAL;
34
35 static const REGISTER_VAL ar5k0007_init[] = {
36 #include "ar5210/ar5k_0007.ini"
37 };
38
39 /* Default Power Settings for channels outside of EEPROM range */
40 static const uint8_t ar5k0007_pwrSettings[17] = {
41 /* gain delta pc dac */
42 /* 54 48 36 24 18 12 9 54 48 36 24 18 12 9 6 ob db */
43 9, 9, 0, 0, 0, 0, 0, 2, 2, 6, 6, 6, 6, 6, 6, 2, 2
44 };
45
46 /*
47 * The delay, in usecs, between writing AR_RC with a reset
48 * request and waiting for the chip to settle. If this is
49 * too short then the chip does not come out of sleep state.
50 * Note this value was empirically derived and may be dependent
51 * on the host machine (don't know--the problem was identified
52 * on an IBM 570e laptop; 10us delays worked on other systems).
53 */
54 #define AR_RC_SETTLE_TIME 20000
55
56 static HAL_BOOL ar5210SetResetReg(struct ath_hal *,
57 uint32_t resetMask, u_int delay);
58 static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *);
59 static void ar5210SetOperatingMode(struct ath_hal *, int opmode);
60
61 /*
62 * Places the device in and out of reset and then places sane
63 * values in the registers based on EEPROM config, initialization
64 * vectors (as determined by the mode), and station configuration
65 *
66 * bChannelChange is used to preserve DMA/PCU registers across
67 * a HW Reset during channel change.
68 */
69 HAL_BOOL
ar5210Reset(struct ath_hal * ah,HAL_OPMODE opmode,struct ieee80211_channel * chan,HAL_BOOL bChannelChange,HAL_RESET_TYPE resetType,HAL_STATUS * status)70 ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
71 struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
72 HAL_RESET_TYPE resetType,
73 HAL_STATUS *status)
74 {
75 #define N(a) (sizeof (a) /sizeof (a[0]))
76 #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
77 struct ath_hal_5210 *ahp = AH5210(ah);
78 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
79 HAL_CHANNEL_INTERNAL *ichan;
80 HAL_STATUS ecode;
81 uint32_t ledstate;
82 int i, q;
83
84 HALDEBUG(ah, HAL_DEBUG_RESET,
85 "%s: opmode %u channel %u/0x%x %s channel\n", __func__,
86 opmode, chan->ic_freq, chan->ic_flags,
87 bChannelChange ? "change" : "same");
88
89 if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
90 /* Only 11a mode */
91 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);
92 FAIL(HAL_EINVAL);
93 }
94 /*
95 * Map public channel to private.
96 */
97 ichan = ath_hal_checkchannel(ah, chan);
98 if (ichan == AH_NULL) {
99 HALDEBUG(ah, HAL_DEBUG_ANY,
100 "%s: invalid channel %u/0x%x; no mapping\n",
101 __func__, chan->ic_freq, chan->ic_flags);
102 FAIL(HAL_EINVAL);
103 }
104 switch (opmode) {
105 case HAL_M_STA:
106 case HAL_M_IBSS:
107 case HAL_M_HOSTAP:
108 case HAL_M_MONITOR:
109 break;
110 default:
111 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
112 __func__, opmode);
113 FAIL(HAL_EINVAL);
114 break;
115 }
116
117 ledstate = OS_REG_READ(ah, AR_PCICFG) &
118 (AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
119
120 if (!ar5210ChipReset(ah, chan)) {
121 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
122 __func__);
123 FAIL(HAL_EIO);
124 }
125
126 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
127 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));
128 ar5210SetOperatingMode(ah, opmode);
129
130 switch (opmode) {
131 case HAL_M_HOSTAP:
132 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
133 OS_REG_WRITE(ah, AR_PCICFG,
134 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
135 break;
136 case HAL_M_IBSS:
137 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD);
138 OS_REG_WRITE(ah, AR_PCICFG,
139 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
140 break;
141 case HAL_M_STA:
142 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
143 OS_REG_WRITE(ah, AR_PCICFG,
144 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
145 break;
146 case HAL_M_MONITOR:
147 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
148 OS_REG_WRITE(ah, AR_PCICFG,
149 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
150 break;
151 }
152
153 /* Restore previous led state */
154 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
155
156 #if 0
157 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
158 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
159 #endif
160 /* BSSID, association id, ps-poll */
161 ar5210WriteAssocid(ah, ahp->ah_bssid, ahp->ah_associd);
162
163 OS_REG_WRITE(ah, AR_TXDP0, 0);
164 OS_REG_WRITE(ah, AR_TXDP1, 0);
165 OS_REG_WRITE(ah, AR_RXDP, 0);
166
167 /*
168 * Initialize interrupt state.
169 */
170 (void) OS_REG_READ(ah, AR_ISR); /* cleared on read */
171 OS_REG_WRITE(ah, AR_IMR, 0);
172 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
173 ahp->ah_maskReg = 0;
174
175 (void) OS_REG_READ(ah, AR_BSR); /* cleared on read */
176 OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B);
177 OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B);
178
179 OS_REG_WRITE(ah, AR_TOPS, 8); /* timeout prescale */
180 OS_REG_WRITE(ah, AR_RXNOFRM, 8); /* RX no frame timeout */
181 OS_REG_WRITE(ah, AR_RPGTO, 0); /* RX frame gap timeout */
182 OS_REG_WRITE(ah, AR_TXNOFRM, 0); /* TX no frame timeout */
183
184 OS_REG_WRITE(ah, AR_SFR, 0);
185 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */
186 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
187 OS_REG_WRITE(ah, AR_CFP_DUR, 0);
188
189 ar5210SetRxFilter(ah, 0); /* nothing for now */
190 OS_REG_WRITE(ah, AR_MCAST_FIL0, 0); /* multicast filter */
191 OS_REG_WRITE(ah, AR_MCAST_FIL1, 0); /* XXX was 2 */
192
193 OS_REG_WRITE(ah, AR_TX_MASK0, 0);
194 OS_REG_WRITE(ah, AR_TX_MASK1, 0);
195 OS_REG_WRITE(ah, AR_CLR_TMASK, 1);
196 OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */
197
198 ar5210UpdateDiagReg(ah, 0);
199
200 OS_REG_WRITE(ah, AR_CFP_PERIOD, 0);
201 OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */
202 OS_REG_WRITE(ah, AR_TSF_L32, 0); /* local clock */
203 OS_REG_WRITE(ah, AR_TIMER1, ~0); /* next DMA beacon alert */
204 OS_REG_WRITE(ah, AR_TIMER2, ~0); /* next SW beacon alert */
205 OS_REG_WRITE(ah, AR_TIMER3, 1); /* next ATIM window */
206
207 /* Write the INI values for PHYreg initialization */
208 for (i = 0; i < N(ar5k0007_init); i++) {
209 uint32_t reg = ar5k0007_init[i].Offset;
210 /* On channel change, don't reset the PCU registers */
211 if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
212 OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);
213 }
214
215 /* Setup the transmit power values for cards since 0x0[0-2]05 */
216 if (!ar5210SetTransmitPower(ah, chan)) {
217 HALDEBUG(ah, HAL_DEBUG_ANY,
218 "%s: error init'ing transmit power\n", __func__);
219 FAIL(HAL_EIO);
220 }
221
222 OS_REG_WRITE(ah, AR_PHY(10),
223 (OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) |
224 (ee->ee_xlnaOn << 8));
225 OS_REG_WRITE(ah, AR_PHY(13),
226 (ee->ee_xpaOff << 24) | (ee->ee_xpaOff << 16) |
227 (ee->ee_xpaOn << 8) | ee->ee_xpaOn);
228 OS_REG_WRITE(ah, AR_PHY(17),
229 (OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) |
230 ((ee->ee_antenna >> 1) & 0x3F80));
231 OS_REG_WRITE(ah, AR_PHY(18),
232 (OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) |
233 ((ee->ee_antenna << 10) & 0x3F000));
234 OS_REG_WRITE(ah, AR_PHY(25),
235 (OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) |
236 ((ee->ee_thresh62 << 12) & 0x7F000));
237 OS_REG_WRITE(ah, AR_PHY(68),
238 (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) |
239 (ee->ee_antenna & 0x3));
240
241 if (!ar5210SetChannel(ah, chan)) {
242 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
243 __func__);
244 FAIL(HAL_EIO);
245 }
246 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
247 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
248
249 /* Activate the PHY */
250 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE);
251
252 OS_DELAY(1000); /* Wait a bit (1 msec) */
253
254 /* calibrate the HW and poll the bit going to 0 for completion */
255 OS_REG_WRITE(ah, AR_PHY_AGCCTL,
256 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
257 (void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0);
258
259 /* Perform noise floor calibration and set status */
260 if (!ar5210CalNoiseFloor(ah, ichan)) {
261 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
262 HALDEBUG(ah, HAL_DEBUG_ANY,
263 "%s: noise floor calibration failed\n", __func__);
264 FAIL(HAL_EIO);
265 }
266
267 for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
268 ar5210ResetTxQueue(ah, q);
269
270 if (AH_PRIVATE(ah)->ah_rfkillEnabled)
271 ar5210EnableRfKill(ah);
272
273 /*
274 * Writing to AR_BEACON will start timers. Hence it should be
275 * the last register to be written. Do not reset tsf, do not
276 * enable beacons at this point, but preserve other values
277 * like beaconInterval.
278 */
279 OS_REG_WRITE(ah, AR_BEACON,
280 (OS_REG_READ(ah, AR_BEACON) &
281 ~(AR_BEACON_EN | AR_BEACON_RESET_TSF)));
282
283 /* Restore user-specified slot time and timeouts */
284 if (ahp->ah_sifstime != (u_int) -1)
285 ar5210SetSifsTime(ah, ahp->ah_sifstime);
286 if (ahp->ah_slottime != (u_int) -1)
287 ar5210SetSlotTime(ah, ahp->ah_slottime);
288 if (ahp->ah_acktimeout != (u_int) -1)
289 ar5210SetAckTimeout(ah, ahp->ah_acktimeout);
290 if (ahp->ah_ctstimeout != (u_int) -1)
291 ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout);
292 if (AH_PRIVATE(ah)->ah_diagreg != 0)
293 ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);
294
295 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
296
297 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
298
299 return AH_TRUE;
300 bad:
301 if (status != AH_NULL)
302 *status = ecode;
303 return AH_FALSE;
304 #undef FAIL
305 #undef N
306 }
307
308 static void
ar5210SetOperatingMode(struct ath_hal * ah,int opmode)309 ar5210SetOperatingMode(struct ath_hal *ah, int opmode)
310 {
311 struct ath_hal_5210 *ahp = AH5210(ah);
312 uint32_t val;
313
314 val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
315 switch (opmode) {
316 case HAL_M_HOSTAP:
317 OS_REG_WRITE(ah, AR_STA_ID1, val
318 | AR_STA_ID1_AP
319 | AR_STA_ID1_NO_PSPOLL
320 | AR_STA_ID1_DESC_ANTENNA
321 | ahp->ah_staId1Defaults);
322 break;
323 case HAL_M_IBSS:
324 OS_REG_WRITE(ah, AR_STA_ID1, val
325 | AR_STA_ID1_ADHOC
326 | AR_STA_ID1_NO_PSPOLL
327 | AR_STA_ID1_DESC_ANTENNA
328 | ahp->ah_staId1Defaults);
329 break;
330 case HAL_M_STA:
331 OS_REG_WRITE(ah, AR_STA_ID1, val
332 | AR_STA_ID1_NO_PSPOLL
333 | AR_STA_ID1_PWR_SV
334 | ahp->ah_staId1Defaults);
335 break;
336 case HAL_M_MONITOR:
337 OS_REG_WRITE(ah, AR_STA_ID1, val
338 | AR_STA_ID1_NO_PSPOLL
339 | ahp->ah_staId1Defaults);
340 break;
341 }
342 }
343
344 void
ar5210SetPCUConfig(struct ath_hal * ah)345 ar5210SetPCUConfig(struct ath_hal *ah)
346 {
347 ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
348 }
349
350 /*
351 * Places the PHY and Radio chips into reset. A full reset
352 * must be called to leave this state. The PCI/MAC/PCU are
353 * not placed into reset as we must receive interrupt to
354 * re-enable the hardware.
355 */
356 HAL_BOOL
ar5210PhyDisable(struct ath_hal * ah)357 ar5210PhyDisable(struct ath_hal *ah)
358 {
359 return ar5210SetResetReg(ah, AR_RC_RPHY, 10);
360 }
361
362 /*
363 * Places all of hardware into reset
364 */
365 HAL_BOOL
ar5210Disable(struct ath_hal * ah)366 ar5210Disable(struct ath_hal *ah)
367 {
368 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
369 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
370 return AH_FALSE;
371
372 /*
373 * Reset the HW - PCI must be reset after the rest of the
374 * device has been reset
375 */
376 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
377 return AH_FALSE;
378 OS_DELAY(1000);
379 (void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME);
380 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
381
382 return AH_TRUE;
383 #undef AR_RC_HW
384 }
385
386 /*
387 * Places the hardware into reset and then pulls it out of reset
388 */
389 HAL_BOOL
ar5210ChipReset(struct ath_hal * ah,struct ieee80211_channel * chan)390 ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan)
391 {
392 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
393
394 HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__,
395 chan && IEEE80211_IS_CHAN_TURBO(chan) ?
396 "enabled" : "disabled");
397
398 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
399 return AH_FALSE;
400
401 /* Place chip in turbo before reset to cleanly reset clocks */
402 OS_REG_WRITE(ah, AR_PHY_FRCTL,
403 chan && IEEE80211_IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0);
404
405 /*
406 * Reset the HW.
407 * PCI must be reset after the rest of the device has been reset.
408 */
409 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
410 return AH_FALSE;
411 OS_DELAY(1000);
412 if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME))
413 return AH_FALSE;
414 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
415
416 /*
417 * Bring out of sleep mode (AGAIN)
418 *
419 * WARNING WARNING WARNING
420 *
421 * There is a problem with the chip where it doesn't always indicate
422 * that it's awake, so initializePowerUp() will fail.
423 */
424 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
425 return AH_FALSE;
426
427 /* Clear warm reset reg */
428 return ar5210SetResetReg(ah, 0, 10);
429 #undef AR_RC_HW
430 }
431
432 enum {
433 FIRPWR_M = 0x03fc0000,
434 FIRPWR_S = 18,
435 KCOARSEHIGH_M = 0x003f8000,
436 KCOARSEHIGH_S = 15,
437 KCOARSELOW_M = 0x00007f80,
438 KCOARSELOW_S = 7,
439 ADCSAT_ICOUNT_M = 0x0001f800,
440 ADCSAT_ICOUNT_S = 11,
441 ADCSAT_THRESH_M = 0x000007e0,
442 ADCSAT_THRESH_S = 5
443 };
444
445 /*
446 * Recalibrate the lower PHY chips to account for temperature/environment
447 * changes.
448 */
449 HAL_BOOL
ar5210PerCalibrationN(struct ath_hal * ah,struct ieee80211_channel * chan,u_int chainMask,HAL_BOOL longCal,HAL_BOOL * isCalDone)450 ar5210PerCalibrationN(struct ath_hal *ah,
451 struct ieee80211_channel *chan, u_int chainMask,
452 HAL_BOOL longCal, HAL_BOOL *isCalDone)
453 {
454 uint32_t regBeacon;
455 uint32_t reg9858, reg985c, reg9868;
456 HAL_CHANNEL_INTERNAL *ichan;
457
458 ichan = ath_hal_checkchannel(ah, chan);
459 if (ichan == AH_NULL)
460 return AH_FALSE;
461 /* Disable tx and rx */
462 ar5210UpdateDiagReg(ah,
463 OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
464
465 /* Disable Beacon Enable */
466 regBeacon = OS_REG_READ(ah, AR_BEACON);
467 OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);
468
469 /* Delay 4ms to ensure that all tx and rx activity has ceased */
470 OS_DELAY(4000);
471
472 /* Disable AGC to radio traffic */
473 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
474 /* Wait for the AGC traffic to cease. */
475 OS_DELAY(10);
476
477 /* Change Channel to relock synth */
478 if (!ar5210SetChannel(ah, chan))
479 return AH_FALSE;
480
481 /* wait for the synthesizer lock to stabilize */
482 OS_DELAY(1000);
483
484 /* Re-enable AGC to radio traffic */
485 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
486
487 /*
488 * Configure the AGC so that it is highly unlikely (if not
489 * impossible) for it to send any gain changes to the analog
490 * chip. We store off the current values so that they can
491 * be rewritten below. Setting the following values:
492 * firpwr = -1
493 * Kcoursehigh = -1
494 * Kcourselow = -127
495 * ADCsat_icount = 2
496 * ADCsat_thresh = 12
497 */
498 reg9858 = OS_REG_READ(ah, 0x9858);
499 reg985c = OS_REG_READ(ah, 0x985c);
500 reg9868 = OS_REG_READ(ah, 0x9868);
501
502 OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) |
503 ((-1 << FIRPWR_S) & FIRPWR_M));
504 OS_REG_WRITE(ah, 0x985c,
505 (reg985c & ~(KCOARSEHIGH_M | KCOARSELOW_M)) |
506 ((-1 << KCOARSEHIGH_S) & KCOARSEHIGH_M) |
507 ((-127 << KCOARSELOW_S) & KCOARSELOW_M));
508 OS_REG_WRITE(ah, 0x9868,
509 (reg9868 & ~(ADCSAT_ICOUNT_M | ADCSAT_THRESH_M)) |
510 ((2 << ADCSAT_ICOUNT_S) & ADCSAT_ICOUNT_M) |
511 ((12 << ADCSAT_THRESH_S) & ADCSAT_THRESH_M));
512
513 /* Wait for AGC changes to be enacted */
514 OS_DELAY(20);
515
516 /*
517 * We disable RF mix/gain stages for the PGA to avoid a
518 * race condition that will occur with receiving a frame
519 * and performing the AGC calibration. This will be
520 * re-enabled at the end of offset cal. We turn off AGC
521 * writes during this write as it will go over the analog bus.
522 */
523 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
524 OS_DELAY(10); /* wait for the AGC traffic to cease */
525 OS_REG_WRITE(ah, 0x98D4, 0x21);
526 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
527
528 /* wait to make sure that additional AGC traffic has quiesced */
529 OS_DELAY(1000);
530
531 /* AGC calibration (this was added to make the NF threshold check work) */
532 OS_REG_WRITE(ah, AR_PHY_AGCCTL,
533 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
534 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) {
535 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n",
536 __func__);
537 }
538
539 /* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */
540 OS_REG_WRITE(ah, 0x9858, reg9858);
541 OS_REG_WRITE(ah, 0x985c, reg985c);
542 OS_REG_WRITE(ah, 0x9868, reg9868);
543
544 /* Perform noise floor and set status */
545 if (!ar5210CalNoiseFloor(ah, ichan)) {
546 /*
547 * Delay 5ms before retrying the noise floor -
548 * just to make sure. We're in an error
549 * condition here
550 */
551 HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL,
552 "%s: Performing 2nd Noise Cal\n", __func__);
553 OS_DELAY(5000);
554 if (!ar5210CalNoiseFloor(ah, ichan))
555 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
556 }
557
558 /* Clear tx and rx disable bit */
559 ar5210UpdateDiagReg(ah,
560 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
561
562 /* Re-enable Beacons */
563 OS_REG_WRITE(ah, AR_BEACON, regBeacon);
564
565 *isCalDone = AH_TRUE;
566
567 return AH_TRUE;
568 }
569
570 HAL_BOOL
ar5210PerCalibration(struct ath_hal * ah,struct ieee80211_channel * chan,HAL_BOOL * isIQdone)571 ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
572 HAL_BOOL *isIQdone)
573 {
574 return ar5210PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
575 }
576
577 HAL_BOOL
ar5210ResetCalValid(struct ath_hal * ah,const struct ieee80211_channel * chan)578 ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
579 {
580 return AH_TRUE;
581 }
582
583 /*
584 * Writes the given reset bit mask into the reset register
585 */
586 static HAL_BOOL
ar5210SetResetReg(struct ath_hal * ah,uint32_t resetMask,u_int delay)587 ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
588 {
589 uint32_t mask = resetMask ? resetMask : ~0;
590 HAL_BOOL rt;
591
592 OS_REG_WRITE(ah, AR_RC, resetMask);
593 /* need to wait at least 128 clocks when reseting PCI before read */
594 OS_DELAY(delay);
595
596 resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
597 mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
598 rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
599 if ((resetMask & AR_RC_RMAC) == 0) {
600 if (isBigEndian()) {
601 /*
602 * Set CFG, little-endian for descriptor accesses.
603 */
604 mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD;
605 OS_REG_WRITE(ah, AR_CFG, mask);
606 } else
607 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
608 }
609 return rt;
610 }
611
612
613 /*
614 * Returns: the pcdac value
615 */
616 static uint8_t
getPcdac(struct ath_hal * ah,const struct tpcMap * pRD,uint8_t dBm)617 getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm)
618 {
619 int32_t i;
620 int useNextEntry = AH_FALSE;
621 uint32_t interp;
622
623 for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) {
624 /* Check for exact entry */
625 if (dBm == AR_I2DBM(i)) {
626 if (pRD->pcdac[i] != 63)
627 return pRD->pcdac[i];
628 useNextEntry = AH_TRUE;
629 } else if (dBm + 1 == AR_I2DBM(i) && i > 0) {
630 /* Interpolate for between entry with a logish scale */
631 if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) {
632 interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999;
633 interp = (interp / 1000) + pRD->pcdac[i-1];
634 return interp;
635 }
636 useNextEntry = AH_TRUE;
637 } else if (useNextEntry == AH_TRUE) {
638 /* Grab the next lowest */
639 if (pRD->pcdac[i] != 63)
640 return pRD->pcdac[i];
641 }
642 }
643
644 /* Return the lowest Entry if we haven't returned */
645 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++)
646 if (pRD->pcdac[i] != 63)
647 return pRD->pcdac[i];
648
649 /* No value to return from table */
650 #ifdef AH_DEBUG
651 ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__);
652 #endif
653 return 1;
654 }
655
656 /*
657 * Find or interpolates the gainF value from the table ptr.
658 */
659 static uint8_t
getGainF(struct ath_hal * ah,const struct tpcMap * pRD,uint8_t pcdac,uint8_t * dBm)660 getGainF(struct ath_hal *ah, const struct tpcMap *pRD,
661 uint8_t pcdac, uint8_t *dBm)
662 {
663 uint32_t interp;
664 int low, high, i;
665
666 low = high = -1;
667
668 *dBm = 0; /* avoid gcc warnings */
669 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) {
670 if(pRD->pcdac[i] == 63)
671 continue;
672 if (pcdac == pRD->pcdac[i]) {
673 *dBm = AR_I2DBM(i);
674 return pRD->gainF[i]; /* Exact Match */
675 }
676 if (pcdac > pRD->pcdac[i])
677 low = i;
678 if (pcdac < pRD->pcdac[i]) {
679 high = i;
680 if (low == -1) {
681 *dBm = AR_I2DBM(i);
682 /* PCDAC is lower than lowest setting */
683 return pRD->gainF[i];
684 }
685 break;
686 }
687 }
688 if (i >= AR_TP_SCALING_ENTRIES && low == -1) {
689 /* No settings were found */
690 #ifdef AH_DEBUG
691 ath_hal_printf(ah,
692 "%s: no valid entries in the pcdac table: %d\n",
693 __func__, pcdac);
694 #endif
695 return 63;
696 }
697 if (i >= AR_TP_SCALING_ENTRIES) {
698 /* PCDAC setting was above the max setting in the table */
699 *dBm = AR_I2DBM(low);
700 return pRD->gainF[low];
701 }
702 /* Only exact if table has no missing entries */
703 *dBm = (low + high) + 3;
704
705 /*
706 * Perform interpolation between low and high values to find gainF
707 * linearly scale the pcdac between low and high
708 */
709 interp = ((pcdac - pRD->pcdac[low]) * 1000) /
710 (pRD->pcdac[high] - pRD->pcdac[low]);
711 /*
712 * Multiply the scale ratio by the gainF difference
713 * (plus a rnd up factor)
714 */
715 interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000;
716
717 /* Add ratioed gain_f to low gain_f value */
718 return interp + pRD->gainF[low];
719 }
720
721 HAL_BOOL
ar5210SetTxPowerLimit(struct ath_hal * ah,uint32_t limit)722 ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
723 {
724 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER);
725 /* XXX flush to h/w */
726 return AH_TRUE;
727 }
728
729 /*
730 * Get TXPower values and set them in the radio
731 */
732 static HAL_BOOL
setupPowerSettings(struct ath_hal * ah,const struct ieee80211_channel * chan,uint8_t cp[17])733 setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan,
734 uint8_t cp[17])
735 {
736 uint16_t freq = ath_hal_gethwchannel(ah, chan);
737 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
738 uint8_t gainFRD, gainF36, gainF48, gainF54;
739 uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
740 uint32_t rd, group;
741 const struct tpcMap *pRD;
742
743 /* Set OB/DB Values regardless of channel */
744 cp[15] = (ee->ee_biasCurrents >> 4) & 0x7;
745 cp[16] = ee->ee_biasCurrents & 0x7;
746
747 if (freq < 5170 || freq > 5320) {
748 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n",
749 __func__, freq);
750 return AH_FALSE;
751 }
752
753 HALASSERT(ee->ee_version >= AR_EEPROM_VER1 &&
754 ee->ee_version < AR_EEPROM_VER3);
755
756 /* Match regulatory domain */
757 for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++)
758 if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd])
759 break;
760 if (rd == AR_REG_DOMAINS_MAX) {
761 #ifdef AH_DEBUG
762 ath_hal_printf(ah,
763 "%s: no calibrated regulatory domain matches the "
764 "current regularly domain (0x%0x)\n", __func__,
765 AH_PRIVATE(ah)->ah_currentRD);
766 #endif
767 return AH_FALSE;
768 }
769 group = ((freq - 5170) / 10);
770
771 if (group > 11) {
772 /* Pull 5.29 into the 5.27 group */
773 group--;
774 }
775
776 /* Integer divide will set group from 0 to 4 */
777 group = group / 3;
778 pRD = &ee->ee_tpc[group];
779
780 /* Set PC DAC Values */
781 cp[14] = pRD->regdmn[rd];
782 cp[9] = AH_MIN(pRD->regdmn[rd], pRD->rate36);
783 cp[8] = AH_MIN(pRD->regdmn[rd], pRD->rate48);
784 cp[7] = AH_MIN(pRD->regdmn[rd], pRD->rate54);
785
786 /* Find Corresponding gainF values for RD, 36, 48, 54 */
787 gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD);
788 gainF36 = getGainF(ah, pRD, cp[9], &dBm36);
789 gainF48 = getGainF(ah, pRD, cp[8], &dBm48);
790 gainF54 = getGainF(ah, pRD, cp[7], &dBm54);
791
792 /* Power Scale if requested */
793 if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {
794 static const uint16_t tpcScaleReductionTable[5] =
795 { 0, 3, 6, 9, AR5210_MAX_RATE_POWER };
796 uint16_t tpScale;
797
798 tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
799 if (dBmRD < tpScale+3)
800 dBmRD = 3; /* min */
801 else
802 dBmRD -= tpScale;
803 cp[14] = getPcdac(ah, pRD, dBmRD);
804 gainFRD = getGainF(ah, pRD, cp[14], &dontcare);
805 dBm36 = AH_MIN(dBm36, dBmRD);
806 cp[9] = getPcdac(ah, pRD, dBm36);
807 gainF36 = getGainF(ah, pRD, cp[9], &dontcare);
808 dBm48 = AH_MIN(dBm48, dBmRD);
809 cp[8] = getPcdac(ah, pRD, dBm48);
810 gainF48 = getGainF(ah, pRD, cp[8], &dontcare);
811 dBm54 = AH_MIN(dBm54, dBmRD);
812 cp[7] = getPcdac(ah, pRD, dBm54);
813 gainF54 = getGainF(ah, pRD, cp[7], &dontcare);
814 }
815 /* Record current dBm at rate 6 */
816 AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD;
817
818 cp[13] = cp[12] = cp[11] = cp[10] = cp[14];
819
820 /* Set GainF Values */
821 cp[0] = gainFRD - gainF54;
822 cp[1] = gainFRD - gainF48;
823 cp[2] = gainFRD - gainF36;
824 /* 9, 12, 18, 24 have no gain_delta from 6 */
825 cp[3] = cp[4] = cp[5] = cp[6] = 0;
826 return AH_TRUE;
827 }
828
829 /*
830 * Places the device in and out of reset and then places sane
831 * values in the registers based on EEPROM config, initialization
832 * vectors (as determined by the mode), and station configuration
833 */
834 HAL_BOOL
ar5210SetTransmitPower(struct ath_hal * ah,const struct ieee80211_channel * chan)835 ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
836 {
837 #define N(a) (sizeof (a) / sizeof (a[0]))
838 static const uint32_t pwr_regs_start[17] = {
839 0x00000000, 0x00000000, 0x00000000,
840 0x00000000, 0x00000000, 0xf0000000,
841 0xcc000000, 0x00000000, 0x00000000,
842 0x00000000, 0x0a000000, 0x000000e2,
843 0x0a000020, 0x01000002, 0x01000018,
844 0x40000000, 0x00000418
845 };
846 uint16_t i;
847 uint8_t cp[sizeof(ar5k0007_pwrSettings)];
848 uint32_t pwr_regs[17];
849
850 OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs));
851 OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp));
852
853 /* Check the EEPROM tx power calibration settings */
854 if (!setupPowerSettings(ah, chan, cp)) {
855 #ifdef AH_DEBUG
856 ath_hal_printf(ah, "%s: unable to setup power settings\n",
857 __func__);
858 #endif
859 return AH_FALSE;
860 }
861 if (cp[15] < 1 || cp[15] > 5) {
862 #ifdef AH_DEBUG
863 ath_hal_printf(ah, "%s: OB out of range (%u)\n",
864 __func__, cp[15]);
865 #endif
866 return AH_FALSE;
867 }
868 if (cp[16] < 1 || cp[16] > 5) {
869 #ifdef AH_DEBUG
870 ath_hal_printf(ah, "%s: DB out of range (%u)\n",
871 __func__, cp[16]);
872 #endif
873 return AH_FALSE;
874 }
875
876 /* reverse bits of the transmit power array */
877 for (i = 0; i < 7; i++)
878 cp[i] = ath_hal_reverseBits(cp[i], 5);
879 for (i = 7; i < 15; i++)
880 cp[i] = ath_hal_reverseBits(cp[i], 6);
881
882 /* merge transmit power values into the register - quite gross */
883 pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F);
884 pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) |
885 ((cp[1] >> 3) & 0x03);
886 pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F);
887 pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) |
888 ((cp[4] >> 4) & 0x01);
889 pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07);
890 pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) |
891 ((cp[7] >> 5) & 0x01);
892 pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F);
893 pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07);
894 pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01);
895 pwr_regs[9] |= ((cp[13] << 5) & 0xE0);
896 pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07);
897 pwr_regs[11] |= ((cp[14] >> 5) & 0x01);
898
899 /* Set OB */
900 pwr_regs[8] |= (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80;
901 pwr_regs[9] |= (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03;
902
903 /* Set DB */
904 pwr_regs[9] |= (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C;
905
906 /* Write the registers */
907 for (i = 0; i < N(pwr_regs)-1; i++)
908 OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]);
909 /* last write is a flush */
910 OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]);
911
912 return AH_TRUE;
913 #undef N
914 }
915
916 /*
917 * Takes the MHz channel value and sets the Channel value
918 *
919 * ASSUMES: Writes enabled to analog bus before AGC is active
920 * or by disabling the AGC.
921 */
922 static HAL_BOOL
ar5210SetChannel(struct ath_hal * ah,struct ieee80211_channel * chan)923 ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)
924 {
925 uint16_t freq = ath_hal_gethwchannel(ah, chan);
926 uint32_t data;
927
928 /* Set the Channel */
929 data = ath_hal_reverseBits((freq - 5120)/10, 5);
930 data = (data << 1) | 0x41;
931 OS_REG_WRITE(ah, AR_PHY(0x27), data);
932 OS_REG_WRITE(ah, AR_PHY(0x30), 0);
933 AH_PRIVATE(ah)->ah_curchan = chan;
934 return AH_TRUE;
935 }
936
937 int16_t
ar5210GetNoiseFloor(struct ath_hal * ah)938 ar5210GetNoiseFloor(struct ath_hal *ah)
939 {
940 int16_t nf;
941
942 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
943 if (nf & 0x100)
944 nf = 0 - ((nf ^ 0x1ff) + 1);
945 return nf;
946 }
947
948 #define NORMAL_NF_THRESH (-72)
949 /*
950 * Peform the noisefloor calibration and check for
951 * any constant channel interference
952 *
953 * Returns: TRUE for a successful noise floor calibration; else FALSE
954 */
955 HAL_BOOL
ar5210CalNoiseFloor(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * ichan)956 ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
957 {
958 int32_t nf, nfLoops;
959
960 /* Calibrate the noise floor */
961 OS_REG_WRITE(ah, AR_PHY_AGCCTL,
962 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF);
963
964 /* Do not read noise floor until it has done the first update */
965 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) {
966 #ifdef ATH_HAL_DEBUG
967 ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n",
968 OS_REG_READ(ah, AR_PHY_AGCCTL));
969 ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n",
970 OS_REG_READ(ah, AR_RC));
971 ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n",
972 OS_REG_READ(ah, AR_PHY_ACTIVE));
973 #endif /* ATH_HAL_DEBUG */
974 return AH_FALSE;
975 }
976
977 nf = 0;
978 /* Keep checking until the floor is below the threshold or the nf is done */
979 for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) {
980 OS_DELAY(1000); /* Sleep for 1 ms */
981 nf = ar5210GetNoiseFloor(ah);
982 }
983
984 if (nf > NORMAL_NF_THRESH) {
985 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n",
986 __func__, nf);
987 ichan->rawNoiseFloor = 0;
988 return AH_FALSE;
989 }
990 ichan->rawNoiseFloor = nf;
991 return AH_TRUE;
992 }
993
994 /*
995 * Adjust NF based on statistical values for 5GHz frequencies.
996 */
997 int16_t
ar5210GetNfAdjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)998 ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
999 {
1000 return 0;
1001 }
1002
1003 HAL_RFGAIN
ar5210GetRfgain(struct ath_hal * ah)1004 ar5210GetRfgain(struct ath_hal *ah)
1005 {
1006 return HAL_RFGAIN_INACTIVE;
1007 }
1008