Searched defs:clks (Results 1 – 16 of 16) sorted by relevance
538 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; in fetch_pipe_params() local
112 struct dm_pp_clock_levels *clks) in get_default_clock_levels()
1003 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) in dm_set_dcn_clocks()
697 enum smu_clk_type clks[] = { in renoir_force_dpm_limit_value() enum
794 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params() local
794 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params() local
840 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
908 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params() local
1283 enum smu_clk_type clks[] = { in vangogh_force_dpm_limit_value() enum
329 struct dc_clocks clks; member
769 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold() local
1132 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in iceland_calculate_mclk_params() local
884 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in tonga_calculate_mclk_params() local
1087 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in ci_calculate_mclk_params() local
4866 u32 clks = reference_clock * 5 / ss.rate; in si_populate_mclk_value() local
2798 u32 clks = reference_clock * 5 / ss.rate; in ci_calculate_mclk_params() local