1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 *
29 * Copyright (c) 2011 The FreeBSD Foundation
30 * All rights reserved.
31 *
32 * This software was developed by Konstantin Belousov under sponsorship from
33 * the FreeBSD Foundation.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 * SUCH DAMAGE.
55 */
56 #include <sys/cdefs.h>
57 __FBSDID("$FreeBSD$");
58
59 #include <dev/drm2/drmP.h>
60 #include <dev/drm2/drm.h>
61 #include <dev/drm2/i915/i915_drm.h>
62 #include <dev/drm2/i915/i915_drv.h>
63 #include <dev/drm2/i915/intel_drv.h>
64 #include <dev/iicbus/iic.h>
65 #include <dev/iicbus/iiconf.h>
66 #include <dev/iicbus/iicbus.h>
67 #include "iicbus_if.h"
68 #include "iicbb_if.h"
69
70 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
71
72 struct gmbus_port {
73 const char *name;
74 int reg;
75 };
76
77 static const struct gmbus_port gmbus_ports[] = {
78 { "ssc", GPIOB },
79 { "vga", GPIOA },
80 { "panel", GPIOC },
81 { "dpc", GPIOD },
82 { "dpb", GPIOE },
83 { "dpd", GPIOF },
84 };
85
86 /* Intel GPIO access functions */
87
88 #define I2C_RISEFALL_TIME 10
89
90 struct intel_iic_softc {
91 struct drm_device *drm_dev;
92 device_t iic_dev;
93 bool force_bit_dev;
94 char name[32];
95 uint32_t reg;
96 uint32_t reg0;
97 };
98
99 void
intel_iic_reset(struct drm_device * dev)100 intel_iic_reset(struct drm_device *dev)
101 {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
104 }
105
106 static int
intel_iicbus_reset(device_t idev,u_char speed,u_char addr,u_char * oldaddr)107 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
108 {
109 struct intel_iic_softc *sc;
110 struct drm_device *dev;
111
112 sc = device_get_softc(idev);
113 dev = sc->drm_dev;
114
115 intel_iic_reset(dev);
116 return (0);
117 }
118
intel_i2c_quirk_set(struct drm_i915_private * dev_priv,bool enable)119 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
120 {
121 u32 val;
122
123 /* When using bit bashing for I2C, this bit needs to be set to 1 */
124 if (!IS_PINEVIEW(dev_priv->dev))
125 return;
126
127 val = I915_READ(DSPCLK_GATE_D);
128 if (enable)
129 val |= DPCUNIT_CLOCK_GATE_DISABLE;
130 else
131 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
132 I915_WRITE(DSPCLK_GATE_D, val);
133 }
134
get_reserved(device_t idev)135 static u32 get_reserved(device_t idev)
136 {
137 struct intel_iic_softc *sc = device_get_softc(idev);
138 struct drm_device *dev = sc->drm_dev;
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 u32 reserved = 0;
141
142 if (!IS_I830(dev) && !IS_845G(dev))
143 reserved = I915_READ_NOTRACE(sc->reg) &
144 (GPIO_DATA_PULLUP_DISABLE |
145 GPIO_CLOCK_PULLUP_DISABLE);
146
147 return reserved;
148 }
149
get_clock(device_t adapter)150 static int get_clock(device_t adapter)
151 {
152 struct intel_iic_softc *sc = device_get_softc(adapter);
153 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
154 u32 reserved = get_reserved(adapter);
155 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
156 I915_WRITE_NOTRACE(sc->reg, reserved);
157 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
158 }
159
get_data(device_t adapter)160 static int get_data(device_t adapter)
161 {
162 struct intel_iic_softc *sc = device_get_softc(adapter);
163 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
164 u32 reserved = get_reserved(adapter);
165 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
166 I915_WRITE_NOTRACE(sc->reg, reserved);
167 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
168 }
169
set_clock(device_t adapter,int state_high)170 static void set_clock(device_t adapter, int state_high)
171 {
172 struct intel_iic_softc *sc = device_get_softc(adapter);
173 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
174 u32 reserved = get_reserved(adapter);
175 u32 clock_bits;
176
177 if (state_high)
178 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
179 else
180 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
181 GPIO_CLOCK_VAL_MASK;
182
183 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
184 POSTING_READ(sc->reg);
185 }
186
set_data(device_t adapter,int state_high)187 static void set_data(device_t adapter, int state_high)
188 {
189 struct intel_iic_softc *sc = device_get_softc(adapter);
190 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
191 u32 reserved = get_reserved(adapter);
192 u32 data_bits;
193
194 if (state_high)
195 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
196 else
197 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
198 GPIO_DATA_VAL_MASK;
199
200 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
201 POSTING_READ(sc->reg);
202 }
203
204 static int
intel_gpio_pre_xfer(device_t adapter)205 intel_gpio_pre_xfer(device_t adapter)
206 {
207 struct intel_iic_softc *sc = device_get_softc(adapter);
208 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
209
210 intel_iic_reset(sc->drm_dev);
211 intel_i2c_quirk_set(dev_priv, true);
212 IICBB_SETSDA(adapter, 1);
213 IICBB_SETSCL(adapter, 1);
214 DELAY(I2C_RISEFALL_TIME);
215 return 0;
216 }
217
218 static void
intel_gpio_post_xfer(device_t adapter)219 intel_gpio_post_xfer(device_t adapter)
220 {
221 struct intel_iic_softc *sc = device_get_softc(adapter);
222 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
223
224 IICBB_SETSDA(adapter, 1);
225 IICBB_SETSCL(adapter, 1);
226 intel_i2c_quirk_set(dev_priv, false);
227 }
228
229 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct iic_msg * msg,u32 gmbus1_index)230 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct iic_msg *msg,
231 u32 gmbus1_index)
232 {
233 int reg_offset = dev_priv->gpio_mmio_base;
234 u16 len = msg->len;
235 u8 *buf = msg->buf;
236
237 I915_WRITE(GMBUS1 + reg_offset,
238 gmbus1_index |
239 GMBUS_CYCLE_WAIT |
240 (len << GMBUS_BYTE_COUNT_SHIFT) |
241 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
242 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
243 while (len) {
244 int ret;
245 u32 val, loop = 0;
246 u32 gmbus2;
247
248 ret = _intel_wait_for(sc->drm_dev,
249 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
250 (GMBUS_SATOER | GMBUS_HW_RDY)),
251 50, 1, "915gbr");
252 if (ret)
253 return -ETIMEDOUT;
254 if (gmbus2 & GMBUS_SATOER)
255 return -ENXIO;
256
257 val = I915_READ(GMBUS3 + reg_offset);
258 do {
259 *buf++ = val & 0xff;
260 val >>= 8;
261 } while (--len && ++loop < 4);
262 }
263
264 return 0;
265 }
266
267 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct iic_msg * msg)268 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct iic_msg *msg)
269 {
270 int reg_offset = dev_priv->gpio_mmio_base;
271 u16 len = msg->len;
272 u8 *buf = msg->buf;
273 u32 val, loop;
274
275 val = loop = 0;
276 while (len && loop < 4) {
277 val |= *buf++ << (8 * loop++);
278 len -= 1;
279 }
280
281 I915_WRITE(GMBUS3 + reg_offset, val);
282 I915_WRITE(GMBUS1 + reg_offset,
283 GMBUS_CYCLE_WAIT |
284 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
285 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
286 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
287 while (len) {
288 int ret;
289 u32 gmbus2;
290
291 val = loop = 0;
292 do {
293 val |= *buf++ << (8 * loop);
294 } while (--len && ++loop < 4);
295
296 I915_WRITE(GMBUS3 + reg_offset, val);
297
298 ret = _intel_wait_for(sc->drm_dev,
299 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
300 (GMBUS_SATOER | GMBUS_HW_RDY)),
301 50, 1, "915gbw");
302 if (ret)
303 return -ETIMEDOUT;
304 if (gmbus2 & GMBUS_SATOER)
305 return -ENXIO;
306 }
307 return 0;
308 }
309
310 /*
311 * The gmbus controller can combine a 1 or 2 byte write with a read that
312 * immediately follows it by using an "INDEX" cycle.
313 */
314 static bool
gmbus_is_index_read(struct iic_msg * msgs,int i,int num)315 gmbus_is_index_read(struct iic_msg *msgs, int i, int num)
316 {
317 return (i + 1 < num &&
318 !(msgs[i].flags & IIC_M_RD) && msgs[i].len <= 2 &&
319 (msgs[i + 1].flags & IIC_M_RD));
320 }
321
322 static int
gmbus_xfer_index_read(struct drm_i915_private * dev_priv,struct iic_msg * msgs)323 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct iic_msg *msgs)
324 {
325 int reg_offset = dev_priv->gpio_mmio_base;
326 u32 gmbus1_index = 0;
327 u32 gmbus5 = 0;
328 int ret;
329
330 if (msgs[0].len == 2)
331 gmbus5 = GMBUS_2BYTE_INDEX_EN |
332 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
333 if (msgs[0].len == 1)
334 gmbus1_index = GMBUS_CYCLE_INDEX |
335 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
336
337 /* GMBUS5 holds 16-bit index */
338 if (gmbus5)
339 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
340
341 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
342
343 /* Clear GMBUS5 after each index transfer */
344 if (gmbus5)
345 I915_WRITE(GMBUS5 + reg_offset, 0);
346
347 return ret;
348 }
349
350 static int
gmbus_xfer(device_t adapter,struct iic_msg * msgs,uint32_t num)351 gmbus_xfer(device_t adapter,
352 struct iic_msg *msgs,
353 uint32_t num)
354 {
355 struct intel_iic_softc *sc = device_get_softc(adapter);
356 struct drm_i915_private *dev_priv = sc->drm_dev->dev_private;
357 int error, i, ret, reg_offset, unit;
358
359 error = 0;
360 unit = device_get_unit(adapter);
361
362 sx_xlock(&dev_priv->gmbus_sx);
363 if (sc->force_bit_dev) {
364 error = -IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, num);
365 goto out;
366 }
367
368 reg_offset = dev_priv->gpio_mmio_base;
369
370 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
371
372 for (i = 0; i < num; i++) {
373 u32 gmbus2;
374
375 if (gmbus_is_index_read(msgs, i, num)) {
376 error = gmbus_xfer_index_read(dev_priv, &msgs[i]);
377 i += 1; /* set i to the index of the read xfer */
378 } else if (msgs[i].flags & IIC_M_RD) {
379 error = gmbus_xfer_read(dev_priv, &msgs[i], 0);
380 } else {
381 error = gmbus_xfer_write(dev_priv, &msgs[i]);
382 }
383
384 if (error == -ETIMEDOUT)
385 goto timeout;
386 if (error == -ENXIO)
387 goto clear_err;
388
389 ret = _intel_wait_for(sc->drm_dev,
390 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
391 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE)),
392 50, 1, "915gbh");
393 if (ret)
394 goto timeout;
395 if (gmbus2 & GMBUS_SATOER)
396 goto clear_err;
397 }
398
399 /* Generate a STOP condition on the bus. Note that gmbus can't generata
400 * a STOP on the very first cycle. To simplify the code we
401 * unconditionally generate the STOP condition with an additional gmbus
402 * cycle. */
403 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
404
405 /* Mark the GMBUS interface as disabled after waiting for idle.
406 * We will re-enable it at the start of the next xfer,
407 * till then let it sleep.
408 */
409 if (_intel_wait_for(dev,
410 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
411 10, 1, "915gbu")) {
412 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
413 sc->name);
414 error = -ETIMEDOUT;
415 }
416 I915_WRITE(GMBUS0 + reg_offset, 0);
417 goto out;
418
419 clear_err:
420 /*
421 * Wait for bus to IDLE before clearing NAK.
422 * If we clear the NAK while bus is still active, then it will stay
423 * active and the next transaction may fail.
424 */
425 if (_intel_wait_for(dev,
426 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
427 10, 1, "915gbu"))
428 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", sc->name);
429
430 /* Toggle the Software Clear Interrupt bit. This has the effect
431 * of resetting the GMBUS controller and so clearing the
432 * BUS_ERROR raised by the slave's NAK.
433 */
434 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
435 I915_WRITE(GMBUS1 + reg_offset, 0);
436 I915_WRITE(GMBUS0 + reg_offset, 0);
437
438 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
439 sc->name, msgs[i].slave,
440 (msgs[i].flags & IIC_M_RD) ? 'r' : 'w', msgs[i].len);
441
442 /*
443 * If no ACK is received during the address phase of a transaction,
444 * the adapter must report -ENXIO.
445 * It is not clear what to return if no ACK is received at other times.
446 * So, we always return -ENXIO in all NAK cases, to ensure we send
447 * it at least during the one case that is specified.
448 */
449 error = -ENXIO;
450 goto out;
451
452 timeout:
453 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
454 sc->name, sc->reg0 & 0xff);
455 I915_WRITE(GMBUS0 + reg_offset, 0);
456
457 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
458 sc->force_bit_dev = true;
459 error = -IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, num);
460
461 out:
462 sx_xunlock(&dev_priv->gmbus_sx);
463 return -error;
464 }
465
466 static int
intel_gmbus_probe(device_t dev)467 intel_gmbus_probe(device_t dev)
468 {
469
470 return (BUS_PROBE_SPECIFIC);
471 }
472
473 static int
intel_gmbus_attach(device_t idev)474 intel_gmbus_attach(device_t idev)
475 {
476 struct drm_i915_private *dev_priv;
477 struct intel_iic_softc *sc;
478 int pin, port;
479
480 sc = device_get_softc(idev);
481 sc->drm_dev = device_get_softc(device_get_parent(idev));
482 dev_priv = sc->drm_dev->dev_private;
483 pin = device_get_unit(idev);
484 port = pin + 1;
485
486 snprintf(sc->name, sizeof(sc->name), "gmbus %s",
487 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
488 "reserved");
489 device_set_desc(idev, sc->name);
490
491 /* By default use a conservative clock rate */
492 sc->reg0 = port | GMBUS_RATE_100KHZ;
493
494 /* gmbus seems to be broken on i830 */
495 if (IS_I830(sc->drm_dev))
496 sc->force_bit_dev = true;
497 #if 0
498 if (IS_GEN2(sc->drm_dev)) {
499 sc->force_bit_dev = true;
500 }
501 #endif
502
503 /* add bus interface device */
504 sc->iic_dev = device_add_child(idev, "iicbus", -1);
505 if (sc->iic_dev == NULL)
506 return (ENXIO);
507 device_quiet(sc->iic_dev);
508 bus_generic_attach(idev);
509
510 return (0);
511 }
512
513 static int
intel_gmbus_detach(device_t idev)514 intel_gmbus_detach(device_t idev)
515 {
516 struct intel_iic_softc *sc;
517 struct drm_i915_private *dev_priv;
518 device_t child;
519 int u;
520
521 sc = device_get_softc(idev);
522 u = device_get_unit(idev);
523 dev_priv = sc->drm_dev->dev_private;
524
525 child = sc->iic_dev;
526 bus_generic_detach(idev);
527 if (child != NULL)
528 device_delete_child(idev, child);
529
530 return (0);
531 }
532
533 static int
intel_iicbb_probe(device_t dev)534 intel_iicbb_probe(device_t dev)
535 {
536
537 return (BUS_PROBE_DEFAULT);
538 }
539
540 static int
intel_iicbb_attach(device_t idev)541 intel_iicbb_attach(device_t idev)
542 {
543 struct intel_iic_softc *sc;
544 struct drm_i915_private *dev_priv;
545 int pin, port;
546
547 sc = device_get_softc(idev);
548 sc->drm_dev = device_get_softc(device_get_parent(idev));
549 dev_priv = sc->drm_dev->dev_private;
550 pin = device_get_unit(idev);
551 port = pin + 1;
552
553 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s",
554 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
555 "reserved");
556 device_set_desc(idev, sc->name);
557
558 if (!intel_gmbus_is_port_valid(port))
559 pin = 1 ; /* GPIOA, VGA */
560 sc->reg0 = pin | GMBUS_RATE_100KHZ;
561 sc->reg = dev_priv->gpio_mmio_base + gmbus_ports[pin].reg;
562
563 /* add generic bit-banging code */
564 sc->iic_dev = device_add_child(idev, "iicbb", -1);
565 if (sc->iic_dev == NULL)
566 return (ENXIO);
567 device_quiet(sc->iic_dev);
568 bus_generic_attach(idev);
569 iicbus_set_nostop(idev, true);
570
571 return (0);
572 }
573
574 static int
intel_iicbb_detach(device_t idev)575 intel_iicbb_detach(device_t idev)
576 {
577 struct intel_iic_softc *sc;
578 device_t child;
579
580 sc = device_get_softc(idev);
581 child = sc->iic_dev;
582 bus_generic_detach(idev);
583 if (child)
584 device_delete_child(idev, child);
585 return (0);
586 }
587
588 static device_method_t intel_gmbus_methods[] = {
589 DEVMETHOD(device_probe, intel_gmbus_probe),
590 DEVMETHOD(device_attach, intel_gmbus_attach),
591 DEVMETHOD(device_detach, intel_gmbus_detach),
592 DEVMETHOD(iicbus_reset, intel_iicbus_reset),
593 DEVMETHOD(iicbus_transfer, gmbus_xfer),
594 DEVMETHOD_END
595 };
596 static driver_t intel_gmbus_driver = {
597 "intel_gmbus",
598 intel_gmbus_methods,
599 sizeof(struct intel_iic_softc)
600 };
601 static devclass_t intel_gmbus_devclass;
602 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
603 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
604 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
605
606 static device_method_t intel_iicbb_methods[] = {
607 DEVMETHOD(device_probe, intel_iicbb_probe),
608 DEVMETHOD(device_attach, intel_iicbb_attach),
609 DEVMETHOD(device_detach, intel_iicbb_detach),
610
611 DEVMETHOD(bus_add_child, bus_generic_add_child),
612 DEVMETHOD(bus_print_child, bus_generic_print_child),
613
614 DEVMETHOD(iicbb_callback, iicbus_null_callback),
615 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
616 DEVMETHOD(iicbb_setsda, set_data),
617 DEVMETHOD(iicbb_setscl, set_clock),
618 DEVMETHOD(iicbb_getsda, get_data),
619 DEVMETHOD(iicbb_getscl, get_clock),
620 DEVMETHOD(iicbb_pre_xfer, intel_gpio_pre_xfer),
621 DEVMETHOD(iicbb_post_xfer, intel_gpio_post_xfer),
622 DEVMETHOD_END
623 };
624 static driver_t intel_iicbb_driver = {
625 "intel_iicbb",
626 intel_iicbb_methods,
627 sizeof(struct intel_iic_softc)
628 };
629 static devclass_t intel_iicbb_devclass;
630 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
631 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
632 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
633
intel_setup_gmbus(struct drm_device * dev)634 int intel_setup_gmbus(struct drm_device *dev)
635 {
636 struct drm_i915_private *dev_priv = dev->dev_private;
637 device_t iic_dev;
638 int ret, i;
639
640 if (HAS_PCH_SPLIT(dev))
641 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
642 else
643 dev_priv->gpio_mmio_base = 0;
644
645 sx_init(&dev_priv->gmbus_sx, "gmbus");
646
647 /*
648 * The Giant there is recursed, most likely. Normally, the
649 * intel_setup_gmbus() is called from the attach method of the
650 * driver.
651 */
652 mtx_lock(&Giant);
653 for (i = 0; i <= GMBUS_NUM_PORTS; i++) {
654 /*
655 * Initialized bbbus_bridge before gmbus_bridge, since
656 * gmbus may decide to force quirk transfer in the
657 * attachment code.
658 */
659 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev,
660 "intel_iicbb", i);
661 if (dev_priv->bbbus_bridge[i] == NULL) {
662 DRM_ERROR("bbbus bridge %d creation failed\n", i);
663 ret = -ENXIO;
664 goto err;
665 }
666 device_quiet(dev_priv->bbbus_bridge[i]);
667 ret = -device_probe_and_attach(dev_priv->bbbus_bridge[i]);
668 if (ret != 0) {
669 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
670 ret);
671 goto err;
672 }
673
674 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
675 -1);
676 if (iic_dev == NULL) {
677 DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
678 goto err;
679 }
680 iic_dev = device_find_child(iic_dev, "iicbus", -1);
681 if (iic_dev == NULL) {
682 DRM_ERROR(
683 "bbbus bridge doesn't have iicbus grandchild\n");
684 goto err;
685 }
686
687 dev_priv->bbbus[i] = iic_dev;
688
689 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev,
690 "intel_gmbus", i);
691 if (dev_priv->gmbus_bridge[i] == NULL) {
692 DRM_ERROR("gmbus bridge %d creation failed\n", i);
693 ret = -ENXIO;
694 goto err;
695 }
696 device_quiet(dev_priv->gmbus_bridge[i]);
697 ret = -device_probe_and_attach(dev_priv->gmbus_bridge[i]);
698 if (ret != 0) {
699 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
700 ret);
701 ret = -ENXIO;
702 goto err;
703 }
704
705 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
706 "iicbus", -1);
707 if (iic_dev == NULL) {
708 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
709 goto err;
710 }
711 dev_priv->gmbus[i] = iic_dev;
712
713 intel_iic_reset(dev);
714 }
715 mtx_unlock(&Giant);
716
717 return 0;
718
719 err:
720 intel_teardown_gmbus_m(dev, i);
721 mtx_unlock(&Giant);
722 return ret;
723 }
724
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned port)725 device_t intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
726 unsigned port)
727 {
728
729 if (!intel_gmbus_is_port_valid(port))
730 DRM_ERROR("GMBUS get adapter %d: invalid port\n", port);
731 return (intel_gmbus_is_port_valid(port) ? dev_priv->gmbus[port - 1] :
732 NULL);
733 }
734
intel_gmbus_set_speed(device_t adapter,int speed)735 void intel_gmbus_set_speed(device_t adapter, int speed)
736 {
737 struct intel_iic_softc *sc;
738
739 sc = device_get_softc(device_get_parent(adapter));
740
741 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
742 }
743
intel_gmbus_force_bit(device_t adapter,bool force_bit)744 void intel_gmbus_force_bit(device_t adapter, bool force_bit)
745 {
746 struct intel_iic_softc *sc;
747
748 sc = device_get_softc(device_get_parent(adapter));
749 sc->force_bit_dev = force_bit;
750 }
751
752 static void
intel_teardown_gmbus_m(struct drm_device * dev,int m)753 intel_teardown_gmbus_m(struct drm_device *dev, int m)
754 {
755 struct drm_i915_private *dev_priv;
756
757 dev_priv = dev->dev_private;
758
759 sx_destroy(&dev_priv->gmbus_sx);
760 }
761
intel_teardown_gmbus(struct drm_device * dev)762 void intel_teardown_gmbus(struct drm_device *dev)
763 {
764
765 mtx_lock(&Giant);
766 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
767 mtx_unlock(&Giant);
768 }
769