1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief SI implementation of the TargetRegisterInfo class.
12 //
13 //===----------------------------------------------------------------------===//
14
15
16 #include "SIRegisterInfo.h"
17 #include "SIInstrInfo.h"
18 #include "SIMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/RegisterScavenging.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/LLVMContext.h"
24
25 using namespace llvm;
26
SIRegisterInfo()27 SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}
28
reserveRegisterTuples(BitVector & Reserved,unsigned Reg) const29 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
30 MCRegAliasIterator R(Reg, this, true);
31
32 for (; R.isValid(); ++R)
33 Reserved.set(*R);
34 }
35
getReservedRegs(const MachineFunction & MF) const36 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
37 BitVector Reserved(getNumRegs());
38 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
39
40 // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
41 // this seems likely to result in bugs, so I'm marking them as reserved.
42 reserveRegisterTuples(Reserved, AMDGPU::EXEC);
43 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
44
45 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
46 reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
47 reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
48
49 // Tonga and Iceland can only allocate a fixed number of SGPRs due
50 // to a hw bug.
51 if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) {
52 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
53 // Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
54 // Assume XNACK_MASK is unused.
55 unsigned Limit = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG - 4;
56
57 for (unsigned i = Limit; i < NumSGPRs; ++i) {
58 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
59 reserveRegisterTuples(Reserved, Reg);
60 }
61 }
62
63 return Reserved;
64 }
65
getRegPressureSetLimit(const MachineFunction & MF,unsigned Idx) const66 unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
67 unsigned Idx) const {
68
69 const AMDGPUSubtarget &STI = MF.getSubtarget<AMDGPUSubtarget>();
70 // FIXME: We should adjust the max number of waves based on LDS size.
71 unsigned SGPRLimit = getNumSGPRsAllowed(STI.getGeneration(),
72 STI.getMaxWavesPerCU());
73 unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
74
75 for (regclass_iterator I = regclass_begin(), E = regclass_end();
76 I != E; ++I) {
77
78 unsigned NumSubRegs = std::max((int)(*I)->getSize() / 4, 1);
79 unsigned Limit;
80
81 if (isSGPRClass(*I)) {
82 Limit = SGPRLimit / NumSubRegs;
83 } else {
84 Limit = VGPRLimit / NumSubRegs;
85 }
86
87 const int *Sets = getRegClassPressureSets(*I);
88 assert(Sets);
89 for (unsigned i = 0; Sets[i] != -1; ++i) {
90 if (Sets[i] == (int)Idx)
91 return Limit;
92 }
93 }
94 return 256;
95 }
96
requiresRegisterScavenging(const MachineFunction & Fn) const97 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
98 return Fn.getFrameInfo()->hasStackObjects();
99 }
100
getNumSubRegsForSpillOp(unsigned Op)101 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
102
103 switch (Op) {
104 case AMDGPU::SI_SPILL_S512_SAVE:
105 case AMDGPU::SI_SPILL_S512_RESTORE:
106 case AMDGPU::SI_SPILL_V512_SAVE:
107 case AMDGPU::SI_SPILL_V512_RESTORE:
108 return 16;
109 case AMDGPU::SI_SPILL_S256_SAVE:
110 case AMDGPU::SI_SPILL_S256_RESTORE:
111 case AMDGPU::SI_SPILL_V256_SAVE:
112 case AMDGPU::SI_SPILL_V256_RESTORE:
113 return 8;
114 case AMDGPU::SI_SPILL_S128_SAVE:
115 case AMDGPU::SI_SPILL_S128_RESTORE:
116 case AMDGPU::SI_SPILL_V128_SAVE:
117 case AMDGPU::SI_SPILL_V128_RESTORE:
118 return 4;
119 case AMDGPU::SI_SPILL_V96_SAVE:
120 case AMDGPU::SI_SPILL_V96_RESTORE:
121 return 3;
122 case AMDGPU::SI_SPILL_S64_SAVE:
123 case AMDGPU::SI_SPILL_S64_RESTORE:
124 case AMDGPU::SI_SPILL_V64_SAVE:
125 case AMDGPU::SI_SPILL_V64_RESTORE:
126 return 2;
127 case AMDGPU::SI_SPILL_S32_SAVE:
128 case AMDGPU::SI_SPILL_S32_RESTORE:
129 case AMDGPU::SI_SPILL_V32_SAVE:
130 case AMDGPU::SI_SPILL_V32_RESTORE:
131 return 1;
132 default: llvm_unreachable("Invalid spill opcode");
133 }
134 }
135
buildScratchLoadStore(MachineBasicBlock::iterator MI,unsigned LoadStoreOp,unsigned Value,unsigned ScratchRsrcReg,unsigned ScratchOffset,int64_t Offset,RegScavenger * RS) const136 void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
137 unsigned LoadStoreOp,
138 unsigned Value,
139 unsigned ScratchRsrcReg,
140 unsigned ScratchOffset,
141 int64_t Offset,
142 RegScavenger *RS) const {
143
144 MachineBasicBlock *MBB = MI->getParent();
145 const MachineFunction *MF = MI->getParent()->getParent();
146 const SIInstrInfo *TII =
147 static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
148 LLVMContext &Ctx = MF->getFunction()->getContext();
149 DebugLoc DL = MI->getDebugLoc();
150 bool IsLoad = TII->get(LoadStoreOp).mayLoad();
151
152 bool RanOutOfSGPRs = false;
153 unsigned SOffset = ScratchOffset;
154
155 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
156 unsigned Size = NumSubRegs * 4;
157
158 if (!isUInt<12>(Offset + Size)) {
159 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
160 if (SOffset == AMDGPU::NoRegister) {
161 RanOutOfSGPRs = true;
162 SOffset = AMDGPU::SGPR0;
163 }
164 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
165 .addReg(ScratchOffset)
166 .addImm(Offset);
167 Offset = 0;
168 }
169
170 if (RanOutOfSGPRs)
171 Ctx.emitError("Ran out of SGPRs for spilling VGPRS");
172
173 for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
174 unsigned SubReg = NumSubRegs > 1 ?
175 getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
176 Value;
177 bool IsKill = (i == e - 1);
178
179 BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
180 .addReg(SubReg, getDefRegState(IsLoad))
181 .addReg(ScratchRsrcReg, getKillRegState(IsKill))
182 .addReg(SOffset)
183 .addImm(Offset)
184 .addImm(0) // glc
185 .addImm(0) // slc
186 .addImm(0) // tfe
187 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad));
188 }
189 }
190
eliminateFrameIndex(MachineBasicBlock::iterator MI,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const191 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
192 int SPAdj, unsigned FIOperandNum,
193 RegScavenger *RS) const {
194 MachineFunction *MF = MI->getParent()->getParent();
195 MachineBasicBlock *MBB = MI->getParent();
196 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
197 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
198 const SIInstrInfo *TII =
199 static_cast<const SIInstrInfo *>(MF->getSubtarget().getInstrInfo());
200 DebugLoc DL = MI->getDebugLoc();
201
202 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
203 int Index = MI->getOperand(FIOperandNum).getIndex();
204
205 switch (MI->getOpcode()) {
206 // SGPR register spill
207 case AMDGPU::SI_SPILL_S512_SAVE:
208 case AMDGPU::SI_SPILL_S256_SAVE:
209 case AMDGPU::SI_SPILL_S128_SAVE:
210 case AMDGPU::SI_SPILL_S64_SAVE:
211 case AMDGPU::SI_SPILL_S32_SAVE: {
212 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
213
214 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
215 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
216 &AMDGPU::SGPR_32RegClass, i);
217 struct SIMachineFunctionInfo::SpilledReg Spill =
218 MFI->getSpilledReg(MF, Index, i);
219
220 if (Spill.VGPR == AMDGPU::NoRegister) {
221 LLVMContext &Ctx = MF->getFunction()->getContext();
222 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
223 }
224
225 BuildMI(*MBB, MI, DL,
226 TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
227 Spill.VGPR)
228 .addReg(SubReg)
229 .addImm(Spill.Lane);
230
231 }
232 MI->eraseFromParent();
233 break;
234 }
235
236 // SGPR register restore
237 case AMDGPU::SI_SPILL_S512_RESTORE:
238 case AMDGPU::SI_SPILL_S256_RESTORE:
239 case AMDGPU::SI_SPILL_S128_RESTORE:
240 case AMDGPU::SI_SPILL_S64_RESTORE:
241 case AMDGPU::SI_SPILL_S32_RESTORE: {
242 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
243
244 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
245 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
246 &AMDGPU::SGPR_32RegClass, i);
247 struct SIMachineFunctionInfo::SpilledReg Spill =
248 MFI->getSpilledReg(MF, Index, i);
249
250 if (Spill.VGPR == AMDGPU::NoRegister) {
251 LLVMContext &Ctx = MF->getFunction()->getContext();
252 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
253 }
254
255 BuildMI(*MBB, MI, DL,
256 TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
257 SubReg)
258 .addReg(Spill.VGPR)
259 .addImm(Spill.Lane)
260 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
261 }
262
263 // TODO: only do this when it is needed
264 switch (MF->getSubtarget<AMDGPUSubtarget>().getGeneration()) {
265 case AMDGPUSubtarget::SOUTHERN_ISLANDS:
266 // "VALU writes SGPR" -> "SMRD reads that SGPR" needs "S_NOP 3" on SI
267 TII->insertNOPs(MI, 3);
268 break;
269 case AMDGPUSubtarget::SEA_ISLANDS:
270 break;
271 default: // VOLCANIC_ISLANDS and later
272 // "VALU writes SGPR -> VMEM reads that SGPR" needs "S_NOP 4" on VI
273 // and later. This also applies to VALUs which write VCC, but we're
274 // unlikely to see VMEM use VCC.
275 TII->insertNOPs(MI, 4);
276 }
277
278 MI->eraseFromParent();
279 break;
280 }
281
282 // VGPR register spill
283 case AMDGPU::SI_SPILL_V512_SAVE:
284 case AMDGPU::SI_SPILL_V256_SAVE:
285 case AMDGPU::SI_SPILL_V128_SAVE:
286 case AMDGPU::SI_SPILL_V96_SAVE:
287 case AMDGPU::SI_SPILL_V64_SAVE:
288 case AMDGPU::SI_SPILL_V32_SAVE:
289 buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
290 TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
291 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
292 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
293 FrameInfo->getObjectOffset(Index), RS);
294 MI->eraseFromParent();
295 break;
296 case AMDGPU::SI_SPILL_V32_RESTORE:
297 case AMDGPU::SI_SPILL_V64_RESTORE:
298 case AMDGPU::SI_SPILL_V96_RESTORE:
299 case AMDGPU::SI_SPILL_V128_RESTORE:
300 case AMDGPU::SI_SPILL_V256_RESTORE:
301 case AMDGPU::SI_SPILL_V512_RESTORE: {
302 buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
303 TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
304 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
305 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
306 FrameInfo->getObjectOffset(Index), RS);
307 MI->eraseFromParent();
308 break;
309 }
310
311 default: {
312 int64_t Offset = FrameInfo->getObjectOffset(Index);
313 FIOp.ChangeToImmediate(Offset);
314 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
315 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
316 BuildMI(*MBB, MI, MI->getDebugLoc(),
317 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
318 .addImm(Offset);
319 FIOp.ChangeToRegister(TmpReg, false, false, true);
320 }
321 }
322 }
323 }
324
getCFGStructurizerRegClass(MVT VT) const325 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
326 MVT VT) const {
327 switch(VT.SimpleTy) {
328 default:
329 case MVT::i32: return &AMDGPU::VGPR_32RegClass;
330 }
331 }
332
getHWRegIndex(unsigned Reg) const333 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
334 return getEncodingValue(Reg) & 0xff;
335 }
336
getPhysRegClass(unsigned Reg) const337 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
338 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
339
340 static const TargetRegisterClass *BaseClasses[] = {
341 &AMDGPU::VGPR_32RegClass,
342 &AMDGPU::SReg_32RegClass,
343 &AMDGPU::VReg_64RegClass,
344 &AMDGPU::SReg_64RegClass,
345 &AMDGPU::VReg_96RegClass,
346 &AMDGPU::VReg_128RegClass,
347 &AMDGPU::SReg_128RegClass,
348 &AMDGPU::VReg_256RegClass,
349 &AMDGPU::SReg_256RegClass,
350 &AMDGPU::VReg_512RegClass,
351 &AMDGPU::SReg_512RegClass
352 };
353
354 for (const TargetRegisterClass *BaseClass : BaseClasses) {
355 if (BaseClass->contains(Reg)) {
356 return BaseClass;
357 }
358 }
359 return nullptr;
360 }
361
hasVGPRs(const TargetRegisterClass * RC) const362 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
363 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) ||
364 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
365 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
366 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
367 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
368 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
369 }
370
getEquivalentVGPRClass(const TargetRegisterClass * SRC) const371 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
372 const TargetRegisterClass *SRC) const {
373 if (hasVGPRs(SRC)) {
374 return SRC;
375 } else if (SRC == &AMDGPU::SCCRegRegClass) {
376 return &AMDGPU::VCCRegRegClass;
377 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
378 return &AMDGPU::VGPR_32RegClass;
379 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
380 return &AMDGPU::VReg_64RegClass;
381 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
382 return &AMDGPU::VReg_128RegClass;
383 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
384 return &AMDGPU::VReg_256RegClass;
385 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
386 return &AMDGPU::VReg_512RegClass;
387 }
388 return nullptr;
389 }
390
getSubRegClass(const TargetRegisterClass * RC,unsigned SubIdx) const391 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
392 const TargetRegisterClass *RC, unsigned SubIdx) const {
393 if (SubIdx == AMDGPU::NoSubRegister)
394 return RC;
395
396 // If this register has a sub-register, we can safely assume it is a 32-bit
397 // register, because all of SI's sub-registers are 32-bit.
398 if (isSGPRClass(RC)) {
399 return &AMDGPU::SGPR_32RegClass;
400 } else {
401 return &AMDGPU::VGPR_32RegClass;
402 }
403 }
404
getPhysRegSubReg(unsigned Reg,const TargetRegisterClass * SubRC,unsigned Channel) const405 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
406 const TargetRegisterClass *SubRC,
407 unsigned Channel) const {
408
409 switch (Reg) {
410 case AMDGPU::VCC:
411 switch(Channel) {
412 case 0: return AMDGPU::VCC_LO;
413 case 1: return AMDGPU::VCC_HI;
414 default: llvm_unreachable("Invalid SubIdx for VCC");
415 }
416
417 case AMDGPU::FLAT_SCR:
418 switch (Channel) {
419 case 0:
420 return AMDGPU::FLAT_SCR_LO;
421 case 1:
422 return AMDGPU::FLAT_SCR_HI;
423 default:
424 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
425 }
426 break;
427
428 case AMDGPU::EXEC:
429 switch (Channel) {
430 case 0:
431 return AMDGPU::EXEC_LO;
432 case 1:
433 return AMDGPU::EXEC_HI;
434 default:
435 llvm_unreachable("Invalid SubIdx for EXEC");
436 }
437 break;
438 }
439
440 const TargetRegisterClass *RC = getPhysRegClass(Reg);
441 // 32-bit registers don't have sub-registers, so we can just return the
442 // Reg. We need to have this check here, because the calculation below
443 // using getHWRegIndex() will fail with special 32-bit registers like
444 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
445 if (RC->getSize() == 4) {
446 assert(Channel == 0);
447 return Reg;
448 }
449
450 unsigned Index = getHWRegIndex(Reg);
451 return SubRC->getRegister(Index + Channel);
452 }
453
opCanUseLiteralConstant(unsigned OpType) const454 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
455 return OpType == AMDGPU::OPERAND_REG_IMM32;
456 }
457
opCanUseInlineConstant(unsigned OpType) const458 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
459 if (opCanUseLiteralConstant(OpType))
460 return true;
461
462 return OpType == AMDGPU::OPERAND_REG_INLINE_C;
463 }
464
getPreloadedValue(const MachineFunction & MF,enum PreloadedValue Value) const465 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
466 enum PreloadedValue Value) const {
467
468 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
469 switch (Value) {
470 case SIRegisterInfo::TGID_X:
471 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
472 case SIRegisterInfo::TGID_Y:
473 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
474 case SIRegisterInfo::TGID_Z:
475 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
476 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
477 if (MFI->getShaderType() != ShaderType::COMPUTE)
478 return MFI->ScratchOffsetReg;
479 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
480 case SIRegisterInfo::SCRATCH_PTR:
481 return AMDGPU::SGPR2_SGPR3;
482 case SIRegisterInfo::INPUT_PTR:
483 return AMDGPU::SGPR0_SGPR1;
484 case SIRegisterInfo::TIDIG_X:
485 return AMDGPU::VGPR0;
486 case SIRegisterInfo::TIDIG_Y:
487 return AMDGPU::VGPR1;
488 case SIRegisterInfo::TIDIG_Z:
489 return AMDGPU::VGPR2;
490 }
491 llvm_unreachable("unexpected preloaded value type");
492 }
493
494 /// \brief Returns a register that is not used at any point in the function.
495 /// If all registers are used, then this function will return
496 // AMDGPU::NoRegister.
findUnusedRegister(const MachineRegisterInfo & MRI,const TargetRegisterClass * RC) const497 unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
498 const TargetRegisterClass *RC) const {
499
500 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
501 I != E; ++I) {
502 if (!MRI.isPhysRegUsed(*I))
503 return *I;
504 }
505 return AMDGPU::NoRegister;
506 }
507
getNumVGPRsAllowed(unsigned WaveCount) const508 unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
509 switch(WaveCount) {
510 case 10: return 24;
511 case 9: return 28;
512 case 8: return 32;
513 case 7: return 36;
514 case 6: return 40;
515 case 5: return 48;
516 case 4: return 64;
517 case 3: return 84;
518 case 2: return 128;
519 default: return 256;
520 }
521 }
522
getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,unsigned WaveCount) const523 unsigned SIRegisterInfo::getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
524 unsigned WaveCount) const {
525 if (gen >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
526 switch (WaveCount) {
527 case 10: return 80;
528 case 9: return 80;
529 case 8: return 96;
530 default: return 102;
531 }
532 } else {
533 switch(WaveCount) {
534 case 10: return 48;
535 case 9: return 56;
536 case 8: return 64;
537 case 7: return 72;
538 case 6: return 80;
539 case 5: return 96;
540 default: return 103;
541 }
542 }
543 }
544