1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm.h>
34 #include <dev/drm2/i915/i915_drm.h>
35 #include <dev/drm2/i915/i915_drv.h>
36 #include <dev/drm2/i915/intel_drv.h>
37 #include <sys/sched.h>
38 #include <sys/sf_buf.h>
39 #include <sys/sleepqueue.h>
40
41 static void i915_capture_error_state(struct drm_device *dev);
42 static u32 ring_last_seqno(struct intel_ring_buffer *ring);
43
44 /* For display hotplug interrupt */
45 static void
ironlake_enable_display_irq(drm_i915_private_t * dev_priv,u32 mask)46 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
47 {
48 if ((dev_priv->irq_mask & mask) != 0) {
49 dev_priv->irq_mask &= ~mask;
50 I915_WRITE(DEIMR, dev_priv->irq_mask);
51 POSTING_READ(DEIMR);
52 }
53 }
54
55 static inline void
ironlake_disable_display_irq(drm_i915_private_t * dev_priv,u32 mask)56 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
57 {
58 if ((dev_priv->irq_mask & mask) != mask) {
59 dev_priv->irq_mask |= mask;
60 I915_WRITE(DEIMR, dev_priv->irq_mask);
61 POSTING_READ(DEIMR);
62 }
63 }
64
65 void
i915_enable_pipestat(drm_i915_private_t * dev_priv,int pipe,u32 mask)66 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
67 {
68 if ((dev_priv->pipestat[pipe] & mask) != mask) {
69 u32 reg = PIPESTAT(pipe);
70
71 dev_priv->pipestat[pipe] |= mask;
72 /* Enable the interrupt, clear any pending status */
73 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
74 POSTING_READ(reg);
75 }
76 }
77
78 void
i915_disable_pipestat(drm_i915_private_t * dev_priv,int pipe,u32 mask)79 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
80 {
81 if ((dev_priv->pipestat[pipe] & mask) != 0) {
82 u32 reg = PIPESTAT(pipe);
83
84 dev_priv->pipestat[pipe] &= ~mask;
85 I915_WRITE(reg, dev_priv->pipestat[pipe]);
86 POSTING_READ(reg);
87 }
88 }
89
90 /**
91 * intel_enable_asle - enable ASLE interrupt for OpRegion
92 */
intel_enable_asle(struct drm_device * dev)93 void intel_enable_asle(struct drm_device *dev)
94 {
95 drm_i915_private_t *dev_priv = dev->dev_private;
96
97 /* FIXME: opregion/asle for VLV */
98 if (IS_VALLEYVIEW(dev))
99 return;
100
101 mtx_lock(&dev_priv->irq_lock);
102
103 if (HAS_PCH_SPLIT(dev))
104 ironlake_enable_display_irq(dev_priv, DE_GSE);
105 else {
106 i915_enable_pipestat(dev_priv, 1,
107 PIPE_LEGACY_BLC_EVENT_ENABLE);
108 if (INTEL_INFO(dev)->gen >= 4)
109 i915_enable_pipestat(dev_priv, 0,
110 PIPE_LEGACY_BLC_EVENT_ENABLE);
111 }
112
113 mtx_unlock(&dev_priv->irq_lock);
114 }
115
116 /**
117 * i915_pipe_enabled - check if a pipe is enabled
118 * @dev: DRM device
119 * @pipe: pipe to check
120 *
121 * Reading certain registers when the pipe is disabled can hang the chip.
122 * Use this routine to make sure the PLL is running and the pipe is active
123 * before reading such registers if unsure.
124 */
125 static int
i915_pipe_enabled(struct drm_device * dev,int pipe)126 i915_pipe_enabled(struct drm_device *dev, int pipe)
127 {
128 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
129 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
130 }
131
132 /* Called from drm generic code, passed a 'crtc', which
133 * we use as a pipe index
134 */
i915_get_vblank_counter(struct drm_device * dev,int pipe)135 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
136 {
137 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
138 unsigned long high_frame;
139 unsigned long low_frame;
140 u32 high1, high2, low;
141
142 if (!i915_pipe_enabled(dev, pipe)) {
143 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
144 "pipe %c\n", pipe_name(pipe));
145 return 0;
146 }
147
148 high_frame = PIPEFRAME(pipe);
149 low_frame = PIPEFRAMEPIXEL(pipe);
150
151 /*
152 * High & low register fields aren't synchronized, so make sure
153 * we get a low value that's stable across two reads of the high
154 * register.
155 */
156 do {
157 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
158 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
159 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
160 } while (high1 != high2);
161
162 high1 >>= PIPE_FRAME_HIGH_SHIFT;
163 low >>= PIPE_FRAME_LOW_SHIFT;
164 return (high1 << 8) | low;
165 }
166
gm45_get_vblank_counter(struct drm_device * dev,int pipe)167 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
168 {
169 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
170 int reg = PIPE_FRMCOUNT_GM45(pipe);
171
172 if (!i915_pipe_enabled(dev, pipe)) {
173 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
174 "pipe %c\n", pipe_name(pipe));
175 return 0;
176 }
177
178 return I915_READ(reg);
179 }
180
i915_get_crtc_scanoutpos(struct drm_device * dev,int pipe,int * vpos,int * hpos)181 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
182 int *vpos, int *hpos)
183 {
184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
185 u32 vbl = 0, position = 0;
186 int vbl_start, vbl_end, htotal, vtotal;
187 bool in_vbl = true;
188 int ret = 0;
189
190 if (!i915_pipe_enabled(dev, pipe)) {
191 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
192 "pipe %c\n", pipe_name(pipe));
193 return 0;
194 }
195
196 /* Get vtotal. */
197 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
198
199 if (INTEL_INFO(dev)->gen >= 4) {
200 /* No obvious pixelcount register. Only query vertical
201 * scanout position from Display scan line register.
202 */
203 position = I915_READ(PIPEDSL(pipe));
204
205 /* Decode into vertical scanout position. Don't have
206 * horizontal scanout position.
207 */
208 *vpos = position & 0x1fff;
209 *hpos = 0;
210 } else {
211 /* Have access to pixelcount since start of frame.
212 * We can split this into vertical and horizontal
213 * scanout position.
214 */
215 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
216
217 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
218 *vpos = position / htotal;
219 *hpos = position - (*vpos * htotal);
220 }
221
222 /* Query vblank area. */
223 vbl = I915_READ(VBLANK(pipe));
224
225 /* Test position against vblank region. */
226 vbl_start = vbl & 0x1fff;
227 vbl_end = (vbl >> 16) & 0x1fff;
228
229 if ((*vpos < vbl_start) || (*vpos > vbl_end))
230 in_vbl = false;
231
232 /* Inside "upper part" of vblank area? Apply corrective offset: */
233 if (in_vbl && (*vpos >= vbl_start))
234 *vpos = *vpos - vtotal;
235
236 /* Readouts valid? */
237 if (vbl > 0)
238 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
239
240 /* In vblank? */
241 if (in_vbl)
242 ret |= DRM_SCANOUTPOS_INVBL;
243
244 return ret;
245 }
246
i915_get_vblank_timestamp(struct drm_device * dev,int pipe,int * max_error,struct timeval * vblank_time,unsigned flags)247 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
248 int *max_error,
249 struct timeval *vblank_time,
250 unsigned flags)
251 {
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct drm_crtc *crtc;
254
255 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
256 DRM_ERROR("Invalid crtc %d\n", pipe);
257 return -EINVAL;
258 }
259
260 /* Get drm_crtc to timestamp: */
261 crtc = intel_get_crtc_for_pipe(dev, pipe);
262 if (crtc == NULL) {
263 DRM_ERROR("Invalid crtc %d\n", pipe);
264 return -EINVAL;
265 }
266
267 if (!crtc->enabled) {
268 #if 0
269 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
270 #endif
271 return -EBUSY;
272 }
273
274 /* Helper routine in DRM core does all the work: */
275 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
276 vblank_time, flags,
277 crtc);
278 }
279
280 /*
281 * Handle hotplug events outside the interrupt handler proper.
282 */
i915_hotplug_work_func(void * context,int pending)283 static void i915_hotplug_work_func(void *context, int pending)
284 {
285 drm_i915_private_t *dev_priv = context;
286 struct drm_device *dev = dev_priv->dev;
287 struct drm_mode_config *mode_config = &dev->mode_config;
288 struct intel_encoder *encoder;
289
290 DRM_DEBUG("running encoder hotplug functions\n");
291
292 sx_xlock(&mode_config->mutex);
293 DRM_DEBUG_KMS("running encoder hotplug functions\n");
294
295 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
296 if (encoder->hot_plug)
297 encoder->hot_plug(encoder);
298
299 sx_xunlock(&mode_config->mutex);
300
301 /* Just fire off a uevent and let userspace tell us what to do */
302 #if 0
303 drm_helper_hpd_irq_event(dev);
304 #endif
305 }
306
i915_handle_rps_change(struct drm_device * dev)307 static void i915_handle_rps_change(struct drm_device *dev)
308 {
309 drm_i915_private_t *dev_priv = dev->dev_private;
310 u32 busy_up, busy_down, max_avg, min_avg;
311 u8 new_delay = dev_priv->cur_delay;
312
313 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
314 busy_up = I915_READ(RCPREVBSYTUPAVG);
315 busy_down = I915_READ(RCPREVBSYTDNAVG);
316 max_avg = I915_READ(RCBMAXAVG);
317 min_avg = I915_READ(RCBMINAVG);
318
319 /* Handle RCS change request from hw */
320 if (busy_up > max_avg) {
321 if (dev_priv->cur_delay != dev_priv->max_delay)
322 new_delay = dev_priv->cur_delay - 1;
323 if (new_delay < dev_priv->max_delay)
324 new_delay = dev_priv->max_delay;
325 } else if (busy_down < min_avg) {
326 if (dev_priv->cur_delay != dev_priv->min_delay)
327 new_delay = dev_priv->cur_delay + 1;
328 if (new_delay > dev_priv->min_delay)
329 new_delay = dev_priv->min_delay;
330 }
331
332 if (ironlake_set_drps(dev, new_delay))
333 dev_priv->cur_delay = new_delay;
334
335 return;
336 }
337
notify_ring(struct drm_device * dev,struct intel_ring_buffer * ring)338 static void notify_ring(struct drm_device *dev,
339 struct intel_ring_buffer *ring)
340 {
341 struct drm_i915_private *dev_priv = dev->dev_private;
342
343 if (ring->obj == NULL)
344 return;
345
346 CTR2(KTR_DRM, "request_complete %s %d", ring->name, ring->get_seqno(ring));
347
348 mtx_lock(&dev_priv->irq_lock);
349 wakeup(ring);
350 mtx_unlock(&dev_priv->irq_lock);
351 if (i915_enable_hangcheck) {
352 dev_priv->hangcheck_count = 0;
353 callout_schedule(&dev_priv->hangcheck_timer,
354 DRM_I915_HANGCHECK_PERIOD);
355 }
356 }
357
gen6_pm_rps_work(void * context,int pending)358 static void gen6_pm_rps_work(void *context, int pending)
359 {
360 struct drm_device *dev;
361 drm_i915_private_t *dev_priv = context;
362 u32 pm_iir, pm_imr;
363 u8 new_delay;
364
365 dev = dev_priv->dev;
366 new_delay = dev_priv->cur_delay;
367
368 mtx_lock(&dev_priv->rps_lock);
369 pm_iir = dev_priv->pm_iir;
370 dev_priv->pm_iir = 0;
371 pm_imr = I915_READ(GEN6_PMIMR);
372 I915_WRITE(GEN6_PMIMR, 0);
373 mtx_unlock(&dev_priv->rps_lock);
374
375 if (!pm_iir)
376 return;
377
378 DRM_LOCK(dev);
379 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
380 if (dev_priv->cur_delay != dev_priv->max_delay)
381 new_delay = dev_priv->cur_delay + 1;
382 if (new_delay > dev_priv->max_delay)
383 new_delay = dev_priv->max_delay;
384 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
385 gen6_gt_force_wake_get(dev_priv);
386 if (dev_priv->cur_delay != dev_priv->min_delay)
387 new_delay = dev_priv->cur_delay - 1;
388 if (new_delay < dev_priv->min_delay) {
389 new_delay = dev_priv->min_delay;
390 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
391 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
392 ((new_delay << 16) & 0x3f0000));
393 } else {
394 /* Make sure we continue to get down interrupts
395 * until we hit the minimum frequency */
396 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
397 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
398 }
399 gen6_gt_force_wake_put(dev_priv);
400 }
401
402 gen6_set_rps(dev, new_delay);
403 dev_priv->cur_delay = new_delay;
404
405 /*
406 * rps_lock not held here because clearing is non-destructive. There is
407 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
408 * by holding struct_mutex for the duration of the write.
409 */
410 DRM_UNLOCK(dev);
411 }
412
snb_gt_irq_handler(struct drm_device * dev,struct drm_i915_private * dev_priv,u32 gt_iir)413 static void snb_gt_irq_handler(struct drm_device *dev,
414 struct drm_i915_private *dev_priv,
415 u32 gt_iir)
416 {
417
418 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
419 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
420 notify_ring(dev, &dev_priv->rings[RCS]);
421 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
422 notify_ring(dev, &dev_priv->rings[VCS]);
423 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
424 notify_ring(dev, &dev_priv->rings[BCS]);
425
426 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
427 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
428 GT_RENDER_CS_ERROR_INTERRUPT)) {
429 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
430 i915_handle_error(dev, false);
431 }
432 }
433
gen6_queue_rps_work(struct drm_i915_private * dev_priv,u32 pm_iir)434 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
435 u32 pm_iir)
436 {
437
438 /*
439 * IIR bits should never already be set because IMR should
440 * prevent an interrupt from being shown in IIR. The warning
441 * displays a case where we've unsafely cleared
442 * dev_priv->pm_iir. Although missing an interrupt of the same
443 * type is not a problem, it displays a problem in the logic.
444 *
445 * The mask bit in IMR is cleared by rps_work.
446 */
447
448 mtx_lock(&dev_priv->rps_lock);
449 if (dev_priv->pm_iir & pm_iir)
450 printf("Missed a PM interrupt\n");
451 dev_priv->pm_iir |= pm_iir;
452 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
453 POSTING_READ(GEN6_PMIMR);
454 mtx_unlock(&dev_priv->rps_lock);
455
456 taskqueue_enqueue(dev_priv->tq, &dev_priv->rps_task);
457 }
458
valleyview_irq_handler(DRM_IRQ_ARGS)459 static void valleyview_irq_handler(DRM_IRQ_ARGS)
460 {
461 struct drm_device *dev = (struct drm_device *) arg;
462 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
463 u32 iir, gt_iir, pm_iir;
464 int pipe;
465 u32 pipe_stats[I915_MAX_PIPES];
466 u32 vblank_status;
467 int vblank = 0;
468 bool blc_event;
469
470 atomic_inc(&dev_priv->irq_received);
471
472 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
473 PIPE_VBLANK_INTERRUPT_STATUS;
474
475 while (true) {
476 iir = I915_READ(VLV_IIR);
477 gt_iir = I915_READ(GTIIR);
478 pm_iir = I915_READ(GEN6_PMIIR);
479
480 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
481 goto out;
482
483 snb_gt_irq_handler(dev, dev_priv, gt_iir);
484
485 mtx_lock(&dev_priv->irq_lock);
486 for_each_pipe(pipe) {
487 int reg = PIPESTAT(pipe);
488 pipe_stats[pipe] = I915_READ(reg);
489
490 /*
491 * Clear the PIPE*STAT regs before the IIR
492 */
493 if (pipe_stats[pipe] & 0x8000ffff) {
494 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
495 DRM_DEBUG_DRIVER("pipe %c underrun\n",
496 pipe_name(pipe));
497 I915_WRITE(reg, pipe_stats[pipe]);
498 }
499 }
500 mtx_unlock(&dev_priv->irq_lock);
501
502 /* Consume port. Then clear IIR or we'll miss events */
503 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
504 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
505
506 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
507 hotplug_status);
508 if (hotplug_status & dev_priv->hotplug_supported_mask)
509 taskqueue_enqueue(dev_priv->tq,
510 &dev_priv->hotplug_task);
511
512 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
513 I915_READ(PORT_HOTPLUG_STAT);
514 }
515
516
517 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
518 drm_handle_vblank(dev, 0);
519 vblank++;
520 intel_finish_page_flip(dev, 0);
521 }
522
523 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
524 drm_handle_vblank(dev, 1);
525 vblank++;
526 intel_finish_page_flip(dev, 0);
527 }
528
529 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
530 blc_event = true;
531
532 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
533 gen6_queue_rps_work(dev_priv, pm_iir);
534
535 I915_WRITE(GTIIR, gt_iir);
536 I915_WRITE(GEN6_PMIIR, pm_iir);
537 I915_WRITE(VLV_IIR, iir);
538 }
539
540 out:
541 return;
542 }
543
pch_irq_handler(struct drm_device * dev,u32 pch_iir)544 static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
545 {
546 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
547 int pipe;
548
549 if (pch_iir & SDE_AUDIO_POWER_MASK)
550 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
551 (pch_iir & SDE_AUDIO_POWER_MASK) >>
552 SDE_AUDIO_POWER_SHIFT);
553
554 if (pch_iir & SDE_GMBUS)
555 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
556
557 if (pch_iir & SDE_AUDIO_HDCP_MASK)
558 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
559
560 if (pch_iir & SDE_AUDIO_TRANS_MASK)
561 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
562
563 if (pch_iir & SDE_POISON)
564 DRM_ERROR("PCH poison interrupt\n");
565
566 if (pch_iir & SDE_FDI_MASK)
567 for_each_pipe(pipe)
568 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
569 pipe_name(pipe),
570 I915_READ(FDI_RX_IIR(pipe)));
571
572 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
573 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
574
575 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
576 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
577
578 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
579 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
580 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
581 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
582 }
583
ivybridge_irq_handler(DRM_IRQ_ARGS)584 static void ivybridge_irq_handler(DRM_IRQ_ARGS)
585 {
586 struct drm_device *dev = (struct drm_device *) arg;
587 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
588 u32 de_iir, gt_iir, de_ier, pm_iir;
589 int i;
590
591 atomic_inc(&dev_priv->irq_received);
592
593 /* disable master interrupt before clearing iir */
594 de_ier = I915_READ(DEIER);
595 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
596 POSTING_READ(DEIER);
597
598 gt_iir = I915_READ(GTIIR);
599 if (gt_iir) {
600 snb_gt_irq_handler(dev, dev_priv, gt_iir);
601 I915_WRITE(GTIIR, gt_iir);
602 }
603
604 de_iir = I915_READ(DEIIR);
605 if (de_iir) {
606 if (de_iir & DE_GSE_IVB)
607 intel_opregion_gse_intr(dev);
608
609 for (i = 0; i < 3; i++) {
610 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
611 intel_prepare_page_flip(dev, i);
612 intel_finish_page_flip_plane(dev, i);
613 }
614 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
615 drm_handle_vblank(dev, i);
616 }
617
618 /* check event from PCH */
619 if (de_iir & DE_PCH_EVENT_IVB) {
620 u32 pch_iir = I915_READ(SDEIIR);
621
622 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
623 taskqueue_enqueue(dev_priv->tq,
624 &dev_priv->hotplug_task);
625 pch_irq_handler(dev, pch_iir);
626
627 /* clear PCH hotplug event before clear CPU irq */
628 I915_WRITE(SDEIIR, pch_iir);
629 }
630
631 I915_WRITE(DEIIR, de_iir);
632 }
633
634 pm_iir = I915_READ(GEN6_PMIIR);
635 if (pm_iir) {
636 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
637 gen6_queue_rps_work(dev_priv, pm_iir);
638 I915_WRITE(GEN6_PMIIR, pm_iir);
639 }
640
641 I915_WRITE(DEIER, de_ier);
642 POSTING_READ(DEIER);
643
644 CTR3(KTR_DRM, "ivybridge_irq de %x gt %x pm %x", de_iir,
645 gt_iir, pm_iir);
646 }
647
ilk_gt_irq_handler(struct drm_device * dev,struct drm_i915_private * dev_priv,u32 gt_iir)648 static void ilk_gt_irq_handler(struct drm_device *dev,
649 struct drm_i915_private *dev_priv,
650 u32 gt_iir)
651 {
652 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
653 notify_ring(dev, &dev_priv->rings[RCS]);
654 if (gt_iir & GT_BSD_USER_INTERRUPT)
655 notify_ring(dev, &dev_priv->rings[VCS]);
656 }
657
ironlake_irq_handler(DRM_IRQ_ARGS)658 static void ironlake_irq_handler(DRM_IRQ_ARGS)
659 {
660 struct drm_device *dev = (struct drm_device *) arg;
661 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
662 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
663 u32 hotplug_mask;
664
665 atomic_inc(&dev_priv->irq_received);
666
667 /* disable master interrupt before clearing iir */
668 de_ier = I915_READ(DEIER);
669 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
670 POSTING_READ(DEIER);
671
672 de_iir = I915_READ(DEIIR);
673 gt_iir = I915_READ(GTIIR);
674 pch_iir = I915_READ(SDEIIR);
675 pm_iir = I915_READ(GEN6_PMIIR);
676
677 CTR4(KTR_DRM, "ironlake_irq de %x gt %x pch %x pm %x", de_iir,
678 gt_iir, pch_iir, pm_iir);
679
680 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
681 (!IS_GEN6(dev) || pm_iir == 0))
682 goto done;
683
684 if (HAS_PCH_CPT(dev))
685 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
686 else
687 hotplug_mask = SDE_HOTPLUG_MASK;
688
689 if (IS_GEN5(dev))
690 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
691 else
692 snb_gt_irq_handler(dev, dev_priv, gt_iir);
693
694 if (de_iir & DE_GSE)
695 intel_opregion_gse_intr(dev);
696
697 if (de_iir & DE_PLANEA_FLIP_DONE) {
698 intel_prepare_page_flip(dev, 0);
699 intel_finish_page_flip_plane(dev, 0);
700 }
701
702 if (de_iir & DE_PLANEB_FLIP_DONE) {
703 intel_prepare_page_flip(dev, 1);
704 intel_finish_page_flip_plane(dev, 1);
705 }
706
707 if (de_iir & DE_PIPEA_VBLANK)
708 drm_handle_vblank(dev, 0);
709
710 if (de_iir & DE_PIPEB_VBLANK)
711 drm_handle_vblank(dev, 1);
712
713 /* check event from PCH */
714 if (de_iir & DE_PCH_EVENT) {
715 if (pch_iir & hotplug_mask)
716 taskqueue_enqueue(dev_priv->tq,
717 &dev_priv->hotplug_task);
718 pch_irq_handler(dev, pch_iir);
719 }
720
721 if (de_iir & DE_PCU_EVENT) {
722 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
723 i915_handle_rps_change(dev);
724 }
725
726 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
727 gen6_queue_rps_work(dev_priv, pm_iir);
728
729 /* should clear PCH hotplug event before clear CPU irq */
730 I915_WRITE(SDEIIR, pch_iir);
731 I915_WRITE(GTIIR, gt_iir);
732 I915_WRITE(DEIIR, de_iir);
733 I915_WRITE(GEN6_PMIIR, pm_iir);
734
735 done:
736 I915_WRITE(DEIER, de_ier);
737 POSTING_READ(DEIER);
738 }
739
740 /**
741 * i915_error_work_func - do process context error handling work
742 * @work: work struct
743 *
744 * Fire an error uevent so userspace can see that a hang or error
745 * was detected.
746 */
i915_error_work_func(void * context,int pending)747 static void i915_error_work_func(void *context, int pending)
748 {
749 drm_i915_private_t *dev_priv = context;
750 struct drm_device *dev = dev_priv->dev;
751
752 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */
753
754 if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
755 DRM_DEBUG_DRIVER("resetting chip\n");
756 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */
757 if (!i915_reset(dev)) {
758 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
759 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); */
760 }
761 mtx_lock(&dev_priv->error_completion_lock);
762 dev_priv->error_completion++;
763 wakeup(&dev_priv->error_completion);
764 mtx_unlock(&dev_priv->error_completion_lock);
765 }
766 }
767
768 static struct drm_i915_error_object *
i915_error_object_create(struct drm_i915_private * dev_priv,struct drm_i915_gem_object * src)769 i915_error_object_create(struct drm_i915_private *dev_priv,
770 struct drm_i915_gem_object *src)
771 {
772 struct drm_i915_error_object *dst;
773 struct sf_buf *sf;
774 void *d, *s;
775 int page, page_count;
776 u32 reloc_offset;
777
778 if (src == NULL || src->pages == NULL)
779 return NULL;
780
781 page_count = src->base.size / PAGE_SIZE;
782
783 dst = malloc(sizeof(*dst) + page_count * sizeof(u32 *), DRM_I915_GEM,
784 M_NOWAIT);
785 if (dst == NULL)
786 return (NULL);
787
788 reloc_offset = src->gtt_offset;
789 for (page = 0; page < page_count; page++) {
790 d = malloc(PAGE_SIZE, DRM_I915_GEM, M_NOWAIT);
791 if (d == NULL)
792 goto unwind;
793
794 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
795 src->has_global_gtt_mapping) {
796 /* Simply ignore tiling or any overlapping fence.
797 * It's part of the error state, and this hopefully
798 * captures what the GPU read.
799 */
800 s = pmap_mapdev_attr(src->base.dev->agp->base +
801 reloc_offset, PAGE_SIZE, PAT_WRITE_COMBINING);
802 memcpy(d, s, PAGE_SIZE);
803 pmap_unmapdev((vm_offset_t)s, PAGE_SIZE);
804 } else {
805 drm_clflush_pages(&src->pages[page], 1);
806
807 sched_pin();
808 sf = sf_buf_alloc(src->pages[page], SFB_CPUPRIVATE |
809 SFB_NOWAIT);
810 if (sf != NULL) {
811 s = (void *)(uintptr_t)sf_buf_kva(sf);
812 memcpy(d, s, PAGE_SIZE);
813 sf_buf_free(sf);
814 } else {
815 bzero(d, PAGE_SIZE);
816 strcpy(d, "XXXKIB");
817 }
818 sched_unpin();
819
820 drm_clflush_pages(&src->pages[page], 1);
821 }
822
823 dst->pages[page] = d;
824
825 reloc_offset += PAGE_SIZE;
826 }
827 dst->page_count = page_count;
828 dst->gtt_offset = src->gtt_offset;
829
830 return dst;
831
832 unwind:
833 while (page--)
834 free(dst->pages[page], DRM_I915_GEM);
835 free(dst, DRM_I915_GEM);
836 return NULL;
837 }
838
839 static void
i915_error_object_free(struct drm_i915_error_object * obj)840 i915_error_object_free(struct drm_i915_error_object *obj)
841 {
842 int page;
843
844 if (obj == NULL)
845 return;
846
847 for (page = 0; page < obj->page_count; page++)
848 free(obj->pages[page], DRM_I915_GEM);
849
850 free(obj, DRM_I915_GEM);
851 }
852
853 void
i915_error_state_free(struct drm_i915_error_state * error)854 i915_error_state_free(struct drm_i915_error_state *error)
855 {
856 int i;
857
858 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
859 i915_error_object_free(error->ring[i].batchbuffer);
860 i915_error_object_free(error->ring[i].ringbuffer);
861 free(error->ring[i].requests, DRM_I915_GEM);
862 }
863
864 free(error->active_bo, DRM_I915_GEM);
865 free(error->overlay, DRM_I915_GEM);
866 free(error, DRM_I915_GEM);
867 }
868
capture_bo(struct drm_i915_error_buffer * err,struct drm_i915_gem_object * obj)869 static void capture_bo(struct drm_i915_error_buffer *err,
870 struct drm_i915_gem_object *obj)
871 {
872 err->size = obj->base.size;
873 err->name = obj->base.name;
874 err->seqno = obj->last_rendering_seqno;
875 err->gtt_offset = obj->gtt_offset;
876 err->read_domains = obj->base.read_domains;
877 err->write_domain = obj->base.write_domain;
878 err->fence_reg = obj->fence_reg;
879 err->pinned = 0;
880 if (obj->pin_count > 0)
881 err->pinned = 1;
882 if (obj->user_pin_count > 0)
883 err->pinned = -1;
884 err->tiling = obj->tiling_mode;
885 err->dirty = obj->dirty;
886 err->purgeable = obj->madv != I915_MADV_WILLNEED;
887 err->ring = obj->ring ? obj->ring->id : -1;
888 err->cache_level = obj->cache_level;
889 }
890
capture_active_bo(struct drm_i915_error_buffer * err,int count,struct list_head * head)891 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
892 int count, struct list_head *head)
893 {
894 struct drm_i915_gem_object *obj;
895 int i = 0;
896
897 list_for_each_entry(obj, head, mm_list) {
898 capture_bo(err++, obj);
899 if (++i == count)
900 break;
901 }
902
903 return i;
904 }
905
capture_pinned_bo(struct drm_i915_error_buffer * err,int count,struct list_head * head)906 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
907 int count, struct list_head *head)
908 {
909 struct drm_i915_gem_object *obj;
910 int i = 0;
911
912 list_for_each_entry(obj, head, gtt_list) {
913 if (obj->pin_count == 0)
914 continue;
915
916 capture_bo(err++, obj);
917 if (++i == count)
918 break;
919 }
920
921 return i;
922 }
923
i915_gem_record_fences(struct drm_device * dev,struct drm_i915_error_state * error)924 static void i915_gem_record_fences(struct drm_device *dev,
925 struct drm_i915_error_state *error)
926 {
927 struct drm_i915_private *dev_priv = dev->dev_private;
928 int i;
929
930 /* Fences */
931 switch (INTEL_INFO(dev)->gen) {
932 case 7:
933 case 6:
934 for (i = 0; i < 16; i++)
935 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
936 break;
937 case 5:
938 case 4:
939 for (i = 0; i < 16; i++)
940 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
941 break;
942 case 3:
943 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
944 for (i = 0; i < 8; i++)
945 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
946 case 2:
947 for (i = 0; i < 8; i++)
948 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
949 break;
950
951 }
952 }
953
954 static struct drm_i915_error_object *
i915_error_first_batchbuffer(struct drm_i915_private * dev_priv,struct intel_ring_buffer * ring)955 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
956 struct intel_ring_buffer *ring)
957 {
958 struct drm_i915_gem_object *obj;
959 u32 seqno;
960
961 if (!ring->get_seqno)
962 return NULL;
963
964 seqno = ring->get_seqno(ring);
965 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
966 if (obj->ring != ring)
967 continue;
968
969 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
970 continue;
971
972 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
973 continue;
974
975 /* We need to copy these to an anonymous buffer as the simplest
976 * method to avoid being overwritten by userspace.
977 */
978 return i915_error_object_create(dev_priv, obj);
979 }
980
981 return NULL;
982 }
983
i915_record_ring_state(struct drm_device * dev,struct drm_i915_error_state * error,struct intel_ring_buffer * ring)984 static void i915_record_ring_state(struct drm_device *dev,
985 struct drm_i915_error_state *error,
986 struct intel_ring_buffer *ring)
987 {
988 struct drm_i915_private *dev_priv = dev->dev_private;
989
990 if (INTEL_INFO(dev)->gen >= 6) {
991 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
992 error->semaphore_mboxes[ring->id][0]
993 = I915_READ(RING_SYNC_0(ring->mmio_base));
994 error->semaphore_mboxes[ring->id][1]
995 = I915_READ(RING_SYNC_1(ring->mmio_base));
996 }
997
998 if (INTEL_INFO(dev)->gen >= 4) {
999 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1000 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1001 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1002 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1003 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1004 if (ring->id == RCS) {
1005 error->instdone1 = I915_READ(INSTDONE1);
1006 error->bbaddr = I915_READ64(BB_ADDR);
1007 }
1008 } else {
1009 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1010 error->ipeir[ring->id] = I915_READ(IPEIR);
1011 error->ipehr[ring->id] = I915_READ(IPEHR);
1012 error->instdone[ring->id] = I915_READ(INSTDONE);
1013 }
1014
1015 sleepq_lock(ring);
1016 error->waiting[ring->id] = sleepq_sleepcnt(ring, 0) != 0;
1017 sleepq_release(ring);
1018 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1019 error->seqno[ring->id] = ring->get_seqno(ring);
1020 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1021 error->head[ring->id] = I915_READ_HEAD(ring);
1022 error->tail[ring->id] = I915_READ_TAIL(ring);
1023
1024 error->cpu_ring_head[ring->id] = ring->head;
1025 error->cpu_ring_tail[ring->id] = ring->tail;
1026 }
1027
i915_gem_record_rings(struct drm_device * dev,struct drm_i915_error_state * error)1028 static void i915_gem_record_rings(struct drm_device *dev,
1029 struct drm_i915_error_state *error)
1030 {
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct intel_ring_buffer *ring;
1033 struct drm_i915_gem_request *request;
1034 int i, count;
1035
1036 for_each_ring(ring, dev_priv, i) {
1037 i915_record_ring_state(dev, error, ring);
1038
1039 error->ring[i].batchbuffer =
1040 i915_error_first_batchbuffer(dev_priv, ring);
1041
1042 error->ring[i].ringbuffer =
1043 i915_error_object_create(dev_priv, ring->obj);
1044
1045 count = 0;
1046 list_for_each_entry(request, &ring->request_list, list)
1047 count++;
1048
1049 error->ring[i].num_requests = count;
1050 error->ring[i].requests =
1051 malloc(count*sizeof(struct drm_i915_error_request),
1052 DRM_I915_GEM, M_WAITOK);
1053 if (error->ring[i].requests == NULL) {
1054 error->ring[i].num_requests = 0;
1055 continue;
1056 }
1057
1058 count = 0;
1059 list_for_each_entry(request, &ring->request_list, list) {
1060 struct drm_i915_error_request *erq;
1061
1062 erq = &error->ring[i].requests[count++];
1063 erq->seqno = request->seqno;
1064 erq->jiffies = request->emitted_jiffies;
1065 erq->tail = request->tail;
1066 }
1067 }
1068 }
1069
i915_capture_error_state(struct drm_device * dev)1070 static void i915_capture_error_state(struct drm_device *dev)
1071 {
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 struct drm_i915_gem_object *obj;
1074 struct drm_i915_error_state *error;
1075 int i, pipe;
1076
1077 mtx_lock(&dev_priv->error_lock);
1078 error = dev_priv->first_error;
1079 mtx_unlock(&dev_priv->error_lock);
1080 if (error)
1081 return;
1082
1083 /* Account for pipe specific data like PIPE*STAT */
1084 error = malloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT | M_ZERO);
1085 if (!error) {
1086 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1087 return;
1088 }
1089
1090 DRM_INFO("capturing error event; look for more information in sysctl hw.dri.%d.info.i915_error_state\n",
1091 dev->sysctl_node_idx);
1092
1093 refcount_init(&error->ref, 1);
1094 error->eir = I915_READ(EIR);
1095 error->pgtbl_er = I915_READ(PGTBL_ER);
1096
1097 if (HAS_PCH_SPLIT(dev))
1098 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1099 else if (IS_VALLEYVIEW(dev))
1100 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1101 else if (IS_GEN2(dev))
1102 error->ier = I915_READ16(IER);
1103 else
1104 error->ier = I915_READ(IER);
1105
1106 for_each_pipe(pipe)
1107 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1108
1109 if (INTEL_INFO(dev)->gen >= 6) {
1110 error->error = I915_READ(ERROR_GEN6);
1111 error->done_reg = I915_READ(DONE_REG);
1112 }
1113
1114 i915_gem_record_fences(dev, error);
1115 i915_gem_record_rings(dev, error);
1116
1117 /* Record buffers on the active and pinned lists. */
1118 error->active_bo = NULL;
1119 error->pinned_bo = NULL;
1120
1121 i = 0;
1122 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1123 i++;
1124 error->active_bo_count = i;
1125 list_for_each_entry(obj, &dev_priv->mm.gtt_list, mm_list)
1126 if (obj->pin_count)
1127 i++;
1128 error->pinned_bo_count = i - error->active_bo_count;
1129
1130 error->active_bo = NULL;
1131 error->pinned_bo = NULL;
1132 if (i) {
1133 error->active_bo = malloc(sizeof(*error->active_bo)*i,
1134 DRM_I915_GEM, M_NOWAIT);
1135 if (error->active_bo)
1136 error->pinned_bo =
1137 error->active_bo + error->active_bo_count;
1138 }
1139
1140 if (error->active_bo)
1141 error->active_bo_count =
1142 capture_active_bo(error->active_bo,
1143 error->active_bo_count,
1144 &dev_priv->mm.active_list);
1145
1146 if (error->pinned_bo)
1147 error->pinned_bo_count =
1148 capture_pinned_bo(error->pinned_bo,
1149 error->pinned_bo_count,
1150 &dev_priv->mm.gtt_list);
1151
1152 microtime(&error->time);
1153
1154 error->overlay = intel_overlay_capture_error_state(dev);
1155 error->display = intel_display_capture_error_state(dev);
1156
1157 mtx_lock(&dev_priv->error_lock);
1158 if (dev_priv->first_error == NULL) {
1159 dev_priv->first_error = error;
1160 error = NULL;
1161 }
1162 mtx_unlock(&dev_priv->error_lock);
1163
1164 if (error)
1165 i915_error_state_free(error);
1166 }
1167
i915_destroy_error_state(struct drm_device * dev)1168 void i915_destroy_error_state(struct drm_device *dev)
1169 {
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 struct drm_i915_error_state *error;
1172
1173 mtx_lock(&dev_priv->error_lock);
1174 error = dev_priv->first_error;
1175 dev_priv->first_error = NULL;
1176 mtx_unlock(&dev_priv->error_lock);
1177
1178 if (error && refcount_release(&error->ref))
1179 i915_error_state_free(error);
1180 }
1181
1182 #define pr_err(...) printf(__VA_ARGS__)
1183
i915_report_and_clear_eir(struct drm_device * dev)1184 static void i915_report_and_clear_eir(struct drm_device *dev)
1185 {
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 u32 eir = I915_READ(EIR);
1188 int pipe;
1189
1190 if (!eir)
1191 return;
1192
1193 printf("i915: render error detected, EIR: 0x%08x\n", eir);
1194
1195 if (IS_G4X(dev)) {
1196 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1197 u32 ipeir = I915_READ(IPEIR_I965);
1198
1199 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1200 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1201 pr_err(" INSTDONE: 0x%08x\n",
1202 I915_READ(INSTDONE_I965));
1203 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1204 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1205 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1206 I915_WRITE(IPEIR_I965, ipeir);
1207 POSTING_READ(IPEIR_I965);
1208 }
1209 if (eir & GM45_ERROR_PAGE_TABLE) {
1210 u32 pgtbl_err = I915_READ(PGTBL_ER);
1211 pr_err("page table error\n");
1212 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1213 I915_WRITE(PGTBL_ER, pgtbl_err);
1214 POSTING_READ(PGTBL_ER);
1215 }
1216 }
1217
1218 if (!IS_GEN2(dev)) {
1219 if (eir & I915_ERROR_PAGE_TABLE) {
1220 u32 pgtbl_err = I915_READ(PGTBL_ER);
1221 pr_err("page table error\n");
1222 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
1223 I915_WRITE(PGTBL_ER, pgtbl_err);
1224 POSTING_READ(PGTBL_ER);
1225 }
1226 }
1227
1228 if (eir & I915_ERROR_MEMORY_REFRESH) {
1229 pr_err("memory refresh error:\n");
1230 for_each_pipe(pipe)
1231 pr_err("pipe %c stat: 0x%08x\n",
1232 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1233 /* pipestat has already been acked */
1234 }
1235 if (eir & I915_ERROR_INSTRUCTION) {
1236 pr_err("instruction error\n");
1237 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
1238 if (INTEL_INFO(dev)->gen < 4) {
1239 u32 ipeir = I915_READ(IPEIR);
1240
1241 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1242 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1243 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1244 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
1245 I915_WRITE(IPEIR, ipeir);
1246 POSTING_READ(IPEIR);
1247 } else {
1248 u32 ipeir = I915_READ(IPEIR_I965);
1249
1250 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1251 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1252 pr_err(" INSTDONE: 0x%08x\n",
1253 I915_READ(INSTDONE_I965));
1254 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1255 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1256 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1257 I915_WRITE(IPEIR_I965, ipeir);
1258 POSTING_READ(IPEIR_I965);
1259 }
1260 }
1261
1262 I915_WRITE(EIR, eir);
1263 POSTING_READ(EIR);
1264 eir = I915_READ(EIR);
1265 if (eir) {
1266 /*
1267 * some errors might have become stuck,
1268 * mask them.
1269 */
1270 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1271 I915_WRITE(EMR, I915_READ(EMR) | eir);
1272 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1273 }
1274 }
1275
1276 /**
1277 * i915_handle_error - handle an error interrupt
1278 * @dev: drm device
1279 *
1280 * Do some basic checking of regsiter state at error interrupt time and
1281 * dump it to the syslog. Also call i915_capture_error_state() to make
1282 * sure we get a record and make it available in debugfs. Fire a uevent
1283 * so userspace knows something bad happened (should trigger collection
1284 * of a ring dump etc.).
1285 */
i915_handle_error(struct drm_device * dev,bool wedged)1286 void i915_handle_error(struct drm_device *dev, bool wedged)
1287 {
1288 struct drm_i915_private *dev_priv = dev->dev_private;
1289 struct intel_ring_buffer *ring;
1290 int i;
1291
1292 i915_capture_error_state(dev);
1293 i915_report_and_clear_eir(dev);
1294
1295 if (wedged) {
1296 mtx_lock(&dev_priv->error_completion_lock);
1297 dev_priv->error_completion = 0;
1298 dev_priv->mm.wedged = 1;
1299 /* unlock acts as rel barrier for store to wedged */
1300 mtx_unlock(&dev_priv->error_completion_lock);
1301
1302 /*
1303 * Wakeup waiting processes so they don't hang
1304 */
1305 for_each_ring(ring, dev_priv, i) {
1306 mtx_lock(&dev_priv->irq_lock);
1307 wakeup(ring);
1308 mtx_unlock(&dev_priv->irq_lock);
1309 }
1310 }
1311
1312 taskqueue_enqueue(dev_priv->tq, &dev_priv->error_task);
1313 }
1314
i915_pageflip_stall_check(struct drm_device * dev,int pipe)1315 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1316 {
1317 drm_i915_private_t *dev_priv = dev->dev_private;
1318 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1320 struct drm_i915_gem_object *obj;
1321 struct intel_unpin_work *work;
1322 bool stall_detected;
1323
1324 /* Ignore early vblank irqs */
1325 if (intel_crtc == NULL)
1326 return;
1327
1328 mtx_lock(&dev->event_lock);
1329 work = intel_crtc->unpin_work;
1330
1331 if (work == NULL ||
1332 work->pending ||
1333 !work->enable_stall_check) {
1334 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1335 mtx_unlock(&dev->event_lock);
1336 return;
1337 }
1338
1339 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1340 obj = work->pending_flip_obj;
1341 if (INTEL_INFO(dev)->gen >= 4) {
1342 int dspsurf = DSPSURF(intel_crtc->plane);
1343 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1344 obj->gtt_offset;
1345 } else {
1346 int dspaddr = DSPADDR(intel_crtc->plane);
1347 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1348 crtc->y * crtc->fb->pitches[0] +
1349 crtc->x * crtc->fb->bits_per_pixel/8);
1350 }
1351
1352 mtx_unlock(&dev->event_lock);
1353
1354 if (stall_detected) {
1355 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1356 intel_prepare_page_flip(dev, intel_crtc->plane);
1357 }
1358 }
1359
1360 /* Called from drm generic code, passed 'crtc' which
1361 * we use as a pipe index
1362 */
i915_enable_vblank(struct drm_device * dev,int pipe)1363 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1364 {
1365 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1366
1367 if (!i915_pipe_enabled(dev, pipe))
1368 return -EINVAL;
1369
1370 mtx_lock(&dev_priv->irq_lock);
1371 if (INTEL_INFO(dev)->gen >= 4)
1372 i915_enable_pipestat(dev_priv, pipe,
1373 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1374 else
1375 i915_enable_pipestat(dev_priv, pipe,
1376 PIPE_VBLANK_INTERRUPT_ENABLE);
1377
1378 /* maintain vblank delivery even in deep C-states */
1379 if (dev_priv->info->gen == 3)
1380 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1381 mtx_unlock(&dev_priv->irq_lock);
1382 CTR1(KTR_DRM, "i915_enable_vblank %d", pipe);
1383
1384 return 0;
1385 }
1386
ironlake_enable_vblank(struct drm_device * dev,int pipe)1387 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1388 {
1389 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1390
1391 if (!i915_pipe_enabled(dev, pipe))
1392 return -EINVAL;
1393
1394 mtx_lock(&dev_priv->irq_lock);
1395 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1396 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1397 mtx_unlock(&dev_priv->irq_lock);
1398 CTR1(KTR_DRM, "ironlake_enable_vblank %d", pipe);
1399
1400 return 0;
1401 }
1402
ivybridge_enable_vblank(struct drm_device * dev,int pipe)1403 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1404 {
1405 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1406
1407 if (!i915_pipe_enabled(dev, pipe))
1408 return -EINVAL;
1409
1410 mtx_lock(&dev_priv->irq_lock);
1411 ironlake_enable_display_irq(dev_priv,
1412 DE_PIPEA_VBLANK_IVB << (5 * pipe));
1413 mtx_unlock(&dev_priv->irq_lock);
1414 CTR1(KTR_DRM, "ivybridge_enable_vblank %d", pipe);
1415
1416 return 0;
1417 }
1418
valleyview_enable_vblank(struct drm_device * dev,int pipe)1419 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1420 {
1421 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1422 u32 dpfl, imr;
1423
1424 if (!i915_pipe_enabled(dev, pipe))
1425 return -EINVAL;
1426
1427 mtx_lock(&dev_priv->irq_lock);
1428 dpfl = I915_READ(VLV_DPFLIPSTAT);
1429 imr = I915_READ(VLV_IMR);
1430 if (pipe == 0) {
1431 dpfl |= PIPEA_VBLANK_INT_EN;
1432 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1433 } else {
1434 dpfl |= PIPEA_VBLANK_INT_EN;
1435 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1436 }
1437 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1438 I915_WRITE(VLV_IMR, imr);
1439 mtx_unlock(&dev_priv->irq_lock);
1440
1441 return 0;
1442 }
1443
1444 /* Called from drm generic code, passed 'crtc' which
1445 * we use as a pipe index
1446 */
i915_disable_vblank(struct drm_device * dev,int pipe)1447 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1448 {
1449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1450
1451 mtx_lock(&dev_priv->irq_lock);
1452 if (dev_priv->info->gen == 3)
1453 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1454
1455 i915_disable_pipestat(dev_priv, pipe,
1456 PIPE_VBLANK_INTERRUPT_ENABLE |
1457 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1458 mtx_unlock(&dev_priv->irq_lock);
1459 CTR1(KTR_DRM, "i915_disable_vblank %d", pipe);
1460 }
1461
ironlake_disable_vblank(struct drm_device * dev,int pipe)1462 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1463 {
1464 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1465
1466 mtx_lock(&dev_priv->irq_lock);
1467 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1468 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1469 mtx_unlock(&dev_priv->irq_lock);
1470 CTR1(KTR_DRM, "ironlake_disable_vblank %d", pipe);
1471 }
1472
ivybridge_disable_vblank(struct drm_device * dev,int pipe)1473 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1474 {
1475 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1476
1477 mtx_lock(&dev_priv->irq_lock);
1478 ironlake_disable_display_irq(dev_priv,
1479 DE_PIPEA_VBLANK_IVB << (pipe * 5));
1480 mtx_unlock(&dev_priv->irq_lock);
1481 CTR1(KTR_DRM, "ivybridge_disable_vblank %d", pipe);
1482 }
1483
valleyview_disable_vblank(struct drm_device * dev,int pipe)1484 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1485 {
1486 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1487 u32 dpfl, imr;
1488
1489 mtx_lock(&dev_priv->irq_lock);
1490 dpfl = I915_READ(VLV_DPFLIPSTAT);
1491 imr = I915_READ(VLV_IMR);
1492 if (pipe == 0) {
1493 dpfl &= ~PIPEA_VBLANK_INT_EN;
1494 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1495 } else {
1496 dpfl &= ~PIPEB_VBLANK_INT_EN;
1497 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1498 }
1499 I915_WRITE(VLV_IMR, imr);
1500 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1501 mtx_unlock(&dev_priv->irq_lock);
1502 }
1503
1504 static u32
ring_last_seqno(struct intel_ring_buffer * ring)1505 ring_last_seqno(struct intel_ring_buffer *ring)
1506 {
1507
1508 if (list_empty(&ring->request_list))
1509 return (0);
1510 else
1511 return (list_entry(ring->request_list.prev,
1512 struct drm_i915_gem_request, list)->seqno);
1513 }
1514
i915_hangcheck_ring_idle(struct intel_ring_buffer * ring,bool * err)1515 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1516 {
1517 if (list_empty(&ring->request_list) ||
1518 i915_seqno_passed(ring->get_seqno(ring),
1519 ring_last_seqno(ring))) {
1520 /* Issue a wake-up to catch stuck h/w. */
1521 sleepq_lock(ring);
1522 if (sleepq_sleepcnt(ring, 0) != 0) {
1523 sleepq_release(ring);
1524 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1525 ring->name);
1526 wakeup(ring);
1527 *err = true;
1528 } else
1529 sleepq_release(ring);
1530 return true;
1531 }
1532 return false;
1533 }
1534
kick_ring(struct intel_ring_buffer * ring)1535 static bool kick_ring(struct intel_ring_buffer *ring)
1536 {
1537 struct drm_device *dev = ring->dev;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 u32 tmp = I915_READ_CTL(ring);
1540 if (tmp & RING_WAIT) {
1541 DRM_ERROR("Kicking stuck wait on %s\n",
1542 ring->name);
1543 I915_WRITE_CTL(ring, tmp);
1544 return true;
1545 }
1546 return false;
1547 }
1548
i915_hangcheck_hung(struct drm_device * dev)1549 static bool i915_hangcheck_hung(struct drm_device *dev)
1550 {
1551 drm_i915_private_t *dev_priv = dev->dev_private;
1552
1553 if (dev_priv->hangcheck_count++ > 1) {
1554 bool hung = true;
1555
1556 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1557 i915_handle_error(dev, true);
1558
1559 if (!IS_GEN2(dev)) {
1560 struct intel_ring_buffer *ring;
1561 int i;
1562
1563 /* Is the chip hanging on a WAIT_FOR_EVENT?
1564 * If so we can simply poke the RB_WAIT bit
1565 * and break the hang. This should work on
1566 * all but the second generation chipsets.
1567 */
1568 for_each_ring(ring, dev_priv, i)
1569 hung &= !kick_ring(ring);
1570 }
1571
1572 return hung;
1573 }
1574
1575 return false;
1576 }
1577
1578 /**
1579 * This is called when the chip hasn't reported back with completed
1580 * batchbuffers in a long time. The first time this is called we simply record
1581 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1582 * again, we assume the chip is wedged and try to fix it.
1583 */
i915_hangcheck_elapsed(void * data)1584 void i915_hangcheck_elapsed(void *data)
1585 {
1586 struct drm_device *dev = (struct drm_device *)data;
1587 drm_i915_private_t *dev_priv = dev->dev_private;
1588 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1589 struct intel_ring_buffer *ring;
1590 bool err = false, idle;
1591 int i;
1592
1593 if (!i915_enable_hangcheck)
1594 return;
1595
1596 memset(acthd, 0, sizeof(acthd));
1597 idle = true;
1598 for_each_ring(ring, dev_priv, i) {
1599 idle &= i915_hangcheck_ring_idle(ring, &err);
1600 acthd[i] = intel_ring_get_active_head(ring);
1601 }
1602
1603 /* If all work is done then ACTHD clearly hasn't advanced. */
1604 if (idle) {
1605 if (err) {
1606 if (i915_hangcheck_hung(dev))
1607 return;
1608
1609 goto repeat;
1610 }
1611
1612 dev_priv->hangcheck_count = 0;
1613 return;
1614 }
1615
1616 if (INTEL_INFO(dev)->gen < 4) {
1617 instdone = I915_READ(INSTDONE);
1618 instdone1 = 0;
1619 } else {
1620 instdone = I915_READ(INSTDONE_I965);
1621 instdone1 = I915_READ(INSTDONE1);
1622 }
1623 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1624 dev_priv->last_instdone == instdone &&
1625 dev_priv->last_instdone1 == instdone1) {
1626 if (i915_hangcheck_hung(dev))
1627 return;
1628 } else {
1629 dev_priv->hangcheck_count = 0;
1630
1631 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1632 dev_priv->last_instdone = instdone;
1633 dev_priv->last_instdone1 = instdone1;
1634 }
1635
1636 repeat:
1637 /* Reset timer case chip hangs without another request being added */
1638 callout_schedule(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD);
1639 }
1640
1641 /* drm_dma.h hooks
1642 */
ironlake_irq_preinstall(struct drm_device * dev)1643 static void ironlake_irq_preinstall(struct drm_device *dev)
1644 {
1645 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1646
1647 atomic_set(&dev_priv->irq_received, 0);
1648
1649 I915_WRITE(HWSTAM, 0xeffe);
1650
1651 /* XXX hotplug from PCH */
1652
1653 I915_WRITE(DEIMR, 0xffffffff);
1654 I915_WRITE(DEIER, 0x0);
1655 POSTING_READ(DEIER);
1656
1657 /* and GT */
1658 I915_WRITE(GTIMR, 0xffffffff);
1659 I915_WRITE(GTIER, 0x0);
1660 POSTING_READ(GTIER);
1661
1662 /* south display irq */
1663 I915_WRITE(SDEIMR, 0xffffffff);
1664 I915_WRITE(SDEIER, 0x0);
1665 POSTING_READ(SDEIER);
1666 }
1667
valleyview_irq_preinstall(struct drm_device * dev)1668 static void valleyview_irq_preinstall(struct drm_device *dev)
1669 {
1670 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1671 int pipe;
1672
1673 atomic_set(&dev_priv->irq_received, 0);
1674
1675 /* VLV magic */
1676 I915_WRITE(VLV_IMR, 0);
1677 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1678 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1679 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1680
1681 /* and GT */
1682 I915_WRITE(GTIIR, I915_READ(GTIIR));
1683 I915_WRITE(GTIIR, I915_READ(GTIIR));
1684 I915_WRITE(GTIMR, 0xffffffff);
1685 I915_WRITE(GTIER, 0x0);
1686 POSTING_READ(GTIER);
1687
1688 I915_WRITE(DPINVGTT, 0xff);
1689
1690 I915_WRITE(PORT_HOTPLUG_EN, 0);
1691 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1692 for_each_pipe(pipe)
1693 I915_WRITE(PIPESTAT(pipe), 0xffff);
1694 I915_WRITE(VLV_IIR, 0xffffffff);
1695 I915_WRITE(VLV_IMR, 0xffffffff);
1696 I915_WRITE(VLV_IER, 0x0);
1697 POSTING_READ(VLV_IER);
1698 }
1699
1700 /*
1701 * Enable digital hotplug on the PCH, and configure the DP short pulse
1702 * duration to 2ms (which is the minimum in the Display Port spec)
1703 *
1704 * This register is the same on all known PCH chips.
1705 */
1706
ironlake_enable_pch_hotplug(struct drm_device * dev)1707 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1708 {
1709 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1710 u32 hotplug;
1711
1712 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1713 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1714 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1715 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1716 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1717 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1718 }
1719
ironlake_irq_postinstall(struct drm_device * dev)1720 static int ironlake_irq_postinstall(struct drm_device *dev)
1721 {
1722 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1723 /* enable kind of interrupts always enabled */
1724 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1725 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1726 u32 render_irqs;
1727 u32 hotplug_mask;
1728
1729 dev_priv->irq_mask = ~display_mask;
1730
1731 /* should always can generate irq */
1732 I915_WRITE(DEIIR, I915_READ(DEIIR));
1733 I915_WRITE(DEIMR, dev_priv->irq_mask);
1734 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1735 POSTING_READ(DEIER);
1736
1737 dev_priv->gt_irq_mask = ~0;
1738
1739 I915_WRITE(GTIIR, I915_READ(GTIIR));
1740 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1741
1742 if (IS_GEN6(dev))
1743 render_irqs =
1744 GT_USER_INTERRUPT |
1745 GEN6_BSD_USER_INTERRUPT |
1746 GEN6_BLITTER_USER_INTERRUPT;
1747 else
1748 render_irqs =
1749 GT_USER_INTERRUPT |
1750 GT_PIPE_NOTIFY |
1751 GT_BSD_USER_INTERRUPT;
1752 I915_WRITE(GTIER, render_irqs);
1753 POSTING_READ(GTIER);
1754
1755 if (HAS_PCH_CPT(dev)) {
1756 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1757 SDE_PORTB_HOTPLUG_CPT |
1758 SDE_PORTC_HOTPLUG_CPT |
1759 SDE_PORTD_HOTPLUG_CPT);
1760 } else {
1761 hotplug_mask = (SDE_CRT_HOTPLUG |
1762 SDE_PORTB_HOTPLUG |
1763 SDE_PORTC_HOTPLUG |
1764 SDE_PORTD_HOTPLUG |
1765 SDE_AUX_MASK);
1766 }
1767
1768 dev_priv->pch_irq_mask = ~hotplug_mask;
1769
1770 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1771 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1772 I915_WRITE(SDEIER, hotplug_mask);
1773 POSTING_READ(SDEIER);
1774
1775 ironlake_enable_pch_hotplug(dev);
1776
1777 if (IS_IRONLAKE_M(dev)) {
1778 /* Clear & enable PCU event interrupts */
1779 I915_WRITE(DEIIR, DE_PCU_EVENT);
1780 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1781 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1782 }
1783
1784 return 0;
1785 }
1786
ivybridge_irq_postinstall(struct drm_device * dev)1787 static int ivybridge_irq_postinstall(struct drm_device *dev)
1788 {
1789 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1790 /* enable kind of interrupts always enabled */
1791 u32 display_mask =
1792 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1793 DE_PLANEC_FLIP_DONE_IVB |
1794 DE_PLANEB_FLIP_DONE_IVB |
1795 DE_PLANEA_FLIP_DONE_IVB;
1796 u32 render_irqs;
1797 u32 hotplug_mask;
1798
1799 dev_priv->irq_mask = ~display_mask;
1800
1801 /* should always can generate irq */
1802 I915_WRITE(DEIIR, I915_READ(DEIIR));
1803 I915_WRITE(DEIMR, dev_priv->irq_mask);
1804 I915_WRITE(DEIER,
1805 display_mask |
1806 DE_PIPEC_VBLANK_IVB |
1807 DE_PIPEB_VBLANK_IVB |
1808 DE_PIPEA_VBLANK_IVB);
1809 POSTING_READ(DEIER);
1810
1811 dev_priv->gt_irq_mask = ~0;
1812
1813 I915_WRITE(GTIIR, I915_READ(GTIIR));
1814 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1815
1816 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1817 GEN6_BLITTER_USER_INTERRUPT;
1818 I915_WRITE(GTIER, render_irqs);
1819 POSTING_READ(GTIER);
1820
1821 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1822 SDE_PORTB_HOTPLUG_CPT |
1823 SDE_PORTC_HOTPLUG_CPT |
1824 SDE_PORTD_HOTPLUG_CPT);
1825 dev_priv->pch_irq_mask = ~hotplug_mask;
1826
1827 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1828 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1829 I915_WRITE(SDEIER, hotplug_mask);
1830 POSTING_READ(SDEIER);
1831
1832 ironlake_enable_pch_hotplug(dev);
1833
1834 return 0;
1835 }
1836
valleyview_irq_postinstall(struct drm_device * dev)1837 static int valleyview_irq_postinstall(struct drm_device *dev)
1838 {
1839 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1840 u32 render_irqs;
1841 u32 enable_mask;
1842 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1843 u16 msid;
1844
1845 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1846 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1847 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1848
1849 dev_priv->irq_mask = ~enable_mask;
1850
1851 dev_priv->pipestat[0] = 0;
1852 dev_priv->pipestat[1] = 0;
1853
1854 /* Hack for broken MSIs on VLV */
1855 pci_write_config(dev->dev, 0x94, 0xfee00000, 4);
1856 msid = pci_read_config(dev->dev, 0x98, 2);
1857 msid &= 0xff; /* mask out delivery bits */
1858 msid |= (1<<14);
1859 pci_write_config(dev->dev, 0x98, msid, 2);
1860
1861 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1862 I915_WRITE(VLV_IER, enable_mask);
1863 I915_WRITE(VLV_IIR, 0xffffffff);
1864 I915_WRITE(PIPESTAT(0), 0xffff);
1865 I915_WRITE(PIPESTAT(1), 0xffff);
1866 POSTING_READ(VLV_IER);
1867
1868 I915_WRITE(VLV_IIR, 0xffffffff);
1869 I915_WRITE(VLV_IIR, 0xffffffff);
1870
1871 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1872 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1873 GT_GEN6_BLT_USER_INTERRUPT |
1874 GT_GEN6_BSD_USER_INTERRUPT |
1875 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1876 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1877 GT_PIPE_NOTIFY |
1878 GT_RENDER_CS_ERROR_INTERRUPT |
1879 GT_SYNC_STATUS |
1880 GT_USER_INTERRUPT;
1881
1882 dev_priv->gt_irq_mask = ~render_irqs;
1883
1884 I915_WRITE(GTIIR, I915_READ(GTIIR));
1885 I915_WRITE(GTIIR, I915_READ(GTIIR));
1886 I915_WRITE(GTIMR, 0);
1887 I915_WRITE(GTIER, render_irqs);
1888 POSTING_READ(GTIER);
1889
1890 /* ack & enable invalid PTE error interrupts */
1891 #if 0 /* FIXME: add support to irq handler for checking these bits */
1892 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1893 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1894 #endif
1895
1896 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1897 #if 0 /* FIXME: check register definitions; some have moved */
1898 /* Note HDMI and DP share bits */
1899 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1900 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1901 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1902 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1903 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1904 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1905 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1906 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1907 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1908 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1909 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1910 hotplug_en |= CRT_HOTPLUG_INT_EN;
1911 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1912 }
1913 #endif
1914
1915 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1916
1917 return 0;
1918 }
1919
valleyview_irq_uninstall(struct drm_device * dev)1920 static void valleyview_irq_uninstall(struct drm_device *dev)
1921 {
1922 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1923 int pipe;
1924
1925 if (!dev_priv)
1926 return;
1927
1928 for_each_pipe(pipe)
1929 I915_WRITE(PIPESTAT(pipe), 0xffff);
1930
1931 I915_WRITE(HWSTAM, 0xffffffff);
1932 I915_WRITE(PORT_HOTPLUG_EN, 0);
1933 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1934 for_each_pipe(pipe)
1935 I915_WRITE(PIPESTAT(pipe), 0xffff);
1936 I915_WRITE(VLV_IIR, 0xffffffff);
1937 I915_WRITE(VLV_IMR, 0xffffffff);
1938 I915_WRITE(VLV_IER, 0x0);
1939 POSTING_READ(VLV_IER);
1940 }
1941
ironlake_irq_uninstall(struct drm_device * dev)1942 static void ironlake_irq_uninstall(struct drm_device *dev)
1943 {
1944 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1945
1946 if (!dev_priv)
1947 return;
1948
1949 I915_WRITE(HWSTAM, 0xffffffff);
1950
1951 I915_WRITE(DEIMR, 0xffffffff);
1952 I915_WRITE(DEIER, 0x0);
1953 I915_WRITE(DEIIR, I915_READ(DEIIR));
1954
1955 I915_WRITE(GTIMR, 0xffffffff);
1956 I915_WRITE(GTIER, 0x0);
1957 I915_WRITE(GTIIR, I915_READ(GTIIR));
1958
1959 I915_WRITE(SDEIMR, 0xffffffff);
1960 I915_WRITE(SDEIER, 0x0);
1961 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1962 }
1963
i8xx_irq_preinstall(struct drm_device * dev)1964 static void i8xx_irq_preinstall(struct drm_device * dev)
1965 {
1966 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1967 int pipe;
1968
1969 atomic_set(&dev_priv->irq_received, 0);
1970
1971 for_each_pipe(pipe)
1972 I915_WRITE(PIPESTAT(pipe), 0);
1973 I915_WRITE16(IMR, 0xffff);
1974 I915_WRITE16(IER, 0x0);
1975 POSTING_READ16(IER);
1976 }
1977
i8xx_irq_postinstall(struct drm_device * dev)1978 static int i8xx_irq_postinstall(struct drm_device *dev)
1979 {
1980 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1981
1982 dev_priv->pipestat[0] = 0;
1983 dev_priv->pipestat[1] = 0;
1984
1985 I915_WRITE16(EMR,
1986 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1987
1988 /* Unmask the interrupts that we always want on. */
1989 dev_priv->irq_mask =
1990 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1991 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1992 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1993 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
1994 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1995 I915_WRITE16(IMR, dev_priv->irq_mask);
1996
1997 I915_WRITE16(IER,
1998 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1999 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2000 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2001 I915_USER_INTERRUPT);
2002 POSTING_READ16(IER);
2003
2004 return 0;
2005 }
2006
i8xx_irq_handler(DRM_IRQ_ARGS)2007 static void i8xx_irq_handler(DRM_IRQ_ARGS)
2008 {
2009 struct drm_device *dev = (struct drm_device *) arg;
2010 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2011 u16 iir, new_iir;
2012 u32 pipe_stats[2];
2013 int irq_received;
2014 int pipe;
2015 u16 flip_mask =
2016 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2017 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2018
2019 atomic_inc(&dev_priv->irq_received);
2020
2021 iir = I915_READ16(IIR);
2022 if (iir == 0)
2023 return;
2024
2025 while (iir & ~flip_mask) {
2026 /* Can't rely on pipestat interrupt bit in iir as it might
2027 * have been cleared after the pipestat interrupt was received.
2028 * It doesn't set the bit in iir again, but it still produces
2029 * interrupts (for non-MSI).
2030 */
2031 mtx_lock(&dev_priv->irq_lock);
2032 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2033 i915_handle_error(dev, false);
2034
2035 for_each_pipe(pipe) {
2036 int reg = PIPESTAT(pipe);
2037 pipe_stats[pipe] = I915_READ(reg);
2038
2039 /*
2040 * Clear the PIPE*STAT regs before the IIR
2041 */
2042 if (pipe_stats[pipe] & 0x8000ffff) {
2043 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2044 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2045 pipe_name(pipe));
2046 I915_WRITE(reg, pipe_stats[pipe]);
2047 irq_received = 1;
2048 }
2049 }
2050 mtx_unlock(&dev_priv->irq_lock);
2051
2052 I915_WRITE16(IIR, iir & ~flip_mask);
2053 new_iir = I915_READ16(IIR); /* Flush posted writes */
2054
2055 i915_update_dri1_breadcrumb(dev);
2056
2057 if (iir & I915_USER_INTERRUPT)
2058 notify_ring(dev, &dev_priv->rings[RCS]);
2059
2060 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2061 drm_handle_vblank(dev, 0)) {
2062 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2063 intel_prepare_page_flip(dev, 0);
2064 intel_finish_page_flip(dev, 0);
2065 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2066 }
2067 }
2068
2069 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2070 drm_handle_vblank(dev, 1)) {
2071 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2072 intel_prepare_page_flip(dev, 1);
2073 intel_finish_page_flip(dev, 1);
2074 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2075 }
2076 }
2077
2078 iir = new_iir;
2079 }
2080 }
2081
i8xx_irq_uninstall(struct drm_device * dev)2082 static void i8xx_irq_uninstall(struct drm_device * dev)
2083 {
2084 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2085 int pipe;
2086
2087 for_each_pipe(pipe) {
2088 /* Clear enable bits; then clear status bits */
2089 I915_WRITE(PIPESTAT(pipe), 0);
2090 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2091 }
2092 I915_WRITE16(IMR, 0xffff);
2093 I915_WRITE16(IER, 0x0);
2094 I915_WRITE16(IIR, I915_READ16(IIR));
2095 }
2096
i915_irq_preinstall(struct drm_device * dev)2097 static void i915_irq_preinstall(struct drm_device * dev)
2098 {
2099 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2100 int pipe;
2101
2102 atomic_set(&dev_priv->irq_received, 0);
2103
2104 if (I915_HAS_HOTPLUG(dev)) {
2105 I915_WRITE(PORT_HOTPLUG_EN, 0);
2106 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2107 }
2108
2109 I915_WRITE16(HWSTAM, 0xeffe);
2110 for_each_pipe(pipe)
2111 I915_WRITE(PIPESTAT(pipe), 0);
2112 I915_WRITE(IMR, 0xffffffff);
2113 I915_WRITE(IER, 0x0);
2114 POSTING_READ(IER);
2115 }
2116
i915_irq_postinstall(struct drm_device * dev)2117 static int i915_irq_postinstall(struct drm_device *dev)
2118 {
2119 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2120 u32 enable_mask;
2121
2122 dev_priv->pipestat[0] = 0;
2123 dev_priv->pipestat[1] = 0;
2124
2125 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2126
2127 /* Unmask the interrupts that we always want on. */
2128 dev_priv->irq_mask =
2129 ~(I915_ASLE_INTERRUPT |
2130 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2131 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2132 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2133 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2134 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2135
2136 enable_mask =
2137 I915_ASLE_INTERRUPT |
2138 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2139 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2140 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2141 I915_USER_INTERRUPT;
2142
2143 if (I915_HAS_HOTPLUG(dev)) {
2144 /* Enable in IER... */
2145 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2146 /* and unmask in IMR */
2147 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2148 }
2149
2150 I915_WRITE(IMR, dev_priv->irq_mask);
2151 I915_WRITE(IER, enable_mask);
2152 POSTING_READ(IER);
2153
2154 if (I915_HAS_HOTPLUG(dev)) {
2155 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2156
2157 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2158 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2159 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2160 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2161 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2162 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2163 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2164 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2165 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2166 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2167 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2168 hotplug_en |= CRT_HOTPLUG_INT_EN;
2169 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2170 }
2171
2172 /* Ignore TV since it's buggy */
2173
2174 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2175 }
2176
2177 intel_opregion_enable_asle(dev);
2178
2179 return 0;
2180 }
2181
i915_irq_handler(DRM_IRQ_ARGS)2182 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2183 {
2184 struct drm_device *dev = (struct drm_device *) arg;
2185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2186 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2187 u32 flip_mask =
2188 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2189 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2190 u32 flip[2] = {
2191 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2192 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2193 };
2194 int pipe;
2195
2196 atomic_inc(&dev_priv->irq_received);
2197
2198 iir = I915_READ(IIR);
2199 do {
2200 bool irq_received = (iir & ~flip_mask) != 0;
2201 bool blc_event = false;
2202
2203 /* Can't rely on pipestat interrupt bit in iir as it might
2204 * have been cleared after the pipestat interrupt was received.
2205 * It doesn't set the bit in iir again, but it still produces
2206 * interrupts (for non-MSI).
2207 */
2208 mtx_lock(&dev_priv->irq_lock);
2209 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2210 i915_handle_error(dev, false);
2211
2212 for_each_pipe(pipe) {
2213 int reg = PIPESTAT(pipe);
2214 pipe_stats[pipe] = I915_READ(reg);
2215
2216 /* Clear the PIPE*STAT regs before the IIR */
2217 if (pipe_stats[pipe] & 0x8000ffff) {
2218 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2219 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2220 pipe_name(pipe));
2221 I915_WRITE(reg, pipe_stats[pipe]);
2222 irq_received = true;
2223 }
2224 }
2225 mtx_unlock(&dev_priv->irq_lock);
2226
2227 if (!irq_received)
2228 break;
2229
2230 /* Consume port. Then clear IIR or we'll miss events */
2231 if ((I915_HAS_HOTPLUG(dev)) &&
2232 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2233 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2234
2235 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2236 hotplug_status);
2237 if (hotplug_status & dev_priv->hotplug_supported_mask)
2238 taskqueue_enqueue(dev_priv->tq,
2239 &dev_priv->hotplug_task);
2240
2241 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2242 POSTING_READ(PORT_HOTPLUG_STAT);
2243 }
2244
2245 I915_WRITE(IIR, iir & ~flip_mask);
2246 new_iir = I915_READ(IIR); /* Flush posted writes */
2247
2248 if (iir & I915_USER_INTERRUPT)
2249 notify_ring(dev, &dev_priv->rings[RCS]);
2250
2251 for_each_pipe(pipe) {
2252 int plane = pipe;
2253 if (IS_MOBILE(dev))
2254 plane = !plane;
2255 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2256 drm_handle_vblank(dev, pipe)) {
2257 if (iir & flip[plane]) {
2258 intel_prepare_page_flip(dev, plane);
2259 intel_finish_page_flip(dev, pipe);
2260 flip_mask &= ~flip[plane];
2261 }
2262 }
2263
2264 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2265 blc_event = true;
2266 }
2267
2268 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2269 intel_opregion_asle_intr(dev);
2270
2271
2272 /* With MSI, interrupts are only generated when iir
2273 * transitions from zero to nonzero. If another bit got
2274 * set while we were handling the existing iir bits, then
2275 * we would never get another interrupt.
2276 *
2277 * This is fine on non-MSI as well, as if we hit this path
2278 * we avoid exiting the interrupt handler only to generate
2279 * another one.
2280 *
2281 * Note that for MSI this could cause a stray interrupt report
2282 * if an interrupt landed in the time between writing IIR and
2283 * the posting read. This should be rare enough to never
2284 * trigger the 99% of 100,000 interrupts test for disabling
2285 * stray interrupts.
2286 */
2287 iir = new_iir;
2288 } while (iir & ~flip_mask);
2289
2290 i915_update_dri1_breadcrumb(dev);
2291 }
2292
i915_irq_uninstall(struct drm_device * dev)2293 static void i915_irq_uninstall(struct drm_device * dev)
2294 {
2295 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2296 int pipe;
2297
2298 if (!dev_priv)
2299 return;
2300
2301 if (I915_HAS_HOTPLUG(dev)) {
2302 I915_WRITE(PORT_HOTPLUG_EN, 0);
2303 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2304 }
2305
2306 I915_WRITE16(HWSTAM, 0xffff);
2307 for_each_pipe(pipe) {
2308 /* Clear enable bits; then clear status bits */
2309 I915_WRITE(PIPESTAT(pipe), 0);
2310 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2311 }
2312 I915_WRITE(IMR, 0xffffffff);
2313 I915_WRITE(IER, 0x0);
2314
2315 I915_WRITE(IIR, I915_READ(IIR));
2316 }
2317
i965_irq_preinstall(struct drm_device * dev)2318 static void i965_irq_preinstall(struct drm_device * dev)
2319 {
2320 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2321 int pipe;
2322
2323 atomic_set(&dev_priv->irq_received, 0);
2324
2325 if (I915_HAS_HOTPLUG(dev)) {
2326 I915_WRITE(PORT_HOTPLUG_EN, 0);
2327 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2328 }
2329
2330 I915_WRITE(HWSTAM, 0xeffe);
2331 for_each_pipe(pipe)
2332 I915_WRITE(PIPESTAT(pipe), 0);
2333 I915_WRITE(IMR, 0xffffffff);
2334 I915_WRITE(IER, 0x0);
2335 POSTING_READ(IER);
2336 }
2337
i965_irq_postinstall(struct drm_device * dev)2338 static int i965_irq_postinstall(struct drm_device *dev)
2339 {
2340 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2341 u32 enable_mask;
2342 u32 error_mask;
2343
2344 /* Unmask the interrupts that we always want on. */
2345 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2346 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2347 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2348 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2349 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2350 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2351
2352 enable_mask = ~dev_priv->irq_mask;
2353 enable_mask |= I915_USER_INTERRUPT;
2354
2355 if (IS_G4X(dev))
2356 enable_mask |= I915_BSD_USER_INTERRUPT;
2357
2358 dev_priv->pipestat[0] = 0;
2359 dev_priv->pipestat[1] = 0;
2360
2361 if (I915_HAS_HOTPLUG(dev)) {
2362 /* Enable in IER... */
2363 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2364 /* and unmask in IMR */
2365 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2366 }
2367
2368 /*
2369 * Enable some error detection, note the instruction error mask
2370 * bit is reserved, so we leave it masked.
2371 */
2372 if (IS_G4X(dev)) {
2373 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2374 GM45_ERROR_MEM_PRIV |
2375 GM45_ERROR_CP_PRIV |
2376 I915_ERROR_MEMORY_REFRESH);
2377 } else {
2378 error_mask = ~(I915_ERROR_PAGE_TABLE |
2379 I915_ERROR_MEMORY_REFRESH);
2380 }
2381 I915_WRITE(EMR, error_mask);
2382
2383 I915_WRITE(IMR, dev_priv->irq_mask);
2384 I915_WRITE(IER, enable_mask);
2385 POSTING_READ(IER);
2386
2387 if (I915_HAS_HOTPLUG(dev)) {
2388 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2389
2390 /* Note HDMI and DP share bits */
2391 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2392 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2393 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2394 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2395 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2396 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2397 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2398 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2399 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2400 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2401 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2402 hotplug_en |= CRT_HOTPLUG_INT_EN;
2403
2404 /* Programming the CRT detection parameters tends
2405 to generate a spurious hotplug event about three
2406 seconds later. So just do it once.
2407 */
2408 if (IS_G4X(dev))
2409 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2410 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2411 }
2412
2413 /* Ignore TV since it's buggy */
2414
2415 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2416 }
2417
2418 intel_opregion_enable_asle(dev);
2419
2420 return 0;
2421 }
2422
i965_irq_handler(DRM_IRQ_ARGS)2423 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2424 {
2425 struct drm_device *dev = (struct drm_device *) arg;
2426 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2427 u32 iir, new_iir;
2428 u32 pipe_stats[I915_MAX_PIPES];
2429 int irq_received;
2430 int pipe;
2431
2432 atomic_inc(&dev_priv->irq_received);
2433
2434 iir = I915_READ(IIR);
2435
2436 for (;;) {
2437 bool blc_event = false;
2438
2439 irq_received = iir != 0;
2440
2441 /* Can't rely on pipestat interrupt bit in iir as it might
2442 * have been cleared after the pipestat interrupt was received.
2443 * It doesn't set the bit in iir again, but it still produces
2444 * interrupts (for non-MSI).
2445 */
2446 mtx_lock(&dev_priv->irq_lock);
2447 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2448 i915_handle_error(dev, false);
2449
2450 for_each_pipe(pipe) {
2451 int reg = PIPESTAT(pipe);
2452 pipe_stats[pipe] = I915_READ(reg);
2453
2454 /*
2455 * Clear the PIPE*STAT regs before the IIR
2456 */
2457 if (pipe_stats[pipe] & 0x8000ffff) {
2458 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2459 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2460 pipe_name(pipe));
2461 I915_WRITE(reg, pipe_stats[pipe]);
2462 irq_received = 1;
2463 }
2464 }
2465 mtx_unlock(&dev_priv->irq_lock);
2466
2467 if (!irq_received)
2468 break;
2469
2470 /* Consume port. Then clear IIR or we'll miss events */
2471 if ((I915_HAS_HOTPLUG(dev)) &&
2472 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2473 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2474
2475 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2476 hotplug_status);
2477 if (hotplug_status & dev_priv->hotplug_supported_mask)
2478 taskqueue_enqueue(dev_priv->tq,
2479 &dev_priv->hotplug_task);
2480
2481 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2482 I915_READ(PORT_HOTPLUG_STAT);
2483 }
2484
2485 I915_WRITE(IIR, iir);
2486 new_iir = I915_READ(IIR); /* Flush posted writes */
2487
2488 if (iir & I915_USER_INTERRUPT)
2489 notify_ring(dev, &dev_priv->rings[RCS]);
2490 if (iir & I915_BSD_USER_INTERRUPT)
2491 notify_ring(dev, &dev_priv->rings[VCS]);
2492
2493 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2494 intel_prepare_page_flip(dev, 0);
2495
2496 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2497 intel_prepare_page_flip(dev, 1);
2498
2499 for_each_pipe(pipe) {
2500 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2501 drm_handle_vblank(dev, pipe)) {
2502 i915_pageflip_stall_check(dev, pipe);
2503 intel_finish_page_flip(dev, pipe);
2504 }
2505
2506 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2507 blc_event = true;
2508 }
2509
2510
2511 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2512 intel_opregion_asle_intr(dev);
2513
2514 /* With MSI, interrupts are only generated when iir
2515 * transitions from zero to nonzero. If another bit got
2516 * set while we were handling the existing iir bits, then
2517 * we would never get another interrupt.
2518 *
2519 * This is fine on non-MSI as well, as if we hit this path
2520 * we avoid exiting the interrupt handler only to generate
2521 * another one.
2522 *
2523 * Note that for MSI this could cause a stray interrupt report
2524 * if an interrupt landed in the time between writing IIR and
2525 * the posting read. This should be rare enough to never
2526 * trigger the 99% of 100,000 interrupts test for disabling
2527 * stray interrupts.
2528 */
2529 iir = new_iir;
2530 }
2531
2532 i915_update_dri1_breadcrumb(dev);
2533 }
2534
i965_irq_uninstall(struct drm_device * dev)2535 static void i965_irq_uninstall(struct drm_device * dev)
2536 {
2537 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2538 int pipe;
2539
2540 if (I915_HAS_HOTPLUG(dev)) {
2541 I915_WRITE(PORT_HOTPLUG_EN, 0);
2542 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2543 }
2544
2545 I915_WRITE(HWSTAM, 0xffffffff);
2546 for_each_pipe(pipe)
2547 I915_WRITE(PIPESTAT(pipe), 0);
2548 I915_WRITE(IMR, 0xffffffff);
2549 I915_WRITE(IER, 0x0);
2550
2551 for_each_pipe(pipe)
2552 I915_WRITE(PIPESTAT(pipe),
2553 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2554 I915_WRITE(IIR, I915_READ(IIR));
2555 }
2556
intel_irq_init(struct drm_device * dev)2557 void intel_irq_init(struct drm_device *dev)
2558 {
2559 struct drm_i915_private *dev_priv = dev->dev_private;
2560
2561 TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func,
2562 dev->dev_private);
2563 TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func,
2564 dev->dev_private);
2565 TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work,
2566 dev->dev_private);
2567
2568 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2569 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2570 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2571 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2572 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2573 }
2574 if (drm_core_check_feature(dev, DRIVER_MODESET))
2575 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2576 else
2577 dev->driver->get_vblank_timestamp = NULL;
2578 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2579
2580 if (IS_VALLEYVIEW(dev)) {
2581 dev->driver->irq_handler = valleyview_irq_handler;
2582 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2583 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2584 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2585 dev->driver->enable_vblank = valleyview_enable_vblank;
2586 dev->driver->disable_vblank = valleyview_disable_vblank;
2587 } else if (IS_IVYBRIDGE(dev)) {
2588 /* Share pre & uninstall handlers with ILK/SNB */
2589 dev->driver->irq_handler = ivybridge_irq_handler;
2590 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2591 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2592 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2593 dev->driver->enable_vblank = ivybridge_enable_vblank;
2594 dev->driver->disable_vblank = ivybridge_disable_vblank;
2595 } else if (IS_HASWELL(dev)) {
2596 /* Share interrupts handling with IVB */
2597 dev->driver->irq_handler = ivybridge_irq_handler;
2598 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2599 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2600 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2601 dev->driver->enable_vblank = ivybridge_enable_vblank;
2602 dev->driver->disable_vblank = ivybridge_disable_vblank;
2603 } else if (HAS_PCH_SPLIT(dev)) {
2604 dev->driver->irq_handler = ironlake_irq_handler;
2605 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2606 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2607 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2608 dev->driver->enable_vblank = ironlake_enable_vblank;
2609 dev->driver->disable_vblank = ironlake_disable_vblank;
2610 } else {
2611 if (INTEL_INFO(dev)->gen == 2) {
2612 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2613 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2614 dev->driver->irq_handler = i8xx_irq_handler;
2615 dev->driver->irq_uninstall = i8xx_irq_uninstall;
2616 } else if (INTEL_INFO(dev)->gen == 3) {
2617 /* IIR "flip pending" means done if this bit is set */
2618 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2619
2620 dev->driver->irq_preinstall = i915_irq_preinstall;
2621 dev->driver->irq_postinstall = i915_irq_postinstall;
2622 dev->driver->irq_uninstall = i915_irq_uninstall;
2623 dev->driver->irq_handler = i915_irq_handler;
2624 } else {
2625 dev->driver->irq_preinstall = i965_irq_preinstall;
2626 dev->driver->irq_postinstall = i965_irq_postinstall;
2627 dev->driver->irq_uninstall = i965_irq_uninstall;
2628 dev->driver->irq_handler = i965_irq_handler;
2629 }
2630 dev->driver->enable_vblank = i915_enable_vblank;
2631 dev->driver->disable_vblank = i915_disable_vblank;
2632 }
2633 }
2634