1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Interface definition for SIRegisterInfo 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H 17 #define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H 18 19 #include "AMDGPURegisterInfo.h" 20 #include "AMDGPUSubtarget.h" 21 #include "llvm/Support/Debug.h" 22 23 namespace llvm { 24 25 struct SIRegisterInfo : public AMDGPURegisterInfo { 26 private: 27 void reserveRegisterTuples(BitVector &, unsigned Reg) const; 28 29 public: 30 SIRegisterInfo(); 31 32 BitVector getReservedRegs(const MachineFunction &MF) const override; 33 34 unsigned getRegPressureSetLimit(const MachineFunction &MF, 35 unsigned Idx) const override; 36 37 bool requiresRegisterScavenging(const MachineFunction &Fn) const override; 38 39 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 40 unsigned FIOperandNum, 41 RegScavenger *RS) const override; 42 43 /// \brief get the register class of the specified type to use in the 44 /// CFGStructurizer 45 const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override; 46 47 unsigned getHWRegIndex(unsigned Reg) const override; 48 49 /// \brief Return the 'base' register class for this register. 50 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc. 51 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const; 52 53 /// \returns true if this class contains only SGPR registers isSGPRClassSIRegisterInfo54 bool isSGPRClass(const TargetRegisterClass *RC) const { 55 if (!RC) 56 return false; 57 58 return !hasVGPRs(RC); 59 } 60 61 /// \returns true if this class ID contains only SGPR registers isSGPRClassIDSIRegisterInfo62 bool isSGPRClassID(unsigned RCID) const { 63 if (static_cast<int>(RCID) == -1) 64 return false; 65 66 return isSGPRClass(getRegClass(RCID)); 67 } 68 69 /// \returns true if this class contains VGPR registers. 70 bool hasVGPRs(const TargetRegisterClass *RC) const; 71 72 /// \returns A VGPR reg class with the same width as \p SRC 73 const TargetRegisterClass *getEquivalentVGPRClass( 74 const TargetRegisterClass *SRC) const; 75 76 /// \returns The register class that is used for a sub-register of \p RC for 77 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will 78 /// be returned. 79 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC, 80 unsigned SubIdx) const; 81 82 /// \p Channel This is the register channel (e.g. a value from 0-16), not the 83 /// SubReg index. 84 /// \returns The sub-register of Reg that is in Channel. 85 unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC, 86 unsigned Channel) const; 87 88 /// \returns True if operands defined with this operand type can accept 89 /// a literal constant (i.e. any 32-bit immediate). 90 bool opCanUseLiteralConstant(unsigned OpType) const; 91 92 /// \returns True if operands defined with this operand type can accept 93 /// an inline constant. i.e. An integer value in the range (-16, 64) or 94 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f. 95 bool opCanUseInlineConstant(unsigned OpType) const; 96 97 enum PreloadedValue { 98 TGID_X, 99 TGID_Y, 100 TGID_Z, 101 SCRATCH_WAVE_OFFSET, 102 SCRATCH_PTR, 103 INPUT_PTR, 104 TIDIG_X, 105 TIDIG_Y, 106 TIDIG_Z 107 }; 108 109 /// \brief Returns the physical register that \p Value is stored in. 110 unsigned getPreloadedValue(const MachineFunction &MF, 111 enum PreloadedValue Value) const; 112 113 /// \brief Give the maximum number of VGPRs that can be used by \p WaveCount 114 /// concurrent waves. 115 unsigned getNumVGPRsAllowed(unsigned WaveCount) const; 116 117 /// \brief Give the maximum number of SGPRs that can be used by \p WaveCount 118 /// concurrent waves. 119 unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen, 120 unsigned WaveCount) const; 121 122 unsigned findUnusedRegister(const MachineRegisterInfo &MRI, 123 const TargetRegisterClass *RC) const; 124 125 private: 126 void buildScratchLoadStore(MachineBasicBlock::iterator MI, 127 unsigned LoadStoreOp, unsigned Value, 128 unsigned ScratchRsrcReg, unsigned ScratchOffset, 129 int64_t Offset, RegScavenger *RS) const; 130 }; 131 132 } // End namespace llvm 133 134 #endif 135