1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2024 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
6 Support.
7
8 This file is part of GAS.
9
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 02110-1301, USA. */
24
25 #include "as.h"
26 #include "config.h"
27 #include "subsegs.h"
28 #include "safe-ctype.h"
29
30 #include "opcode/mips.h"
31 #include "itbl-ops.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
34
35 /* Check assumptions made in this file. */
36 typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1];
37 typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1];
38
39 #ifdef DEBUG
40 #define DBG(x) printf x
41 #else
42 #define DBG(x)
43 #endif
44
45 #define streq(a, b) (strcmp (a, b) == 0)
46
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
49
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
mips_output_flavor(void)52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
53 #undef OBJ_PROCESS_STAB
54 #undef OUTPUT_FLAVOR
55 #undef S_GET_ALIGN
56 #undef S_GET_SIZE
57 #undef S_SET_ALIGN
58 #undef S_SET_SIZE
59 #undef obj_frob_file
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
62 #undef obj_pop_insert
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65
66 #include "obj-elf.h"
67 /* Fix any of them that we actually care about. */
68 #undef OUTPUT_FLAVOR
69 #define OUTPUT_FLAVOR mips_output_flavor()
70
71 #include "elf/mips.h"
72
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
76 #endif
77
78 int mips_flag_mdebug = -1;
79
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
83 #ifdef TE_IRIX
84 int mips_flag_pdr = false;
85 #else
86 int mips_flag_pdr = true;
87 #endif
88
89 #include "ecoff.h"
90
91 static char *mips_regmask_frag;
92 static char *mips_flags_frag;
93
94 #define ZERO 0
95 #define ATREG 1
96 #define S0 16
97 #define S7 23
98 #define TREG 24
99 #define PIC_CALL_REG 25
100 #define KT0 26
101 #define KT1 27
102 #define GP 28
103 #define SP 29
104 #define FP 30
105 #define RA 31
106
107 #define FCSR 31
108
109 #define ILLEGAL_REG (32)
110
111 #define AT mips_opts.at
112
113 extern int target_big_endian;
114
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME ".rodata"
117
118 /* Ways in which an instruction can be "appended" to the output. */
119 enum append_method {
120 /* Just add it normally. */
121 APPEND_ADD,
122
123 /* Add it normally and then add a nop. */
124 APPEND_ADD_WITH_NOP,
125
126 /* Turn an instruction with a delay slot into a "compact" version. */
127 APPEND_ADD_COMPACT,
128
129 /* Insert the instruction before the last one. */
130 APPEND_SWAP
131 };
132
133 /* Information about an instruction, including its format, operands
134 and fixups. */
135 struct mips_cl_insn
136 {
137 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
138 const struct mips_opcode *insn_mo;
139
140 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
141 a copy of INSN_MO->match with the operands filled in. If we have
142 decided to use an extended MIPS16 instruction, this includes the
143 extension. */
144 unsigned long insn_opcode;
145
146 /* The name if this is an label. */
147 char label[16];
148
149 /* The target label name if this is an branch. */
150 char target[16];
151
152 /* The frag that contains the instruction. */
153 struct frag *frag;
154
155 /* The offset into FRAG of the first instruction byte. */
156 long where;
157
158 /* The relocs associated with the instruction, if any. */
159 fixS *fixp[3];
160
161 /* True if this entry cannot be moved from its current position. */
162 unsigned int fixed_p : 1;
163
164 /* True if this instruction occurred in a .set noreorder block. */
165 unsigned int noreorder_p : 1;
166
167 /* True for mips16 instructions that jump to an absolute address. */
168 unsigned int mips16_absolute_jump_p : 1;
169
170 /* True if this instruction is complete. */
171 unsigned int complete_p : 1;
172
173 /* True if this instruction is cleared from history by unconditional
174 branch. */
175 unsigned int cleared_p : 1;
176 };
177
178 /* The ABI to use. */
179 enum mips_abi_level
180 {
181 NO_ABI = 0,
182 O32_ABI,
183 O64_ABI,
184 N32_ABI,
185 N64_ABI,
186 EABI_ABI
187 };
188
189 /* MIPS ABI we are using for this output file. */
190 static enum mips_abi_level mips_abi = NO_ABI;
191
192 /* Whether or not we have code that can call pic code. */
193 int mips_abicalls = false;
194
195 /* Whether or not we have code which can be put into a shared
196 library. */
197 static bool mips_in_shared = true;
198
199 /* This is the set of options which may be modified by the .set
200 pseudo-op. We use a struct so that .set push and .set pop are more
201 reliable. */
202
203 struct mips_set_options
204 {
205 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
206 if it has not been initialized. Changed by `.set mipsN', and the
207 -mipsN command line option, and the default CPU. */
208 int isa;
209 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
210 <asename>', by command line options, and based on the default
211 architecture. */
212 int ase;
213 /* Whether we are assembling for the mips16 processor. 0 if we are
214 not, 1 if we are, and -1 if the value has not been initialized.
215 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
216 -nomips16 command line options, and the default CPU. */
217 int mips16;
218 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
219 1 if we are, and -1 if the value has not been initialized. Changed
220 by `.set micromips' and `.set nomicromips', and the -mmicromips
221 and -mno-micromips command line options, and the default CPU. */
222 int micromips;
223 /* Non-zero if we should not reorder instructions. Changed by `.set
224 reorder' and `.set noreorder'. */
225 int noreorder;
226 /* Non-zero if we should not permit the register designated "assembler
227 temporary" to be used in instructions. The value is the register
228 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
229 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
230 unsigned int at;
231 /* Non-zero if we should warn when a macro instruction expands into
232 more than one machine instruction. Changed by `.set nomacro' and
233 `.set macro'. */
234 int warn_about_macros;
235 /* Non-zero if we should not move instructions. Changed by `.set
236 move', `.set volatile', `.set nomove', and `.set novolatile'. */
237 int nomove;
238 /* Non-zero if we should not optimize branches by moving the target
239 of the branch into the delay slot. Actually, we don't perform
240 this optimization anyhow. Changed by `.set bopt' and `.set
241 nobopt'. */
242 int nobopt;
243 /* Non-zero if we should not autoextend mips16 instructions.
244 Changed by `.set autoextend' and `.set noautoextend'. */
245 int noautoextend;
246 /* True if we should only emit 32-bit microMIPS instructions.
247 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
248 and -mno-insn32 command line options. */
249 bool insn32;
250 /* Restrict general purpose registers and floating point registers
251 to 32 bit. This is initially determined when -mgp32 or -mfp32
252 is passed but can changed if the assembler code uses .set mipsN. */
253 int gp;
254 int fp;
255 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
256 command line option, and the default CPU. */
257 int arch;
258 /* True if ".set sym32" is in effect. */
259 bool sym32;
260 /* True if floating-point operations are not allowed. Changed by .set
261 softfloat or .set hardfloat, by command line options -msoft-float or
262 -mhard-float. The default is false. */
263 bool soft_float;
264
265 /* True if only single-precision floating-point operations are allowed.
266 Changed by .set singlefloat or .set doublefloat, command-line options
267 -msingle-float or -mdouble-float. The default is false. */
268 bool single_float;
269
270 /* 1 if single-precision operations on odd-numbered registers are
271 allowed. */
272 int oddspreg;
273
274 /* The set of ASEs that should be enabled for the user specified
275 architecture. This cannot be inferred from 'arch' for all cores
276 as processors only have a unique 'arch' if they add architecture
277 specific instructions (UDI). */
278 int init_ase;
279 };
280
281 /* Specifies whether module level options have been checked yet. */
282 static bool file_mips_opts_checked = false;
283
284 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
285 value has not been initialized. Changed by `.nan legacy' and
286 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
287 options, and the default CPU. */
288 static int mips_nan2008 = -1;
289
290 /* This is the struct we use to hold the module level set of options.
291 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
292 fp fields to -1 to indicate that they have not been initialized. */
293
294 static struct mips_set_options file_mips_opts =
295 {
296 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
297 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
298 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
299 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ false,
300 /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
301 /* init_ase */ 0
302 };
303
304 /* This is similar to file_mips_opts, but for the current set of options. */
305
306 static struct mips_set_options mips_opts =
307 {
308 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
309 /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
310 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ false,
311 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ false,
312 /* soft_float */ false, /* single_float */ false, /* oddspreg */ -1,
313 /* init_ase */ 0
314 };
315
316 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
317 static unsigned int file_ase_explicit;
318
319 /* These variables are filled in with the masks of registers used.
320 The object format code reads them and puts them in the appropriate
321 place. */
322 unsigned long mips_gprmask;
323 unsigned long mips_cprmask[4];
324
325 /* True if any MIPS16 code was produced. */
326 static int file_ase_mips16;
327
328 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
329 || mips_opts.isa == ISA_MIPS32R2 \
330 || mips_opts.isa == ISA_MIPS32R3 \
331 || mips_opts.isa == ISA_MIPS32R5 \
332 || mips_opts.isa == ISA_MIPS64 \
333 || mips_opts.isa == ISA_MIPS64R2 \
334 || mips_opts.isa == ISA_MIPS64R3 \
335 || mips_opts.isa == ISA_MIPS64R5)
336
337 /* True if any microMIPS code was produced. */
338 static int file_ase_micromips;
339
340 /* True if we want to create R_MIPS_JALR for jalr $25. */
341 #ifdef TE_IRIX
342 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
343 #else
344 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
345 because there's no place for any addend, the only acceptable
346 expression is a bare symbol. */
347 #define MIPS_JALR_HINT_P(EXPR) \
348 (!HAVE_IN_PLACE_ADDENDS \
349 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 #endif
351
352 /* The argument of the -march= flag. The architecture we are assembling. */
353 static const char *mips_arch_string;
354
355 /* The argument of the -mtune= flag. The architecture for which we
356 are optimizing. */
357 static int mips_tune = CPU_UNKNOWN;
358 static const char *mips_tune_string;
359
360 /* True when generating 32-bit code for a 64-bit processor. */
361 static int mips_32bitmode = 0;
362
363 /* True if the given ABI requires 32-bit registers. */
364 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
365
366 /* Likewise 64-bit registers. */
367 #define ABI_NEEDS_64BIT_REGS(ABI) \
368 ((ABI) == N32_ABI \
369 || (ABI) == N64_ABI \
370 || (ABI) == O64_ABI)
371
372 #define ISA_IS_R6(ISA) \
373 ((ISA) == ISA_MIPS32R6 \
374 || (ISA) == ISA_MIPS64R6)
375
376 /* Return true if ISA supports 64 bit wide gp registers. */
377 #define ISA_HAS_64BIT_REGS(ISA) \
378 ((ISA) == ISA_MIPS3 \
379 || (ISA) == ISA_MIPS4 \
380 || (ISA) == ISA_MIPS5 \
381 || (ISA) == ISA_MIPS64 \
382 || (ISA) == ISA_MIPS64R2 \
383 || (ISA) == ISA_MIPS64R3 \
384 || (ISA) == ISA_MIPS64R5 \
385 || (ISA) == ISA_MIPS64R6)
386
387 /* Return true if ISA supports 64 bit wide float registers. */
388 #define ISA_HAS_64BIT_FPRS(ISA) \
389 ((ISA) == ISA_MIPS3 \
390 || (ISA) == ISA_MIPS4 \
391 || (ISA) == ISA_MIPS5 \
392 || (ISA) == ISA_MIPS32R2 \
393 || (ISA) == ISA_MIPS32R3 \
394 || (ISA) == ISA_MIPS32R5 \
395 || (ISA) == ISA_MIPS32R6 \
396 || (ISA) == ISA_MIPS64 \
397 || (ISA) == ISA_MIPS64R2 \
398 || (ISA) == ISA_MIPS64R3 \
399 || (ISA) == ISA_MIPS64R5 \
400 || (ISA) == ISA_MIPS64R6)
401
402 /* Return true if ISA supports 64-bit right rotate (dror et al.)
403 instructions. */
404 #define ISA_HAS_DROR(ISA) \
405 ((ISA) == ISA_MIPS64R2 \
406 || (ISA) == ISA_MIPS64R3 \
407 || (ISA) == ISA_MIPS64R5 \
408 || (ISA) == ISA_MIPS64R6 \
409 || (mips_opts.micromips \
410 && ISA_HAS_64BIT_REGS (ISA)) \
411 )
412
413 /* Return true if ISA supports 32-bit right rotate (ror et al.)
414 instructions. */
415 #define ISA_HAS_ROR(ISA) \
416 ((ISA) == ISA_MIPS32R2 \
417 || (ISA) == ISA_MIPS32R3 \
418 || (ISA) == ISA_MIPS32R5 \
419 || (ISA) == ISA_MIPS32R6 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
424 || (mips_opts.ase & ASE_SMARTMIPS) \
425 || mips_opts.micromips \
426 )
427
428 /* Return true if ISA supports single-precision floats in odd registers. */
429 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
430 (((ISA) == ISA_MIPS32 \
431 || (ISA) == ISA_MIPS32R2 \
432 || (ISA) == ISA_MIPS32R3 \
433 || (ISA) == ISA_MIPS32R5 \
434 || (ISA) == ISA_MIPS32R6 \
435 || (ISA) == ISA_MIPS64 \
436 || (ISA) == ISA_MIPS64R2 \
437 || (ISA) == ISA_MIPS64R3 \
438 || (ISA) == ISA_MIPS64R5 \
439 || (ISA) == ISA_MIPS64R6 \
440 || (CPU) == CPU_ALLEGREX \
441 || (CPU) == CPU_R5900) \
442 && ((CPU) != CPU_GS464 \
443 || (CPU) != CPU_GS464E \
444 || (CPU) != CPU_GS264E))
445
446 /* Return true if ISA supports move to/from high part of a 64-bit
447 floating-point register. */
448 #define ISA_HAS_MXHC1(ISA) \
449 ((ISA) == ISA_MIPS32R2 \
450 || (ISA) == ISA_MIPS32R3 \
451 || (ISA) == ISA_MIPS32R5 \
452 || (ISA) == ISA_MIPS32R6 \
453 || (ISA) == ISA_MIPS64R2 \
454 || (ISA) == ISA_MIPS64R3 \
455 || (ISA) == ISA_MIPS64R5 \
456 || (ISA) == ISA_MIPS64R6)
457
458 /* Return true if ISA supports legacy NAN. */
459 #define ISA_HAS_LEGACY_NAN(ISA) \
460 ((ISA) == ISA_MIPS1 \
461 || (ISA) == ISA_MIPS2 \
462 || (ISA) == ISA_MIPS3 \
463 || (ISA) == ISA_MIPS4 \
464 || (ISA) == ISA_MIPS5 \
465 || (ISA) == ISA_MIPS32 \
466 || (ISA) == ISA_MIPS32R2 \
467 || (ISA) == ISA_MIPS32R3 \
468 || (ISA) == ISA_MIPS32R5 \
469 || (ISA) == ISA_MIPS64 \
470 || (ISA) == ISA_MIPS64R2 \
471 || (ISA) == ISA_MIPS64R3 \
472 || (ISA) == ISA_MIPS64R5)
473
474 #define GPR_SIZE \
475 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
476 ? 32 \
477 : mips_opts.gp)
478
479 #define FPR_SIZE \
480 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 ? 32 \
482 : mips_opts.fp)
483
484 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
485
486 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
487
488 /* True if relocations are stored in-place. */
489 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
490
491 /* The ABI-derived address size. */
492 #define HAVE_64BIT_ADDRESSES \
493 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
494 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
495
496 /* The size of symbolic constants (i.e., expressions of the form
497 "SYMBOL" or "SYMBOL + OFFSET"). */
498 #define HAVE_32BIT_SYMBOLS \
499 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
500 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
501
502 /* Addresses are loaded in different ways, depending on the address size
503 in use. The n32 ABI Documentation also mandates the use of additions
504 with overflow checking, but existing implementations don't follow it. */
505 #define ADDRESS_ADD_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
507
508 #define ADDRESS_ADDI_INSN \
509 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
510
511 #define ADDRESS_LOAD_INSN \
512 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
513
514 #define ADDRESS_STORE_INSN \
515 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
516
517 /* Return true if the given CPU supports the MIPS16 ASE. */
518 #define CPU_HAS_MIPS16(cpu) \
519 (startswith (TARGET_CPU, "mips16") \
520 || startswith (TARGET_CANONICAL, "mips-lsi-elf"))
521
522 /* Return true if the given CPU supports the microMIPS ASE. */
523 #define CPU_HAS_MICROMIPS(cpu) 0
524
525 /* True if CPU has a dror instruction. */
526 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
527
528 /* True if CPU has a ror instruction. */
529 #define CPU_HAS_ROR(CPU) (CPU_HAS_DROR (CPU) || (CPU) == CPU_ALLEGREX)
530
531 /* True if CPU is in the Octeon family. */
532 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
533 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
534
535 /* True if CPU has seq/sne and seqi/snei instructions. */
536 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
537
538 /* True, if CPU has support for ldc1 and sdc1. */
539 #define CPU_HAS_LDC1_SDC1(CPU) (mips_opts.isa != ISA_MIPS1 \
540 && (CPU) != CPU_ALLEGREX \
541 && (CPU) != CPU_R5900)
542
543 /* True if mflo and mfhi can be immediately followed by instructions
544 which write to the HI and LO registers.
545
546 According to MIPS specifications, MIPS ISAs I, II, and III need
547 (at least) two instructions between the reads of HI/LO and
548 instructions which write them, and later ISAs do not. Contradicting
549 the MIPS specifications, some MIPS IV processor user manuals (e.g.
550 the UM for the NEC Vr5000) document needing the instructions between
551 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
552 MIPS64 and later ISAs to have the interlocks, plus any specific
553 earlier-ISA CPUs for which CPU documentation declares that the
554 instructions are really interlocked. */
555 #define hilo_interlocks \
556 (mips_opts.isa == ISA_MIPS32 \
557 || mips_opts.isa == ISA_MIPS32R2 \
558 || mips_opts.isa == ISA_MIPS32R3 \
559 || mips_opts.isa == ISA_MIPS32R5 \
560 || mips_opts.isa == ISA_MIPS32R6 \
561 || mips_opts.isa == ISA_MIPS64 \
562 || mips_opts.isa == ISA_MIPS64R2 \
563 || mips_opts.isa == ISA_MIPS64R3 \
564 || mips_opts.isa == ISA_MIPS64R5 \
565 || mips_opts.isa == ISA_MIPS64R6 \
566 || mips_opts.arch == CPU_ALLEGREX \
567 || mips_opts.arch == CPU_R4010 \
568 || mips_opts.arch == CPU_R5900 \
569 || mips_opts.arch == CPU_R10000 \
570 || mips_opts.arch == CPU_R12000 \
571 || mips_opts.arch == CPU_R14000 \
572 || mips_opts.arch == CPU_R16000 \
573 || mips_opts.arch == CPU_RM7000 \
574 || mips_opts.arch == CPU_VR5500 \
575 || mips_opts.micromips \
576 )
577
578 /* Whether the processor uses hardware interlocks to protect reads
579 from the GPRs after they are loaded from memory, and thus does not
580 require nops to be inserted. This applies to instructions marked
581 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
582 level I and microMIPS mode instructions are always interlocked. */
583 #define gpr_interlocks \
584 (mips_opts.isa != ISA_MIPS1 \
585 || mips_opts.arch == CPU_R3900 \
586 || mips_opts.arch == CPU_R5900 \
587 || mips_opts.micromips \
588 )
589
590 /* Whether the processor uses hardware interlocks to avoid delays
591 required by coprocessor instructions, and thus does not require
592 nops to be inserted. This applies to instructions marked
593 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
594 instructions marked INSN_WRITE_COND_CODE and ones marked
595 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
596 levels I, II, and III and microMIPS mode instructions are always
597 interlocked. */
598 /* Itbl support may require additional care here. */
599 #define cop_interlocks \
600 ((mips_opts.isa != ISA_MIPS1 \
601 && mips_opts.isa != ISA_MIPS2 \
602 && mips_opts.isa != ISA_MIPS3) \
603 || mips_opts.arch == CPU_R4300 \
604 || mips_opts.micromips \
605 )
606
607 /* Whether the processor uses hardware interlocks to protect reads
608 from coprocessor registers after they are loaded from memory, and
609 thus does not require nops to be inserted. This applies to
610 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
611 requires at MIPS ISA level I and microMIPS mode instructions are
612 always interlocked. */
613 #define cop_mem_interlocks \
614 (mips_opts.isa != ISA_MIPS1 \
615 || mips_opts.micromips \
616 )
617
618 /* Is this a mfhi or mflo instruction? */
619 #define MF_HILO_INSN(PINFO) \
620 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
621
622 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
623 has been selected. This implies, in particular, that addresses of text
624 labels have their LSB set. */
625 #define HAVE_CODE_COMPRESSION \
626 ((mips_opts.mips16 | mips_opts.micromips) != 0)
627
628 /* The minimum and maximum signed values that can be stored in a GPR. */
629 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
630 #define GPR_SMIN (-GPR_SMAX - 1)
631
632 /* MIPS PIC level. */
633
634 enum mips_pic_level mips_pic;
635
636 /* 1 if we should generate 32 bit offsets from the $gp register in
637 SVR4_PIC mode. Currently has no meaning in other modes. */
638 static int mips_big_got = 0;
639
640 /* 1 if trap instructions should used for overflow rather than break
641 instructions. */
642 static int mips_trap = 0;
643
644 /* 1 if double width floating point constants should not be constructed
645 by assembling two single width halves into two single width floating
646 point registers which just happen to alias the double width destination
647 register. On some architectures this aliasing can be disabled by a bit
648 in the status register, and the setting of this bit cannot be determined
649 automatically at assemble time. */
650 static int mips_disable_float_construction;
651
652 /* Non-zero if any .set noreorder directives were used. */
653
654 static int mips_any_noreorder;
655
656 /* Non-zero if nops should be inserted when the register referenced in
657 an mfhi/mflo instruction is read in the next two instructions. */
658 static int mips_7000_hilo_fix;
659
660 /* The size of objects in the small data section. */
661 static unsigned int g_switch_value = 8;
662 /* Whether the -G option was used. */
663 static int g_switch_seen = 0;
664
665 #define N_RMASK 0xc4
666 #define N_VFP 0xd4
667
668 /* If we can determine in advance that GP optimization won't be
669 possible, we can skip the relaxation stuff that tries to produce
670 GP-relative references. This makes delay slot optimization work
671 better.
672
673 This function can only provide a guess, but it seems to work for
674 gcc output. It needs to guess right for gcc, otherwise gcc
675 will put what it thinks is a GP-relative instruction in a branch
676 delay slot.
677
678 I don't know if a fix is needed for the SVR4_PIC mode. I've only
679 fixed it for the non-PIC mode. KR 95/04/07 */
680 static int nopic_need_relax (symbolS *, int);
681
682 /* Handle of the OPCODE hash table. */
683 static htab_t op_hash = NULL;
684
685 /* The opcode hash table we use for the mips16. */
686 static htab_t mips16_op_hash = NULL;
687
688 /* The opcode hash table we use for the microMIPS ASE. */
689 static htab_t micromips_op_hash = NULL;
690
691 /* This array holds the chars that always start a comment. If the
692 pre-processor is disabled, these aren't very useful. */
693 const char comment_chars[] = "#";
694
695 /* This array holds the chars that only start a comment at the beginning of
696 a line. If the line seems to have the form '# 123 filename'
697 .line and .file directives will appear in the pre-processed output. */
698 /* Note that input_file.c hand checks for '#' at the beginning of the
699 first line of the input file. This is because the compiler outputs
700 #NO_APP at the beginning of its output. */
701 /* Also note that C style comments are always supported. */
702 const char line_comment_chars[] = "#";
703
704 /* This array holds machine specific line separator characters. */
705 const char line_separator_chars[] = ";";
706
707 /* Chars that can be used to separate mant from exp in floating point nums. */
708 const char EXP_CHARS[] = "eE";
709
710 /* Chars that mean this number is a floating point constant.
711 As in 0f12.456
712 or 0d1.2345e12. */
713 const char FLT_CHARS[] = "rRsSfFdDxXpP";
714
715 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
716 changed in read.c . Ideally it shouldn't have to know about it at all,
717 but nothing is ideal around here. */
718
719 /* Types of printf format used for instruction-related error messages.
720 "I" means int ("%d") and "S" means string ("%s"). */
721 enum mips_insn_error_format
722 {
723 ERR_FMT_PLAIN,
724 ERR_FMT_I,
725 ERR_FMT_SS,
726 };
727
728 /* Information about an error that was found while assembling the current
729 instruction. */
730 struct mips_insn_error
731 {
732 /* We sometimes need to match an instruction against more than one
733 opcode table entry. Errors found during this matching are reported
734 against a particular syntactic argument rather than against the
735 instruction as a whole. We grade these messages so that errors
736 against argument N have a greater priority than an error against
737 any argument < N, since the former implies that arguments up to N
738 were acceptable and that the opcode entry was therefore a closer match.
739 If several matches report an error against the same argument,
740 we only use that error if it is the same in all cases.
741
742 min_argnum is the minimum argument number for which an error message
743 should be accepted. It is 0 if MSG is against the instruction as
744 a whole. */
745 int min_argnum;
746
747 /* The printf()-style message, including its format and arguments. */
748 enum mips_insn_error_format format;
749 const char *msg;
750 union
751 {
752 int i;
753 const char *ss[2];
754 } u;
755 };
756
757 /* The error that should be reported for the current instruction. */
758 static struct mips_insn_error insn_error;
759
760 static int auto_align = 1;
761
762 /* When outputting SVR4 PIC code, the assembler needs to know the
763 offset in the stack frame from which to restore the $gp register.
764 This is set by the .cprestore pseudo-op, and saved in this
765 variable. */
766 static offsetT mips_cprestore_offset = -1;
767
768 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
769 more optimizations, it can use a register value instead of a memory-saved
770 offset and even an other register than $gp as global pointer. */
771 static offsetT mips_cpreturn_offset = -1;
772 static int mips_cpreturn_register = -1;
773 static int mips_gp_register = GP;
774 static int mips_gprel_offset = 0;
775
776 /* Whether mips_cprestore_offset has been set in the current function
777 (or whether it has already been warned about, if not). */
778 static int mips_cprestore_valid = 0;
779
780 /* This is the register which holds the stack frame, as set by the
781 .frame pseudo-op. This is needed to implement .cprestore. */
782 static int mips_frame_reg = SP;
783
784 /* Whether mips_frame_reg has been set in the current function
785 (or whether it has already been warned about, if not). */
786 static int mips_frame_reg_valid = 0;
787
788 /* To output NOP instructions correctly, we need to keep information
789 about the previous two instructions. */
790
791 /* Whether we are optimizing. The default value of 2 means to remove
792 unneeded NOPs and swap branch instructions when possible. A value
793 of 1 means to not swap branches. A value of 0 means to always
794 insert NOPs. */
795 static int mips_optimize = 2;
796
797 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
798 equivalent to seeing no -g option at all. */
799 static int mips_debug = 0;
800
801 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
802 #define MAX_VR4130_NOPS 4
803
804 /* The maximum number of NOPs needed to fill delay slots. */
805 #define MAX_DELAY_NOPS 2
806
807 /* The maximum number of NOPs needed for any purpose. */
808 #define MAX_NOPS 4
809
810 /* The maximum range of context length of ll/sc. */
811 #define MAX_LLSC_RANGE 20
812
813 /* A list of previous instructions, with index 0 being the most recent.
814 We need to look back MAX_NOPS instructions when filling delay slots
815 or working around processor errata. We need to look back one
816 instruction further if we're thinking about using history[0] to
817 fill a branch delay slot. */
818 static struct mips_cl_insn history[1 + MAX_NOPS + MAX_LLSC_RANGE];
819
820 /* The maximum number of LABELS detect for the same address. */
821 #define MAX_LABELS_SAME 10
822
823 /* Arrays of operands for each instruction. */
824 #define MAX_OPERANDS 6
825 struct mips_operand_array
826 {
827 const struct mips_operand *operand[MAX_OPERANDS];
828 };
829 static struct mips_operand_array *mips_operands;
830 static struct mips_operand_array *mips16_operands;
831 static struct mips_operand_array *micromips_operands;
832
833 /* Nop instructions used by emit_nop. */
834 static struct mips_cl_insn nop_insn;
835 static struct mips_cl_insn mips16_nop_insn;
836 static struct mips_cl_insn micromips_nop16_insn;
837 static struct mips_cl_insn micromips_nop32_insn;
838
839 /* Sync instructions used by insert sync. */
840 static struct mips_cl_insn sync_insn;
841
842 /* The appropriate nop for the current mode. */
843 #define NOP_INSN (mips_opts.mips16 \
844 ? &mips16_nop_insn \
845 : (mips_opts.micromips \
846 ? (mips_opts.insn32 \
847 ? µmips_nop32_insn \
848 : µmips_nop16_insn) \
849 : &nop_insn))
850
851 /* The size of NOP_INSN in bytes. */
852 #define NOP_INSN_SIZE ((mips_opts.mips16 \
853 || (mips_opts.micromips && !mips_opts.insn32)) \
854 ? 2 : 4)
855
856 /* If this is set, it points to a frag holding nop instructions which
857 were inserted before the start of a noreorder section. If those
858 nops turn out to be unnecessary, the size of the frag can be
859 decreased. */
860 static fragS *prev_nop_frag;
861
862 /* The number of nop instructions we created in prev_nop_frag. */
863 static int prev_nop_frag_holds;
864
865 /* The number of nop instructions that we know we need in
866 prev_nop_frag. */
867 static int prev_nop_frag_required;
868
869 /* The number of instructions we've seen since prev_nop_frag. */
870 static int prev_nop_frag_since;
871
872 /* Relocations against symbols are sometimes done in two parts, with a HI
873 relocation and a LO relocation. Each relocation has only 16 bits of
874 space to store an addend. This means that in order for the linker to
875 handle carries correctly, it must be able to locate both the HI and
876 the LO relocation. This means that the relocations must appear in
877 order in the relocation table.
878
879 In order to implement this, we keep track of each unmatched HI
880 relocation. We then sort them so that they immediately precede the
881 corresponding LO relocation. */
882
883 struct mips_hi_fixup
884 {
885 /* Next HI fixup. */
886 struct mips_hi_fixup *next;
887 /* This fixup. */
888 fixS *fixp;
889 /* The section this fixup is in. */
890 segT seg;
891 };
892
893 /* The list of unmatched HI relocs. */
894
895 static struct mips_hi_fixup *mips_hi_fixup_list;
896
897 /* Map mips16 register numbers to normal MIPS register numbers. */
898
899 static const unsigned int mips16_to_32_reg_map[] =
900 {
901 16, 17, 2, 3, 4, 5, 6, 7
902 };
903
904 /* Map microMIPS register numbers to normal MIPS register numbers. */
905
906 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
907
908 /* The microMIPS registers with type h. */
909 static const unsigned int micromips_to_32_reg_h_map1[] =
910 {
911 5, 5, 6, 4, 4, 4, 4, 4
912 };
913 static const unsigned int micromips_to_32_reg_h_map2[] =
914 {
915 6, 7, 7, 21, 22, 5, 6, 7
916 };
917
918 /* The microMIPS registers with type m. */
919 static const unsigned int micromips_to_32_reg_m_map[] =
920 {
921 0, 17, 2, 3, 16, 18, 19, 20
922 };
923
924 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
925
926 /* Classifies the kind of instructions we're interested in when
927 implementing -mfix-vr4120. */
928 enum fix_vr4120_class
929 {
930 FIX_VR4120_MACC,
931 FIX_VR4120_DMACC,
932 FIX_VR4120_MULT,
933 FIX_VR4120_DMULT,
934 FIX_VR4120_DIV,
935 FIX_VR4120_MTHILO,
936 NUM_FIX_VR4120_CLASSES
937 };
938
939 /* ...likewise -mtrap-zero-jump. */
940 static bfd_boolean mips_trap_zero_jump;
941
942 /* ...likewise -mfix-loongson2f-jump. */
943 static bool mips_fix_loongson2f_jump;
944
945 /* ...likewise -mfix-loongson2f-nop. */
946 static bool mips_fix_loongson2f_nop;
947
948 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
949 static bool mips_fix_loongson2f;
950
951 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
952 there must be at least one other instruction between an instruction
953 of type X and an instruction of type Y. */
954 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
955
956 /* True if -mfix-vr4120 is in force. */
957 static int mips_fix_vr4120;
958
959 /* ...likewise -mfix-vr4130. */
960 static int mips_fix_vr4130;
961
962 /* ...likewise -mfix-24k. */
963 static int mips_fix_24k;
964
965 /* ...likewise -mfix-rm7000 */
966 static int mips_fix_rm7000;
967
968 /* ...likewise -mfix-cn63xxp1 */
969 static bool mips_fix_cn63xxp1;
970
971 /* ...likewise -mfix-r5900 */
972 static bool mips_fix_r5900;
973 static bool mips_fix_r5900_explicit;
974
975 /* ...likewise -mfix-loongson3-llsc. */
976 static bool mips_fix_loongson3_llsc = DEFAULT_MIPS_FIX_LOONGSON3_LLSC;
977
978 /* We don't relax branches by default, since this causes us to expand
979 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
980 fail to compute the offset before expanding the macro to the most
981 efficient expansion. */
982
983 static int mips_relax_branch;
984
985 static int mips_fix_loongson2f_btb;
986
987 /* TRUE if checks are suppressed for invalid branches between ISA modes.
988 Needed for broken assembly produced by some GCC versions and some
989 sloppy code out there, where branches to data labels are present. */
990 static bool mips_ignore_branch_isa;
991
992 /* The expansion of many macros depends on the type of symbol that
993 they refer to. For example, when generating position-dependent code,
994 a macro that refers to a symbol may have two different expansions,
995 one which uses GP-relative addresses and one which uses absolute
996 addresses. When generating SVR4-style PIC, a macro may have
997 different expansions for local and global symbols.
998
999 We handle these situations by generating both sequences and putting
1000 them in variant frags. In position-dependent code, the first sequence
1001 will be the GP-relative one and the second sequence will be the
1002 absolute one. In SVR4 PIC, the first sequence will be for global
1003 symbols and the second will be for local symbols.
1004
1005 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
1006 SECOND are the lengths of the two sequences in bytes. These fields
1007 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1008 the subtype has the following flags:
1009
1010 RELAX_PIC
1011 Set if generating PIC code.
1012
1013 RELAX_USE_SECOND
1014 Set if it has been decided that we should use the second
1015 sequence instead of the first.
1016
1017 RELAX_SECOND_LONGER
1018 Set in the first variant frag if the macro's second implementation
1019 is longer than its first. This refers to the macro as a whole,
1020 not an individual relaxation.
1021
1022 RELAX_NOMACRO
1023 Set in the first variant frag if the macro appeared in a .set nomacro
1024 block and if one alternative requires a warning but the other does not.
1025
1026 RELAX_DELAY_SLOT
1027 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1028 delay slot.
1029
1030 RELAX_DELAY_SLOT_16BIT
1031 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1032 16-bit instruction.
1033
1034 RELAX_DELAY_SLOT_SIZE_FIRST
1035 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1036 the macro is of the wrong size for the branch delay slot.
1037
1038 RELAX_DELAY_SLOT_SIZE_SECOND
1039 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1040 the macro is of the wrong size for the branch delay slot.
1041
1042 The frag's "opcode" points to the first fixup for relaxable code.
1043
1044 Relaxable macros are generated using a sequence such as:
1045
1046 relax_start (SYMBOL);
1047 ... generate first expansion ...
1048 relax_switch ();
1049 ... generate second expansion ...
1050 relax_end ();
1051
1052 The code and fixups for the unwanted alternative are discarded
1053 by md_convert_frag. */
1054 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1055 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1056
1057 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1058 #define RELAX_SECOND(X) ((X) & 0xff)
1059 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1060 #define RELAX_USE_SECOND 0x20000
1061 #define RELAX_SECOND_LONGER 0x40000
1062 #define RELAX_NOMACRO 0x80000
1063 #define RELAX_DELAY_SLOT 0x100000
1064 #define RELAX_DELAY_SLOT_16BIT 0x200000
1065 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1066 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1067
1068 /* Branch without likely bit. If label is out of range, we turn:
1069
1070 beq reg1, reg2, label
1071 delay slot
1072
1073 into
1074
1075 bne reg1, reg2, 0f
1076 nop
1077 j label
1078 0: delay slot
1079
1080 with the following opcode replacements:
1081
1082 beq <-> bne
1083 blez <-> bgtz
1084 bltz <-> bgez
1085 bc1f <-> bc1t
1086
1087 bltzal <-> bgezal (with jal label instead of j label)
1088
1089 Even though keeping the delay slot instruction in the delay slot of
1090 the branch would be more efficient, it would be very tricky to do
1091 correctly, because we'd have to introduce a variable frag *after*
1092 the delay slot instruction, and expand that instead. Let's do it
1093 the easy way for now, even if the branch-not-taken case now costs
1094 one additional instruction. Out-of-range branches are not supposed
1095 to be common, anyway.
1096
1097 Branch likely. If label is out of range, we turn:
1098
1099 beql reg1, reg2, label
1100 delay slot (annulled if branch not taken)
1101
1102 into
1103
1104 beql reg1, reg2, 1f
1105 nop
1106 beql $0, $0, 2f
1107 nop
1108 1: j[al] label
1109 delay slot (executed only if branch taken)
1110 2:
1111
1112 It would be possible to generate a shorter sequence by losing the
1113 likely bit, generating something like:
1114
1115 bne reg1, reg2, 0f
1116 nop
1117 j[al] label
1118 delay slot (executed only if branch taken)
1119 0:
1120
1121 beql -> bne
1122 bnel -> beq
1123 blezl -> bgtz
1124 bgtzl -> blez
1125 bltzl -> bgez
1126 bgezl -> bltz
1127 bc1fl -> bc1t
1128 bc1tl -> bc1f
1129
1130 bltzall -> bgezal (with jal label instead of j label)
1131 bgezall -> bltzal (ditto)
1132
1133
1134 but it's not clear that it would actually improve performance. */
1135 #define RELAX_BRANCH_ENCODE(at, pic, \
1136 uncond, likely, link, toofar) \
1137 ((relax_substateT) \
1138 (0xc0000000 \
1139 | ((at) & 0x1f) \
1140 | ((pic) ? 0x20 : 0) \
1141 | ((toofar) ? 0x40 : 0) \
1142 | ((link) ? 0x80 : 0) \
1143 | ((likely) ? 0x100 : 0) \
1144 | ((uncond) ? 0x200 : 0)))
1145 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1146 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1147 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1148 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1149 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1150 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1151 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1152
1153 /* For mips16 code, we use an entirely different form of relaxation.
1154 mips16 supports two versions of most instructions which take
1155 immediate values: a small one which takes some small value, and a
1156 larger one which takes a 16 bit value. Since branches also follow
1157 this pattern, relaxing these values is required.
1158
1159 We can assemble both mips16 and normal MIPS code in a single
1160 object. Therefore, we need to support this type of relaxation at
1161 the same time that we support the relaxation described above. We
1162 use the high bit of the subtype field to distinguish these cases.
1163
1164 The information we store for this type of relaxation is the
1165 argument code found in the opcode file for this relocation, whether
1166 the user explicitly requested a small or extended form, and whether
1167 the relocation is in a jump or jal delay slot. That tells us the
1168 size of the value, and how it should be stored. We also store
1169 whether the fragment is considered to be extended or not. We also
1170 store whether this is known to be a branch to a different section,
1171 whether we have tried to relax this frag yet, and whether we have
1172 ever extended a PC relative fragment because of a shift count. */
1173 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1174 small, ext, \
1175 dslot, jal_dslot) \
1176 (0x80000000 \
1177 | ((type) & 0xff) \
1178 | ((e2) ? 0x100 : 0) \
1179 | ((pic) ? 0x200 : 0) \
1180 | ((sym32) ? 0x400 : 0) \
1181 | ((nomacro) ? 0x800 : 0) \
1182 | ((small) ? 0x1000 : 0) \
1183 | ((ext) ? 0x2000 : 0) \
1184 | ((dslot) ? 0x4000 : 0) \
1185 | ((jal_dslot) ? 0x8000 : 0))
1186
1187 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1188 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1189 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1190 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1191 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1192 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1193 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1194 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1195 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1196 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1197
1198 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1199 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1200 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1201 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1202 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1203 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1204 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1205 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1206 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1207
1208 /* For microMIPS code, we use relaxation similar to one we use for
1209 MIPS16 code. Some instructions that take immediate values support
1210 two encodings: a small one which takes some small value, and a
1211 larger one which takes a 16 bit value. As some branches also follow
1212 this pattern, relaxing these values is required.
1213
1214 We can assemble both microMIPS and normal MIPS code in a single
1215 object. Therefore, we need to support this type of relaxation at
1216 the same time that we support the relaxation described above. We
1217 use one of the high bits of the subtype field to distinguish these
1218 cases.
1219
1220 The information we store for this type of relaxation is the argument
1221 code found in the opcode file for this relocation, the register
1222 selected as the assembler temporary, whether in the 32-bit
1223 instruction mode, whether the branch is unconditional, whether it is
1224 compact, whether there is no delay-slot instruction available to fill
1225 in, whether it stores the link address implicitly in $ra, whether
1226 relaxation of out-of-range 32-bit branches to a sequence of
1227 instructions is enabled, and whether the displacement of a branch is
1228 too large to fit as an immediate argument of a 16-bit and a 32-bit
1229 branch, respectively. */
1230 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1231 uncond, compact, link, nods, \
1232 relax32, toofar16, toofar32) \
1233 (0x40000000 \
1234 | ((type) & 0xff) \
1235 | (((at) & 0x1f) << 8) \
1236 | ((insn32) ? 0x2000 : 0) \
1237 | ((pic) ? 0x4000 : 0) \
1238 | ((uncond) ? 0x8000 : 0) \
1239 | ((compact) ? 0x10000 : 0) \
1240 | ((link) ? 0x20000 : 0) \
1241 | ((nods) ? 0x40000 : 0) \
1242 | ((relax32) ? 0x80000 : 0) \
1243 | ((toofar16) ? 0x100000 : 0) \
1244 | ((toofar32) ? 0x200000 : 0))
1245 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1246 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1247 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1248 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1249 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1250 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1251 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1252 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1253 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1254 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1255
1256 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1257 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1258 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1259 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1260 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1261 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1262
1263 /* Sign-extend 16-bit value X. */
1264 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1265
1266 /* Is the given value a sign-extended 32-bit value? */
1267 #define IS_SEXT_32BIT_NUM(x) \
1268 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1269 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1270
1271 /* Is the given value a sign-extended 16-bit value? */
1272 #define IS_SEXT_16BIT_NUM(x) \
1273 (((x) &~ (offsetT) 0x7fff) == 0 \
1274 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1275
1276 /* Is the given value a sign-extended 12-bit value? */
1277 #define IS_SEXT_12BIT_NUM(x) \
1278 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1279
1280 /* Is the given value a sign-extended 9-bit value? */
1281 #define IS_SEXT_9BIT_NUM(x) \
1282 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1283
1284 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1285 #define IS_ZEXT_32BIT_NUM(x) \
1286 (((x) &~ (offsetT) 0xffffffff) == 0 \
1287 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1288
1289 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1290 SHIFT places. */
1291 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1292 (((STRUCT) >> (SHIFT)) & (MASK))
1293
1294 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1295 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1296 (!(MICROMIPS) \
1297 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1298 : EXTRACT_BITS ((INSN).insn_opcode, \
1299 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1300 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1301 EXTRACT_BITS ((INSN).insn_opcode, \
1302 MIPS16OP_MASK_##FIELD, \
1303 MIPS16OP_SH_##FIELD)
1304
1305 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1306 #define MIPS16_EXTEND (0xf000U << 16)
1307
1308 /* Whether or not we are emitting a branch-likely macro. */
1309 static bool emit_branch_likely_macro = false;
1310
1311 /* Global variables used when generating relaxable macros. See the
1312 comment above RELAX_ENCODE for more details about how relaxation
1313 is used. */
1314 static struct {
1315 /* 0 if we're not emitting a relaxable macro.
1316 1 if we're emitting the first of the two relaxation alternatives.
1317 2 if we're emitting the second alternative. */
1318 int sequence;
1319
1320 /* The first relaxable fixup in the current frag. (In other words,
1321 the first fixup that refers to relaxable code.) */
1322 fixS *first_fixup;
1323
1324 /* sizes[0] says how many bytes of the first alternative are stored in
1325 the current frag. Likewise sizes[1] for the second alternative. */
1326 unsigned int sizes[2];
1327
1328 /* The symbol on which the choice of sequence depends. */
1329 symbolS *symbol;
1330 } mips_relax;
1331
1332 /* Global variables used to decide whether a macro needs a warning. */
1333 static struct {
1334 /* True if the macro is in a branch delay slot. */
1335 bool delay_slot_p;
1336
1337 /* Set to the length in bytes required if the macro is in a delay slot
1338 that requires a specific length of instruction, otherwise zero. */
1339 unsigned int delay_slot_length;
1340
1341 /* For relaxable macros, sizes[0] is the length of the first alternative
1342 in bytes and sizes[1] is the length of the second alternative.
1343 For non-relaxable macros, both elements give the length of the
1344 macro in bytes. */
1345 unsigned int sizes[2];
1346
1347 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1348 instruction of the first alternative in bytes and first_insn_sizes[1]
1349 is the length of the first instruction of the second alternative.
1350 For non-relaxable macros, both elements give the length of the first
1351 instruction in bytes.
1352
1353 Set to zero if we haven't yet seen the first instruction. */
1354 unsigned int first_insn_sizes[2];
1355
1356 /* For relaxable macros, insns[0] is the number of instructions for the
1357 first alternative and insns[1] is the number of instructions for the
1358 second alternative.
1359
1360 For non-relaxable macros, both elements give the number of
1361 instructions for the macro. */
1362 unsigned int insns[2];
1363
1364 /* The first variant frag for this macro. */
1365 fragS *first_frag;
1366 } mips_macro_warning;
1367
1368 /* Prototypes for static functions. */
1369
1370 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1371
1372 static void append_insn
1373 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *,
1374 bool expansionp);
1375 static void mips_no_prev_insn (void);
1376 static void macro_build (expressionS *, const char *, const char *, ...);
1377 static void mips16_macro_build
1378 (expressionS *, const char *, const char *, va_list *);
1379 static void load_register (int, expressionS *, int);
1380 static void macro_build (expressionS *, const char *, const char *, ...);
1381 static void macro_start (void);
1382 static void macro_end (void);
1383 static void macro (struct mips_cl_insn *ip, char *str);
1384 static void mips16_macro (struct mips_cl_insn * ip);
1385 static void mips_ip (char *str, struct mips_cl_insn * ip);
1386 static void mips16_ip (char *str, struct mips_cl_insn * ip);
1387 static unsigned long mips16_immed_extend (offsetT, unsigned int);
1388 static void mips16_immed
1389 (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT,
1390 unsigned int, unsigned long *);
1391 static size_t my_getSmallExpression
1392 (expressionS *, bfd_reloc_code_real_type *, char *);
1393 static void my_getExpression (expressionS *, char *);
1394 static void s_align (int);
1395 static void s_change_sec (int);
1396 static void s_change_section (int);
1397 static void s_cons (int);
1398 static void s_float_cons (int);
1399 static void s_mips_globl (int);
1400 static void s_option (int);
1401 static void s_mipsset (int);
1402 static void s_abicalls (int);
1403 static void s_cpload (int);
1404 static void s_cpsetup (int);
1405 static void s_cplocal (int);
1406 static void s_cprestore (int);
1407 static void s_cpreturn (int);
1408 static void s_dtprelword (int);
1409 static void s_dtpreldword (int);
1410 static void s_tprelword (int);
1411 static void s_tpreldword (int);
1412 static void s_gpvalue (int);
1413 static void s_gpword (int);
1414 static void s_gpdword (int);
1415 static void s_ehword (int);
1416 static void s_cpadd (int);
1417 static void s_insn (int);
1418 static void s_nan (int);
1419 static void s_module (int);
1420 static void s_mips_ent (int);
1421 static void s_mips_end (int);
1422 static void s_mips_frame (int);
1423 static void s_mips_mask (int reg_type);
1424 static void s_mips_stab (int);
1425 static void s_mips_weakext (int);
1426 static void s_mips_file (int);
1427 static void s_mips_loc (int);
1428 static bool pic_need_relax (symbolS *);
1429 static int relaxed_branch_length (fragS *, asection *, int);
1430 static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int);
1431 static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int);
1432 static void file_mips_check_options (void);
1433
1434 /* Table and functions used to map between CPU/ISA names, and
1435 ISA levels, and CPU numbers. */
1436
1437 struct mips_cpu_info
1438 {
1439 const char *name; /* CPU or ISA name. */
1440 int flags; /* MIPS_CPU_* flags. */
1441 int ase; /* Set of ASEs implemented by the CPU. */
1442 int isa; /* ISA level. */
1443 int cpu; /* CPU number (default CPU if ISA). */
1444 };
1445
1446 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1447
1448 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1449 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1450 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1451
1452 /* Command-line options. */
1453 const char *md_shortopts = "O::g::G:";
1454
1455 enum options
1456 {
1457 OPTION_MARCH = OPTION_MD_BASE,
1458 OPTION_MTUNE,
1459 OPTION_MIPS1,
1460 OPTION_MIPS2,
1461 OPTION_MIPS3,
1462 OPTION_MIPS4,
1463 OPTION_MIPS5,
1464 OPTION_MIPS32,
1465 OPTION_MIPS64,
1466 OPTION_MIPS32R2,
1467 OPTION_MIPS32R3,
1468 OPTION_MIPS32R5,
1469 OPTION_MIPS32R6,
1470 OPTION_MIPS64R2,
1471 OPTION_MIPS64R3,
1472 OPTION_MIPS64R5,
1473 OPTION_MIPS64R6,
1474 OPTION_MIPS16,
1475 OPTION_NO_MIPS16,
1476 OPTION_MIPS3D,
1477 OPTION_NO_MIPS3D,
1478 OPTION_MDMX,
1479 OPTION_NO_MDMX,
1480 OPTION_DSP,
1481 OPTION_NO_DSP,
1482 OPTION_MT,
1483 OPTION_NO_MT,
1484 OPTION_VIRT,
1485 OPTION_NO_VIRT,
1486 OPTION_MSA,
1487 OPTION_NO_MSA,
1488 OPTION_SMARTMIPS,
1489 OPTION_NO_SMARTMIPS,
1490 OPTION_DSPR2,
1491 OPTION_NO_DSPR2,
1492 OPTION_DSPR3,
1493 OPTION_NO_DSPR3,
1494 OPTION_EVA,
1495 OPTION_NO_EVA,
1496 OPTION_XPA,
1497 OPTION_NO_XPA,
1498 OPTION_MICROMIPS,
1499 OPTION_NO_MICROMIPS,
1500 OPTION_MCU,
1501 OPTION_NO_MCU,
1502 OPTION_MIPS16E2,
1503 OPTION_NO_MIPS16E2,
1504 OPTION_CRC,
1505 OPTION_NO_CRC,
1506 OPTION_M4650,
1507 OPTION_NO_M4650,
1508 OPTION_M4010,
1509 OPTION_NO_M4010,
1510 OPTION_M4100,
1511 OPTION_NO_M4100,
1512 OPTION_M3900,
1513 OPTION_NO_M3900,
1514 OPTION_M7000_HILO_FIX,
1515 OPTION_MNO_7000_HILO_FIX,
1516 OPTION_FIX_24K,
1517 OPTION_NO_FIX_24K,
1518 OPTION_FIX_RM7000,
1519 OPTION_NO_FIX_RM7000,
1520 OPTION_FIX_LOONGSON3_LLSC,
1521 OPTION_NO_FIX_LOONGSON3_LLSC,
1522 OPTION_FIX_LOONGSON2F_JUMP,
1523 OPTION_NO_FIX_LOONGSON2F_JUMP,
1524 OPTION_FIX_LOONGSON2F_NOP,
1525 OPTION_NO_FIX_LOONGSON2F_NOP,
1526 OPTION_FIX_VR4120,
1527 OPTION_NO_FIX_VR4120,
1528 OPTION_FIX_VR4130,
1529 OPTION_NO_FIX_VR4130,
1530 OPTION_FIX_CN63XXP1,
1531 OPTION_NO_FIX_CN63XXP1,
1532 OPTION_FIX_R5900,
1533 OPTION_NO_FIX_R5900,
1534 OPTION_TRAP,
1535 OPTION_BREAK,
1536 OPTION_EB,
1537 OPTION_EL,
1538 OPTION_FP32,
1539 OPTION_GP32,
1540 OPTION_CONSTRUCT_FLOATS,
1541 OPTION_NO_CONSTRUCT_FLOATS,
1542 OPTION_FP64,
1543 OPTION_FPXX,
1544 OPTION_GP64,
1545 OPTION_RELAX_BRANCH,
1546 OPTION_NO_RELAX_BRANCH,
1547 OPTION_IGNORE_BRANCH_ISA,
1548 OPTION_NO_IGNORE_BRANCH_ISA,
1549 OPTION_INSN32,
1550 OPTION_NO_INSN32,
1551 OPTION_MSHARED,
1552 OPTION_MNO_SHARED,
1553 OPTION_MSYM32,
1554 OPTION_MNO_SYM32,
1555 OPTION_SOFT_FLOAT,
1556 OPTION_HARD_FLOAT,
1557 OPTION_SINGLE_FLOAT,
1558 OPTION_DOUBLE_FLOAT,
1559 OPTION_32,
1560 OPTION_CALL_SHARED,
1561 OPTION_CALL_NONPIC,
1562 OPTION_NON_SHARED,
1563 OPTION_XGOT,
1564 OPTION_MABI,
1565 OPTION_N32,
1566 OPTION_64,
1567 OPTION_MDEBUG,
1568 OPTION_NO_MDEBUG,
1569 OPTION_PDR,
1570 OPTION_NO_PDR,
1571 OPTION_MVXWORKS_PIC,
1572 OPTION_NAN,
1573 OPTION_ODD_SPREG,
1574 OPTION_NO_ODD_SPREG,
1575 OPTION_GINV,
1576 OPTION_NO_GINV,
1577 OPTION_LOONGSON_MMI,
1578 OPTION_NO_LOONGSON_MMI,
1579 OPTION_LOONGSON_CAM,
1580 OPTION_NO_LOONGSON_CAM,
1581 OPTION_LOONGSON_EXT,
1582 OPTION_NO_LOONGSON_EXT,
1583 OPTION_LOONGSON_EXT2,
1584 OPTION_NO_LOONGSON_EXT2,
1585 OPTION_FIX_LOONGSON2F_BTB,
1586 OPTION_NO_FIX_LOONGSON2F_BTB,
1587 OPTION_END_OF_ENUM
1588 };
1589
1590 struct option md_longopts[] =
1591 {
1592 /* Options which specify architecture. */
1593 {"march", required_argument, NULL, OPTION_MARCH},
1594 {"mtune", required_argument, NULL, OPTION_MTUNE},
1595 {"mips0", no_argument, NULL, OPTION_MIPS1},
1596 {"mips1", no_argument, NULL, OPTION_MIPS1},
1597 {"mips2", no_argument, NULL, OPTION_MIPS2},
1598 {"mips3", no_argument, NULL, OPTION_MIPS3},
1599 {"mips4", no_argument, NULL, OPTION_MIPS4},
1600 {"mips5", no_argument, NULL, OPTION_MIPS5},
1601 {"mips32", no_argument, NULL, OPTION_MIPS32},
1602 {"mips64", no_argument, NULL, OPTION_MIPS64},
1603 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
1604 {"mips32r3", no_argument, NULL, OPTION_MIPS32R3},
1605 {"mips32r5", no_argument, NULL, OPTION_MIPS32R5},
1606 {"mips32r6", no_argument, NULL, OPTION_MIPS32R6},
1607 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
1608 {"mips64r3", no_argument, NULL, OPTION_MIPS64R3},
1609 {"mips64r5", no_argument, NULL, OPTION_MIPS64R5},
1610 {"mips64r6", no_argument, NULL, OPTION_MIPS64R6},
1611
1612 /* Options which specify Application Specific Extensions (ASEs). */
1613 {"mips16", no_argument, NULL, OPTION_MIPS16},
1614 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
1615 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
1616 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
1617 {"mdmx", no_argument, NULL, OPTION_MDMX},
1618 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
1619 {"mdsp", no_argument, NULL, OPTION_DSP},
1620 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
1621 {"mmt", no_argument, NULL, OPTION_MT},
1622 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
1623 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
1624 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
1625 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
1626 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
1627 {"mdspr3", no_argument, NULL, OPTION_DSPR3},
1628 {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
1629 {"meva", no_argument, NULL, OPTION_EVA},
1630 {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
1631 {"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
1632 {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
1633 {"mmcu", no_argument, NULL, OPTION_MCU},
1634 {"mno-mcu", no_argument, NULL, OPTION_NO_MCU},
1635 {"mvirt", no_argument, NULL, OPTION_VIRT},
1636 {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
1637 {"mmsa", no_argument, NULL, OPTION_MSA},
1638 {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
1639 {"mxpa", no_argument, NULL, OPTION_XPA},
1640 {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
1641 {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2},
1642 {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2},
1643 {"mcrc", no_argument, NULL, OPTION_CRC},
1644 {"mno-crc", no_argument, NULL, OPTION_NO_CRC},
1645 {"mginv", no_argument, NULL, OPTION_GINV},
1646 {"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
1647 {"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
1648 {"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
1649 {"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
1650 {"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
1651 {"mloongson-ext", no_argument, NULL, OPTION_LOONGSON_EXT},
1652 {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
1653 {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2},
1654 {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2},
1655
1656 /* Old-style architecture options. Don't add more of these. */
1657 {"m4650", no_argument, NULL, OPTION_M4650},
1658 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
1659 {"m4010", no_argument, NULL, OPTION_M4010},
1660 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
1661 {"m4100", no_argument, NULL, OPTION_M4100},
1662 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
1663 {"m3900", no_argument, NULL, OPTION_M3900},
1664 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
1665
1666 /* Options which enable bug fixes. */
1667 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
1668 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1669 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
1670 {"mfix-loongson3-llsc", no_argument, NULL, OPTION_FIX_LOONGSON3_LLSC},
1671 {"mno-fix-loongson3-llsc", no_argument, NULL, OPTION_NO_FIX_LOONGSON3_LLSC},
1672 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
1673 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
1674 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
1675 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
1676 {"mfix-loongson2f-btb", no_argument, NULL, OPTION_FIX_LOONGSON2F_BTB},
1677 {"mno-fix-loongson2f-btb", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_BTB},
1678 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
1679 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
1680 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
1681 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
1682 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
1683 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
1684 {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000},
1685 {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000},
1686 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
1687 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
1688 {"mfix-r5900", no_argument, NULL, OPTION_FIX_R5900},
1689 {"mno-fix-r5900", no_argument, NULL, OPTION_NO_FIX_R5900},
1690
1691 /* Miscellaneous options. */
1692 {"trap", no_argument, NULL, OPTION_TRAP},
1693 {"no-break", no_argument, NULL, OPTION_TRAP},
1694 {"break", no_argument, NULL, OPTION_BREAK},
1695 {"no-trap", no_argument, NULL, OPTION_BREAK},
1696 {"EB", no_argument, NULL, OPTION_EB},
1697 {"EL", no_argument, NULL, OPTION_EL},
1698 {"mfp32", no_argument, NULL, OPTION_FP32},
1699 {"mgp32", no_argument, NULL, OPTION_GP32},
1700 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
1701 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
1702 {"mfp64", no_argument, NULL, OPTION_FP64},
1703 {"mfpxx", no_argument, NULL, OPTION_FPXX},
1704 {"mgp64", no_argument, NULL, OPTION_GP64},
1705 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
1706 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
1707 {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA},
1708 {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA},
1709 {"minsn32", no_argument, NULL, OPTION_INSN32},
1710 {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32},
1711 {"mshared", no_argument, NULL, OPTION_MSHARED},
1712 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
1713 {"msym32", no_argument, NULL, OPTION_MSYM32},
1714 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
1715 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
1716 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
1717 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
1718 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
1719 {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG},
1720 {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG},
1721
1722 /* Strictly speaking this next option is ELF specific,
1723 but we allow it for other ports as well in order to
1724 make testing easier. */
1725 {"32", no_argument, NULL, OPTION_32},
1726
1727 /* ELF-specific options. */
1728 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
1729 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
1730 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
1731 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
1732 {"xgot", no_argument, NULL, OPTION_XGOT},
1733 {"mabi", required_argument, NULL, OPTION_MABI},
1734 {"n32", no_argument, NULL, OPTION_N32},
1735 {"64", no_argument, NULL, OPTION_64},
1736 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
1737 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
1738 {"mpdr", no_argument, NULL, OPTION_PDR},
1739 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
1740 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
1741 {"mnan", required_argument, NULL, OPTION_NAN},
1742
1743 {NULL, no_argument, NULL, 0}
1744 };
1745 size_t md_longopts_size = sizeof (md_longopts);
1746
1747 /* Information about either an Application Specific Extension or an
1748 optional architecture feature that, for simplicity, we treat in the
1749 same way as an ASE. */
1750 struct mips_ase
1751 {
1752 /* The name of the ASE, used in both the command-line and .set options. */
1753 const char *name;
1754
1755 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1756 and 64-bit architectures, the flags here refer to the subset that
1757 is available on both. */
1758 unsigned int flags;
1759
1760 /* The ASE_* flag used for instructions that are available on 64-bit
1761 architectures but that are not included in FLAGS. */
1762 unsigned int flags64;
1763
1764 /* The command-line options that turn the ASE on and off. */
1765 int option_on;
1766 int option_off;
1767
1768 /* The minimum required architecture revisions for MIPS32, MIPS64,
1769 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1770 int mips32_rev;
1771 int mips64_rev;
1772 int micromips32_rev;
1773 int micromips64_rev;
1774
1775 /* The architecture where the ASE was removed or -1 if the extension has not
1776 been removed. */
1777 int rem_rev;
1778 };
1779
1780 /* A table of all supported ASEs. */
1781 static const struct mips_ase mips_ases[] = {
1782 { "dsp", ASE_DSP, ASE_DSP64,
1783 OPTION_DSP, OPTION_NO_DSP,
1784 2, 2, 2, 2,
1785 -1 },
1786
1787 { "dspr2", ASE_DSP | ASE_DSPR2, 0,
1788 OPTION_DSPR2, OPTION_NO_DSPR2,
1789 2, 2, 2, 2,
1790 -1 },
1791
1792 { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
1793 OPTION_DSPR3, OPTION_NO_DSPR3,
1794 6, 6, -1, -1,
1795 -1 },
1796
1797 { "eva", ASE_EVA, 0,
1798 OPTION_EVA, OPTION_NO_EVA,
1799 2, 2, 2, 2,
1800 -1 },
1801
1802 { "mcu", ASE_MCU, 0,
1803 OPTION_MCU, OPTION_NO_MCU,
1804 2, 2, 2, 2,
1805 -1 },
1806
1807 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1808 { "mdmx", ASE_MDMX, 0,
1809 OPTION_MDMX, OPTION_NO_MDMX,
1810 -1, 1, -1, -1,
1811 6 },
1812
1813 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1814 { "mips3d", ASE_MIPS3D, 0,
1815 OPTION_MIPS3D, OPTION_NO_MIPS3D,
1816 2, 1, -1, -1,
1817 6 },
1818
1819 { "mt", ASE_MT, 0,
1820 OPTION_MT, OPTION_NO_MT,
1821 2, 2, -1, -1,
1822 -1 },
1823
1824 { "smartmips", ASE_SMARTMIPS, 0,
1825 OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS,
1826 1, -1, -1, -1,
1827 6 },
1828
1829 { "virt", ASE_VIRT, ASE_VIRT64,
1830 OPTION_VIRT, OPTION_NO_VIRT,
1831 2, 2, 2, 2,
1832 -1 },
1833
1834 { "msa", ASE_MSA, ASE_MSA64,
1835 OPTION_MSA, OPTION_NO_MSA,
1836 2, 2, 2, 2,
1837 -1 },
1838
1839 { "xpa", ASE_XPA, 0,
1840 OPTION_XPA, OPTION_NO_XPA,
1841 2, 2, 2, 2,
1842 -1 },
1843
1844 { "mips16e2", ASE_MIPS16E2, 0,
1845 OPTION_MIPS16E2, OPTION_NO_MIPS16E2,
1846 2, 2, -1, -1,
1847 6 },
1848
1849 { "crc", ASE_CRC, ASE_CRC64,
1850 OPTION_CRC, OPTION_NO_CRC,
1851 6, 6, -1, -1,
1852 -1 },
1853
1854 { "ginv", ASE_GINV, 0,
1855 OPTION_GINV, OPTION_NO_GINV,
1856 6, 6, 6, 6,
1857 -1 },
1858
1859 { "loongson-mmi", ASE_LOONGSON_MMI, 0,
1860 OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
1861 0, 0, -1, -1,
1862 -1 },
1863
1864 { "loongson-cam", ASE_LOONGSON_CAM, 0,
1865 OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
1866 0, 0, -1, -1,
1867 -1 },
1868
1869 { "loongson-ext", ASE_LOONGSON_EXT, 0,
1870 OPTION_LOONGSON_EXT, OPTION_NO_LOONGSON_EXT,
1871 0, 0, -1, -1,
1872 -1 },
1873
1874 { "loongson-ext2", ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2, 0,
1875 OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2,
1876 0, 0, -1, -1,
1877 -1 },
1878 };
1879
1880 /* The set of ASEs that require -mfp64. */
1881 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1882
1883 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1884 static const unsigned int mips_ase_groups[] = {
1885 ASE_DSP | ASE_DSPR2 | ASE_DSPR3,
1886 ASE_LOONGSON_EXT | ASE_LOONGSON_EXT2
1887 };
1888
1889 /* Pseudo-op table.
1890
1891 The following pseudo-ops from the Kane and Heinrich MIPS book
1892 should be defined here, but are currently unsupported: .alias,
1893 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1894
1895 The following pseudo-ops from the Kane and Heinrich MIPS book are
1896 specific to the type of debugging information being generated, and
1897 should be defined by the object format: .aent, .begin, .bend,
1898 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1899 .vreg.
1900
1901 The following pseudo-ops from the Kane and Heinrich MIPS book are
1902 not MIPS CPU specific, but are also not specific to the object file
1903 format. This file is probably the best place to define them, but
1904 they are not currently supported: .asm0, .endr, .lab, .struct. */
1905
1906 static const pseudo_typeS mips_pseudo_table[] =
1907 {
1908 /* MIPS specific pseudo-ops. */
1909 {"option", s_option, 0},
1910 {"set", s_mipsset, 0},
1911 {"rdata", s_change_sec, 'r'},
1912 {"sdata", s_change_sec, 's'},
1913 {"livereg", s_ignore, 0},
1914 {"abicalls", s_abicalls, 0},
1915 {"cpload", s_cpload, 0},
1916 {"cpsetup", s_cpsetup, 0},
1917 {"cplocal", s_cplocal, 0},
1918 {"cprestore", s_cprestore, 0},
1919 {"cpreturn", s_cpreturn, 0},
1920 {"dtprelword", s_dtprelword, 0},
1921 {"dtpreldword", s_dtpreldword, 0},
1922 {"tprelword", s_tprelword, 0},
1923 {"tpreldword", s_tpreldword, 0},
1924 {"gpvalue", s_gpvalue, 0},
1925 {"gpword", s_gpword, 0},
1926 {"gpdword", s_gpdword, 0},
1927 {"ehword", s_ehword, 0},
1928 {"cpadd", s_cpadd, 0},
1929 {"insn", s_insn, 0},
1930 {"nan", s_nan, 0},
1931 {"module", s_module, 0},
1932
1933 /* Relatively generic pseudo-ops that happen to be used on MIPS
1934 chips. */
1935 {"asciiz", stringer, 8 + 1},
1936 {"bss", s_change_sec, 'b'},
1937 {"err", s_err, 0},
1938 {"half", s_cons, 1},
1939 {"dword", s_cons, 3},
1940 {"weakext", s_mips_weakext, 0},
1941 {"origin", s_org, 0},
1942 {"repeat", s_rept, 0},
1943
1944 /* For MIPS this is non-standard, but we define it for consistency. */
1945 {"sbss", s_change_sec, 'B'},
1946
1947 /* These pseudo-ops are defined in read.c, but must be overridden
1948 here for one reason or another. */
1949 {"align", s_align, 0},
1950 {"byte", s_cons, 0},
1951 {"data", s_change_sec, 'd'},
1952 {"double", s_float_cons, 'd'},
1953 {"float", s_float_cons, 'f'},
1954 {"globl", s_mips_globl, 0},
1955 {"global", s_mips_globl, 0},
1956 {"hword", s_cons, 1},
1957 {"int", s_cons, 2},
1958 {"long", s_cons, 2},
1959 {"octa", s_cons, 4},
1960 {"quad", s_cons, 3},
1961 {"section", s_change_section, 0},
1962 {"short", s_cons, 1},
1963 {"single", s_float_cons, 'f'},
1964 {"stabd", s_mips_stab, 'd'},
1965 {"stabn", s_mips_stab, 'n'},
1966 {"stabs", s_mips_stab, 's'},
1967 {"text", s_change_sec, 't'},
1968 {"word", s_cons, 2},
1969
1970 { "extern", ecoff_directive_extern, 0},
1971
1972 { NULL, NULL, 0 },
1973 };
1974
1975 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1976 {
1977 /* These pseudo-ops should be defined by the object file format.
1978 However, a.out doesn't support them, so we have versions here. */
1979 {"aent", s_mips_ent, 1},
1980 {"bgnb", s_ignore, 0},
1981 {"end", s_mips_end, 0},
1982 {"endb", s_ignore, 0},
1983 {"ent", s_mips_ent, 0},
1984 {"file", s_mips_file, 0},
1985 {"fmask", s_mips_mask, 'F'},
1986 {"frame", s_mips_frame, 0},
1987 {"loc", s_mips_loc, 0},
1988 {"mask", s_mips_mask, 'R'},
1989 {"verstamp", s_ignore, 0},
1990 { NULL, NULL, 0 },
1991 };
1992
1993 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1994 purpose of the `.dc.a' internal pseudo-op. */
1995
1996 int
mips_address_bytes(void)1997 mips_address_bytes (void)
1998 {
1999 file_mips_check_options ();
2000 return HAVE_64BIT_ADDRESSES ? 8 : 4;
2001 }
2002
2003 extern void pop_insert (const pseudo_typeS *);
2004
2005 void
mips_pop_insert(void)2006 mips_pop_insert (void)
2007 {
2008 pop_insert (mips_pseudo_table);
2009 if (! ECOFF_DEBUGGING)
2010 pop_insert (mips_nonecoff_pseudo_table);
2011 }
2012
2013 /* Symbols labelling the current insn. */
2014
2015 struct insn_label_list
2016 {
2017 struct insn_label_list *next;
2018 symbolS *label;
2019 };
2020
2021 static struct insn_label_list *free_insn_labels;
2022 #define label_list tc_segment_info_data.labels
2023
2024 static void mips_clear_insn_labels (void);
2025 static void mips_mark_labels (void);
2026 static void mips_compressed_mark_labels (void);
2027
2028 static inline void
mips_clear_insn_labels(void)2029 mips_clear_insn_labels (void)
2030 {
2031 struct insn_label_list **pl;
2032 segment_info_type *si;
2033
2034 if (now_seg)
2035 {
2036 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
2037 ;
2038
2039 si = seg_info (now_seg);
2040 *pl = si->label_list;
2041 si->label_list = NULL;
2042 }
2043 }
2044
2045 /* Mark instruction labels in MIPS16/microMIPS mode. */
2046
2047 static inline void
mips_mark_labels(void)2048 mips_mark_labels (void)
2049 {
2050 if (HAVE_CODE_COMPRESSION)
2051 mips_compressed_mark_labels ();
2052 }
2053
2054 static char *expr_parse_end;
2055
2056 /* An expression in a macro instruction. This is set by mips_ip and
2057 mips16_ip and when populated is always an O_constant. */
2058
2059 static expressionS imm_expr;
2060
2061 /* The relocatable field in an instruction and the relocs associated
2062 with it. These variables are used for instructions like LUI and
2063 JAL as well as true offsets. They are also used for address
2064 operands in macros. */
2065
2066 static expressionS offset_expr;
2067 static bfd_reloc_code_real_type offset_reloc[3]
2068 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2069
2070 /* This is set to the resulting size of the instruction to be produced
2071 by mips16_ip if an explicit extension is used or by mips_ip if an
2072 explicit size is supplied. */
2073
2074 static unsigned int forced_insn_length;
2075
2076 /* True if we are assembling an instruction. All dot symbols defined during
2077 this time should be treated as code labels. */
2078
2079 static bool mips_assembling_insn;
2080
2081 /* The pdr segment for per procedure frame/regmask info. Not used for
2082 ECOFF debugging. */
2083
2084 static segT pdr_seg;
2085
2086 /* The default target format to use. */
2087
2088 #if defined (TE_FreeBSD)
2089 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2090 #elif defined (TE_TMIPS)
2091 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2092 #else
2093 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2094 #endif
2095
2096 const char *
mips_target_format(void)2097 mips_target_format (void)
2098 {
2099 switch (OUTPUT_FLAVOR)
2100 {
2101 case bfd_target_elf_flavour:
2102 #ifdef TE_VXWORKS
2103 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
2104 return (target_big_endian
2105 ? "elf32-bigmips-vxworks"
2106 : "elf32-littlemips-vxworks");
2107 #endif
2108 return (target_big_endian
2109 ? (HAVE_64BIT_OBJECTS
2110 ? ELF_TARGET ("elf64-", "big")
2111 : (HAVE_NEWABI
2112 ? ELF_TARGET ("elf32-n", "big")
2113 : ELF_TARGET ("elf32-", "big")))
2114 : (HAVE_64BIT_OBJECTS
2115 ? ELF_TARGET ("elf64-", "little")
2116 : (HAVE_NEWABI
2117 ? ELF_TARGET ("elf32-n", "little")
2118 : ELF_TARGET ("elf32-", "little"))));
2119 default:
2120 abort ();
2121 return NULL;
2122 }
2123 }
2124
2125 /* Return the ISA revision that is currently in use, or 0 if we are
2126 generating code for MIPS V or below. */
2127
2128 static int
mips_isa_rev(void)2129 mips_isa_rev (void)
2130 {
2131 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
2132 return 2;
2133
2134 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
2135 return 3;
2136
2137 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
2138 return 5;
2139
2140 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
2141 return 6;
2142
2143 /* microMIPS implies revision 2 or above. */
2144 if (mips_opts.micromips)
2145 return 2;
2146
2147 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2148 return 1;
2149
2150 return 0;
2151 }
2152
2153 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2154
2155 static unsigned int
mips_ase_mask(unsigned int flags)2156 mips_ase_mask (unsigned int flags)
2157 {
2158 unsigned int i;
2159
2160 for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++)
2161 if (flags & mips_ase_groups[i])
2162 flags |= mips_ase_groups[i];
2163 return flags;
2164 }
2165
2166 /* Check whether the current ISA supports ASE. Issue a warning if
2167 appropriate. */
2168
2169 static void
mips_check_isa_supports_ase(const struct mips_ase * ase)2170 mips_check_isa_supports_ase (const struct mips_ase *ase)
2171 {
2172 const char *base;
2173 int min_rev, size;
2174 static unsigned int warned_isa;
2175 static unsigned int warned_fp32;
2176
2177 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2178 min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev;
2179 else
2180 min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev;
2181 if ((min_rev < 0 || mips_isa_rev () < min_rev)
2182 && (warned_isa & ase->flags) != ase->flags)
2183 {
2184 warned_isa |= ase->flags;
2185 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2186 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2187 if (min_rev < 0)
2188 as_warn (_("the %d-bit %s architecture does not support the"
2189 " `%s' extension"), size, base, ase->name);
2190 else
2191 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2192 ase->name, base, size, min_rev);
2193 }
2194 else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev)
2195 && (warned_isa & ase->flags) != ase->flags)
2196 {
2197 warned_isa |= ase->flags;
2198 base = mips_opts.micromips ? "microMIPS" : "MIPS";
2199 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2200 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2201 ase->name, base, size, ase->rem_rev);
2202 }
2203
2204 if ((ase->flags & FP64_ASES)
2205 && mips_opts.fp != 64
2206 && (warned_fp32 & ase->flags) != ase->flags)
2207 {
2208 warned_fp32 |= ase->flags;
2209 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
2210 }
2211 }
2212
2213 /* Check all enabled ASEs to see whether they are supported by the
2214 chosen architecture. */
2215
2216 static void
mips_check_isa_supports_ases(void)2217 mips_check_isa_supports_ases (void)
2218 {
2219 unsigned int i, mask;
2220
2221 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2222 {
2223 mask = mips_ase_mask (mips_ases[i].flags);
2224 if ((mips_opts.ase & mask) == mips_ases[i].flags)
2225 mips_check_isa_supports_ase (&mips_ases[i]);
2226 }
2227 }
2228
2229 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2230 that were affected. */
2231
2232 static unsigned int
mips_set_ase(const struct mips_ase * ase,struct mips_set_options * opts,bool enabled_p)2233 mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
2234 bool enabled_p)
2235 {
2236 unsigned int mask;
2237
2238 mask = mips_ase_mask (ase->flags);
2239 opts->ase &= ~mask;
2240
2241 /* Clear combination ASE flags, which need to be recalculated based on
2242 updated regular ASE settings. */
2243 opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6);
2244
2245 if (enabled_p)
2246 opts->ase |= ase->flags;
2247
2248 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2249 instructions which are only valid when both ASEs are enabled.
2250 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2251 if ((opts->ase & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT))
2252 {
2253 opts->ase |= ASE_XPA_VIRT;
2254 mask |= ASE_XPA_VIRT;
2255 }
2256 if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
2257 {
2258 opts->ase |= ASE_MIPS16E2_MT;
2259 mask |= ASE_MIPS16E2_MT;
2260 }
2261
2262 /* The EVA Extension has instructions which are only valid when the R6 ISA
2263 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2264 present. */
2265 if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa))
2266 {
2267 opts->ase |= ASE_EVA_R6;
2268 mask |= ASE_EVA_R6;
2269 }
2270
2271 return mask;
2272 }
2273
2274 /* Return the ASE called NAME, or null if none. */
2275
2276 static const struct mips_ase *
mips_lookup_ase(const char * name)2277 mips_lookup_ase (const char *name)
2278 {
2279 unsigned int i;
2280
2281 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
2282 if (strcmp (name, mips_ases[i].name) == 0)
2283 return &mips_ases[i];
2284 return NULL;
2285 }
2286
2287 /* Return the length of a microMIPS instruction in bytes. If bits of
2288 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2289 otherwise it is a 32-bit instruction. */
2290
2291 static inline unsigned int
micromips_insn_length(const struct mips_opcode * mo)2292 micromips_insn_length (const struct mips_opcode *mo)
2293 {
2294 return mips_opcode_32bit_p (mo) ? 4 : 2;
2295 }
2296
2297 /* Return the length of MIPS16 instruction OPCODE. */
2298
2299 static inline unsigned int
mips16_opcode_length(unsigned long opcode)2300 mips16_opcode_length (unsigned long opcode)
2301 {
2302 return (opcode >> 16) == 0 ? 2 : 4;
2303 }
2304
2305 /* Return the length of instruction INSN. */
2306
2307 static inline unsigned int
insn_length(const struct mips_cl_insn * insn)2308 insn_length (const struct mips_cl_insn *insn)
2309 {
2310 if (mips_opts.micromips)
2311 return micromips_insn_length (insn->insn_mo);
2312 else if (mips_opts.mips16)
2313 return mips16_opcode_length (insn->insn_opcode);
2314 else
2315 return 4;
2316 }
2317
2318 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2319
2320 static void
create_insn(struct mips_cl_insn * insn,const struct mips_opcode * mo)2321 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
2322 {
2323 size_t i;
2324
2325 insn->insn_mo = mo;
2326 insn->insn_opcode = mo->match;
2327 insn->frag = NULL;
2328 insn->where = 0;
2329 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2330 insn->fixp[i] = NULL;
2331 insn->fixed_p = (mips_opts.noreorder > 0);
2332 insn->noreorder_p = (mips_opts.noreorder > 0);
2333 insn->mips16_absolute_jump_p = 0;
2334 insn->complete_p = 0;
2335 insn->cleared_p = 0;
2336 }
2337
2338 /* Get a list of all the operands in INSN. */
2339
2340 static const struct mips_operand_array *
insn_operands(const struct mips_cl_insn * insn)2341 insn_operands (const struct mips_cl_insn *insn)
2342 {
2343 if (insn->insn_mo >= &mips_opcodes[0]
2344 && insn->insn_mo < &mips_opcodes[NUMOPCODES])
2345 return &mips_operands[insn->insn_mo - &mips_opcodes[0]];
2346
2347 if (insn->insn_mo >= &mips16_opcodes[0]
2348 && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes])
2349 return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]];
2350
2351 if (insn->insn_mo >= µmips_opcodes[0]
2352 && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes])
2353 return µmips_operands[insn->insn_mo - µmips_opcodes[0]];
2354
2355 abort ();
2356 }
2357
2358 /* Get a description of operand OPNO of INSN. */
2359
2360 static const struct mips_operand *
insn_opno(const struct mips_cl_insn * insn,unsigned opno)2361 insn_opno (const struct mips_cl_insn *insn, unsigned opno)
2362 {
2363 const struct mips_operand_array *operands;
2364
2365 operands = insn_operands (insn);
2366 if (opno >= MAX_OPERANDS || !operands->operand[opno])
2367 abort ();
2368 return operands->operand[opno];
2369 }
2370
2371 /* Install UVAL as the value of OPERAND in INSN. */
2372
2373 static inline void
insn_insert_operand(struct mips_cl_insn * insn,const struct mips_operand * operand,unsigned int uval)2374 insn_insert_operand (struct mips_cl_insn *insn,
2375 const struct mips_operand *operand, unsigned int uval)
2376 {
2377 if (mips_opts.mips16
2378 && operand->type == OP_INT && operand->lsb == 0
2379 && mips_opcode_32bit_p (insn->insn_mo))
2380 insn->insn_opcode |= mips16_immed_extend (uval, operand->size);
2381 else
2382 insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval);
2383 }
2384
2385 /* Extract the value of OPERAND from INSN. */
2386
2387 static inline unsigned
insn_extract_operand(const struct mips_cl_insn * insn,const struct mips_operand * operand)2388 insn_extract_operand (const struct mips_cl_insn *insn,
2389 const struct mips_operand *operand)
2390 {
2391 return mips_extract_operand (operand, insn->insn_opcode);
2392 }
2393
2394 /* Record the current MIPS16/microMIPS mode in now_seg. */
2395
2396 static void
mips_record_compressed_mode(void)2397 mips_record_compressed_mode (void)
2398 {
2399 segment_info_type *si;
2400
2401 si = seg_info (now_seg);
2402 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
2403 si->tc_segment_info_data.mips16 = mips_opts.mips16;
2404 if (si->tc_segment_info_data.micromips != mips_opts.micromips)
2405 si->tc_segment_info_data.micromips = mips_opts.micromips;
2406 }
2407
2408 /* Read a standard MIPS instruction from BUF. */
2409
2410 static unsigned long
read_insn(char * buf)2411 read_insn (char *buf)
2412 {
2413 if (target_big_endian)
2414 return bfd_getb32 ((bfd_byte *) buf);
2415 else
2416 return bfd_getl32 ((bfd_byte *) buf);
2417 }
2418
2419 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2420 the next byte. */
2421
2422 static char *
write_insn(char * buf,unsigned int insn)2423 write_insn (char *buf, unsigned int insn)
2424 {
2425 md_number_to_chars (buf, insn, 4);
2426 return buf + 4;
2427 }
2428
2429 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2430 has length LENGTH. */
2431
2432 static unsigned long
read_compressed_insn(char * buf,unsigned int length)2433 read_compressed_insn (char *buf, unsigned int length)
2434 {
2435 unsigned long insn;
2436 unsigned int i;
2437
2438 insn = 0;
2439 for (i = 0; i < length; i += 2)
2440 {
2441 insn <<= 16;
2442 if (target_big_endian)
2443 insn |= bfd_getb16 ((char *) buf);
2444 else
2445 insn |= bfd_getl16 ((char *) buf);
2446 buf += 2;
2447 }
2448 return insn;
2449 }
2450
2451 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2452 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2453
2454 static char *
write_compressed_insn(char * buf,unsigned int insn,unsigned int length)2455 write_compressed_insn (char *buf, unsigned int insn, unsigned int length)
2456 {
2457 unsigned int i;
2458
2459 for (i = 0; i < length; i += 2)
2460 md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2);
2461 return buf + length;
2462 }
2463
2464 /* Install INSN at the location specified by its "frag" and "where" fields. */
2465
2466 static void
install_insn(const struct mips_cl_insn * insn)2467 install_insn (const struct mips_cl_insn *insn)
2468 {
2469 char *f = insn->frag->fr_literal + insn->where;
2470 if (HAVE_CODE_COMPRESSION)
2471 write_compressed_insn (f, insn->insn_opcode, insn_length (insn));
2472 else
2473 write_insn (f, insn->insn_opcode);
2474 mips_record_compressed_mode ();
2475 }
2476
2477 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2478 and install the opcode in the new location. */
2479
2480 static void
move_insn(struct mips_cl_insn * insn,fragS * frag,long where)2481 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
2482 {
2483 size_t i;
2484
2485 insn->frag = frag;
2486 insn->where = where;
2487 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
2488 if (insn->fixp[i] != NULL)
2489 {
2490 insn->fixp[i]->fx_frag = frag;
2491 insn->fixp[i]->fx_where = where;
2492 }
2493 install_insn (insn);
2494 }
2495
2496 /* Add INSN to the end of the output. */
2497
2498 static void
add_fixed_insn(struct mips_cl_insn * insn)2499 add_fixed_insn (struct mips_cl_insn *insn)
2500 {
2501 char *f = frag_more (insn_length (insn));
2502 move_insn (insn, frag_now, f - frag_now->fr_literal);
2503 }
2504
2505 /* Start a variant frag and move INSN to the start of the variant part,
2506 marking it as fixed. The other arguments are as for frag_var. */
2507
2508 static void
add_relaxed_insn(struct mips_cl_insn * insn,int max_chars,int var,relax_substateT subtype,symbolS * symbol,offsetT offset)2509 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
2510 relax_substateT subtype, symbolS *symbol, offsetT offset)
2511 {
2512 frag_grow (max_chars);
2513 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
2514 insn->fixed_p = 1;
2515 frag_var (rs_machine_dependent, max_chars, var,
2516 subtype, symbol, offset, NULL);
2517 }
2518
2519 /* Insert N copies of INSN into the history buffer, starting at
2520 position FIRST. Neither FIRST nor N need to be clipped. */
2521
2522 static void
insert_into_history(unsigned int first,unsigned int n,const struct mips_cl_insn * insn)2523 insert_into_history (unsigned int first, unsigned int n,
2524 const struct mips_cl_insn *insn)
2525 {
2526 if (mips_relax.sequence != 2)
2527 {
2528 unsigned int i;
2529
2530 for (i = ARRAY_SIZE (history); i-- > first;)
2531 if (i >= first + n)
2532 history[i] = history[i - n];
2533 else
2534 history[i] = *insn;
2535 }
2536 }
2537
2538 /* Clear the error in insn_error. */
2539
2540 static void
clear_insn_error(void)2541 clear_insn_error (void)
2542 {
2543 memset (&insn_error, 0, sizeof (insn_error));
2544 }
2545
2546 /* Possibly record error message MSG for the current instruction.
2547 If the error is about a particular argument, ARGNUM is the 1-based
2548 number of that argument, otherwise it is 0. FORMAT is the format
2549 of MSG. Return true if MSG was used, false if the current message
2550 was kept. */
2551
2552 static bool
set_insn_error_format(int argnum,enum mips_insn_error_format format,const char * msg)2553 set_insn_error_format (int argnum, enum mips_insn_error_format format,
2554 const char *msg)
2555 {
2556 if (argnum == 0)
2557 {
2558 /* Give priority to errors against specific arguments, and to
2559 the first whole-instruction message. */
2560 if (insn_error.msg)
2561 return false;
2562 }
2563 else
2564 {
2565 /* Keep insn_error if it is against a later argument. */
2566 if (argnum < insn_error.min_argnum)
2567 return false;
2568
2569 /* If both errors are against the same argument but are different,
2570 give up on reporting a specific error for this argument.
2571 See the comment about mips_insn_error for details. */
2572 if (argnum == insn_error.min_argnum
2573 && insn_error.msg
2574 && strcmp (insn_error.msg, msg) != 0)
2575 {
2576 insn_error.msg = 0;
2577 insn_error.min_argnum += 1;
2578 return false;
2579 }
2580 }
2581 insn_error.min_argnum = argnum;
2582 insn_error.format = format;
2583 insn_error.msg = msg;
2584 return true;
2585 }
2586
2587 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2588 as for set_insn_error_format. */
2589
2590 static void
set_insn_error(int argnum,const char * msg)2591 set_insn_error (int argnum, const char *msg)
2592 {
2593 set_insn_error_format (argnum, ERR_FMT_PLAIN, msg);
2594 }
2595
2596 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2597 as for set_insn_error_format. */
2598
2599 static void
set_insn_error_i(int argnum,const char * msg,int i)2600 set_insn_error_i (int argnum, const char *msg, int i)
2601 {
2602 if (set_insn_error_format (argnum, ERR_FMT_I, msg))
2603 insn_error.u.i = i;
2604 }
2605
2606 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2607 are as for set_insn_error_format. */
2608
2609 static void
set_insn_error_ss(int argnum,const char * msg,const char * s1,const char * s2)2610 set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2)
2611 {
2612 if (set_insn_error_format (argnum, ERR_FMT_SS, msg))
2613 {
2614 insn_error.u.ss[0] = s1;
2615 insn_error.u.ss[1] = s2;
2616 }
2617 }
2618
2619 /* Report the error in insn_error, which is against assembly code STR. */
2620
2621 static void
report_insn_error(const char * str)2622 report_insn_error (const char *str)
2623 {
2624 const char *msg = concat (insn_error.msg, " `%s'", NULL);
2625
2626 switch (insn_error.format)
2627 {
2628 case ERR_FMT_PLAIN:
2629 as_bad (msg, str);
2630 break;
2631
2632 case ERR_FMT_I:
2633 as_bad (msg, insn_error.u.i, str);
2634 break;
2635
2636 case ERR_FMT_SS:
2637 as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str);
2638 break;
2639 }
2640
2641 free ((char *) msg);
2642 }
2643
2644 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2645 the idea is to make it obvious at a glance that each errata is
2646 included. */
2647
2648 static void
init_vr4120_conflicts(void)2649 init_vr4120_conflicts (void)
2650 {
2651 #define CONFLICT(FIRST, SECOND) \
2652 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2653
2654 /* Errata 21 - [D]DIV[U] after [D]MACC */
2655 CONFLICT (MACC, DIV);
2656 CONFLICT (DMACC, DIV);
2657
2658 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2659 CONFLICT (DMULT, DMULT);
2660 CONFLICT (DMULT, DMACC);
2661 CONFLICT (DMACC, DMULT);
2662 CONFLICT (DMACC, DMACC);
2663
2664 /* Errata 24 - MT{LO,HI} after [D]MACC */
2665 CONFLICT (MACC, MTHILO);
2666 CONFLICT (DMACC, MTHILO);
2667
2668 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2669 instruction is executed immediately after a MACC or DMACC
2670 instruction, the result of [either instruction] is incorrect." */
2671 CONFLICT (MACC, MULT);
2672 CONFLICT (MACC, DMULT);
2673 CONFLICT (DMACC, MULT);
2674 CONFLICT (DMACC, DMULT);
2675
2676 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2677 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2678 DDIV or DDIVU instruction, the result of the MACC or
2679 DMACC instruction is incorrect.". */
2680 CONFLICT (DMULT, MACC);
2681 CONFLICT (DMULT, DMACC);
2682 CONFLICT (DIV, MACC);
2683 CONFLICT (DIV, DMACC);
2684
2685 #undef CONFLICT
2686 }
2687
2688 struct regname {
2689 const char *name;
2690 unsigned int num;
2691 };
2692
2693 #define RNUM_MASK 0x00000ff
2694 #define RTYPE_MASK 0x0ffff00
2695 #define RTYPE_NUM 0x0000100
2696 #define RTYPE_FPU 0x0000200
2697 #define RTYPE_FCC 0x0000400
2698 #define RTYPE_VEC 0x0000800
2699 #define RTYPE_GP 0x0001000
2700 #define RTYPE_CP0 0x0002000
2701 #define RTYPE_PC 0x0004000
2702 #define RTYPE_ACC 0x0008000
2703 #define RTYPE_CCC 0x0010000
2704 #define RTYPE_VI 0x0020000
2705 #define RTYPE_VF 0x0040000
2706 #define RTYPE_R5900_I 0x0080000
2707 #define RTYPE_R5900_Q 0x0100000
2708 #define RTYPE_R5900_R 0x0200000
2709 #define RTYPE_R5900_ACC 0x0400000
2710 #define RTYPE_MSA 0x0800000
2711 #define RWARN 0x8000000
2712
2713 #define GENERIC_REGISTER_NUMBERS \
2714 {"$0", RTYPE_NUM | 0}, \
2715 {"$1", RTYPE_NUM | 1}, \
2716 {"$2", RTYPE_NUM | 2}, \
2717 {"$3", RTYPE_NUM | 3}, \
2718 {"$4", RTYPE_NUM | 4}, \
2719 {"$5", RTYPE_NUM | 5}, \
2720 {"$6", RTYPE_NUM | 6}, \
2721 {"$7", RTYPE_NUM | 7}, \
2722 {"$8", RTYPE_NUM | 8}, \
2723 {"$9", RTYPE_NUM | 9}, \
2724 {"$10", RTYPE_NUM | 10}, \
2725 {"$11", RTYPE_NUM | 11}, \
2726 {"$12", RTYPE_NUM | 12}, \
2727 {"$13", RTYPE_NUM | 13}, \
2728 {"$14", RTYPE_NUM | 14}, \
2729 {"$15", RTYPE_NUM | 15}, \
2730 {"$16", RTYPE_NUM | 16}, \
2731 {"$17", RTYPE_NUM | 17}, \
2732 {"$18", RTYPE_NUM | 18}, \
2733 {"$19", RTYPE_NUM | 19}, \
2734 {"$20", RTYPE_NUM | 20}, \
2735 {"$21", RTYPE_NUM | 21}, \
2736 {"$22", RTYPE_NUM | 22}, \
2737 {"$23", RTYPE_NUM | 23}, \
2738 {"$24", RTYPE_NUM | 24}, \
2739 {"$25", RTYPE_NUM | 25}, \
2740 {"$26", RTYPE_NUM | 26}, \
2741 {"$27", RTYPE_NUM | 27}, \
2742 {"$28", RTYPE_NUM | 28}, \
2743 {"$29", RTYPE_NUM | 29}, \
2744 {"$30", RTYPE_NUM | 30}, \
2745 {"$31", RTYPE_NUM | 31}
2746
2747 #define FPU_REGISTER_NAMES \
2748 {"$f0", RTYPE_FPU | 0}, \
2749 {"$f1", RTYPE_FPU | 1}, \
2750 {"$f2", RTYPE_FPU | 2}, \
2751 {"$f3", RTYPE_FPU | 3}, \
2752 {"$f4", RTYPE_FPU | 4}, \
2753 {"$f5", RTYPE_FPU | 5}, \
2754 {"$f6", RTYPE_FPU | 6}, \
2755 {"$f7", RTYPE_FPU | 7}, \
2756 {"$f8", RTYPE_FPU | 8}, \
2757 {"$f9", RTYPE_FPU | 9}, \
2758 {"$f10", RTYPE_FPU | 10}, \
2759 {"$f11", RTYPE_FPU | 11}, \
2760 {"$f12", RTYPE_FPU | 12}, \
2761 {"$f13", RTYPE_FPU | 13}, \
2762 {"$f14", RTYPE_FPU | 14}, \
2763 {"$f15", RTYPE_FPU | 15}, \
2764 {"$f16", RTYPE_FPU | 16}, \
2765 {"$f17", RTYPE_FPU | 17}, \
2766 {"$f18", RTYPE_FPU | 18}, \
2767 {"$f19", RTYPE_FPU | 19}, \
2768 {"$f20", RTYPE_FPU | 20}, \
2769 {"$f21", RTYPE_FPU | 21}, \
2770 {"$f22", RTYPE_FPU | 22}, \
2771 {"$f23", RTYPE_FPU | 23}, \
2772 {"$f24", RTYPE_FPU | 24}, \
2773 {"$f25", RTYPE_FPU | 25}, \
2774 {"$f26", RTYPE_FPU | 26}, \
2775 {"$f27", RTYPE_FPU | 27}, \
2776 {"$f28", RTYPE_FPU | 28}, \
2777 {"$f29", RTYPE_FPU | 29}, \
2778 {"$f30", RTYPE_FPU | 30}, \
2779 {"$f31", RTYPE_FPU | 31}
2780
2781 #define FPU_CONDITION_CODE_NAMES \
2782 {"$fcc0", RTYPE_FCC | 0}, \
2783 {"$fcc1", RTYPE_FCC | 1}, \
2784 {"$fcc2", RTYPE_FCC | 2}, \
2785 {"$fcc3", RTYPE_FCC | 3}, \
2786 {"$fcc4", RTYPE_FCC | 4}, \
2787 {"$fcc5", RTYPE_FCC | 5}, \
2788 {"$fcc6", RTYPE_FCC | 6}, \
2789 {"$fcc7", RTYPE_FCC | 7}
2790
2791 #define COPROC_CONDITION_CODE_NAMES \
2792 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2793 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2794 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2795 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2796 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2797 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2798 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2799 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2800
2801 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2802 {"$a4", RTYPE_GP | 8}, \
2803 {"$a5", RTYPE_GP | 9}, \
2804 {"$a6", RTYPE_GP | 10}, \
2805 {"$a7", RTYPE_GP | 11}, \
2806 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2807 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2808 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2809 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2810 {"$t0", RTYPE_GP | 12}, \
2811 {"$t1", RTYPE_GP | 13}, \
2812 {"$t2", RTYPE_GP | 14}, \
2813 {"$t3", RTYPE_GP | 15}
2814
2815 #define O32_SYMBOLIC_REGISTER_NAMES \
2816 {"$t0", RTYPE_GP | 8}, \
2817 {"$t1", RTYPE_GP | 9}, \
2818 {"$t2", RTYPE_GP | 10}, \
2819 {"$t3", RTYPE_GP | 11}, \
2820 {"$t4", RTYPE_GP | 12}, \
2821 {"$t5", RTYPE_GP | 13}, \
2822 {"$t6", RTYPE_GP | 14}, \
2823 {"$t7", RTYPE_GP | 15}, \
2824 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2825 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2826 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2827 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2828
2829 /* Remaining symbolic register names. */
2830 #define SYMBOLIC_REGISTER_NAMES \
2831 {"$zero", RTYPE_GP | 0}, \
2832 {"$at", RTYPE_GP | 1}, \
2833 {"$AT", RTYPE_GP | 1}, \
2834 {"$v0", RTYPE_GP | 2}, \
2835 {"$v1", RTYPE_GP | 3}, \
2836 {"$a0", RTYPE_GP | 4}, \
2837 {"$a1", RTYPE_GP | 5}, \
2838 {"$a2", RTYPE_GP | 6}, \
2839 {"$a3", RTYPE_GP | 7}, \
2840 {"$s0", RTYPE_GP | 16}, \
2841 {"$s1", RTYPE_GP | 17}, \
2842 {"$s2", RTYPE_GP | 18}, \
2843 {"$s3", RTYPE_GP | 19}, \
2844 {"$s4", RTYPE_GP | 20}, \
2845 {"$s5", RTYPE_GP | 21}, \
2846 {"$s6", RTYPE_GP | 22}, \
2847 {"$s7", RTYPE_GP | 23}, \
2848 {"$t8", RTYPE_GP | 24}, \
2849 {"$t9", RTYPE_GP | 25}, \
2850 {"$k0", RTYPE_GP | 26}, \
2851 {"$kt0", RTYPE_GP | 26}, \
2852 {"$k1", RTYPE_GP | 27}, \
2853 {"$kt1", RTYPE_GP | 27}, \
2854 {"$gp", RTYPE_GP | 28}, \
2855 {"$sp", RTYPE_GP | 29}, \
2856 {"$s8", RTYPE_GP | 30}, \
2857 {"$fp", RTYPE_GP | 30}, \
2858 {"$ra", RTYPE_GP | 31}
2859
2860 #define MIPS16_SPECIAL_REGISTER_NAMES \
2861 {"$pc", RTYPE_PC | 0}
2862
2863 #define MDMX_VECTOR_REGISTER_NAMES \
2864 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2865 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2866 {"$v2", RTYPE_VEC | 2}, \
2867 {"$v3", RTYPE_VEC | 3}, \
2868 {"$v4", RTYPE_VEC | 4}, \
2869 {"$v5", RTYPE_VEC | 5}, \
2870 {"$v6", RTYPE_VEC | 6}, \
2871 {"$v7", RTYPE_VEC | 7}, \
2872 {"$v8", RTYPE_VEC | 8}, \
2873 {"$v9", RTYPE_VEC | 9}, \
2874 {"$v10", RTYPE_VEC | 10}, \
2875 {"$v11", RTYPE_VEC | 11}, \
2876 {"$v12", RTYPE_VEC | 12}, \
2877 {"$v13", RTYPE_VEC | 13}, \
2878 {"$v14", RTYPE_VEC | 14}, \
2879 {"$v15", RTYPE_VEC | 15}, \
2880 {"$v16", RTYPE_VEC | 16}, \
2881 {"$v17", RTYPE_VEC | 17}, \
2882 {"$v18", RTYPE_VEC | 18}, \
2883 {"$v19", RTYPE_VEC | 19}, \
2884 {"$v20", RTYPE_VEC | 20}, \
2885 {"$v21", RTYPE_VEC | 21}, \
2886 {"$v22", RTYPE_VEC | 22}, \
2887 {"$v23", RTYPE_VEC | 23}, \
2888 {"$v24", RTYPE_VEC | 24}, \
2889 {"$v25", RTYPE_VEC | 25}, \
2890 {"$v26", RTYPE_VEC | 26}, \
2891 {"$v27", RTYPE_VEC | 27}, \
2892 {"$v28", RTYPE_VEC | 28}, \
2893 {"$v29", RTYPE_VEC | 29}, \
2894 {"$v30", RTYPE_VEC | 30}, \
2895 {"$v31", RTYPE_VEC | 31}
2896
2897 #define R5900_I_NAMES \
2898 {"$I", RTYPE_R5900_I | 0}
2899
2900 #define R5900_Q_NAMES \
2901 {"$Q", RTYPE_R5900_Q | 0}
2902
2903 #define R5900_R_NAMES \
2904 {"$R", RTYPE_R5900_R | 0}
2905
2906 #define R5900_ACC_NAMES \
2907 {"$ACC", RTYPE_R5900_ACC | 0 }
2908
2909 #define MIPS_DSP_ACCUMULATOR_NAMES \
2910 {"$ac0", RTYPE_ACC | 0}, \
2911 {"$ac1", RTYPE_ACC | 1}, \
2912 {"$ac2", RTYPE_ACC | 2}, \
2913 {"$ac3", RTYPE_ACC | 3}
2914
2915 static const struct regname reg_names[] = {
2916 GENERIC_REGISTER_NUMBERS,
2917 FPU_REGISTER_NAMES,
2918 FPU_CONDITION_CODE_NAMES,
2919 COPROC_CONDITION_CODE_NAMES,
2920
2921 /* The $txx registers depends on the abi,
2922 these will be added later into the symbol table from
2923 one of the tables below once mips_abi is set after
2924 parsing of arguments from the command line. */
2925 SYMBOLIC_REGISTER_NAMES,
2926
2927 MIPS16_SPECIAL_REGISTER_NAMES,
2928 MDMX_VECTOR_REGISTER_NAMES,
2929 R5900_I_NAMES,
2930 R5900_Q_NAMES,
2931 R5900_R_NAMES,
2932 R5900_ACC_NAMES,
2933 MIPS_DSP_ACCUMULATOR_NAMES,
2934 {0, 0}
2935 };
2936
2937 static const struct regname reg_names_o32[] = {
2938 O32_SYMBOLIC_REGISTER_NAMES,
2939 {0, 0}
2940 };
2941
2942 static const struct regname reg_names_n32n64[] = {
2943 N32N64_SYMBOLIC_REGISTER_NAMES,
2944 {0, 0}
2945 };
2946
2947 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2948 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2949 of these register symbols, return the associated vector register,
2950 otherwise return SYMVAL itself. */
2951
2952 static unsigned int
mips_prefer_vec_regno(unsigned int symval)2953 mips_prefer_vec_regno (unsigned int symval)
2954 {
2955 if ((symval & -2) == (RTYPE_GP | 2))
2956 return RTYPE_VEC | (symval & 1);
2957 return symval;
2958 }
2959
2960 /* Return true if string [S, E) is a valid register name, storing its
2961 symbol value in *SYMVAL_PTR if so. */
2962
2963 static bool
mips_parse_register_1(char * s,char * e,unsigned int * symval_ptr)2964 mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
2965 {
2966 char save_c;
2967 symbolS *symbol;
2968
2969 /* Terminate name. */
2970 save_c = *e;
2971 *e = '\0';
2972
2973 /* Look up the name. */
2974 symbol = symbol_find (s);
2975 *e = save_c;
2976
2977 if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
2978 return false;
2979
2980 *symval_ptr = S_GET_VALUE (symbol);
2981 return true;
2982 }
2983
2984 /* Return true if the string at *SPTR is a valid register name. Allow it
2985 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2986 is nonnull.
2987
2988 When returning true, move *SPTR past the register, store the
2989 register's symbol value in *SYMVAL_PTR and the channel mask in
2990 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2991 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2992 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2993
2994 static bool
mips_parse_register(char ** sptr,unsigned int * symval_ptr,unsigned int * channels_ptr)2995 mips_parse_register (char **sptr, unsigned int *symval_ptr,
2996 unsigned int *channels_ptr)
2997 {
2998 char *s, *e, *m;
2999 const char *q;
3000 unsigned int channels, symval, bit;
3001
3002 /* Find end of name. */
3003 s = e = *sptr;
3004 if (is_name_beginner (*e))
3005 ++e;
3006 while (is_part_of_name (*e))
3007 ++e;
3008
3009 channels = 0;
3010 if (!mips_parse_register_1 (s, e, &symval))
3011 {
3012 if (!channels_ptr)
3013 return false;
3014
3015 /* Eat characters from the end of the string that are valid
3016 channel suffixes. The preceding register must be $ACC or
3017 end with a digit, so there is no ambiguity. */
3018 bit = 1;
3019 m = e;
3020 for (q = "wzyx"; *q; q++, bit <<= 1)
3021 if (m > s && m[-1] == *q)
3022 {
3023 --m;
3024 channels |= bit;
3025 }
3026
3027 if (channels == 0
3028 || !mips_parse_register_1 (s, m, &symval)
3029 || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
3030 return false;
3031 }
3032
3033 *sptr = e;
3034 *symval_ptr = symval;
3035 if (channels_ptr)
3036 *channels_ptr = channels;
3037 return true;
3038 }
3039
3040 /* Check if SPTR points at a valid register specifier according to TYPES.
3041 If so, then return 1, advance S to consume the specifier and store
3042 the register's number in REGNOP, otherwise return 0. */
3043
3044 static int
reg_lookup(char ** s,unsigned int types,unsigned int * regnop)3045 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
3046 {
3047 unsigned int regno;
3048
3049 if (mips_parse_register (s, ®no, NULL))
3050 {
3051 if (types & RTYPE_VEC)
3052 regno = mips_prefer_vec_regno (regno);
3053 if (regno & types)
3054 regno &= RNUM_MASK;
3055 else
3056 regno = ~0;
3057 }
3058 else
3059 {
3060 if (types & RWARN)
3061 as_warn (_("unrecognized register name `%s'"), *s);
3062 regno = ~0;
3063 }
3064 if (regnop)
3065 *regnop = regno;
3066 return regno <= RNUM_MASK;
3067 }
3068
3069 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3070 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3071
3072 static char *
mips_parse_vu0_channels(char * s,unsigned int * channels)3073 mips_parse_vu0_channels (char *s, unsigned int *channels)
3074 {
3075 unsigned int i;
3076
3077 *channels = 0;
3078 for (i = 0; i < 4; i++)
3079 if (*s == "xyzw"[i])
3080 {
3081 *channels |= 1 << (3 - i);
3082 ++s;
3083 }
3084 return s;
3085 }
3086
3087 /* Token types for parsed operand lists. */
3088 enum mips_operand_token_type {
3089 /* A plain register, e.g. $f2. */
3090 OT_REG,
3091
3092 /* A 4-bit XYZW channel mask. */
3093 OT_CHANNELS,
3094
3095 /* A constant vector index, e.g. [1]. */
3096 OT_INTEGER_INDEX,
3097
3098 /* A register vector index, e.g. [$2]. */
3099 OT_REG_INDEX,
3100
3101 /* A continuous range of registers, e.g. $s0-$s4. */
3102 OT_REG_RANGE,
3103
3104 /* A (possibly relocated) expression. */
3105 OT_INTEGER,
3106
3107 /* A floating-point value. */
3108 OT_FLOAT,
3109
3110 /* A single character. This can be '(', ')' or ',', but '(' only appears
3111 before OT_REGs. */
3112 OT_CHAR,
3113
3114 /* A doubled character, either "--" or "++". */
3115 OT_DOUBLE_CHAR,
3116
3117 /* The end of the operand list. */
3118 OT_END
3119 };
3120
3121 /* A parsed operand token. */
3122 struct mips_operand_token
3123 {
3124 /* The type of token. */
3125 enum mips_operand_token_type type;
3126 union
3127 {
3128 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3129 unsigned int regno;
3130
3131 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3132 unsigned int channels;
3133
3134 /* The integer value of an OT_INTEGER_INDEX. */
3135 addressT index;
3136
3137 /* The two register symbol values involved in an OT_REG_RANGE. */
3138 struct {
3139 unsigned int regno1;
3140 unsigned int regno2;
3141 } reg_range;
3142
3143 /* The value of an OT_INTEGER. The value is represented as an
3144 expression and the relocation operators that were applied to
3145 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3146 relocation operators were used. */
3147 struct {
3148 expressionS value;
3149 bfd_reloc_code_real_type relocs[3];
3150 } integer;
3151
3152 /* The binary data for an OT_FLOAT constant, and the number of bytes
3153 in the constant. */
3154 struct {
3155 unsigned char data[8];
3156 int length;
3157 } flt;
3158
3159 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3160 char ch;
3161 } u;
3162 };
3163
3164 /* An obstack used to construct lists of mips_operand_tokens. */
3165 static struct obstack mips_operand_tokens;
3166
3167 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3168
3169 static void
mips_add_token(struct mips_operand_token * token,enum mips_operand_token_type type)3170 mips_add_token (struct mips_operand_token *token,
3171 enum mips_operand_token_type type)
3172 {
3173 token->type = type;
3174 obstack_grow (&mips_operand_tokens, token, sizeof (*token));
3175 }
3176
3177 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3178 and OT_REG tokens for them if so, and return a pointer to the first
3179 unconsumed character. Return null otherwise. */
3180
3181 static char *
mips_parse_base_start(char * s)3182 mips_parse_base_start (char *s)
3183 {
3184 struct mips_operand_token token;
3185 unsigned int regno, channels;
3186 bool decrement_p;
3187
3188 if (*s != '(')
3189 return 0;
3190
3191 ++s;
3192 SKIP_SPACE_TABS (s);
3193
3194 /* Only match "--" as part of a base expression. In other contexts "--X"
3195 is a double negative. */
3196 decrement_p = (s[0] == '-' && s[1] == '-');
3197 if (decrement_p)
3198 {
3199 s += 2;
3200 SKIP_SPACE_TABS (s);
3201 }
3202
3203 /* Allow a channel specifier because that leads to better error messages
3204 than treating something like "$vf0x++" as an expression. */
3205 if (!mips_parse_register (&s, ®no, &channels))
3206 return 0;
3207
3208 token.u.ch = '(';
3209 mips_add_token (&token, OT_CHAR);
3210
3211 if (decrement_p)
3212 {
3213 token.u.ch = '-';
3214 mips_add_token (&token, OT_DOUBLE_CHAR);
3215 }
3216
3217 token.u.regno = regno;
3218 mips_add_token (&token, OT_REG);
3219
3220 if (channels)
3221 {
3222 token.u.channels = channels;
3223 mips_add_token (&token, OT_CHANNELS);
3224 }
3225
3226 /* For consistency, only match "++" as part of base expressions too. */
3227 SKIP_SPACE_TABS (s);
3228 if (s[0] == '+' && s[1] == '+')
3229 {
3230 s += 2;
3231 token.u.ch = '+';
3232 mips_add_token (&token, OT_DOUBLE_CHAR);
3233 }
3234
3235 return s;
3236 }
3237
3238 /* Parse one or more tokens from S. Return a pointer to the first
3239 unconsumed character on success. Return null if an error was found
3240 and store the error text in insn_error. FLOAT_FORMAT is as for
3241 mips_parse_arguments. */
3242
3243 static char *
mips_parse_argument_token(char * s,char float_format)3244 mips_parse_argument_token (char *s, char float_format)
3245 {
3246 char *end, *save_in;
3247 const char *err;
3248 unsigned int regno1, regno2, channels;
3249 struct mips_operand_token token;
3250
3251 /* First look for "($reg", since we want to treat that as an
3252 OT_CHAR and OT_REG rather than an expression. */
3253 end = mips_parse_base_start (s);
3254 if (end)
3255 return end;
3256
3257 /* Handle other characters that end up as OT_CHARs. */
3258 if (*s == ')' || *s == ',')
3259 {
3260 token.u.ch = *s;
3261 mips_add_token (&token, OT_CHAR);
3262 ++s;
3263 return s;
3264 }
3265
3266 /* Handle tokens that start with a register. */
3267 if (mips_parse_register (&s, ®no1, &channels))
3268 {
3269 if (channels)
3270 {
3271 /* A register and a VU0 channel suffix. */
3272 token.u.regno = regno1;
3273 mips_add_token (&token, OT_REG);
3274
3275 token.u.channels = channels;
3276 mips_add_token (&token, OT_CHANNELS);
3277 return s;
3278 }
3279
3280 SKIP_SPACE_TABS (s);
3281 if (*s == '-')
3282 {
3283 /* A register range. */
3284 ++s;
3285 SKIP_SPACE_TABS (s);
3286 if (!mips_parse_register (&s, ®no2, NULL))
3287 {
3288 set_insn_error (0, _("invalid register range"));
3289 return 0;
3290 }
3291
3292 token.u.reg_range.regno1 = regno1;
3293 token.u.reg_range.regno2 = regno2;
3294 mips_add_token (&token, OT_REG_RANGE);
3295 return s;
3296 }
3297
3298 /* Add the register itself. */
3299 token.u.regno = regno1;
3300 mips_add_token (&token, OT_REG);
3301
3302 /* Check for a vector index. */
3303 if (*s == '[')
3304 {
3305 ++s;
3306 SKIP_SPACE_TABS (s);
3307 if (mips_parse_register (&s, &token.u.regno, NULL))
3308 mips_add_token (&token, OT_REG_INDEX);
3309 else
3310 {
3311 expressionS element;
3312
3313 my_getExpression (&element, s);
3314 if (element.X_op != O_constant)
3315 {
3316 set_insn_error (0, _("vector element must be constant"));
3317 return 0;
3318 }
3319 s = expr_parse_end;
3320 token.u.index = element.X_add_number;
3321 mips_add_token (&token, OT_INTEGER_INDEX);
3322 }
3323 SKIP_SPACE_TABS (s);
3324 if (*s != ']')
3325 {
3326 set_insn_error (0, _("missing `]'"));
3327 return 0;
3328 }
3329 ++s;
3330 }
3331 return s;
3332 }
3333
3334 if (float_format)
3335 {
3336 /* First try to treat expressions as floats. */
3337 save_in = input_line_pointer;
3338 input_line_pointer = s;
3339 err = md_atof (float_format, (char *) token.u.flt.data,
3340 &token.u.flt.length);
3341 end = input_line_pointer;
3342 input_line_pointer = save_in;
3343 if (err && *err)
3344 {
3345 set_insn_error (0, err);
3346 return 0;
3347 }
3348 if (s != end)
3349 {
3350 mips_add_token (&token, OT_FLOAT);
3351 return end;
3352 }
3353 }
3354
3355 /* Treat everything else as an integer expression. */
3356 token.u.integer.relocs[0] = BFD_RELOC_UNUSED;
3357 token.u.integer.relocs[1] = BFD_RELOC_UNUSED;
3358 token.u.integer.relocs[2] = BFD_RELOC_UNUSED;
3359 my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s);
3360 s = expr_parse_end;
3361 mips_add_token (&token, OT_INTEGER);
3362 return s;
3363 }
3364
3365 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3366 if expressions should be treated as 32-bit floating-point constants,
3367 'd' if they should be treated as 64-bit floating-point constants,
3368 or 0 if they should be treated as integer expressions (the usual case).
3369
3370 Return a list of tokens on success, otherwise return 0. The caller
3371 must obstack_free the list after use. */
3372
3373 static struct mips_operand_token *
mips_parse_arguments(char * s,char float_format)3374 mips_parse_arguments (char *s, char float_format)
3375 {
3376 struct mips_operand_token token;
3377
3378 SKIP_SPACE_TABS (s);
3379 while (*s)
3380 {
3381 s = mips_parse_argument_token (s, float_format);
3382 if (!s)
3383 {
3384 obstack_free (&mips_operand_tokens,
3385 obstack_finish (&mips_operand_tokens));
3386 return 0;
3387 }
3388 SKIP_SPACE_TABS (s);
3389 }
3390 mips_add_token (&token, OT_END);
3391 return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens);
3392 }
3393
3394 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3395 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3396
3397 static bool
is_opcode_valid(const struct mips_opcode * mo)3398 is_opcode_valid (const struct mips_opcode *mo)
3399 {
3400 int isa = mips_opts.isa;
3401 int ase = mips_opts.ase;
3402 int fp_s, fp_d;
3403 unsigned int i;
3404
3405 if (ISA_HAS_64BIT_REGS (isa))
3406 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3407 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3408 ase |= mips_ases[i].flags64;
3409
3410 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3411 return false;
3412
3413 /* Check whether the instruction or macro requires single-precision or
3414 double-precision floating-point support. Note that this information is
3415 stored differently in the opcode table for insns and macros. */
3416 if (mo->pinfo == INSN_MACRO)
3417 {
3418 fp_s = mo->pinfo2 & INSN2_M_FP_S;
3419 fp_d = mo->pinfo2 & INSN2_M_FP_D;
3420 }
3421 else
3422 {
3423 fp_s = mo->pinfo & FP_S;
3424 fp_d = mo->pinfo & FP_D;
3425 }
3426
3427 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
3428 return false;
3429
3430 if (fp_s && mips_opts.soft_float)
3431 return false;
3432
3433 return true;
3434 }
3435
3436 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3437 selected ISA and architecture. */
3438
3439 static bool
is_opcode_valid_16(const struct mips_opcode * mo)3440 is_opcode_valid_16 (const struct mips_opcode *mo)
3441 {
3442 int isa = mips_opts.isa;
3443 int ase = mips_opts.ase;
3444 unsigned int i;
3445
3446 if (ISA_HAS_64BIT_REGS (isa))
3447 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
3448 if ((ase & mips_ases[i].flags) == mips_ases[i].flags)
3449 ase |= mips_ases[i].flags64;
3450
3451 return opcode_is_member (mo, isa, ase, mips_opts.arch);
3452 }
3453
3454 /* Return TRUE if the size of the microMIPS opcode MO matches one
3455 explicitly requested. Always TRUE in the standard MIPS mode.
3456 Use is_size_valid_16 for MIPS16 opcodes. */
3457
3458 static bool
is_size_valid(const struct mips_opcode * mo)3459 is_size_valid (const struct mips_opcode *mo)
3460 {
3461 if (!mips_opts.micromips)
3462 return true;
3463
3464 if (mips_opts.insn32)
3465 {
3466 if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4)
3467 return false;
3468 if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0)
3469 return false;
3470 }
3471 if (!forced_insn_length)
3472 return true;
3473 if (mo->pinfo == INSN_MACRO)
3474 return false;
3475 return forced_insn_length == micromips_insn_length (mo);
3476 }
3477
3478 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3479 explicitly requested. */
3480
3481 static bool
is_size_valid_16(const struct mips_opcode * mo)3482 is_size_valid_16 (const struct mips_opcode *mo)
3483 {
3484 if (!forced_insn_length)
3485 return true;
3486 if (mo->pinfo == INSN_MACRO)
3487 return false;
3488 if (forced_insn_length == 2 && mips_opcode_32bit_p (mo))
3489 return false;
3490 if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY))
3491 return false;
3492 return true;
3493 }
3494
3495 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3496 of the preceding instruction. Always TRUE in the standard MIPS mode.
3497
3498 We don't accept macros in 16-bit delay slots to avoid a case where
3499 a macro expansion fails because it relies on a preceding 32-bit real
3500 instruction to have matched and does not handle the operands correctly.
3501 The only macros that may expand to 16-bit instructions are JAL that
3502 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3503 and BGT (that likewise cannot be placed in a delay slot) that decay to
3504 a NOP. In all these cases the macros precede any corresponding real
3505 instruction definitions in the opcode table, so they will match in the
3506 second pass where the size of the delay slot is ignored and therefore
3507 produce correct code. */
3508
3509 static bool
is_delay_slot_valid(const struct mips_opcode * mo)3510 is_delay_slot_valid (const struct mips_opcode *mo)
3511 {
3512 if (!mips_opts.micromips)
3513 return true;
3514
3515 if (mo->pinfo == INSN_MACRO)
3516 return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0;
3517 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
3518 && micromips_insn_length (mo) != 4)
3519 return false;
3520 if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
3521 && micromips_insn_length (mo) != 2)
3522 return false;
3523
3524 return true;
3525 }
3526
3527 /* For consistency checking, verify that all bits of OPCODE are specified
3528 either by the match/mask part of the instruction definition, or by the
3529 operand list. Also build up a list of operands in OPERANDS.
3530
3531 INSN_BITS says which bits of the instruction are significant.
3532 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3533 provides the mips_operand description of each operand. DECODE_OPERAND
3534 is null for MIPS16 instructions. */
3535
3536 static int
validate_mips_insn(const struct mips_opcode * opcode,unsigned long insn_bits,const struct mips_operand * (* decode_operand)(const char *),struct mips_operand_array * operands)3537 validate_mips_insn (const struct mips_opcode *opcode,
3538 unsigned long insn_bits,
3539 const struct mips_operand *(*decode_operand) (const char *),
3540 struct mips_operand_array *operands)
3541 {
3542 const char *s;
3543 unsigned long used_bits, doubled, undefined, opno, mask;
3544 const struct mips_operand *operand;
3545
3546 mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask);
3547 if ((mask & opcode->match) != opcode->match)
3548 {
3549 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3550 opcode->name, opcode->args);
3551 return 0;
3552 }
3553 used_bits = 0;
3554 opno = 0;
3555 if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
3556 used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
3557 for (s = opcode->args; *s; ++s)
3558 switch (*s)
3559 {
3560 case ',':
3561 case '(':
3562 case ')':
3563 break;
3564
3565 case '#':
3566 s++;
3567 break;
3568
3569 default:
3570 if (!decode_operand)
3571 operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode));
3572 else
3573 operand = decode_operand (s);
3574 if (!operand && opcode->pinfo != INSN_MACRO)
3575 {
3576 as_bad (_("internal: unknown operand type: %s %s"),
3577 opcode->name, opcode->args);
3578 return 0;
3579 }
3580 gas_assert (opno < MAX_OPERANDS);
3581 operands->operand[opno] = operand;
3582 if (!decode_operand && operand
3583 && operand->type == OP_INT && operand->lsb == 0
3584 && mips_opcode_32bit_p (opcode))
3585 used_bits |= mips16_immed_extend (-1, operand->size);
3586 else if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
3587 {
3588 used_bits = mips_insert_operand (operand, used_bits, -1);
3589 if (operand->type == OP_MDMX_IMM_REG)
3590 /* Bit 5 is the format selector (OB vs QH). The opcode table
3591 has separate entries for each format. */
3592 used_bits &= ~(1 << (operand->lsb + 5));
3593 if (operand->type == OP_ENTRY_EXIT_LIST)
3594 used_bits &= ~(mask & 0x700);
3595 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3596 operand field that cannot be fully described with LSB/SIZE. */
3597 if (operand->type == OP_SAVE_RESTORE_LIST && operand->lsb == 6)
3598 used_bits &= ~0x6000;
3599 }
3600 /* Skip prefix characters. */
3601 if (decode_operand && (*s == '+' || *s == 'm' || *s == '-'))
3602 ++s;
3603 opno += 1;
3604 break;
3605 }
3606 doubled = used_bits & mask & insn_bits;
3607 if (doubled)
3608 {
3609 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3610 " %s %s"), doubled, opcode->name, opcode->args);
3611 return 0;
3612 }
3613 used_bits |= mask;
3614 undefined = ~used_bits & insn_bits;
3615 if (opcode->pinfo != INSN_MACRO && undefined)
3616 {
3617 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3618 undefined, opcode->name, opcode->args);
3619 return 0;
3620 }
3621 used_bits &= ~insn_bits;
3622 if (used_bits)
3623 {
3624 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3625 used_bits, opcode->name, opcode->args);
3626 return 0;
3627 }
3628 return 1;
3629 }
3630
3631 /* The MIPS16 version of validate_mips_insn. */
3632
3633 static int
validate_mips16_insn(const struct mips_opcode * opcode,struct mips_operand_array * operands)3634 validate_mips16_insn (const struct mips_opcode *opcode,
3635 struct mips_operand_array *operands)
3636 {
3637 unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff;
3638
3639 return validate_mips_insn (opcode, insn_bits, 0, operands);
3640 }
3641
3642 /* The microMIPS version of validate_mips_insn. */
3643
3644 static int
validate_micromips_insn(const struct mips_opcode * opc,struct mips_operand_array * operands)3645 validate_micromips_insn (const struct mips_opcode *opc,
3646 struct mips_operand_array *operands)
3647 {
3648 unsigned long insn_bits;
3649 unsigned long major;
3650 unsigned int length;
3651
3652 if (opc->pinfo == INSN_MACRO)
3653 return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
3654 operands);
3655
3656 length = micromips_insn_length (opc);
3657 if (length != 2 && length != 4)
3658 {
3659 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3660 "%s %s"), length, opc->name, opc->args);
3661 return 0;
3662 }
3663 major = opc->match >> (10 + 8 * (length - 2));
3664 if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
3665 || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
3666 {
3667 as_bad (_("internal error: bad microMIPS opcode "
3668 "(opcode/length mismatch): %s %s"), opc->name, opc->args);
3669 return 0;
3670 }
3671
3672 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3673 insn_bits = 1 << 4 * length;
3674 insn_bits <<= 4 * length;
3675 insn_bits -= 1;
3676 return validate_mips_insn (opc, insn_bits, decode_micromips_operand,
3677 operands);
3678 }
3679
3680 /* This function is called once, at assembler startup time. It should set up
3681 all the tables, etc. that the MD part of the assembler will need. */
3682
3683 void
md_begin(void)3684 md_begin (void)
3685 {
3686 int i = 0;
3687 int broken = 0;
3688
3689 if (mips_pic != NO_PIC)
3690 {
3691 if (g_switch_seen && g_switch_value != 0)
3692 as_bad (_("-G may not be used in position-independent code"));
3693 g_switch_value = 0;
3694 }
3695 else if (mips_abicalls)
3696 {
3697 if (g_switch_seen && g_switch_value != 0)
3698 as_bad (_("-G may not be used with abicalls"));
3699 g_switch_value = 0;
3700 }
3701
3702 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
3703 as_warn (_("could not set architecture and machine"));
3704
3705 op_hash = str_htab_create ();
3706
3707 mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES);
3708 for (i = 0; i < NUMOPCODES;)
3709 {
3710 const char *name = mips_opcodes[i].name;
3711
3712 if (str_hash_insert (op_hash, name, &mips_opcodes[i], 0) != NULL)
3713 as_fatal (_("duplicate %s"), name);
3714 do
3715 {
3716 if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff,
3717 decode_mips_operand, &mips_operands[i]))
3718 broken = 1;
3719
3720 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3721 {
3722 create_insn (&nop_insn, mips_opcodes + i);
3723 if (mips_fix_loongson2f_nop)
3724 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
3725 nop_insn.fixed_p = 1;
3726 }
3727
3728 if (sync_insn.insn_mo == NULL && strcmp (name, "sync") == 0)
3729 create_insn (&sync_insn, mips_opcodes + i);
3730
3731 ++i;
3732 }
3733 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
3734 }
3735
3736 mips16_op_hash = str_htab_create ();
3737 mips16_operands = XCNEWVEC (struct mips_operand_array,
3738 bfd_mips16_num_opcodes);
3739
3740 i = 0;
3741 while (i < bfd_mips16_num_opcodes)
3742 {
3743 const char *name = mips16_opcodes[i].name;
3744
3745 if (str_hash_insert (mips16_op_hash, name, &mips16_opcodes[i], 0))
3746 as_fatal (_("duplicate %s"), name);
3747 do
3748 {
3749 if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i]))
3750 broken = 1;
3751 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
3752 {
3753 create_insn (&mips16_nop_insn, mips16_opcodes + i);
3754 mips16_nop_insn.fixed_p = 1;
3755 }
3756 ++i;
3757 }
3758 while (i < bfd_mips16_num_opcodes
3759 && strcmp (mips16_opcodes[i].name, name) == 0);
3760 }
3761
3762 micromips_op_hash = str_htab_create ();
3763 micromips_operands = XCNEWVEC (struct mips_operand_array,
3764 bfd_micromips_num_opcodes);
3765
3766 i = 0;
3767 while (i < bfd_micromips_num_opcodes)
3768 {
3769 const char *name = micromips_opcodes[i].name;
3770
3771 if (str_hash_insert (micromips_op_hash, name, µmips_opcodes[i], 0))
3772 as_fatal (_("duplicate %s"), name);
3773 do
3774 {
3775 struct mips_cl_insn *micromips_nop_insn;
3776
3777 if (!validate_micromips_insn (µmips_opcodes[i],
3778 µmips_operands[i]))
3779 broken = 1;
3780
3781 if (micromips_opcodes[i].pinfo != INSN_MACRO)
3782 {
3783 if (micromips_insn_length (micromips_opcodes + i) == 2)
3784 micromips_nop_insn = µmips_nop16_insn;
3785 else if (micromips_insn_length (micromips_opcodes + i) == 4)
3786 micromips_nop_insn = µmips_nop32_insn;
3787 else
3788 continue;
3789
3790 if (micromips_nop_insn->insn_mo == NULL
3791 && strcmp (name, "nop") == 0)
3792 {
3793 create_insn (micromips_nop_insn, micromips_opcodes + i);
3794 micromips_nop_insn->fixed_p = 1;
3795 }
3796 }
3797 }
3798 while (++i < bfd_micromips_num_opcodes
3799 && strcmp (micromips_opcodes[i].name, name) == 0);
3800 }
3801
3802 if (broken)
3803 as_fatal (_("broken assembler, no assembly attempted"));
3804
3805 /* We add all the general register names to the symbol table. This
3806 helps us detect invalid uses of them. */
3807 for (i = 0; reg_names[i].name; i++)
3808 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
3809 &zero_address_frag,
3810 reg_names[i].num));
3811 if (HAVE_NEWABI)
3812 for (i = 0; reg_names_n32n64[i].name; i++)
3813 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
3814 &zero_address_frag,
3815 reg_names_n32n64[i].num));
3816 else
3817 for (i = 0; reg_names_o32[i].name; i++)
3818 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
3819 &zero_address_frag,
3820 reg_names_o32[i].num));
3821
3822 for (i = 0; i < 32; i++)
3823 {
3824 char regname[16];
3825
3826 /* R5900 VU0 floating-point register. */
3827 sprintf (regname, "$vf%d", i);
3828 symbol_table_insert (symbol_new (regname, reg_section,
3829 &zero_address_frag, RTYPE_VF | i));
3830
3831 /* R5900 VU0 integer register. */
3832 sprintf (regname, "$vi%d", i);
3833 symbol_table_insert (symbol_new (regname, reg_section,
3834 &zero_address_frag, RTYPE_VI | i));
3835
3836 /* MSA register. */
3837 sprintf (regname, "$w%d", i);
3838 symbol_table_insert (symbol_new (regname, reg_section,
3839 &zero_address_frag, RTYPE_MSA | i));
3840 }
3841
3842 obstack_init (&mips_operand_tokens);
3843
3844 mips_no_prev_insn ();
3845
3846 mips_gprmask = 0;
3847 mips_cprmask[0] = 0;
3848 mips_cprmask[1] = 0;
3849 mips_cprmask[2] = 0;
3850 mips_cprmask[3] = 0;
3851
3852 /* set the default alignment for the text section (2**2) */
3853 record_alignment (text_section, 2);
3854
3855 bfd_set_gp_size (stdoutput, g_switch_value);
3856
3857 /* On a native system other than VxWorks, sections must be aligned
3858 to 16 byte boundaries. When configured for an embedded ELF
3859 target, we don't bother. */
3860 if (!startswith (TARGET_OS, "elf")
3861 && !startswith (TARGET_OS, "vxworks"))
3862 {
3863 bfd_set_section_alignment (text_section, 4);
3864 bfd_set_section_alignment (data_section, 4);
3865 bfd_set_section_alignment (bss_section, 4);
3866 }
3867
3868 /* Create a .reginfo section for register masks and a .mdebug
3869 section for debugging information. */
3870 {
3871 segT seg;
3872 subsegT subseg;
3873 flagword flags;
3874 segT sec;
3875
3876 seg = now_seg;
3877 subseg = now_subseg;
3878
3879 /* The ABI says this section should be loaded so that the
3880 running program can access it. However, we don't load it
3881 if we are configured for an embedded target. */
3882 flags = SEC_READONLY | SEC_DATA;
3883 if (!startswith (TARGET_OS, "elf"))
3884 flags |= SEC_ALLOC | SEC_LOAD;
3885
3886 if (mips_abi != N64_ABI)
3887 {
3888 sec = subseg_new (".reginfo", (subsegT) 0);
3889
3890 bfd_set_section_flags (sec, flags);
3891 bfd_set_section_alignment (sec, HAVE_NEWABI ? 3 : 2);
3892
3893 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
3894 }
3895 else
3896 {
3897 /* The 64-bit ABI uses a .MIPS.options section rather than
3898 .reginfo section. */
3899 sec = subseg_new (".MIPS.options", (subsegT) 0);
3900 bfd_set_section_flags (sec, flags);
3901 bfd_set_section_alignment (sec, 3);
3902
3903 /* Set up the option header. */
3904 {
3905 Elf_Internal_Options opthdr;
3906 char *f;
3907
3908 opthdr.kind = ODK_REGINFO;
3909 opthdr.size = (sizeof (Elf_External_Options)
3910 + sizeof (Elf64_External_RegInfo));
3911 opthdr.section = 0;
3912 opthdr.info = 0;
3913 f = frag_more (sizeof (Elf_External_Options));
3914 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
3915 (Elf_External_Options *) f);
3916
3917 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
3918 }
3919 }
3920
3921 sec = subseg_new (".MIPS.abiflags", (subsegT) 0);
3922 bfd_set_section_flags (sec,
3923 SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD);
3924 bfd_set_section_alignment (sec, 3);
3925 mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0));
3926
3927 if (ECOFF_DEBUGGING)
3928 {
3929 sec = subseg_new (".mdebug", (subsegT) 0);
3930 bfd_set_section_flags (sec, SEC_HAS_CONTENTS | SEC_READONLY);
3931 bfd_set_section_alignment (sec, 2);
3932 }
3933 else if (mips_flag_pdr)
3934 {
3935 pdr_seg = subseg_new (".pdr", (subsegT) 0);
3936 bfd_set_section_flags (pdr_seg,
3937 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
3938 bfd_set_section_alignment (pdr_seg, 2);
3939 }
3940
3941 subseg_set (seg, subseg);
3942 }
3943
3944 if (mips_fix_vr4120)
3945 init_vr4120_conflicts ();
3946 }
3947
3948 static inline void
fpabi_incompatible_with(int fpabi,const char * what)3949 fpabi_incompatible_with (int fpabi, const char *what)
3950 {
3951 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3952 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3953 }
3954
3955 static inline void
fpabi_requires(int fpabi,const char * what)3956 fpabi_requires (int fpabi, const char *what)
3957 {
3958 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3959 Tag_GNU_MIPS_ABI_FP, fpabi, what);
3960 }
3961
3962 /* Check -mabi and register sizes against the specified FP ABI. */
3963 static void
check_fpabi(int fpabi)3964 check_fpabi (int fpabi)
3965 {
3966 switch (fpabi)
3967 {
3968 case Val_GNU_MIPS_ABI_FP_DOUBLE:
3969 if (file_mips_opts.soft_float)
3970 fpabi_incompatible_with (fpabi, "softfloat");
3971 else if (file_mips_opts.single_float)
3972 fpabi_incompatible_with (fpabi, "singlefloat");
3973 if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32)
3974 fpabi_incompatible_with (fpabi, "gp=64 fp=32");
3975 else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64)
3976 fpabi_incompatible_with (fpabi, "gp=32 fp=64");
3977 break;
3978
3979 case Val_GNU_MIPS_ABI_FP_XX:
3980 if (mips_abi != O32_ABI)
3981 fpabi_requires (fpabi, "-mabi=32");
3982 else if (file_mips_opts.soft_float)
3983 fpabi_incompatible_with (fpabi, "softfloat");
3984 else if (file_mips_opts.single_float)
3985 fpabi_incompatible_with (fpabi, "singlefloat");
3986 else if (file_mips_opts.fp != 0)
3987 fpabi_requires (fpabi, "fp=xx");
3988 break;
3989
3990 case Val_GNU_MIPS_ABI_FP_64A:
3991 case Val_GNU_MIPS_ABI_FP_64:
3992 if (mips_abi != O32_ABI)
3993 fpabi_requires (fpabi, "-mabi=32");
3994 else if (file_mips_opts.soft_float)
3995 fpabi_incompatible_with (fpabi, "softfloat");
3996 else if (file_mips_opts.single_float)
3997 fpabi_incompatible_with (fpabi, "singlefloat");
3998 else if (file_mips_opts.fp != 64)
3999 fpabi_requires (fpabi, "fp=64");
4000 else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg)
4001 fpabi_incompatible_with (fpabi, "nooddspreg");
4002 else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg)
4003 fpabi_requires (fpabi, "nooddspreg");
4004 break;
4005
4006 case Val_GNU_MIPS_ABI_FP_SINGLE:
4007 if (file_mips_opts.soft_float)
4008 fpabi_incompatible_with (fpabi, "softfloat");
4009 else if (!file_mips_opts.single_float)
4010 fpabi_requires (fpabi, "singlefloat");
4011 break;
4012
4013 case Val_GNU_MIPS_ABI_FP_SOFT:
4014 if (!file_mips_opts.soft_float)
4015 fpabi_requires (fpabi, "softfloat");
4016 break;
4017
4018 case Val_GNU_MIPS_ABI_FP_OLD_64:
4019 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4020 Tag_GNU_MIPS_ABI_FP, fpabi);
4021 break;
4022
4023 case Val_GNU_MIPS_ABI_FP_NAN2008:
4024 /* Silently ignore compatibility value. */
4025 break;
4026
4027 default:
4028 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4029 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi);
4030 break;
4031 }
4032 }
4033
4034 /* Perform consistency checks on the current options. */
4035
4036 static void
mips_check_options(struct mips_set_options * opts,bool abi_checks)4037 mips_check_options (struct mips_set_options *opts, bool abi_checks)
4038 {
4039 /* Check the size of integer registers agrees with the ABI and ISA. */
4040 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
4041 as_bad (_("`gp=64' used with a 32-bit processor"));
4042 else if (abi_checks
4043 && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi))
4044 as_bad (_("`gp=32' used with a 64-bit ABI"));
4045 else if (abi_checks
4046 && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi))
4047 as_bad (_("`gp=64' used with a 32-bit ABI"));
4048
4049 /* Check the size of the float registers agrees with the ABI and ISA. */
4050 switch (opts->fp)
4051 {
4052 case 0:
4053 if (!CPU_HAS_LDC1_SDC1 (opts->arch))
4054 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4055 else if (opts->single_float == 1)
4056 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4057 break;
4058 case 64:
4059 if (!ISA_HAS_64BIT_FPRS (opts->isa))
4060 as_bad (_("`fp=64' used with a 32-bit fpu"));
4061 else if (abi_checks
4062 && ABI_NEEDS_32BIT_REGS (mips_abi)
4063 && !ISA_HAS_MXHC1 (opts->isa))
4064 as_warn (_("`fp=64' used with a 32-bit ABI"));
4065 break;
4066 case 32:
4067 if (abi_checks
4068 && ABI_NEEDS_64BIT_REGS (mips_abi))
4069 as_warn (_("`fp=32' used with a 64-bit ABI"));
4070 if (ISA_IS_R6 (opts->isa) && opts->single_float == 0)
4071 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4072 break;
4073 default:
4074 as_bad (_("Unknown size of floating point registers"));
4075 break;
4076 }
4077
4078 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg)
4079 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4080
4081 if (opts->micromips == 1 && opts->mips16 == 1)
4082 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4083 else if (ISA_IS_R6 (opts->isa)
4084 && (opts->micromips == 1
4085 || opts->mips16 == 1))
4086 as_fatal (_("`%s' cannot be used with `%s'"),
4087 opts->micromips ? "micromips" : "mips16",
4088 mips_cpu_info_from_isa (opts->isa)->name);
4089
4090 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
4091 as_fatal (_("branch relaxation is not supported in `%s'"),
4092 mips_cpu_info_from_isa (opts->isa)->name);
4093 }
4094
4095 /* Perform consistency checks on the module level options exactly once.
4096 This is a deferred check that happens:
4097 at the first .set directive
4098 or, at the first pseudo op that generates code (inc .dc.a)
4099 or, at the first instruction
4100 or, at the end. */
4101
4102 static void
file_mips_check_options(void)4103 file_mips_check_options (void)
4104 {
4105 if (file_mips_opts_checked)
4106 return;
4107
4108 /* The following code determines the register size.
4109 Similar code was added to GCC 3.3 (see override_options() in
4110 config/mips/mips.c). The GAS and GCC code should be kept in sync
4111 as much as possible. */
4112
4113 if (file_mips_opts.gp < 0)
4114 {
4115 /* Infer the integer register size from the ABI and processor.
4116 Restrict ourselves to 32-bit registers if that's all the
4117 processor has, or if the ABI cannot handle 64-bit registers. */
4118 file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi)
4119 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
4120 ? 32 : 64;
4121 }
4122
4123 if (file_mips_opts.fp < 0)
4124 {
4125 /* No user specified float register size.
4126 ??? GAS treats single-float processors as though they had 64-bit
4127 float registers (although it complains when double-precision
4128 instructions are used). As things stand, saying they have 32-bit
4129 registers would lead to spurious "register must be even" messages.
4130 So here we assume float registers are never smaller than the
4131 integer ones. */
4132 if (file_mips_opts.gp == 64)
4133 /* 64-bit integer registers implies 64-bit float registers. */
4134 file_mips_opts.fp = 64;
4135 else if ((file_mips_opts.ase & FP64_ASES)
4136 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
4137 /* Handle ASEs that require 64-bit float registers, if possible. */
4138 file_mips_opts.fp = 64;
4139 else if (ISA_IS_R6 (mips_opts.isa))
4140 /* R6 implies 64-bit float registers. */
4141 file_mips_opts.fp = 64;
4142 else
4143 /* 32-bit float registers. */
4144 file_mips_opts.fp = 32;
4145 }
4146
4147 /* Disable operations on odd-numbered floating-point registers by default
4148 when using the FPXX ABI. */
4149 if (file_mips_opts.oddspreg < 0)
4150 {
4151 if (file_mips_opts.fp == 0)
4152 file_mips_opts.oddspreg = 0;
4153 else
4154 file_mips_opts.oddspreg = 1;
4155 }
4156
4157 /* End of GCC-shared inference code. */
4158
4159 /* This flag is set when we have a 64-bit capable CPU but use only
4160 32-bit wide registers. Note that EABI does not use it. */
4161 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
4162 && ((mips_abi == NO_ABI && file_mips_opts.gp == 32)
4163 || mips_abi == O32_ABI))
4164 mips_32bitmode = 1;
4165
4166 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
4167 as_bad (_("trap exception not supported at ISA 1"));
4168
4169 /* If the selected architecture includes support for ASEs, enable
4170 generation of code for them. */
4171 if (file_mips_opts.mips16 == -1)
4172 file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0;
4173 if (file_mips_opts.micromips == -1)
4174 file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch))
4175 ? 1 : 0;
4176
4177 if (mips_nan2008 == -1)
4178 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
4179 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
4180 as_fatal (_("`%s' does not support legacy NaN"),
4181 mips_cpu_info_from_arch (file_mips_opts.arch)->name);
4182
4183 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4184 being selected implicitly. */
4185 if (file_mips_opts.fp != 64)
4186 file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA;
4187
4188 /* If the user didn't explicitly select or deselect a particular ASE,
4189 use the default setting for the CPU. */
4190 file_mips_opts.ase |= (file_mips_opts.init_ase & ~file_ase_explicit);
4191
4192 /* Set up the current options. These may change throughout assembly. */
4193 mips_opts = file_mips_opts;
4194
4195 mips_check_isa_supports_ases ();
4196 mips_check_options (&file_mips_opts, true);
4197 file_mips_opts_checked = true;
4198
4199 if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch))
4200 as_warn (_("could not set architecture and machine"));
4201 }
4202
4203 void
md_assemble(char * str)4204 md_assemble (char *str)
4205 {
4206 struct mips_cl_insn insn;
4207 bfd_reloc_code_real_type unused_reloc[3]
4208 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4209
4210 file_mips_check_options ();
4211
4212 imm_expr.X_op = O_absent;
4213 offset_expr.X_op = O_absent;
4214 offset_reloc[0] = BFD_RELOC_UNUSED;
4215 offset_reloc[1] = BFD_RELOC_UNUSED;
4216 offset_reloc[2] = BFD_RELOC_UNUSED;
4217
4218 mips_mark_labels ();
4219 mips_assembling_insn = true;
4220 clear_insn_error ();
4221
4222 if (mips_opts.mips16)
4223 mips16_ip (str, &insn);
4224 else
4225 {
4226 mips_ip (str, &insn);
4227 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4228 str, insn.insn_opcode));
4229 }
4230
4231 if (insn_error.msg)
4232 report_insn_error (str);
4233 else if (insn.insn_mo->pinfo == INSN_MACRO)
4234 {
4235 macro_start ();
4236 if (mips_opts.mips16)
4237 mips16_macro (&insn);
4238 else
4239 macro (&insn, str);
4240 macro_end ();
4241 }
4242 else
4243 {
4244 if (offset_expr.X_op != O_absent)
4245 append_insn (&insn, &offset_expr, offset_reloc, false);
4246 else
4247 append_insn (&insn, NULL, unused_reloc, false);
4248 }
4249
4250 mips_assembling_insn = false;
4251 }
4252
4253 /* Convenience functions for abstracting away the differences between
4254 MIPS16 and non-MIPS16 relocations. */
4255
4256 static inline bool
mips16_reloc_p(bfd_reloc_code_real_type reloc)4257 mips16_reloc_p (bfd_reloc_code_real_type reloc)
4258 {
4259 switch (reloc)
4260 {
4261 case BFD_RELOC_MIPS16_JMP:
4262 case BFD_RELOC_MIPS16_GPREL:
4263 case BFD_RELOC_MIPS16_GOT16:
4264 case BFD_RELOC_MIPS16_CALL16:
4265 case BFD_RELOC_MIPS16_HI16_S:
4266 case BFD_RELOC_MIPS16_HI16:
4267 case BFD_RELOC_MIPS16_LO16:
4268 case BFD_RELOC_MIPS16_16_PCREL_S1:
4269 return true;
4270
4271 default:
4272 return false;
4273 }
4274 }
4275
4276 static inline bool
micromips_reloc_p(bfd_reloc_code_real_type reloc)4277 micromips_reloc_p (bfd_reloc_code_real_type reloc)
4278 {
4279 switch (reloc)
4280 {
4281 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4282 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4283 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4284 case BFD_RELOC_MICROMIPS_GPREL16:
4285 case BFD_RELOC_MICROMIPS_JMP:
4286 case BFD_RELOC_MICROMIPS_HI16:
4287 case BFD_RELOC_MICROMIPS_HI16_S:
4288 case BFD_RELOC_MICROMIPS_LO16:
4289 case BFD_RELOC_MICROMIPS_LITERAL:
4290 case BFD_RELOC_MICROMIPS_GOT16:
4291 case BFD_RELOC_MICROMIPS_CALL16:
4292 case BFD_RELOC_MICROMIPS_GOT_HI16:
4293 case BFD_RELOC_MICROMIPS_GOT_LO16:
4294 case BFD_RELOC_MICROMIPS_CALL_HI16:
4295 case BFD_RELOC_MICROMIPS_CALL_LO16:
4296 case BFD_RELOC_MICROMIPS_SUB:
4297 case BFD_RELOC_MICROMIPS_GOT_PAGE:
4298 case BFD_RELOC_MICROMIPS_GOT_OFST:
4299 case BFD_RELOC_MICROMIPS_GOT_DISP:
4300 case BFD_RELOC_MICROMIPS_HIGHEST:
4301 case BFD_RELOC_MICROMIPS_HIGHER:
4302 case BFD_RELOC_MICROMIPS_SCN_DISP:
4303 case BFD_RELOC_MICROMIPS_JALR:
4304 return true;
4305
4306 default:
4307 return false;
4308 }
4309 }
4310
4311 static inline bool
jmp_reloc_p(bfd_reloc_code_real_type reloc)4312 jmp_reloc_p (bfd_reloc_code_real_type reloc)
4313 {
4314 return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP;
4315 }
4316
4317 static inline bool
b_reloc_p(bfd_reloc_code_real_type reloc)4318 b_reloc_p (bfd_reloc_code_real_type reloc)
4319 {
4320 return (reloc == BFD_RELOC_MIPS_26_PCREL_S2
4321 || reloc == BFD_RELOC_MIPS_21_PCREL_S2
4322 || reloc == BFD_RELOC_16_PCREL_S2
4323 || reloc == BFD_RELOC_MIPS16_16_PCREL_S1
4324 || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
4325 || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
4326 || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
4327 }
4328
4329 static inline bool
got16_reloc_p(bfd_reloc_code_real_type reloc)4330 got16_reloc_p (bfd_reloc_code_real_type reloc)
4331 {
4332 return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16
4333 || reloc == BFD_RELOC_MICROMIPS_GOT16);
4334 }
4335
4336 static inline bool
hi16_reloc_p(bfd_reloc_code_real_type reloc)4337 hi16_reloc_p (bfd_reloc_code_real_type reloc)
4338 {
4339 return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S
4340 || reloc == BFD_RELOC_MICROMIPS_HI16_S);
4341 }
4342
4343 static inline bool
lo16_reloc_p(bfd_reloc_code_real_type reloc)4344 lo16_reloc_p (bfd_reloc_code_real_type reloc)
4345 {
4346 return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16
4347 || reloc == BFD_RELOC_MICROMIPS_LO16);
4348 }
4349
4350 static inline bool
jalr_reloc_p(bfd_reloc_code_real_type reloc)4351 jalr_reloc_p (bfd_reloc_code_real_type reloc)
4352 {
4353 return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR;
4354 }
4355
4356 static inline bool
gprel16_reloc_p(bfd_reloc_code_real_type reloc)4357 gprel16_reloc_p (bfd_reloc_code_real_type reloc)
4358 {
4359 return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL
4360 || reloc == BFD_RELOC_MICROMIPS_GPREL16);
4361 }
4362
4363 /* Return true if RELOC is a PC-relative relocation that does not have
4364 full address range. */
4365
4366 static inline bool
limited_pcrel_reloc_p(bfd_reloc_code_real_type reloc)4367 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
4368 {
4369 switch (reloc)
4370 {
4371 case BFD_RELOC_16_PCREL_S2:
4372 case BFD_RELOC_MIPS16_16_PCREL_S1:
4373 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
4374 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
4375 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
4376 case BFD_RELOC_MIPS_21_PCREL_S2:
4377 case BFD_RELOC_MIPS_26_PCREL_S2:
4378 case BFD_RELOC_MIPS_18_PCREL_S3:
4379 case BFD_RELOC_MIPS_19_PCREL_S2:
4380 return true;
4381
4382 case BFD_RELOC_32_PCREL:
4383 case BFD_RELOC_HI16_S_PCREL:
4384 case BFD_RELOC_LO16_PCREL:
4385 return HAVE_64BIT_ADDRESSES;
4386
4387 default:
4388 return false;
4389 }
4390 }
4391
4392 /* Return true if the given relocation might need a matching %lo().
4393 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4394 need a matching %lo() when applied to local symbols. */
4395
4396 static inline bool
reloc_needs_lo_p(bfd_reloc_code_real_type reloc)4397 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
4398 {
4399 return (HAVE_IN_PLACE_ADDENDS
4400 && (hi16_reloc_p (reloc)
4401 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4402 all GOT16 relocations evaluate to "G". */
4403 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
4404 }
4405
4406 /* Return the type of %lo() reloc needed by RELOC, given that
4407 reloc_needs_lo_p. */
4408
4409 static inline bfd_reloc_code_real_type
matching_lo_reloc(bfd_reloc_code_real_type reloc)4410 matching_lo_reloc (bfd_reloc_code_real_type reloc)
4411 {
4412 return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16
4413 : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16
4414 : BFD_RELOC_LO16));
4415 }
4416
4417 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4418 relocation. */
4419
4420 static inline bool
fixup_has_matching_lo_p(fixS * fixp)4421 fixup_has_matching_lo_p (fixS *fixp)
4422 {
4423 return (fixp->fx_next != NULL
4424 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
4425 && fixp->fx_addsy == fixp->fx_next->fx_addsy
4426 && fixp->fx_offset == fixp->fx_next->fx_offset);
4427 }
4428
4429 /* Move all labels in LABELS to the current insertion point. TEXT_P
4430 says whether the labels refer to text or data. */
4431
4432 static void
mips_move_labels(struct insn_label_list * labels,bool text_p)4433 mips_move_labels (struct insn_label_list *labels, bool text_p)
4434 {
4435 struct insn_label_list *l;
4436 valueT val;
4437
4438 for (l = labels; l != NULL; l = l->next)
4439 {
4440 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
4441 symbol_set_frag (l->label, frag_now);
4442 val = (valueT) frag_now_fix ();
4443 /* MIPS16/microMIPS text labels are stored as odd.
4444 We just carry the ISA mode bit forward. */
4445 if (text_p && HAVE_CODE_COMPRESSION)
4446 val |= (S_GET_VALUE (l->label) & 0x1);
4447 S_SET_VALUE (l->label, val);
4448 }
4449 }
4450
4451 /* Move all labels in insn_labels to the current insertion point
4452 and treat them as text labels. */
4453
4454 static void
mips_move_text_labels(void)4455 mips_move_text_labels (void)
4456 {
4457 mips_move_labels (seg_info (now_seg)->label_list, true);
4458 }
4459
4460 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4461
4462 static bool
s_is_linkonce(symbolS * sym,segT from_seg)4463 s_is_linkonce (symbolS *sym, segT from_seg)
4464 {
4465 bool linkonce = false;
4466 segT symseg = S_GET_SEGMENT (sym);
4467
4468 if (symseg != from_seg && !S_IS_LOCAL (sym))
4469 {
4470 if ((bfd_section_flags (symseg) & SEC_LINK_ONCE))
4471 linkonce = true;
4472 /* The GNU toolchain uses an extension for ELF: a section
4473 beginning with the magic string .gnu.linkonce is a
4474 linkonce section. */
4475 if (startswith (segment_name (symseg), ".gnu.linkonce"))
4476 linkonce = true;
4477 }
4478 return linkonce;
4479 }
4480
4481 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4482 linker to handle them specially, such as generating jalx instructions
4483 when needed. We also make them odd for the duration of the assembly,
4484 in order to generate the right sort of code. We will make them even
4485 in the adjust_symtab routine, while leaving them marked. This is
4486 convenient for the debugger and the disassembler. The linker knows
4487 to make them odd again. */
4488
4489 static void
mips_compressed_mark_label(symbolS * label)4490 mips_compressed_mark_label (symbolS *label)
4491 {
4492 gas_assert (HAVE_CODE_COMPRESSION);
4493
4494 if (mips_opts.mips16)
4495 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
4496 else
4497 S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label)));
4498 if ((S_GET_VALUE (label) & 1) == 0
4499 /* Don't adjust the address if the label is global or weak, or
4500 in a link-once section, since we'll be emitting symbol reloc
4501 references to it which will be patched up by the linker, and
4502 the final value of the symbol may or may not be MIPS16/microMIPS. */
4503 && !S_IS_WEAK (label)
4504 && !S_IS_EXTERNAL (label)
4505 && !s_is_linkonce (label, now_seg))
4506 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
4507 }
4508
4509 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4510
4511 static void
mips_compressed_mark_labels(void)4512 mips_compressed_mark_labels (void)
4513 {
4514 struct insn_label_list *l;
4515
4516 for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next)
4517 mips_compressed_mark_label (l->label);
4518 }
4519
4520 /* End the current frag. Make it a variant frag and record the
4521 relaxation info. */
4522
4523 static void
relax_close_frag(void)4524 relax_close_frag (void)
4525 {
4526 mips_macro_warning.first_frag = frag_now;
4527 frag_var (rs_machine_dependent, 0, 0,
4528 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1],
4529 mips_pic != NO_PIC),
4530 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
4531
4532 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
4533 mips_relax.first_fixup = 0;
4534 }
4535
4536 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4537 See the comment above RELAX_ENCODE for more details. */
4538
4539 static void
relax_start(symbolS * symbol)4540 relax_start (symbolS *symbol)
4541 {
4542 gas_assert (mips_relax.sequence == 0);
4543 mips_relax.sequence = 1;
4544 mips_relax.symbol = symbol;
4545 }
4546
4547 /* Start generating the second version of a relaxable sequence.
4548 See the comment above RELAX_ENCODE for more details. */
4549
4550 static void
relax_switch(void)4551 relax_switch (void)
4552 {
4553 gas_assert (mips_relax.sequence == 1);
4554 mips_relax.sequence = 2;
4555 }
4556
4557 /* End the current relaxable sequence. */
4558
4559 static void
relax_end(void)4560 relax_end (void)
4561 {
4562 gas_assert (mips_relax.sequence == 2);
4563 relax_close_frag ();
4564 mips_relax.sequence = 0;
4565 }
4566
4567 /* Return true if IP is a delayed branch or jump. */
4568
4569 static inline bool
delayed_branch_p(const struct mips_cl_insn * ip)4570 delayed_branch_p (const struct mips_cl_insn *ip)
4571 {
4572 return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
4573 | INSN_COND_BRANCH_DELAY
4574 | INSN_COND_BRANCH_LIKELY)) != 0;
4575 }
4576
4577 /* Return true if IP is a compact branch or jump. */
4578
4579 static inline bool
compact_branch_p(const struct mips_cl_insn * ip)4580 compact_branch_p (const struct mips_cl_insn *ip)
4581 {
4582 return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
4583 | INSN2_COND_BRANCH)) != 0;
4584 }
4585
4586 /* Return true if IP is an unconditional branch or jump. */
4587
4588 static inline bool
uncond_branch_p(const struct mips_cl_insn * ip)4589 uncond_branch_p (const struct mips_cl_insn *ip)
4590 {
4591 return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
4592 || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
4593 }
4594
4595 /* Return true if IP is a branch-likely instruction. */
4596
4597 static inline bool
branch_likely_p(const struct mips_cl_insn * ip)4598 branch_likely_p (const struct mips_cl_insn *ip)
4599 {
4600 return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0;
4601 }
4602
4603 /* Return the type of nop that should be used to fill the delay slot
4604 of delayed branch IP. */
4605
4606 static struct mips_cl_insn *
get_delay_slot_nop(const struct mips_cl_insn * ip)4607 get_delay_slot_nop (const struct mips_cl_insn *ip)
4608 {
4609 if (mips_opts.micromips
4610 && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
4611 return µmips_nop32_insn;
4612 return NOP_INSN;
4613 }
4614
4615 /* Return a mask that has bit N set if OPCODE reads the register(s)
4616 in operand N. */
4617
4618 static unsigned int
insn_read_mask(const struct mips_opcode * opcode)4619 insn_read_mask (const struct mips_opcode *opcode)
4620 {
4621 return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT;
4622 }
4623
4624 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4625 in operand N. */
4626
4627 static unsigned int
insn_write_mask(const struct mips_opcode * opcode)4628 insn_write_mask (const struct mips_opcode *opcode)
4629 {
4630 return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT;
4631 }
4632
4633 /* Return a mask of the registers specified by operand OPERAND of INSN.
4634 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4635 is set. */
4636
4637 static unsigned int
operand_reg_mask(const struct mips_cl_insn * insn,const struct mips_operand * operand,unsigned int type_mask)4638 operand_reg_mask (const struct mips_cl_insn *insn,
4639 const struct mips_operand *operand,
4640 unsigned int type_mask)
4641 {
4642 unsigned int uval, vsel;
4643
4644 switch (operand->type)
4645 {
4646 case OP_INT:
4647 case OP_MAPPED_INT:
4648 case OP_MSB:
4649 case OP_PCREL:
4650 case OP_PERF_REG:
4651 case OP_ADDIUSP_INT:
4652 case OP_ENTRY_EXIT_LIST:
4653 case OP_REPEAT_DEST_REG:
4654 case OP_REPEAT_PREV_REG:
4655 case OP_PC:
4656 case OP_VU0_SUFFIX:
4657 case OP_VU0_MATCH_SUFFIX:
4658 case OP_IMM_INDEX:
4659 abort ();
4660
4661 case OP_REG28:
4662 return 1 << 28;
4663
4664 case OP_REG:
4665 case OP_OPTIONAL_REG:
4666 {
4667 const struct mips_reg_operand *reg_op;
4668
4669 reg_op = (const struct mips_reg_operand *) operand;
4670 if (!(type_mask & (1 << reg_op->reg_type)))
4671 return 0;
4672 uval = insn_extract_operand (insn, operand);
4673 return 1u << mips_decode_reg_operand (reg_op, uval);
4674 }
4675
4676 case OP_REG_PAIR:
4677 {
4678 const struct mips_reg_pair_operand *pair_op;
4679
4680 pair_op = (const struct mips_reg_pair_operand *) operand;
4681 if (!(type_mask & (1 << pair_op->reg_type)))
4682 return 0;
4683 uval = insn_extract_operand (insn, operand);
4684 return (1u << pair_op->reg1_map[uval]) | (1u << pair_op->reg2_map[uval]);
4685 }
4686
4687 case OP_CLO_CLZ_DEST:
4688 if (!(type_mask & (1 << OP_REG_GP)))
4689 return 0;
4690 uval = insn_extract_operand (insn, operand);
4691 return (1u << (uval & 31)) | (1u << (uval >> 5));
4692
4693 case OP_SAME_RS_RT:
4694 if (!(type_mask & (1 << OP_REG_GP)))
4695 return 0;
4696 uval = insn_extract_operand (insn, operand);
4697 gas_assert ((uval & 31) == (uval >> 5));
4698 return 1u << (uval & 31);
4699
4700 case OP_CHECK_PREV:
4701 case OP_NON_ZERO_REG:
4702 if (!(type_mask & (1 << OP_REG_GP)))
4703 return 0;
4704 uval = insn_extract_operand (insn, operand);
4705 return 1u << (uval & 31);
4706
4707 case OP_LWM_SWM_LIST:
4708 abort ();
4709
4710 case OP_SAVE_RESTORE_LIST:
4711 abort ();
4712
4713 case OP_MDMX_IMM_REG:
4714 if (!(type_mask & (1 << OP_REG_VEC)))
4715 return 0;
4716 uval = insn_extract_operand (insn, operand);
4717 vsel = uval >> 5;
4718 if ((vsel & 0x18) == 0x18)
4719 return 0;
4720 return 1u << (uval & 31);
4721
4722 case OP_REG_INDEX:
4723 if (!(type_mask & (1 << OP_REG_GP)))
4724 return 0;
4725 return 1u << insn_extract_operand (insn, operand);
4726 }
4727 abort ();
4728 }
4729
4730 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4731 where bit N of OPNO_MASK is set if operand N should be included.
4732 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4733 is set. */
4734
4735 static unsigned int
insn_reg_mask(const struct mips_cl_insn * insn,unsigned int type_mask,unsigned int opno_mask)4736 insn_reg_mask (const struct mips_cl_insn *insn,
4737 unsigned int type_mask, unsigned int opno_mask)
4738 {
4739 unsigned int opno, reg_mask;
4740
4741 opno = 0;
4742 reg_mask = 0;
4743 while (opno_mask != 0)
4744 {
4745 if (opno_mask & 1)
4746 reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask);
4747 opno_mask >>= 1;
4748 opno += 1;
4749 }
4750 return reg_mask;
4751 }
4752
4753 /* Return the mask of core registers that IP reads. */
4754
4755 static unsigned int
gpr_read_mask(const struct mips_cl_insn * ip)4756 gpr_read_mask (const struct mips_cl_insn *ip)
4757 {
4758 unsigned long pinfo, pinfo2;
4759 unsigned int mask;
4760
4761 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo));
4762 pinfo = ip->insn_mo->pinfo;
4763 pinfo2 = ip->insn_mo->pinfo2;
4764 if (pinfo & INSN_UDI)
4765 {
4766 /* UDI instructions have traditionally been assumed to read RS
4767 and RT. */
4768 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip);
4769 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
4770 }
4771 if (pinfo & INSN_READ_GPR_24)
4772 mask |= 1 << 24;
4773 if (pinfo2 & INSN2_READ_GPR_16)
4774 mask |= 1 << 16;
4775 if (pinfo2 & INSN2_READ_SP)
4776 mask |= 1 << SP;
4777 if (pinfo2 & INSN2_READ_GPR_31)
4778 mask |= 1u << 31;
4779 /* Don't include register 0. */
4780 return mask & ~1;
4781 }
4782
4783 /* Return the mask of core registers that IP writes. */
4784
4785 static unsigned int
gpr_write_mask(const struct mips_cl_insn * ip)4786 gpr_write_mask (const struct mips_cl_insn *ip)
4787 {
4788 unsigned long pinfo, pinfo2;
4789 unsigned int mask;
4790
4791 mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo));
4792 pinfo = ip->insn_mo->pinfo;
4793 pinfo2 = ip->insn_mo->pinfo2;
4794 if (pinfo & INSN_WRITE_GPR_24)
4795 mask |= 1 << 24;
4796 if (pinfo & INSN_WRITE_GPR_31)
4797 mask |= 1u << 31;
4798 if (pinfo & INSN_UDI)
4799 /* UDI instructions have traditionally been assumed to write to RD. */
4800 mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip);
4801 if (pinfo2 & INSN2_WRITE_SP)
4802 mask |= 1 << SP;
4803 /* Don't include register 0. */
4804 return mask & ~1;
4805 }
4806
4807 /* Return the mask of floating-point registers that IP reads. */
4808
4809 static unsigned int
fpr_read_mask(const struct mips_cl_insn * ip)4810 fpr_read_mask (const struct mips_cl_insn *ip)
4811 {
4812 unsigned long pinfo;
4813 unsigned int mask;
4814
4815 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4816 | (1 << OP_REG_MSA)),
4817 insn_read_mask (ip->insn_mo));
4818 pinfo = ip->insn_mo->pinfo;
4819 /* Conservatively treat all operands to an FP_D instruction are doubles.
4820 (This is overly pessimistic for things like cvt.d.s.) */
4821 if (FPR_SIZE != 64 && (pinfo & FP_D))
4822 mask |= mask << 1;
4823 return mask;
4824 }
4825
4826 /* Return the mask of floating-point registers that IP writes. */
4827
4828 static unsigned int
fpr_write_mask(const struct mips_cl_insn * ip)4829 fpr_write_mask (const struct mips_cl_insn *ip)
4830 {
4831 unsigned long pinfo;
4832 unsigned int mask;
4833
4834 mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
4835 | (1 << OP_REG_MSA)),
4836 insn_write_mask (ip->insn_mo));
4837 pinfo = ip->insn_mo->pinfo;
4838 /* Conservatively treat all operands to an FP_D instruction are doubles.
4839 (This is overly pessimistic for things like cvt.s.d.) */
4840 if (FPR_SIZE != 64 && (pinfo & FP_D))
4841 mask |= mask << 1;
4842 return mask;
4843 }
4844
4845 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4846 Check whether that is allowed. */
4847
4848 static bool
mips_oddfpreg_ok(const struct mips_opcode * insn,int opnum)4849 mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
4850 {
4851 const char *s = insn->name;
4852 bool oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
4853 || FPR_SIZE == 64) && mips_opts.oddspreg;
4854
4855 if (insn->pinfo == INSN_MACRO)
4856 /* Let a macro pass, we'll catch it later when it is expanded. */
4857 return true;
4858
4859 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4860 otherwise it depends on oddspreg. */
4861 if ((insn->pinfo & FP_S)
4862 && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
4863 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
4864 return FPR_SIZE == 32 || oddspreg;
4865
4866 /* Allow odd registers for single-precision ops and double-precision if the
4867 floating-point registers are 64-bit wide. */
4868 switch (insn->pinfo & (FP_S | FP_D))
4869 {
4870 case FP_S:
4871 case 0:
4872 return oddspreg;
4873 case FP_D:
4874 return FPR_SIZE == 64;
4875 default:
4876 break;
4877 }
4878
4879 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4880 s = strchr (insn->name, '.');
4881 if (s != NULL && opnum == 2)
4882 s = strchr (s + 1, '.');
4883 if (s != NULL && (s[1] == 'w' || s[1] == 's'))
4884 return oddspreg;
4885
4886 return FPR_SIZE == 64;
4887 }
4888
4889 /* Information about an instruction argument that we're trying to match. */
4890 struct mips_arg_info
4891 {
4892 /* The instruction so far. */
4893 struct mips_cl_insn *insn;
4894
4895 /* The first unconsumed operand token. */
4896 struct mips_operand_token *token;
4897
4898 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4899 int opnum;
4900
4901 /* The 1-based argument number, for error reporting. This does not
4902 count elided optional registers, etc.. */
4903 int argnum;
4904
4905 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4906 unsigned int last_regno;
4907
4908 /* If the first operand was an OP_REG, this is the register that it
4909 specified, otherwise it is ILLEGAL_REG. */
4910 unsigned int dest_regno;
4911
4912 /* The value of the last OP_INT operand. Only used for OP_MSB,
4913 where it gives the lsb position. */
4914 unsigned int last_op_int;
4915
4916 /* If true, match routines should assume that no later instruction
4917 alternative matches and should therefore be as accommodating as
4918 possible. Match routines should not report errors if something
4919 is only invalid for !LAX_MATCH. */
4920 bool lax_match;
4921
4922 /* True if a reference to the current AT register was seen. */
4923 bool seen_at;
4924 };
4925
4926 /* Record that the argument is out of range. */
4927
4928 static void
match_out_of_range(struct mips_arg_info * arg)4929 match_out_of_range (struct mips_arg_info *arg)
4930 {
4931 set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum);
4932 }
4933
4934 /* Record that the argument isn't constant but needs to be. */
4935
4936 static void
match_not_constant(struct mips_arg_info * arg)4937 match_not_constant (struct mips_arg_info *arg)
4938 {
4939 set_insn_error_i (arg->argnum, _("operand %d must be constant"),
4940 arg->argnum);
4941 }
4942
4943 /* Try to match an OT_CHAR token for character CH. Consume the token
4944 and return true on success, otherwise return false. */
4945
4946 static bool
match_char(struct mips_arg_info * arg,char ch)4947 match_char (struct mips_arg_info *arg, char ch)
4948 {
4949 if (arg->token->type == OT_CHAR && arg->token->u.ch == ch)
4950 {
4951 ++arg->token;
4952 if (ch == ',')
4953 arg->argnum += 1;
4954 return true;
4955 }
4956 return false;
4957 }
4958
4959 /* Try to get an expression from the next tokens in ARG. Consume the
4960 tokens and return true on success, storing the expression value in
4961 VALUE and relocation types in R. */
4962
4963 static bool
match_expression(struct mips_arg_info * arg,expressionS * value,bfd_reloc_code_real_type * r)4964 match_expression (struct mips_arg_info *arg, expressionS *value,
4965 bfd_reloc_code_real_type *r)
4966 {
4967 /* If the next token is a '(' that was parsed as being part of a base
4968 expression, assume we have an elided offset. The later match will fail
4969 if this turns out to be wrong. */
4970 if (arg->token->type == OT_CHAR && arg->token->u.ch == '(')
4971 {
4972 value->X_op = O_constant;
4973 value->X_add_number = 0;
4974 r[0] = r[1] = r[2] = BFD_RELOC_UNUSED;
4975 return true;
4976 }
4977
4978 /* Reject register-based expressions such as "0+$2" and "(($2))".
4979 For plain registers the default error seems more appropriate. */
4980 if (arg->token->type == OT_INTEGER
4981 && arg->token->u.integer.value.X_op == O_register)
4982 {
4983 set_insn_error (arg->argnum, _("register value used as expression"));
4984 return false;
4985 }
4986
4987 if (arg->token->type == OT_INTEGER)
4988 {
4989 *value = arg->token->u.integer.value;
4990 memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r));
4991 ++arg->token;
4992 return true;
4993 }
4994
4995 set_insn_error_i
4996 (arg->argnum, _("operand %d must be an immediate expression"),
4997 arg->argnum);
4998 return false;
4999 }
5000
5001 /* Try to get a constant expression from the next tokens in ARG. Consume
5002 the tokens and return true on success, storing the constant value
5003 in *VALUE. */
5004
5005 static bool
match_const_int(struct mips_arg_info * arg,offsetT * value)5006 match_const_int (struct mips_arg_info *arg, offsetT *value)
5007 {
5008 expressionS ex;
5009 bfd_reloc_code_real_type r[3];
5010
5011 if (!match_expression (arg, &ex, r))
5012 return false;
5013
5014 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant)
5015 *value = ex.X_add_number;
5016 else
5017 {
5018 if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big)
5019 match_out_of_range (arg);
5020 else
5021 match_not_constant (arg);
5022 return false;
5023 }
5024 return true;
5025 }
5026
5027 /* Return the RTYPE_* flags for a register operand of type TYPE that
5028 appears in instruction OPCODE. */
5029
5030 static unsigned int
convert_reg_type(const struct mips_opcode * opcode,enum mips_reg_operand_type type)5031 convert_reg_type (const struct mips_opcode *opcode,
5032 enum mips_reg_operand_type type)
5033 {
5034 switch (type)
5035 {
5036 case OP_REG_GP:
5037 return RTYPE_NUM | RTYPE_GP;
5038
5039 case OP_REG_FP:
5040 /* Allow vector register names for MDMX if the instruction is a 64-bit
5041 FPR load, store or move (including moves to and from GPRs). */
5042 if ((mips_opts.ase & ASE_MDMX)
5043 && (opcode->pinfo & FP_D)
5044 && (opcode->pinfo & (INSN_COPROC_MOVE
5045 | INSN_COPROC_MEMORY_DELAY
5046 | INSN_LOAD_COPROC
5047 | INSN_LOAD_MEMORY
5048 | INSN_STORE_MEMORY)))
5049 return RTYPE_FPU | RTYPE_VEC;
5050 return RTYPE_FPU;
5051
5052 case OP_REG_CCC:
5053 if (opcode->pinfo & (FP_D | FP_S))
5054 return RTYPE_CCC | RTYPE_FCC;
5055 return RTYPE_CCC;
5056
5057 case OP_REG_VEC:
5058 if (opcode->membership & INSN_5400)
5059 return RTYPE_FPU;
5060 return RTYPE_FPU | RTYPE_VEC;
5061
5062 case OP_REG_ACC:
5063 return RTYPE_ACC;
5064
5065 case OP_REG_COPRO:
5066 case OP_REG_CONTROL:
5067 if (opcode->name[strlen (opcode->name) - 1] == '0')
5068 return RTYPE_NUM | RTYPE_CP0;
5069 return RTYPE_NUM;
5070
5071 case OP_REG_HW:
5072 return RTYPE_NUM;
5073
5074 case OP_REG_VI:
5075 return RTYPE_NUM | RTYPE_VI;
5076
5077 case OP_REG_VF:
5078 return RTYPE_NUM | RTYPE_VF;
5079
5080 case OP_REG_R5900_I:
5081 return RTYPE_R5900_I;
5082
5083 case OP_REG_R5900_Q:
5084 return RTYPE_R5900_Q;
5085
5086 case OP_REG_R5900_R:
5087 return RTYPE_R5900_R;
5088
5089 case OP_REG_R5900_ACC:
5090 return RTYPE_R5900_ACC;
5091
5092 case OP_REG_MSA:
5093 return RTYPE_MSA;
5094
5095 case OP_REG_MSA_CTRL:
5096 return RTYPE_NUM;
5097 }
5098 abort ();
5099 }
5100
5101 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5102
5103 static void
check_regno(struct mips_arg_info * arg,enum mips_reg_operand_type type,unsigned int regno)5104 check_regno (struct mips_arg_info *arg,
5105 enum mips_reg_operand_type type, unsigned int regno)
5106 {
5107 if (AT && type == OP_REG_GP && regno == AT)
5108 arg->seen_at = true;
5109
5110 if (type == OP_REG_FP
5111 && (regno & 1) != 0
5112 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
5113 {
5114 /* This was a warning prior to introducing O32 FPXX and FP64 support
5115 so maintain a warning for FP32 but raise an error for the new
5116 cases. */
5117 if (FPR_SIZE == 32)
5118 as_warn (_("float register should be even, was %d"), regno);
5119 else
5120 as_bad (_("float register should be even, was %d"), regno);
5121 }
5122
5123 if (type == OP_REG_CCC)
5124 {
5125 const char *name;
5126 size_t length;
5127
5128 name = arg->insn->insn_mo->name;
5129 length = strlen (name);
5130 if ((regno & 1) != 0
5131 && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
5132 || (length >= 5 && startswith (name + length - 5, "any2"))))
5133 as_warn (_("condition code register should be even for %s, was %d"),
5134 name, regno);
5135
5136 if ((regno & 3) != 0
5137 && (length >= 5 && startswith (name + length - 5, "any4")))
5138 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5139 name, regno);
5140 }
5141 }
5142
5143 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5144 a register of type TYPE. Return true on success, storing the register
5145 number in *REGNO and warning about any dubious uses. */
5146
5147 static bool
match_regno(struct mips_arg_info * arg,enum mips_reg_operand_type type,unsigned int symval,unsigned int * regno)5148 match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5149 unsigned int symval, unsigned int *regno)
5150 {
5151 if (type == OP_REG_VEC)
5152 symval = mips_prefer_vec_regno (symval);
5153 if (!(symval & convert_reg_type (arg->insn->insn_mo, type)))
5154 return false;
5155
5156 *regno = symval & RNUM_MASK;
5157 check_regno (arg, type, *regno);
5158 return true;
5159 }
5160
5161 /* Try to interpret the next token in ARG as a register of type TYPE.
5162 Consume the token and return true on success, storing the register
5163 number in *REGNO. Return false on failure. */
5164
5165 static bool
match_reg(struct mips_arg_info * arg,enum mips_reg_operand_type type,unsigned int * regno)5166 match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5167 unsigned int *regno)
5168 {
5169 if (arg->token->type == OT_REG
5170 && match_regno (arg, type, arg->token->u.regno, regno))
5171 {
5172 ++arg->token;
5173 return true;
5174 }
5175 return false;
5176 }
5177
5178 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5179 Consume the token and return true on success, storing the register numbers
5180 in *REGNO1 and *REGNO2. Return false on failure. */
5181
5182 static bool
match_reg_range(struct mips_arg_info * arg,enum mips_reg_operand_type type,unsigned int * regno1,unsigned int * regno2)5183 match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type,
5184 unsigned int *regno1, unsigned int *regno2)
5185 {
5186 if (match_reg (arg, type, regno1))
5187 {
5188 *regno2 = *regno1;
5189 return true;
5190 }
5191 if (arg->token->type == OT_REG_RANGE
5192 && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1)
5193 && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2)
5194 && *regno1 <= *regno2)
5195 {
5196 ++arg->token;
5197 return true;
5198 }
5199 return false;
5200 }
5201
5202 /* OP_INT matcher. */
5203
5204 static bool
match_int_operand(struct mips_arg_info * arg,const struct mips_operand * operand_base)5205 match_int_operand (struct mips_arg_info *arg,
5206 const struct mips_operand *operand_base)
5207 {
5208 const struct mips_int_operand *operand;
5209 unsigned int uval;
5210 int min_val, max_val, factor;
5211 offsetT sval;
5212
5213 operand = (const struct mips_int_operand *) operand_base;
5214 factor = 1 << operand->shift;
5215 min_val = mips_int_operand_min (operand);
5216 max_val = mips_int_operand_max (operand);
5217
5218 if (operand_base->lsb == 0
5219 && operand_base->size == 16
5220 && operand->shift == 0
5221 && operand->bias == 0
5222 && (operand->max_val == 32767 || operand->max_val == 65535))
5223 {
5224 /* The operand can be relocated. */
5225 if (!match_expression (arg, &offset_expr, offset_reloc))
5226 return false;
5227
5228 if (offset_expr.X_op == O_big)
5229 {
5230 match_out_of_range (arg);
5231 return false;
5232 }
5233
5234 if (offset_reloc[0] != BFD_RELOC_UNUSED)
5235 /* Relocation operators were used. Accept the argument and
5236 leave the relocation value in offset_expr and offset_relocs
5237 for the caller to process. */
5238 return true;
5239
5240 if (offset_expr.X_op != O_constant)
5241 {
5242 /* Accept non-constant operands if no later alternative matches,
5243 leaving it for the caller to process. */
5244 if (!arg->lax_match)
5245 {
5246 match_not_constant (arg);
5247 return false;
5248 }
5249 offset_reloc[0] = BFD_RELOC_LO16;
5250 return true;
5251 }
5252
5253 /* Clear the global state; we're going to install the operand
5254 ourselves. */
5255 sval = offset_expr.X_add_number;
5256 offset_expr.X_op = O_absent;
5257
5258 /* For compatibility with older assemblers, we accept
5259 0x8000-0xffff as signed 16-bit numbers when only
5260 signed numbers are allowed. */
5261 if (sval > max_val)
5262 {
5263 max_val = ((1 << operand_base->size) - 1) << operand->shift;
5264 if (!arg->lax_match && sval <= max_val)
5265 {
5266 match_out_of_range (arg);
5267 return false;
5268 }
5269 }
5270 }
5271 else
5272 {
5273 if (!match_const_int (arg, &sval))
5274 return false;
5275 }
5276
5277 arg->last_op_int = sval;
5278
5279 if (sval < min_val || sval > max_val || sval % factor)
5280 {
5281 match_out_of_range (arg);
5282 return false;
5283 }
5284
5285 uval = (unsigned int) sval >> operand->shift;
5286 uval -= operand->bias;
5287
5288 /* Handle -mfix-cn63xxp1. */
5289 if (arg->opnum == 1
5290 && mips_fix_cn63xxp1
5291 && !mips_opts.micromips
5292 && strcmp ("pref", arg->insn->insn_mo->name) == 0)
5293 switch (uval)
5294 {
5295 case 5:
5296 case 25:
5297 case 26:
5298 case 27:
5299 case 28:
5300 case 29:
5301 case 30:
5302 case 31:
5303 /* These are ok. */
5304 break;
5305
5306 default:
5307 /* The rest must be changed to 28. */
5308 uval = 28;
5309 break;
5310 }
5311
5312 insn_insert_operand (arg->insn, operand_base, uval);
5313 return true;
5314 }
5315
5316 /* OP_MAPPED_INT matcher. */
5317
5318 static bool
match_mapped_int_operand(struct mips_arg_info * arg,const struct mips_operand * operand_base)5319 match_mapped_int_operand (struct mips_arg_info *arg,
5320 const struct mips_operand *operand_base)
5321 {
5322 const struct mips_mapped_int_operand *operand;
5323 unsigned int uval, num_vals;
5324 offsetT sval;
5325
5326 operand = (const struct mips_mapped_int_operand *) operand_base;
5327 if (!match_const_int (arg, &sval))
5328 return false;
5329
5330 num_vals = 1 << operand_base->size;
5331 for (uval = 0; uval < num_vals; uval++)
5332 if (operand->int_map[uval] == sval)
5333 break;
5334 if (uval == num_vals)
5335 {
5336 match_out_of_range (arg);
5337 return false;
5338 }
5339
5340 insn_insert_operand (arg->insn, operand_base, uval);
5341 return true;
5342 }
5343
5344 /* OP_MSB matcher. */
5345
5346 static bool
match_msb_operand(struct mips_arg_info * arg,const struct mips_operand * operand_base)5347 match_msb_operand (struct mips_arg_info *arg,
5348 const struct mips_operand *operand_base)
5349 {
5350 const struct mips_msb_operand *operand;
5351 int min_val, max_val, max_high;
5352 offsetT size, sval, high;
5353
5354 operand = (const struct mips_msb_operand *) operand_base;
5355 min_val = operand->bias;
5356 max_val = min_val + (1 << operand_base->size) - 1;
5357 max_high = operand->opsize;
5358
5359 if (!match_const_int (arg, &size))
5360 return false;
5361
5362 high = size + arg->last_op_int;
5363 sval = operand->add_lsb ? high : size;
5364
5365 if (size < 0 || high > max_high || sval < min_val || sval > max_val)
5366 {
5367 match_out_of_range (arg);
5368 return false;
5369 }
5370 insn_insert_operand (arg->insn, operand_base, sval - min_val);
5371 return true;
5372 }
5373
5374 /* OP_REG matcher. */
5375
5376 static bool
match_reg_operand(struct mips_arg_info * arg,const struct mips_operand * operand_base)5377 match_reg_operand (struct mips_arg_info *arg,
5378 const struct mips_operand *operand_base)
5379 {
5380 const struct mips_reg_operand *operand;
5381 unsigned int regno, uval, num_vals;
5382
5383 operand = (const struct mips_reg_operand *) operand_base;
5384 if (!match_reg (arg, operand->reg_type, ®no))
5385 return false;
5386
5387 if (operand->reg_map)
5388 {
5389 num_vals = 1 << operand->root.size;
5390 for (uval = 0; uval < num_vals; uval++)
5391 if (operand->reg_map[uval] == regno)
5392 break;
5393 if (num_vals == uval)
5394 return false;
5395 }
5396 else
5397 uval = regno;
5398
5399 arg->last_regno = regno;
5400 if (arg->opnum == 1)
5401 arg->dest_regno = regno;
5402 insn_insert_operand (arg->insn, operand_base, uval);
5403 return true;
5404 }
5405
5406 /* OP_REG_PAIR matcher. */
5407
5408 static bool
match_reg_pair_operand(struct mips_arg_info * arg,const struct mips_operand * operand_base)5409 match_reg_pair_operand (struct mips_arg_info *arg,
5410 const struct mips_operand *operand_base)
5411 {
5412 const struct mips_reg_pair_operand *operand;
5413 unsigned int regno1, regno2, uval, num_vals;
5414
5415 operand = (const struct mips_reg_pair_operand *) operand_base;
5416 if (!match_reg (arg, operand->reg_type, ®no1)
5417 || !match_char (arg, ',')
5418 || !match_reg (arg, operand->reg_type, ®no2))
5419 return false;
5420
5421 num_vals = 1 << operand_base->size;
5422 for (uval = 0; uval < num_vals; uval++)
5423 if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2)
5424 break;
5425 if (uval == num_vals)
5426 return false;
5427
5428 insn_insert_operand (arg->insn, operand_base, uval);
5429 return true;
5430 }
5431
5432 /* OP_PCREL matcher. The caller chooses the relocation type. */
5433
5434 static bool
match_pcrel_operand(struct mips_arg_info * arg)5435 match_pcrel_operand (struct mips_arg_info *arg)
5436 {
5437 bfd_reloc_code_real_type r[3];
5438
5439 return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED;
5440 }
5441
5442 /* OP_PERF_REG matcher. */
5443
5444 static bool
match_perf_reg_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5445 match_perf_reg_operand (struct mips_arg_info *arg,
5446 const struct mips_operand *operand)
5447 {
5448 offsetT sval;
5449
5450 if (!match_const_int (arg, &sval))
5451 return false;
5452
5453 if (sval != 0
5454 && (sval != 1
5455 || (mips_opts.arch == CPU_R5900
5456 && (strcmp (arg->insn->insn_mo->name, "mfps") == 0
5457 || strcmp (arg->insn->insn_mo->name, "mtps") == 0))))
5458 {
5459 set_insn_error (arg->argnum, _("invalid performance register"));
5460 return false;
5461 }
5462
5463 insn_insert_operand (arg->insn, operand, sval);
5464 return true;
5465 }
5466
5467 /* OP_ADDIUSP matcher. */
5468
5469 static bool
match_addiusp_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5470 match_addiusp_operand (struct mips_arg_info *arg,
5471 const struct mips_operand *operand)
5472 {
5473 offsetT sval;
5474 unsigned int uval;
5475
5476 if (!match_const_int (arg, &sval))
5477 return false;
5478
5479 if (sval % 4)
5480 {
5481 match_out_of_range (arg);
5482 return false;
5483 }
5484
5485 sval /= 4;
5486 if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1))
5487 {
5488 match_out_of_range (arg);
5489 return false;
5490 }
5491
5492 uval = (unsigned int) sval;
5493 uval = ((uval >> 1) & ~0xff) | (uval & 0xff);
5494 insn_insert_operand (arg->insn, operand, uval);
5495 return true;
5496 }
5497
5498 /* OP_CLO_CLZ_DEST matcher. */
5499
5500 static bool
match_clo_clz_dest_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5501 match_clo_clz_dest_operand (struct mips_arg_info *arg,
5502 const struct mips_operand *operand)
5503 {
5504 unsigned int regno;
5505
5506 if (!match_reg (arg, OP_REG_GP, ®no))
5507 return false;
5508
5509 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5510 return true;
5511 }
5512
5513 /* OP_CHECK_PREV matcher. */
5514
5515 static bool
match_check_prev_operand(struct mips_arg_info * arg,const struct mips_operand * operand_base)5516 match_check_prev_operand (struct mips_arg_info *arg,
5517 const struct mips_operand *operand_base)
5518 {
5519 const struct mips_check_prev_operand *operand;
5520 unsigned int regno;
5521
5522 operand = (const struct mips_check_prev_operand *) operand_base;
5523
5524 if (!match_reg (arg, OP_REG_GP, ®no))
5525 return false;
5526
5527 if (!operand->zero_ok && regno == 0)
5528 return false;
5529
5530 if ((operand->less_than_ok && regno < arg->last_regno)
5531 || (operand->greater_than_ok && regno > arg->last_regno)
5532 || (operand->equal_ok && regno == arg->last_regno))
5533 {
5534 arg->last_regno = regno;
5535 insn_insert_operand (arg->insn, operand_base, regno);
5536 return true;
5537 }
5538
5539 return false;
5540 }
5541
5542 /* OP_SAME_RS_RT matcher. */
5543
5544 static bool
match_same_rs_rt_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5545 match_same_rs_rt_operand (struct mips_arg_info *arg,
5546 const struct mips_operand *operand)
5547 {
5548 unsigned int regno;
5549
5550 if (!match_reg (arg, OP_REG_GP, ®no))
5551 return false;
5552
5553 if (regno == 0)
5554 {
5555 set_insn_error (arg->argnum, _("the source register must not be $0"));
5556 return false;
5557 }
5558
5559 arg->last_regno = regno;
5560
5561 insn_insert_operand (arg->insn, operand, regno | (regno << 5));
5562 return true;
5563 }
5564
5565 /* OP_LWM_SWM_LIST matcher. */
5566
5567 static bool
match_lwm_swm_list_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5568 match_lwm_swm_list_operand (struct mips_arg_info *arg,
5569 const struct mips_operand *operand)
5570 {
5571 unsigned int reglist, sregs, ra, regno1, regno2;
5572 struct mips_arg_info reset;
5573
5574 reglist = 0;
5575 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5576 return false;
5577 do
5578 {
5579 if (regno2 == FP && regno1 >= S0 && regno1 <= S7)
5580 {
5581 reglist |= 1 << FP;
5582 regno2 = S7;
5583 }
5584 reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1);
5585 reset = *arg;
5586 }
5587 while (match_char (arg, ',')
5588 && match_reg_range (arg, OP_REG_GP, ®no1, ®no2));
5589 *arg = reset;
5590
5591 if (operand->size == 2)
5592 {
5593 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5594
5595 s0, ra
5596 s0, s1, ra, s2, s3
5597 s0-s2, ra
5598
5599 and any permutations of these. */
5600 if ((reglist & 0xfff1ffff) != 0x80010000)
5601 return false;
5602
5603 sregs = (reglist >> 17) & 7;
5604 ra = 0;
5605 }
5606 else
5607 {
5608 /* The list must include at least one of ra and s0-sN,
5609 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5610 which are $23 and $30 respectively.) E.g.:
5611
5612 ra
5613 s0
5614 ra, s0, s1, s2
5615 s0-s8
5616 s0-s5, ra
5617
5618 and any permutations of these. */
5619 if ((reglist & 0x3f00ffff) != 0)
5620 return false;
5621
5622
5623 /* Fix NOP issue: Replace nops by "or at,at,zero". */
5624 ra = (reglist >> 27) & 0x10;
5625 sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff);
5626 }
5627 sregs += 1;
5628 if ((sregs & -sregs) != sregs)
5629 return false;
5630
5631 insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra);
5632 return true;
5633 }
5634
5635 static void
trap_zero_jump(struct mips_cl_insn * ip)5636 trap_zero_jump (struct mips_cl_insn * ip)
5637 {
5638 if (strcmp (ip->insn_mo->name, "j") == 0
5639 || strcmp (ip->insn_mo->name, "jr") == 0
5640 || strcmp (ip->insn_mo->name, "jalr") == 0)
5641 {
5642 int sreg;
5643
5644 if (mips_opts.warn_about_macros)
5645 return;
5646
5647 sreg = EXTRACT_OPERAND (0, RS, *ip);
5648 if (mips_opts.isa == ISA_MIPS32
5649 || mips_opts.isa == ISA_MIPS32R2
5650 || mips_opts.isa == ISA_MIPS64
5651 || mips_opts.isa == ISA_MIPS64R2)
5652 {
5653 expressionS ep;
5654 ep.X_op = O_constant;
5655 ep.X_add_number = 4096;
5656 macro_build (&ep, "tltiu", "s,j", sreg, BFD_RELOC_LO16);
5657 }
5658 else if (mips_opts.isa != ISA_UNKNOWN
5659 && mips_opts.isa != ISA_MIPS1)
5660 macro_build (NULL, "teq", "s,t", sreg, 0);
5661 }
5662 }
5663
5664 /* OP_ENTRY_EXIT_LIST matcher. */
5665
5666 static unsigned int
match_entry_exit_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5667 match_entry_exit_operand (struct mips_arg_info *arg,
5668 const struct mips_operand *operand)
5669 {
5670 unsigned int mask;
5671 bool is_exit;
5672
5673 /* The format is the same for both ENTRY and EXIT, but the constraints
5674 are different. */
5675 is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0;
5676 mask = (is_exit ? 7 << 3 : 0);
5677 do
5678 {
5679 unsigned int regno1, regno2;
5680 bool is_freg;
5681
5682 if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5683 is_freg = false;
5684 else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2))
5685 is_freg = true;
5686 else
5687 return false;
5688
5689 if (is_exit && is_freg && regno1 == 0 && regno2 < 2)
5690 {
5691 mask &= ~(7 << 3);
5692 mask |= (5 + regno2) << 3;
5693 }
5694 else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7)
5695 mask |= (regno2 - 3) << 3;
5696 else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17)
5697 mask |= (regno2 - 15) << 1;
5698 else if (regno1 == RA && regno2 == RA)
5699 mask |= 1;
5700 else
5701 return false;
5702 }
5703 while (match_char (arg, ','));
5704
5705 insn_insert_operand (arg->insn, operand, mask);
5706 return true;
5707 }
5708
5709 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5710 the argument register mask AMASK, the number of static registers
5711 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5712 respectively, and the frame size FRAME_SIZE. */
5713
5714 static unsigned int
mips_encode_save_restore(unsigned int amask,unsigned int nsreg,unsigned int ra,unsigned int s0,unsigned int s1,unsigned int frame_size)5715 mips_encode_save_restore (unsigned int amask, unsigned int nsreg,
5716 unsigned int ra, unsigned int s0, unsigned int s1,
5717 unsigned int frame_size)
5718 {
5719 return ((nsreg << 23) | ((frame_size & 0xf0) << 15) | (amask << 15)
5720 | (ra << 12) | (s0 << 11) | (s1 << 10) | ((frame_size & 0xf) << 6));
5721 }
5722
5723 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5724 argument register mask AMASK, the number of static registers saved
5725 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5726 respectively, and the frame size FRAME_SIZE. */
5727
5728 static unsigned int
mips16_encode_save_restore(unsigned int amask,unsigned int nsreg,unsigned int ra,unsigned int s0,unsigned int s1,unsigned int frame_size)5729 mips16_encode_save_restore (unsigned int amask, unsigned int nsreg,
5730 unsigned int ra, unsigned int s0, unsigned int s1,
5731 unsigned int frame_size)
5732 {
5733 unsigned int args;
5734
5735 args = (ra << 6) | (s0 << 5) | (s1 << 4) | (frame_size & 0xf);
5736 if (nsreg || amask || frame_size == 0 || frame_size > 16)
5737 args |= (MIPS16_EXTEND | (nsreg << 24) | (amask << 16)
5738 | ((frame_size & 0xf0) << 16));
5739 return args;
5740 }
5741
5742 /* OP_SAVE_RESTORE_LIST matcher. */
5743
5744 static bool
match_save_restore_list_operand(struct mips_arg_info * arg)5745 match_save_restore_list_operand (struct mips_arg_info *arg)
5746 {
5747 unsigned int opcode, args, statics, sregs;
5748 unsigned int num_frame_sizes, num_args, num_statics, num_sregs;
5749 unsigned int arg_mask, ra, s0, s1;
5750 offsetT frame_size;
5751
5752 opcode = arg->insn->insn_opcode;
5753 frame_size = 0;
5754 num_frame_sizes = 0;
5755 args = 0;
5756 statics = 0;
5757 sregs = 0;
5758 ra = 0;
5759 s0 = 0;
5760 s1 = 0;
5761 do
5762 {
5763 unsigned int regno1, regno2;
5764
5765 if (arg->token->type == OT_INTEGER)
5766 {
5767 /* Handle the frame size. */
5768 if (!match_const_int (arg, &frame_size))
5769 return false;
5770 num_frame_sizes += 1;
5771 }
5772 else
5773 {
5774 if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2))
5775 return false;
5776
5777 while (regno1 <= regno2)
5778 {
5779 if (regno1 >= 4 && regno1 <= 7)
5780 {
5781 if (num_frame_sizes == 0)
5782 /* args $a0-$a3 */
5783 args |= 1 << (regno1 - 4);
5784 else
5785 /* statics $a0-$a3 */
5786 statics |= 1 << (regno1 - 4);
5787 }
5788 else if (regno1 >= 16 && regno1 <= 23)
5789 /* $s0-$s7 */
5790 sregs |= 1 << (regno1 - 16);
5791 else if (regno1 == 30)
5792 /* $s8 */
5793 sregs |= 1 << 8;
5794 else if (regno1 == 31)
5795 /* Add $ra to insn. */
5796 ra = 1;
5797 else
5798 return false;
5799 regno1 += 1;
5800 if (regno1 == 24)
5801 regno1 = 30;
5802 }
5803 }
5804 }
5805 while (match_char (arg, ','));
5806
5807 /* Encode args/statics combination. */
5808 if (args & statics)
5809 return false;
5810 else if (args == 0xf)
5811 /* All $a0-$a3 are args. */
5812 arg_mask = MIPS_SVRS_ALL_ARGS;
5813 else if (statics == 0xf)
5814 /* All $a0-$a3 are statics. */
5815 arg_mask = MIPS_SVRS_ALL_STATICS;
5816 else
5817 {
5818 /* Count arg registers. */
5819 num_args = 0;
5820 while (args & 0x1)
5821 {
5822 args >>= 1;
5823 num_args += 1;
5824 }
5825 if (args != 0)
5826 return false;
5827
5828 /* Count static registers. */
5829 num_statics = 0;
5830 while (statics & 0x8)
5831 {
5832 statics = (statics << 1) & 0xf;
5833 num_statics += 1;
5834 }
5835 if (statics != 0)
5836 return false;
5837
5838 /* Encode args/statics. */
5839 arg_mask = (num_args << 2) | num_statics;
5840 }
5841
5842 /* Encode $s0/$s1. */
5843 if (sregs & (1 << 0)) /* $s0 */
5844 s0 = 1;
5845 if (sregs & (1 << 1)) /* $s1 */
5846 s1 = 1;
5847 sregs >>= 2;
5848
5849 /* Encode $s2-$s8. */
5850 num_sregs = 0;
5851 while (sregs & 1)
5852 {
5853 sregs >>= 1;
5854 num_sregs += 1;
5855 }
5856 if (sregs != 0)
5857 return false;
5858
5859 /* Encode frame size. */
5860 if (num_frame_sizes == 0)
5861 {
5862 set_insn_error (arg->argnum, _("missing frame size"));
5863 return false;
5864 }
5865 if (num_frame_sizes > 1)
5866 {
5867 set_insn_error (arg->argnum, _("frame size specified twice"));
5868 return false;
5869 }
5870 if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8)
5871 {
5872 set_insn_error (arg->argnum, _("invalid frame size"));
5873 return false;
5874 }
5875 frame_size /= 8;
5876
5877 /* Finally build the instruction. */
5878 if (mips_opts.mips16)
5879 opcode |= mips16_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5880 frame_size);
5881 else if (!mips_opts.micromips)
5882 opcode |= mips_encode_save_restore (arg_mask, num_sregs, ra, s0, s1,
5883 frame_size);
5884 else
5885 abort ();
5886
5887 arg->insn->insn_opcode = opcode;
5888 return true;
5889 }
5890
5891 /* OP_MDMX_IMM_REG matcher. */
5892
5893 static bool
match_mdmx_imm_reg_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5894 match_mdmx_imm_reg_operand (struct mips_arg_info *arg,
5895 const struct mips_operand *operand)
5896 {
5897 unsigned int regno, uval;
5898 bool is_qh;
5899 const struct mips_opcode *opcode;
5900
5901 /* The mips_opcode records whether this is an octobyte or quadhalf
5902 instruction. Start out with that bit in place. */
5903 opcode = arg->insn->insn_mo;
5904 uval = mips_extract_operand (operand, opcode->match);
5905 is_qh = (uval != 0);
5906
5907 if (arg->token->type == OT_REG)
5908 {
5909 if ((opcode->membership & INSN_5400)
5910 && strcmp (opcode->name, "rzu.ob") == 0)
5911 {
5912 set_insn_error_i (arg->argnum, _("operand %d must be an immediate"),
5913 arg->argnum);
5914 return false;
5915 }
5916
5917 if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no))
5918 return false;
5919 ++arg->token;
5920
5921 /* Check whether this is a vector register or a broadcast of
5922 a single element. */
5923 if (arg->token->type == OT_INTEGER_INDEX)
5924 {
5925 if (arg->token->u.index > (is_qh ? 3 : 7))
5926 {
5927 set_insn_error (arg->argnum, _("invalid element selector"));
5928 return false;
5929 }
5930 uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5;
5931 ++arg->token;
5932 }
5933 else
5934 {
5935 /* A full vector. */
5936 if ((opcode->membership & INSN_5400)
5937 && (strcmp (opcode->name, "sll.ob") == 0
5938 || strcmp (opcode->name, "srl.ob") == 0))
5939 {
5940 set_insn_error_i (arg->argnum, _("operand %d must be scalar"),
5941 arg->argnum);
5942 return false;
5943 }
5944
5945 if (is_qh)
5946 uval |= MDMX_FMTSEL_VEC_QH << 5;
5947 else
5948 uval |= MDMX_FMTSEL_VEC_OB << 5;
5949 }
5950 uval |= regno;
5951 }
5952 else
5953 {
5954 offsetT sval;
5955
5956 if (!match_const_int (arg, &sval))
5957 return false;
5958 if (sval < 0 || sval > 31)
5959 {
5960 match_out_of_range (arg);
5961 return false;
5962 }
5963 uval |= (sval & 31);
5964 if (is_qh)
5965 uval |= MDMX_FMTSEL_IMM_QH << 5;
5966 else
5967 uval |= MDMX_FMTSEL_IMM_OB << 5;
5968 }
5969 insn_insert_operand (arg->insn, operand, uval);
5970 return true;
5971 }
5972
5973 /* OP_IMM_INDEX matcher. */
5974
5975 static bool
match_imm_index_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5976 match_imm_index_operand (struct mips_arg_info *arg,
5977 const struct mips_operand *operand)
5978 {
5979 unsigned int max_val;
5980
5981 if (arg->token->type != OT_INTEGER_INDEX)
5982 return false;
5983
5984 max_val = (1 << operand->size) - 1;
5985 if (arg->token->u.index > max_val)
5986 {
5987 match_out_of_range (arg);
5988 return false;
5989 }
5990 insn_insert_operand (arg->insn, operand, arg->token->u.index);
5991 ++arg->token;
5992 return true;
5993 }
5994
5995 /* OP_REG_INDEX matcher. */
5996
5997 static bool
match_reg_index_operand(struct mips_arg_info * arg,const struct mips_operand * operand)5998 match_reg_index_operand (struct mips_arg_info *arg,
5999 const struct mips_operand *operand)
6000 {
6001 unsigned int regno;
6002
6003 if (arg->token->type != OT_REG_INDEX)
6004 return false;
6005
6006 if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no))
6007 return false;
6008
6009 insn_insert_operand (arg->insn, operand, regno);
6010 ++arg->token;
6011 return true;
6012 }
6013
6014 /* OP_PC matcher. */
6015
6016 static bool
match_pc_operand(struct mips_arg_info * arg)6017 match_pc_operand (struct mips_arg_info *arg)
6018 {
6019 if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC))
6020 {
6021 ++arg->token;
6022 return true;
6023 }
6024 return false;
6025 }
6026
6027 /* OP_REG28 matcher. */
6028
6029 static bool
match_reg28_operand(struct mips_arg_info * arg)6030 match_reg28_operand (struct mips_arg_info *arg)
6031 {
6032 unsigned int regno;
6033
6034 if (arg->token->type == OT_REG
6035 && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)
6036 && regno == GP)
6037 {
6038 ++arg->token;
6039 return true;
6040 }
6041 return false;
6042 }
6043
6044 /* OP_NON_ZERO_REG matcher. */
6045
6046 static bool
match_non_zero_reg_operand(struct mips_arg_info * arg,const struct mips_operand * operand)6047 match_non_zero_reg_operand (struct mips_arg_info *arg,
6048 const struct mips_operand *operand)
6049 {
6050 unsigned int regno;
6051
6052 if (!match_reg (arg, OP_REG_GP, ®no))
6053 return false;
6054
6055 if (regno == 0)
6056 {
6057 set_insn_error (arg->argnum, _("the source register must not be $0"));
6058 return false;
6059 }
6060
6061 arg->last_regno = regno;
6062 insn_insert_operand (arg->insn, operand, regno);
6063 return true;
6064 }
6065
6066 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6067 register that we need to match. */
6068
6069 static bool
match_tied_reg_operand(struct mips_arg_info * arg,unsigned int other_regno)6070 match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
6071 {
6072 unsigned int regno;
6073
6074 return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno;
6075 }
6076
6077 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6078 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6079 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6080
6081 Return the constant in IMM and OFFSET as follows:
6082
6083 - If the constant should be loaded via memory, set IMM to O_absent and
6084 OFFSET to the memory address.
6085
6086 - Otherwise, if the constant should be loaded into two 32-bit registers,
6087 set IMM to the O_constant to load into the high register and OFFSET
6088 to the corresponding value for the low register.
6089
6090 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6091
6092 These constants only appear as the last operand in an instruction,
6093 and every instruction that accepts them in any variant accepts them
6094 in all variants. This means we don't have to worry about backing out
6095 any changes if the instruction does not match. We just match
6096 unconditionally and report an error if the constant is invalid. */
6097
6098 static bool
match_float_constant(struct mips_arg_info * arg,expressionS * imm,expressionS * offset,int length,bool using_gprs)6099 match_float_constant (struct mips_arg_info *arg, expressionS *imm,
6100 expressionS *offset, int length, bool using_gprs)
6101 {
6102 char *p;
6103 segT seg, new_seg;
6104 subsegT subseg;
6105 const char *newname;
6106 unsigned char *data;
6107
6108 /* Where the constant is placed is based on how the MIPS assembler
6109 does things:
6110
6111 length == 4 && using_gprs -- immediate value only
6112 length == 8 && using_gprs -- .rdata or immediate value
6113 length == 4 && !using_gprs -- .lit4 or immediate value
6114 length == 8 && !using_gprs -- .lit8 or immediate value
6115
6116 The .lit4 and .lit8 sections are only used if permitted by the
6117 -G argument. */
6118 if (arg->token->type != OT_FLOAT)
6119 {
6120 set_insn_error (arg->argnum, _("floating-point expression required"));
6121 return false;
6122 }
6123
6124 gas_assert (arg->token->u.flt.length == length);
6125 data = arg->token->u.flt.data;
6126 ++arg->token;
6127
6128 /* Handle 32-bit constants for which an immediate value is best. */
6129 if (length == 4
6130 && (using_gprs
6131 || g_switch_value < 4
6132 || (data[0] == 0 && data[1] == 0)
6133 || (data[2] == 0 && data[3] == 0)))
6134 {
6135 imm->X_op = O_constant;
6136 if (!target_big_endian)
6137 imm->X_add_number = bfd_getl32 (data);
6138 else
6139 imm->X_add_number = bfd_getb32 (data);
6140 offset->X_op = O_absent;
6141 return true;
6142 }
6143
6144 /* Handle 64-bit constants for which an immediate value is best. */
6145 if (length == 8
6146 && !mips_disable_float_construction
6147 /* Constants can only be constructed in GPRs and copied to FPRs if the
6148 GPRs are at least as wide as the FPRs or MTHC1 is available.
6149 Unlike most tests for 32-bit floating-point registers this check
6150 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6151 permit 64-bit moves without MXHC1.
6152 Force the constant into memory otherwise. */
6153 && (using_gprs
6154 || GPR_SIZE == 64
6155 || ISA_HAS_MXHC1 (mips_opts.isa)
6156 || FPR_SIZE == 32)
6157 && ((data[0] == 0 && data[1] == 0)
6158 || (data[2] == 0 && data[3] == 0))
6159 && ((data[4] == 0 && data[5] == 0)
6160 || (data[6] == 0 && data[7] == 0)))
6161 {
6162 /* The value is simple enough to load with a couple of instructions.
6163 If using 32-bit registers, set IMM to the high order 32 bits and
6164 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6165 64 bit constant. */
6166 if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64))
6167 {
6168 imm->X_op = O_constant;
6169 offset->X_op = O_constant;
6170 if (!target_big_endian)
6171 {
6172 imm->X_add_number = bfd_getl32 (data + 4);
6173 offset->X_add_number = bfd_getl32 (data);
6174 }
6175 else
6176 {
6177 imm->X_add_number = bfd_getb32 (data);
6178 offset->X_add_number = bfd_getb32 (data + 4);
6179 }
6180 if (offset->X_add_number == 0)
6181 offset->X_op = O_absent;
6182 }
6183 else
6184 {
6185 imm->X_op = O_constant;
6186 if (!target_big_endian)
6187 imm->X_add_number = bfd_getl64 (data);
6188 else
6189 imm->X_add_number = bfd_getb64 (data);
6190 offset->X_op = O_absent;
6191 }
6192 return true;
6193 }
6194
6195 /* Switch to the right section. */
6196 seg = now_seg;
6197 subseg = now_subseg;
6198 if (length == 4)
6199 {
6200 gas_assert (!using_gprs && g_switch_value >= 4);
6201 newname = ".lit4";
6202 }
6203 else
6204 {
6205 if (using_gprs || g_switch_value < 8)
6206 newname = RDATA_SECTION_NAME;
6207 else
6208 newname = ".lit8";
6209 }
6210
6211 new_seg = subseg_new (newname, (subsegT) 0);
6212 bfd_set_section_flags (new_seg,
6213 SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA);
6214 frag_align (length == 4 ? 2 : 3, 0, 0);
6215 if (!startswith (TARGET_OS, "elf"))
6216 record_alignment (new_seg, 4);
6217 else
6218 record_alignment (new_seg, length == 4 ? 2 : 3);
6219 if (seg == now_seg)
6220 as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
6221
6222 /* Set the argument to the current address in the section. */
6223 imm->X_op = O_absent;
6224 offset->X_op = O_symbol;
6225 offset->X_add_symbol = symbol_temp_new_now ();
6226 offset->X_add_number = 0;
6227
6228 /* Put the floating point number into the section. */
6229 p = frag_more (length);
6230 memcpy (p, data, length);
6231
6232 /* Switch back to the original section. */
6233 subseg_set (seg, subseg);
6234 return true;
6235 }
6236
6237 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6238 them. */
6239
6240 static bool
match_vu0_suffix_operand(struct mips_arg_info * arg,const struct mips_operand * operand,bool match_p)6241 match_vu0_suffix_operand (struct mips_arg_info *arg,
6242 const struct mips_operand *operand,
6243 bool match_p)
6244 {
6245 unsigned int uval;
6246
6247 /* The operand can be an XYZW mask or a single 2-bit channel index
6248 (with X being 0). */
6249 gas_assert (operand->size == 2 || operand->size == 4);
6250
6251 /* The suffix can be omitted when it is already part of the opcode. */
6252 if (arg->token->type != OT_CHANNELS)
6253 return match_p;
6254
6255 uval = arg->token->u.channels;
6256 if (operand->size == 2)
6257 {
6258 /* Check that a single bit is set and convert it into a 2-bit index. */
6259 if ((uval & -uval) != uval)
6260 return false;
6261 uval = 4 - ffs (uval);
6262 }
6263
6264 if (match_p && insn_extract_operand (arg->insn, operand) != uval)
6265 return false;
6266
6267 ++arg->token;
6268 if (!match_p)
6269 insn_insert_operand (arg->insn, operand, uval);
6270 return true;
6271 }
6272
6273 /* Try to match a token from ARG against OPERAND. Consume the token
6274 and return true on success, otherwise return false. */
6275
6276 static bool
match_operand(struct mips_arg_info * arg,const struct mips_operand * operand)6277 match_operand (struct mips_arg_info *arg,
6278 const struct mips_operand *operand)
6279 {
6280 switch (operand->type)
6281 {
6282 case OP_INT:
6283 return match_int_operand (arg, operand);
6284
6285 case OP_MAPPED_INT:
6286 return match_mapped_int_operand (arg, operand);
6287
6288 case OP_MSB:
6289 return match_msb_operand (arg, operand);
6290
6291 case OP_REG:
6292 case OP_OPTIONAL_REG:
6293 return match_reg_operand (arg, operand);
6294
6295 case OP_REG_PAIR:
6296 return match_reg_pair_operand (arg, operand);
6297
6298 case OP_PCREL:
6299 return match_pcrel_operand (arg);
6300
6301 case OP_PERF_REG:
6302 return match_perf_reg_operand (arg, operand);
6303
6304 case OP_ADDIUSP_INT:
6305 return match_addiusp_operand (arg, operand);
6306
6307 case OP_CLO_CLZ_DEST:
6308 return match_clo_clz_dest_operand (arg, operand);
6309
6310 case OP_LWM_SWM_LIST:
6311 return match_lwm_swm_list_operand (arg, operand);
6312
6313 case OP_ENTRY_EXIT_LIST:
6314 return match_entry_exit_operand (arg, operand);
6315
6316 case OP_SAVE_RESTORE_LIST:
6317 return match_save_restore_list_operand (arg);
6318
6319 case OP_MDMX_IMM_REG:
6320 return match_mdmx_imm_reg_operand (arg, operand);
6321
6322 case OP_REPEAT_DEST_REG:
6323 return match_tied_reg_operand (arg, arg->dest_regno);
6324
6325 case OP_REPEAT_PREV_REG:
6326 return match_tied_reg_operand (arg, arg->last_regno);
6327
6328 case OP_PC:
6329 return match_pc_operand (arg);
6330
6331 case OP_REG28:
6332 return match_reg28_operand (arg);
6333
6334 case OP_VU0_SUFFIX:
6335 return match_vu0_suffix_operand (arg, operand, false);
6336
6337 case OP_VU0_MATCH_SUFFIX:
6338 return match_vu0_suffix_operand (arg, operand, true);
6339
6340 case OP_IMM_INDEX:
6341 return match_imm_index_operand (arg, operand);
6342
6343 case OP_REG_INDEX:
6344 return match_reg_index_operand (arg, operand);
6345
6346 case OP_SAME_RS_RT:
6347 return match_same_rs_rt_operand (arg, operand);
6348
6349 case OP_CHECK_PREV:
6350 return match_check_prev_operand (arg, operand);
6351
6352 case OP_NON_ZERO_REG:
6353 return match_non_zero_reg_operand (arg, operand);
6354 }
6355 abort ();
6356 }
6357
6358 /* ARG is the state after successfully matching an instruction.
6359 Issue any queued-up warnings. */
6360
6361 static void
check_completed_insn(struct mips_arg_info * arg)6362 check_completed_insn (struct mips_arg_info *arg)
6363 {
6364 if (arg->seen_at)
6365 {
6366 if (AT == ATREG)
6367 as_warn (_("used $at without \".set noat\""));
6368 else
6369 as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
6370 }
6371 }
6372
6373 /* Return true if modifying general-purpose register REG needs a delay. */
6374
6375 static bool
reg_needs_delay(unsigned int reg)6376 reg_needs_delay (unsigned int reg)
6377 {
6378 unsigned long prev_pinfo;
6379
6380 prev_pinfo = history[0].insn_mo->pinfo;
6381 if (!mips_opts.noreorder
6382 && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
6383 || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
6384 && (gpr_write_mask (&history[0]) & (1 << reg)))
6385 return true;
6386
6387 return false;
6388 }
6389
6390 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6391 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6392 by VR4120 errata. */
6393
6394 static unsigned int
classify_vr4120_insn(const char * name)6395 classify_vr4120_insn (const char *name)
6396 {
6397 if (startswith (name, "macc"))
6398 return FIX_VR4120_MACC;
6399 if (startswith (name, "dmacc"))
6400 return FIX_VR4120_DMACC;
6401 if (startswith (name, "mult"))
6402 return FIX_VR4120_MULT;
6403 if (startswith (name, "dmult"))
6404 return FIX_VR4120_DMULT;
6405 if (strstr (name, "div"))
6406 return FIX_VR4120_DIV;
6407 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
6408 return FIX_VR4120_MTHILO;
6409 return NUM_FIX_VR4120_CLASSES;
6410 }
6411
6412 #define INSN_ERET 0x42000018
6413 #define INSN_DERET 0x4200001f
6414 #define INSN_DMULT 0x1c
6415 #define INSN_DMULTU 0x1d
6416
6417 /* Return the number of instructions that must separate INSN1 and INSN2,
6418 where INSN1 is the earlier instruction. Return the worst-case value
6419 for any INSN2 if INSN2 is null. */
6420
6421 static unsigned int
insns_between(const struct mips_cl_insn * insn1,const struct mips_cl_insn * insn2)6422 insns_between (const struct mips_cl_insn *insn1,
6423 const struct mips_cl_insn *insn2)
6424 {
6425 unsigned long pinfo1, pinfo2;
6426 unsigned int mask;
6427
6428 /* If INFO2 is null, pessimistically assume that all flags are set for
6429 the second instruction. */
6430 pinfo1 = insn1->insn_mo->pinfo;
6431 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
6432
6433 /* For most targets, write-after-read dependencies on the HI and LO
6434 registers must be separated by at least two instructions. */
6435 if (!hilo_interlocks)
6436 {
6437 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
6438 return 2;
6439 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
6440 return 2;
6441 }
6442
6443 /* If we're working around r7000 errata, there must be two instructions
6444 between an mfhi or mflo and any instruction that uses the result. */
6445 if (mips_7000_hilo_fix
6446 && !mips_opts.micromips
6447 && MF_HILO_INSN (pinfo1)
6448 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6449 return 2;
6450
6451 /* If we're working around 24K errata, one instruction is required
6452 if an ERET or DERET is followed by a branch instruction. */
6453 if (mips_fix_24k && !mips_opts.micromips)
6454 {
6455 if (insn1->insn_opcode == INSN_ERET
6456 || insn1->insn_opcode == INSN_DERET)
6457 {
6458 if (insn2 == NULL
6459 || insn2->insn_opcode == INSN_ERET
6460 || insn2->insn_opcode == INSN_DERET
6461 || delayed_branch_p (insn2))
6462 return 1;
6463 }
6464 }
6465
6466 /* If we're working around PMC RM7000 errata, there must be three
6467 nops between a dmult and a load instruction. */
6468 if (mips_fix_rm7000 && !mips_opts.micromips)
6469 {
6470 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6471 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6472 {
6473 if (pinfo2 & INSN_LOAD_MEMORY)
6474 return 3;
6475 }
6476 }
6477
6478 /* If working around VR4120 errata, check for combinations that need
6479 a single intervening instruction. */
6480 if (mips_fix_vr4120 && !mips_opts.micromips)
6481 {
6482 unsigned int class1, class2;
6483
6484 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6485 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
6486 {
6487 if (insn2 == NULL)
6488 return 1;
6489 class2 = classify_vr4120_insn (insn2->insn_mo->name);
6490 if (vr4120_conflicts[class1] & (1 << class2))
6491 return 1;
6492 }
6493 }
6494
6495 if (!HAVE_CODE_COMPRESSION)
6496 {
6497 /* Check for GPR or coprocessor load delays. All such delays
6498 are on the RT register. */
6499 /* Itbl support may require additional care here. */
6500 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
6501 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
6502 {
6503 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6504 return 1;
6505 }
6506
6507 /* Check for generic coprocessor hazards.
6508
6509 This case is not handled very well. There is no special
6510 knowledge of CP0 handling, and the coprocessors other than
6511 the floating point unit are not distinguished at all. */
6512 /* Itbl support may require additional care here. FIXME!
6513 Need to modify this to include knowledge about
6514 user specified delays! */
6515 if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
6516 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
6517 {
6518 /* Handle cases where INSN1 writes to a known general coprocessor
6519 register. There must be a one instruction delay before INSN2
6520 if INSN2 reads that register, otherwise no delay is needed. */
6521 mask = fpr_write_mask (insn1);
6522 if (mask != 0)
6523 {
6524 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
6525 return 1;
6526 }
6527 else
6528 {
6529 /* Read-after-write dependencies on the control registers
6530 require a two-instruction gap. */
6531 if ((pinfo1 & INSN_WRITE_COND_CODE)
6532 && (pinfo2 & INSN_READ_COND_CODE))
6533 return 2;
6534
6535 /* We don't know exactly what INSN1 does. If INSN2 is
6536 also a coprocessor instruction, assume there must be
6537 a one instruction gap. */
6538 if (pinfo2 & INSN_COP)
6539 return 1;
6540 }
6541 }
6542
6543 /* Check for read-after-write dependencies on the coprocessor
6544 control registers in cases where INSN1 does not need a general
6545 coprocessor delay. This means that INSN1 is a floating point
6546 comparison instruction. */
6547 /* Itbl support may require additional care here. */
6548 else if (!cop_interlocks
6549 && (pinfo1 & INSN_WRITE_COND_CODE)
6550 && (pinfo2 & INSN_READ_COND_CODE))
6551 return 1;
6552 }
6553
6554 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6555 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6556 and pause. */
6557 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6558 && ((pinfo2 & INSN_NO_DELAY_SLOT)
6559 || (insn2 && delayed_branch_p (insn2))))
6560 return 1;
6561
6562 return 0;
6563 }
6564
6565 /* Return the number of nops that would be needed to work around the
6566 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6567 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6568 that are contained within the first IGNORE instructions of HIST. */
6569
6570 static int
nops_for_vr4130(int ignore,const struct mips_cl_insn * hist,const struct mips_cl_insn * insn)6571 nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
6572 const struct mips_cl_insn *insn)
6573 {
6574 int i, j;
6575 unsigned int mask;
6576
6577 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6578 are not affected by the errata. */
6579 if (insn != 0
6580 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
6581 || strcmp (insn->insn_mo->name, "mtlo") == 0
6582 || strcmp (insn->insn_mo->name, "mthi") == 0))
6583 return 0;
6584
6585 /* Search for the first MFLO or MFHI. */
6586 for (i = 0; i < MAX_VR4130_NOPS; i++)
6587 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
6588 {
6589 /* Extract the destination register. */
6590 mask = gpr_write_mask (&hist[i]);
6591
6592 /* No nops are needed if INSN reads that register. */
6593 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
6594 return 0;
6595
6596 /* ...or if any of the intervening instructions do. */
6597 for (j = 0; j < i; j++)
6598 if (gpr_read_mask (&hist[j]) & mask)
6599 return 0;
6600
6601 if (i >= ignore)
6602 return MAX_VR4130_NOPS - i;
6603 }
6604 return 0;
6605 }
6606
6607 #define BASE_REG_EQ(INSN1, INSN2) \
6608 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6609 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6610
6611 /* Return the minimum alignment for this store instruction. */
6612
6613 static int
fix_24k_align_to(const struct mips_opcode * mo)6614 fix_24k_align_to (const struct mips_opcode *mo)
6615 {
6616 if (strcmp (mo->name, "sh") == 0)
6617 return 2;
6618
6619 if (strcmp (mo->name, "swc1") == 0
6620 || strcmp (mo->name, "swc2") == 0
6621 || strcmp (mo->name, "sw") == 0
6622 || strcmp (mo->name, "sc") == 0
6623 || strcmp (mo->name, "s.s") == 0)
6624 return 4;
6625
6626 if (strcmp (mo->name, "sdc1") == 0
6627 || strcmp (mo->name, "sdc2") == 0
6628 || strcmp (mo->name, "s.d") == 0)
6629 return 8;
6630
6631 /* sb, swl, swr */
6632 return 1;
6633 }
6634
6635 struct fix_24k_store_info
6636 {
6637 /* Immediate offset, if any, for this store instruction. */
6638 short off;
6639 /* Alignment required by this store instruction. */
6640 int align_to;
6641 /* True for register offsets. */
6642 int register_offset;
6643 };
6644
6645 /* Comparison function used by qsort. */
6646
6647 static int
fix_24k_sort(const void * a,const void * b)6648 fix_24k_sort (const void *a, const void *b)
6649 {
6650 const struct fix_24k_store_info *pos1 = a;
6651 const struct fix_24k_store_info *pos2 = b;
6652
6653 return (pos1->off - pos2->off);
6654 }
6655
6656 /* INSN is a store instruction. Try to record the store information
6657 in STINFO. Return false if the information isn't known. */
6658
6659 static bool
fix_24k_record_store_info(struct fix_24k_store_info * stinfo,const struct mips_cl_insn * insn)6660 fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
6661 const struct mips_cl_insn *insn)
6662 {
6663 /* The instruction must have a known offset. */
6664 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
6665 return false;
6666
6667 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
6668 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
6669 return true;
6670 }
6671
6672 /* Return the number of nops that would be needed to work around the 24k
6673 "lost data on stores during refill" errata if instruction INSN
6674 immediately followed the 2 instructions described by HIST.
6675 Ignore hazards that are contained within the first IGNORE
6676 instructions of HIST.
6677
6678 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6679 for the data cache refills and store data. The following describes
6680 the scenario where the store data could be lost.
6681
6682 * A data cache miss, due to either a load or a store, causing fill
6683 data to be supplied by the memory subsystem
6684 * The first three doublewords of fill data are returned and written
6685 into the cache
6686 * A sequence of four stores occurs in consecutive cycles around the
6687 final doubleword of the fill:
6688 * Store A
6689 * Store B
6690 * Store C
6691 * Zero, One or more instructions
6692 * Store D
6693
6694 The four stores A-D must be to different doublewords of the line that
6695 is being filled. The fourth instruction in the sequence above permits
6696 the fill of the final doubleword to be transferred from the FSB into
6697 the cache. In the sequence above, the stores may be either integer
6698 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6699 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6700 different doublewords on the line. If the floating point unit is
6701 running in 1:2 mode, it is not possible to create the sequence above
6702 using only floating point store instructions.
6703
6704 In this case, the cache line being filled is incorrectly marked
6705 invalid, thereby losing the data from any store to the line that
6706 occurs between the original miss and the completion of the five
6707 cycle sequence shown above.
6708
6709 The workarounds are:
6710
6711 * Run the data cache in write-through mode.
6712 * Insert a non-store instruction between
6713 Store A and Store B or Store B and Store C. */
6714
6715 static int
nops_for_24k(int ignore,const struct mips_cl_insn * hist,const struct mips_cl_insn * insn)6716 nops_for_24k (int ignore, const struct mips_cl_insn *hist,
6717 const struct mips_cl_insn *insn)
6718 {
6719 struct fix_24k_store_info pos[3];
6720 int align, i, base_offset;
6721
6722 if (ignore >= 2)
6723 return 0;
6724
6725 /* If the previous instruction wasn't a store, there's nothing to
6726 worry about. */
6727 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6728 return 0;
6729
6730 /* If the instructions after the previous one are unknown, we have
6731 to assume the worst. */
6732 if (!insn)
6733 return 1;
6734
6735 /* Check whether we are dealing with three consecutive stores. */
6736 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
6737 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
6738 return 0;
6739
6740 /* If we don't know the relationship between the store addresses,
6741 assume the worst. */
6742 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
6743 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
6744 return 1;
6745
6746 if (!fix_24k_record_store_info (&pos[0], insn)
6747 || !fix_24k_record_store_info (&pos[1], &hist[0])
6748 || !fix_24k_record_store_info (&pos[2], &hist[1]))
6749 return 1;
6750
6751 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
6752
6753 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6754 X bytes and such that the base register + X is known to be aligned
6755 to align bytes. */
6756
6757 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
6758 align = 8;
6759 else
6760 {
6761 align = pos[0].align_to;
6762 base_offset = pos[0].off;
6763 for (i = 1; i < 3; i++)
6764 if (align < pos[i].align_to)
6765 {
6766 align = pos[i].align_to;
6767 base_offset = pos[i].off;
6768 }
6769 for (i = 0; i < 3; i++)
6770 pos[i].off -= base_offset;
6771 }
6772
6773 pos[0].off &= ~align + 1;
6774 pos[1].off &= ~align + 1;
6775 pos[2].off &= ~align + 1;
6776
6777 /* If any two stores write to the same chunk, they also write to the
6778 same doubleword. The offsets are still sorted at this point. */
6779 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
6780 return 0;
6781
6782 /* A range of at least 9 bytes is needed for the stores to be in
6783 non-overlapping doublewords. */
6784 if (pos[2].off - pos[0].off <= 8)
6785 return 0;
6786
6787 if (pos[2].off - pos[1].off >= 24
6788 || pos[1].off - pos[0].off >= 24
6789 || pos[2].off - pos[0].off >= 32)
6790 return 0;
6791
6792 return 1;
6793 }
6794
6795 /* Return the number of nops that would be needed if instruction INSN
6796 immediately followed the MAX_NOPS instructions given by HIST,
6797 where HIST[0] is the most recent instruction. Ignore hazards
6798 between INSN and the first IGNORE instructions in HIST.
6799
6800 If INSN is null, return the worse-case number of nops for any
6801 instruction. */
6802
6803 static int
nops_for_insn(int ignore,const struct mips_cl_insn * hist,const struct mips_cl_insn * insn)6804 nops_for_insn (int ignore, const struct mips_cl_insn *hist,
6805 const struct mips_cl_insn *insn)
6806 {
6807 int i, nops, tmp_nops;
6808
6809 nops = 0;
6810 for (i = ignore; i < MAX_DELAY_NOPS; i++)
6811 {
6812 tmp_nops = insns_between (hist + i, insn) - i;
6813 if (tmp_nops > nops)
6814 nops = tmp_nops;
6815 }
6816
6817 if (mips_fix_vr4130 && !mips_opts.micromips)
6818 {
6819 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
6820 if (tmp_nops > nops)
6821 nops = tmp_nops;
6822 }
6823
6824 if (mips_fix_24k && !mips_opts.micromips)
6825 {
6826 tmp_nops = nops_for_24k (ignore, hist, insn);
6827 if (tmp_nops > nops)
6828 nops = tmp_nops;
6829 }
6830
6831 return nops;
6832 }
6833
6834 /* The variable arguments provide NUM_INSNS extra instructions that
6835 might be added to HIST. Return the largest number of nops that
6836 would be needed after the extended sequence, ignoring hazards
6837 in the first IGNORE instructions. */
6838
6839 static int
nops_for_sequence(int num_insns,int ignore,const struct mips_cl_insn * hist,...)6840 nops_for_sequence (int num_insns, int ignore,
6841 const struct mips_cl_insn *hist, ...)
6842 {
6843 va_list args;
6844 struct mips_cl_insn buffer[MAX_NOPS];
6845 struct mips_cl_insn *cursor;
6846 int nops;
6847
6848 va_start (args, hist);
6849 cursor = buffer + num_insns;
6850 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
6851 while (cursor > buffer)
6852 *--cursor = *va_arg (args, const struct mips_cl_insn *);
6853
6854 nops = nops_for_insn (ignore, buffer, NULL);
6855 va_end (args);
6856 return nops;
6857 }
6858
6859 /* Like nops_for_insn, but if INSN is a branch, take into account the
6860 worst-case delay for the branch target. */
6861
6862 static int
nops_for_insn_or_target(int ignore,const struct mips_cl_insn * hist,const struct mips_cl_insn * insn)6863 nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
6864 const struct mips_cl_insn *insn)
6865 {
6866 int nops, tmp_nops;
6867
6868 nops = nops_for_insn (ignore, hist, insn);
6869 if (delayed_branch_p (insn))
6870 {
6871 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
6872 hist, insn, get_delay_slot_nop (insn));
6873 if (tmp_nops > nops)
6874 nops = tmp_nops;
6875 }
6876 else if (compact_branch_p (insn))
6877 {
6878 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
6879 if (tmp_nops > nops)
6880 nops = tmp_nops;
6881 }
6882 return nops;
6883 }
6884
6885 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6886
6887 static void
fix_loongson2f_nop(struct mips_cl_insn * ip)6888 fix_loongson2f_nop (struct mips_cl_insn * ip)
6889 {
6890 gas_assert (!HAVE_CODE_COMPRESSION);
6891 if (strcmp (ip->insn_mo->name, "nop") == 0)
6892 ip->insn_opcode = LOONGSON2F_NOP_INSN;
6893 }
6894
6895 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6896 jr target pc &= 'hffff_ffff_cfff_ffff. */
6897
6898 static void
fix_loongson2f_jump(struct mips_cl_insn * ip)6899 fix_loongson2f_jump (struct mips_cl_insn * ip)
6900 {
6901 gas_assert (!HAVE_CODE_COMPRESSION);
6902 if (strcmp (ip->insn_mo->name, "j") == 0
6903 || strcmp (ip->insn_mo->name, "jr") == 0
6904 || strcmp (ip->insn_mo->name, "jalr") == 0)
6905 {
6906 int sreg;
6907 expressionS ep;
6908
6909 if (! mips_opts.at)
6910 return;
6911
6912 sreg = EXTRACT_OPERAND (0, RS, *ip);
6913 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
6914 return;
6915
6916 ep.X_op = O_constant;
6917 ep.X_add_number = 0xcfff0000;
6918 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
6919 ep.X_add_number = 0xffff;
6920 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
6921 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
6922 }
6923 }
6924
6925 static void
fix_loongson2f(struct mips_cl_insn * ip)6926 fix_loongson2f (struct mips_cl_insn * ip)
6927 {
6928 if (mips_fix_loongson2f_nop)
6929 fix_loongson2f_nop (ip);
6930
6931 if (mips_fix_loongson2f_jump)
6932 fix_loongson2f_jump (ip);
6933 }
6934
6935 static bool
has_label_name(const char * arr[],size_t len,const char * s)6936 has_label_name (const char *arr[], size_t len ,const char *s)
6937 {
6938 unsigned long i;
6939 for (i = 0; i < len; i++)
6940 {
6941 if (!arr[i])
6942 return false;
6943 if (streq (arr[i], s))
6944 return true;
6945 }
6946 return false;
6947 }
6948
6949 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6950
6951 static void
fix_loongson3_llsc(struct mips_cl_insn * ip)6952 fix_loongson3_llsc (struct mips_cl_insn * ip)
6953 {
6954 gas_assert (!HAVE_CODE_COMPRESSION);
6955
6956 /* If is an local label and the insn is not sync,
6957 look forward that whether an branch between ll/sc jump to here
6958 if so, insert a sync. */
6959 if (seg_info (now_seg)->label_list
6960 && S_IS_LOCAL (seg_info (now_seg)->label_list->label)
6961 && (strcmp (ip->insn_mo->name, "sync") != 0))
6962 {
6963 unsigned long i;
6964 valueT label_value;
6965 const char *label_names[MAX_LABELS_SAME];
6966 const char *label_name;
6967
6968 label_name = S_GET_NAME (seg_info (now_seg)->label_list->label);
6969 label_names[0] = label_name;
6970 struct insn_label_list *llist = seg_info (now_seg)->label_list;
6971 label_value = S_GET_VALUE (llist->label);
6972
6973 for (i = 1; i < MAX_LABELS_SAME; i++)
6974 {
6975 llist = llist->next;
6976 if (!llist)
6977 break;
6978 if (S_GET_VALUE (llist->label) == label_value)
6979 label_names[i] = S_GET_NAME (llist->label);
6980 else
6981 break;
6982 }
6983 for (; i < MAX_LABELS_SAME; i++)
6984 label_names[i] = NULL;
6985
6986 unsigned long lookback = ARRAY_SIZE (history);
6987 for (i = 0; i < lookback; i++)
6988 {
6989 if (streq (history[i].insn_mo->name, "sc")
6990 || streq (history[i].insn_mo->name, "scd"))
6991 {
6992 unsigned long j;
6993
6994 for (j = i + 1; j < lookback; j++)
6995 {
6996 if (streq (history[j].insn_mo->name, "ll")
6997 || streq (history[j].insn_mo->name, "lld"))
6998 break;
6999
7000 if (delayed_branch_p (&history[j]))
7001 {
7002 if (has_label_name (label_names,
7003 MAX_LABELS_SAME,
7004 history[j].target))
7005 {
7006 add_fixed_insn (&sync_insn);
7007 insert_into_history (0, 1, &sync_insn);
7008 i = lookback;
7009 break;
7010 }
7011 }
7012 }
7013 }
7014 }
7015 }
7016 /* If we find a sc, we look forward to look for an branch insn,
7017 and see whether it jump back and out of ll/sc. */
7018 else if (streq (ip->insn_mo->name, "sc") || streq (ip->insn_mo->name, "scd"))
7019 {
7020 unsigned long lookback = ARRAY_SIZE (history) - 1;
7021 unsigned long i;
7022
7023 for (i = 0; i < lookback; i++)
7024 {
7025 if (streq (history[i].insn_mo->name, "ll")
7026 || streq (history[i].insn_mo->name, "lld"))
7027 break;
7028
7029 if (delayed_branch_p (&history[i]))
7030 {
7031 unsigned long j;
7032
7033 for (j = i + 1; j < lookback; j++)
7034 {
7035 if (streq (history[j].insn_mo->name, "ll")
7036 || streq (history[j].insn_mo->name, "lld"))
7037 break;
7038 }
7039
7040 for (; j < lookback; j++)
7041 {
7042 if (history[j].label[0] != '\0'
7043 && streq (history[j].label, history[i].target)
7044 && strcmp (history[j+1].insn_mo->name, "sync") != 0)
7045 {
7046 add_fixed_insn (&sync_insn);
7047 insert_into_history (++j, 1, &sync_insn);
7048 }
7049 }
7050 }
7051 }
7052 }
7053
7054 /* Skip if there is a sync before ll/lld. */
7055 if ((strcmp (ip->insn_mo->name, "ll") == 0
7056 || strcmp (ip->insn_mo->name, "lld") == 0)
7057 && (strcmp (history[0].insn_mo->name, "sync") != 0))
7058 {
7059 add_fixed_insn (&sync_insn);
7060 insert_into_history (0, 1, &sync_insn);
7061 }
7062 }
7063
7064 /* IP is a branch that has a delay slot, and we need to fill it
7065 automatically. Return true if we can do that by swapping IP
7066 with the previous instruction.
7067 ADDRESS_EXPR is an operand of the instruction to be used with
7068 RELOC_TYPE. */
7069
7070 static bool
can_swap_branch_p(struct mips_cl_insn * ip,expressionS * address_expr,bfd_reloc_code_real_type * reloc_type)7071 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
7072 bfd_reloc_code_real_type *reloc_type)
7073 {
7074 unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
7075 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
7076 unsigned int fpr_read, prev_fpr_write;
7077
7078 /* -O2 and above is required for this optimization. */
7079 if (mips_optimize < 2)
7080 return false;
7081
7082 /* If we have seen .set volatile or .set nomove, don't optimize. */
7083 if (mips_opts.nomove)
7084 return false;
7085
7086 /* We can't swap if the previous instruction's position is fixed. */
7087 if (history[0].fixed_p)
7088 return false;
7089
7090 /* If the previous previous insn was in a .set noreorder, we can't
7091 swap. Actually, the MIPS assembler will swap in this situation.
7092 However, gcc configured -with-gnu-as will generate code like
7093
7094 .set noreorder
7095 lw $4,XXX
7096 .set reorder
7097 INSN
7098 bne $4,$0,foo
7099
7100 in which we can not swap the bne and INSN. If gcc is not configured
7101 -with-gnu-as, it does not output the .set pseudo-ops. */
7102 if (history[1].noreorder_p)
7103 return false;
7104
7105 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7106 This means that the previous instruction was a 4-byte one anyhow. */
7107 if (mips_opts.mips16 && history[0].fixp[0])
7108 return false;
7109
7110 if (mips_fix_loongson2f)
7111 fix_loongson2f (ip);
7112 if (mips_trap_zero_jump)
7113 trap_zero_jump (ip);
7114
7115 /* If the branch is itself the target of a branch, we can not swap.
7116 We cheat on this; all we check for is whether there is a label on
7117 this instruction. If there are any branches to anything other than
7118 a label, users must use .set noreorder. */
7119 if (seg_info (now_seg)->label_list)
7120 return false;
7121
7122 /* If the previous instruction is in a variant frag other than this
7123 branch's one, we cannot do the swap. This does not apply to
7124 MIPS16 code, which uses variant frags for different purposes. */
7125 if (!mips_opts.mips16
7126 && history[0].frag
7127 && history[0].frag->fr_type == rs_machine_dependent)
7128 return false;
7129
7130 /* We do not swap with instructions that cannot architecturally
7131 be placed in a branch delay slot, such as SYNC or ERET. We
7132 also refrain from swapping with a trap instruction, since it
7133 complicates trap handlers to have the trap instruction be in
7134 a delay slot. */
7135 prev_pinfo = history[0].insn_mo->pinfo;
7136 if (prev_pinfo & INSN_NO_DELAY_SLOT)
7137 return false;
7138
7139 /* Check for conflicts between the branch and the instructions
7140 before the candidate delay slot. */
7141 if (nops_for_insn (0, history + 1, ip) > 0)
7142 return false;
7143
7144 /* Check for conflicts between the swapped sequence and the
7145 target of the branch. */
7146 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
7147 return false;
7148
7149 /* If the branch reads a register that the previous
7150 instruction sets, we can not swap. */
7151 gpr_read = gpr_read_mask (ip);
7152 prev_gpr_write = gpr_write_mask (&history[0]);
7153 if (gpr_read & prev_gpr_write)
7154 return false;
7155
7156 fpr_read = fpr_read_mask (ip);
7157 prev_fpr_write = fpr_write_mask (&history[0]);
7158 if (fpr_read & prev_fpr_write)
7159 return false;
7160
7161 /* If the branch writes a register that the previous
7162 instruction sets, we can not swap. */
7163 gpr_write = gpr_write_mask (ip);
7164 if (gpr_write & prev_gpr_write)
7165 return false;
7166
7167 /* If the branch writes a register that the previous
7168 instruction reads, we can not swap. */
7169 prev_gpr_read = gpr_read_mask (&history[0]);
7170 if (gpr_write & prev_gpr_read)
7171 return false;
7172
7173 /* If one instruction sets a condition code and the
7174 other one uses a condition code, we can not swap. */
7175 pinfo = ip->insn_mo->pinfo;
7176 if ((pinfo & INSN_READ_COND_CODE)
7177 && (prev_pinfo & INSN_WRITE_COND_CODE))
7178 return false;
7179 if ((pinfo & INSN_WRITE_COND_CODE)
7180 && (prev_pinfo & INSN_READ_COND_CODE))
7181 return false;
7182
7183 /* If the previous instruction uses the PC, we can not swap. */
7184 prev_pinfo2 = history[0].insn_mo->pinfo2;
7185 if (prev_pinfo2 & INSN2_READ_PC)
7186 return false;
7187
7188 /* If the previous instruction has an incorrect size for a fixed
7189 branch delay slot in microMIPS mode, we cannot swap. */
7190 pinfo2 = ip->insn_mo->pinfo2;
7191 if (mips_opts.micromips
7192 && (pinfo2 & INSN2_BRANCH_DELAY_16BIT)
7193 && insn_length (history) != 2)
7194 return false;
7195 if (mips_opts.micromips
7196 && (pinfo2 & INSN2_BRANCH_DELAY_32BIT)
7197 && insn_length (history) != 4)
7198 return false;
7199
7200 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7201 branch delay slot.
7202
7203 The short loop bug under certain conditions causes loops to execute
7204 only once or twice. We must ensure that the assembler never
7205 generates loops that satisfy all of the following conditions:
7206
7207 - a loop consists of less than or equal to six instructions
7208 (including the branch delay slot);
7209 - a loop contains only one conditional branch instruction at the end
7210 of the loop;
7211 - a loop does not contain any other branch or jump instructions;
7212 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7213
7214 We need to do this because of a hardware bug in the R5900 chip. */
7215 if (mips_fix_r5900
7216 /* Check if instruction has a parameter, ignore "j $31". */
7217 && (address_expr != NULL)
7218 /* Parameter must be 16 bit. */
7219 && (*reloc_type == BFD_RELOC_16_PCREL_S2)
7220 /* Branch to same segment. */
7221 && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg)
7222 /* Branch to same code fragment. */
7223 && (symbol_get_frag (address_expr->X_add_symbol) == frag_now)
7224 /* Can only calculate branch offset if value is known. */
7225 && symbol_constant_p (address_expr->X_add_symbol)
7226 /* Check if branch is really conditional. */
7227 && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */
7228 || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */
7229 || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */
7230 {
7231 int distance;
7232 /* Check if loop is shorter than or equal to 6 instructions
7233 including branch and delay slot. */
7234 distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol);
7235 if (distance <= 20)
7236 {
7237 int i;
7238 int rv;
7239
7240 rv = false;
7241 /* When the loop includes branches or jumps,
7242 it is not a short loop. */
7243 for (i = 0; i < (distance / 4); i++)
7244 {
7245 if ((history[i].cleared_p)
7246 || delayed_branch_p (&history[i]))
7247 {
7248 rv = true;
7249 break;
7250 }
7251 }
7252 if (!rv)
7253 {
7254 /* Insert nop after branch to fix short loop. */
7255 return false;
7256 }
7257 }
7258 }
7259
7260 return true;
7261 }
7262
7263 /* Fix jump through register issue on loongson2f processor for kernel code:
7264 force a BTB clear before the jump to prevent it from being incorrectly
7265 prefetched by the branch prediction engine. */
7266
7267 static void
macro_build_jrpatch(expressionS * ep,unsigned int sreg)7268 macro_build_jrpatch (expressionS *ep, unsigned int sreg)
7269 {
7270 if (!mips_fix_loongson2f_btb)
7271 return;
7272
7273 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == AT)
7274 return;
7275
7276 if (!mips_opts.at)
7277 {
7278 as_warn (_("unable to apply loongson2f BTB workaround when .set noat"));
7279 return;
7280 }
7281
7282 /* li $at, COP_0_BTB_CLEAR | COP_0_RAS_DISABLE */
7283 ep->X_op = O_constant;
7284 ep->X_add_number = 3;
7285 macro_build (ep, "ori", "t,r,i", AT, ZERO, BFD_RELOC_LO16);
7286
7287 /* dmtc0 $at, COP_0_DIAG */
7288 macro_build (NULL, "dmtc0", "t,G", AT, 22);
7289
7290 /* Hide these two instructions to avoid getting a ``macro expanded into
7291 multiple instructions'' warning. */
7292 if (mips_relax.sequence != 2) {
7293 mips_macro_warning.sizes[0] -= 2 * 4;
7294 mips_macro_warning.insns[0] -= 2;
7295 }
7296 if (mips_relax.sequence != 1) {
7297 mips_macro_warning.sizes[1] -= 2 * 4;
7298 mips_macro_warning.insns[1] -= 2;
7299 }
7300 }
7301
7302 /* Decide how we should add IP to the instruction stream.
7303 ADDRESS_EXPR is an operand of the instruction to be used with
7304 RELOC_TYPE. */
7305
7306 static enum append_method
get_append_method(struct mips_cl_insn * ip,expressionS * address_expr,bfd_reloc_code_real_type * reloc_type)7307 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
7308 bfd_reloc_code_real_type *reloc_type)
7309 {
7310 /* The relaxed version of a macro sequence must be inherently
7311 hazard-free. */
7312 if (mips_relax.sequence == 2)
7313 return APPEND_ADD;
7314
7315 /* We must not dabble with instructions in a ".set noreorder" block. */
7316 if (mips_opts.noreorder)
7317 return APPEND_ADD;
7318
7319 /* Otherwise, it's our responsibility to fill branch delay slots. */
7320 if (delayed_branch_p (ip))
7321 {
7322 if (!branch_likely_p (ip)
7323 && can_swap_branch_p (ip, address_expr, reloc_type))
7324 return APPEND_SWAP;
7325
7326 if (mips_opts.mips16
7327 && ISA_SUPPORTS_MIPS16E
7328 && gpr_read_mask (ip) != 0)
7329 return APPEND_ADD_COMPACT;
7330
7331 if (mips_opts.micromips
7332 && ((ip->insn_opcode & 0xffe0) == 0x4580
7333 || (!forced_insn_length
7334 && ((ip->insn_opcode & 0xfc00) == 0xcc00
7335 || (ip->insn_opcode & 0xdc00) == 0x8c00))
7336 || (ip->insn_opcode & 0xdfe00000) == 0x94000000
7337 || (ip->insn_opcode & 0xdc1f0000) == 0x94000000))
7338 return APPEND_ADD_COMPACT;
7339
7340 return APPEND_ADD_WITH_NOP;
7341 }
7342
7343 return APPEND_ADD;
7344 }
7345
7346 /* IP is an instruction whose opcode we have just changed, END points
7347 to the end of the opcode table processed. Point IP->insn_mo to the
7348 new opcode's definition. */
7349
7350 static void
find_altered_opcode(struct mips_cl_insn * ip,const struct mips_opcode * end)7351 find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
7352 {
7353 const struct mips_opcode *mo;
7354
7355 for (mo = ip->insn_mo; mo < end; mo++)
7356 if (mo->pinfo != INSN_MACRO
7357 && (ip->insn_opcode & mo->mask) == mo->match)
7358 {
7359 ip->insn_mo = mo;
7360 return;
7361 }
7362 abort ();
7363 }
7364
7365 /* IP is a MIPS16 instruction whose opcode we have just changed.
7366 Point IP->insn_mo to the new opcode's definition. */
7367
7368 static void
find_altered_mips16_opcode(struct mips_cl_insn * ip)7369 find_altered_mips16_opcode (struct mips_cl_insn *ip)
7370 {
7371 find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]);
7372 }
7373
7374 /* IP is a microMIPS instruction whose opcode we have just changed.
7375 Point IP->insn_mo to the new opcode's definition. */
7376
7377 static void
find_altered_micromips_opcode(struct mips_cl_insn * ip)7378 find_altered_micromips_opcode (struct mips_cl_insn *ip)
7379 {
7380 find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]);
7381 }
7382
7383 /* For microMIPS macros, we need to generate a local number label
7384 as the target of branches. */
7385 #define MICROMIPS_LABEL_CHAR '\037'
7386 static unsigned long micromips_target_label;
7387 static char micromips_target_name[32];
7388
7389 static char *
micromips_label_name(void)7390 micromips_label_name (void)
7391 {
7392 char *p = micromips_target_name;
7393 char symbol_name_temporary[24];
7394 unsigned long l;
7395 int i;
7396
7397 if (*p)
7398 return p;
7399
7400 i = 0;
7401 l = micromips_target_label;
7402 #ifdef LOCAL_LABEL_PREFIX
7403 *p++ = LOCAL_LABEL_PREFIX;
7404 #endif
7405 *p++ = 'L';
7406 *p++ = MICROMIPS_LABEL_CHAR;
7407 do
7408 {
7409 symbol_name_temporary[i++] = l % 10 + '0';
7410 l /= 10;
7411 }
7412 while (l != 0);
7413 while (i > 0)
7414 *p++ = symbol_name_temporary[--i];
7415 *p = '\0';
7416
7417 return micromips_target_name;
7418 }
7419
7420 static void
micromips_label_expr(expressionS * label_expr)7421 micromips_label_expr (expressionS *label_expr)
7422 {
7423 label_expr->X_op = O_symbol;
7424 label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ());
7425 label_expr->X_add_number = 0;
7426 }
7427
7428 static void
micromips_label_inc(void)7429 micromips_label_inc (void)
7430 {
7431 micromips_target_label++;
7432 *micromips_target_name = '\0';
7433 }
7434
7435 static void
micromips_add_label(void)7436 micromips_add_label (void)
7437 {
7438 symbolS *s;
7439
7440 s = colon (micromips_label_name ());
7441 micromips_label_inc ();
7442 S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s)));
7443 }
7444
7445 /* If assembling microMIPS code, then return the microMIPS reloc
7446 corresponding to the requested one if any. Otherwise return
7447 the reloc unchanged. */
7448
7449 static bfd_reloc_code_real_type
micromips_map_reloc(bfd_reloc_code_real_type reloc)7450 micromips_map_reloc (bfd_reloc_code_real_type reloc)
7451 {
7452 static const bfd_reloc_code_real_type relocs[][2] =
7453 {
7454 /* Keep sorted incrementally by the left-hand key. */
7455 { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 },
7456 { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 },
7457 { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP },
7458 { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
7459 { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
7460 { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
7461 { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
7462 { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
7463 { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
7464 { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
7465 { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 },
7466 { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 },
7467 { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 },
7468 { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB },
7469 { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE },
7470 { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST },
7471 { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP },
7472 { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST },
7473 { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER },
7474 { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP },
7475 { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD },
7476 { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM },
7477 { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 },
7478 { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 },
7479 { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL },
7480 { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 },
7481 { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 }
7482 };
7483 bfd_reloc_code_real_type r;
7484 size_t i;
7485
7486 if (!mips_opts.micromips)
7487 return reloc;
7488 for (i = 0; i < ARRAY_SIZE (relocs); i++)
7489 {
7490 r = relocs[i][0];
7491 if (r > reloc)
7492 return reloc;
7493 if (r == reloc)
7494 return relocs[i][1];
7495 }
7496 return reloc;
7497 }
7498
7499 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7500 Return true on success, storing the resolved value in RESULT. */
7501
7502 static bool
calculate_reloc(bfd_reloc_code_real_type reloc,offsetT operand,offsetT * result)7503 calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
7504 offsetT *result)
7505 {
7506 switch (reloc)
7507 {
7508 case BFD_RELOC_MIPS_HIGHEST:
7509 case BFD_RELOC_MICROMIPS_HIGHEST:
7510 *result = ((operand + 0x800080008000ull) >> 48) & 0xffff;
7511 return true;
7512
7513 case BFD_RELOC_MIPS_HIGHER:
7514 case BFD_RELOC_MICROMIPS_HIGHER:
7515 *result = ((operand + 0x80008000ull) >> 32) & 0xffff;
7516 return true;
7517
7518 case BFD_RELOC_HI16_S:
7519 case BFD_RELOC_HI16_S_PCREL:
7520 case BFD_RELOC_MICROMIPS_HI16_S:
7521 case BFD_RELOC_MIPS16_HI16_S:
7522 *result = ((operand + 0x8000) >> 16) & 0xffff;
7523 return true;
7524
7525 case BFD_RELOC_HI16:
7526 case BFD_RELOC_MICROMIPS_HI16:
7527 case BFD_RELOC_MIPS16_HI16:
7528 *result = (operand >> 16) & 0xffff;
7529 return true;
7530
7531 case BFD_RELOC_LO16:
7532 case BFD_RELOC_LO16_PCREL:
7533 case BFD_RELOC_MICROMIPS_LO16:
7534 case BFD_RELOC_MIPS16_LO16:
7535 *result = operand & 0xffff;
7536 return true;
7537
7538 case BFD_RELOC_UNUSED:
7539 *result = operand;
7540 return true;
7541
7542 default:
7543 return false;
7544 }
7545 }
7546
7547 /* Output an instruction. IP is the instruction information.
7548 ADDRESS_EXPR is an operand of the instruction to be used with
7549 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7550 a macro expansion. */
7551
7552 static void
append_insn(struct mips_cl_insn * ip,expressionS * address_expr,bfd_reloc_code_real_type * reloc_type,bool expansionp)7553 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
7554 bfd_reloc_code_real_type *reloc_type, bool expansionp)
7555 {
7556 unsigned long prev_pinfo2, pinfo;
7557 bool relaxed_branch = false;
7558 enum append_method method;
7559 bool relax32;
7560 int branch_disp;
7561
7562 if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION)
7563 fix_loongson2f (ip);
7564
7565 ip->target[0] = '\0';
7566 if (offset_expr.X_op == O_symbol)
7567 strncpy (ip->target, S_GET_NAME (offset_expr.X_add_symbol), 15);
7568 ip->label[0] = '\0';
7569 if (seg_info (now_seg)->label_list)
7570 strncpy (ip->label, S_GET_NAME (seg_info (now_seg)->label_list->label), 15);
7571 if (mips_fix_loongson3_llsc && !HAVE_CODE_COMPRESSION)
7572 fix_loongson3_llsc (ip);
7573
7574 file_ase_mips16 |= mips_opts.mips16;
7575 file_ase_micromips |= mips_opts.micromips;
7576
7577 prev_pinfo2 = history[0].insn_mo->pinfo2;
7578 pinfo = ip->insn_mo->pinfo;
7579
7580 /* Don't raise alarm about `nods' frags as they'll fill in the right
7581 kind of nop in relaxation if required. */
7582 if (mips_opts.micromips
7583 && !expansionp
7584 && !(history[0].frag
7585 && history[0].frag->fr_type == rs_machine_dependent
7586 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
7587 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
7588 && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0
7589 && micromips_insn_length (ip->insn_mo) != 2)
7590 || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
7591 && micromips_insn_length (ip->insn_mo) != 4)))
7592 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7593 (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
7594
7595 if (address_expr == NULL)
7596 ip->complete_p = 1;
7597 else if (reloc_type[0] <= BFD_RELOC_UNUSED
7598 && reloc_type[1] == BFD_RELOC_UNUSED
7599 && reloc_type[2] == BFD_RELOC_UNUSED
7600 && address_expr->X_op == O_constant)
7601 {
7602 switch (*reloc_type)
7603 {
7604 case BFD_RELOC_MIPS_JMP:
7605 {
7606 int shift;
7607
7608 /* Shift is 2, unusually, for microMIPS JALX. */
7609 shift = (mips_opts.micromips
7610 && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2;
7611 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7612 as_bad (_("jump to misaligned address (0x%lx)"),
7613 (unsigned long) address_expr->X_add_number);
7614 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7615 & 0x3ffffff);
7616 ip->complete_p = 1;
7617 }
7618 break;
7619
7620 case BFD_RELOC_MIPS16_JMP:
7621 if ((address_expr->X_add_number & 3) != 0)
7622 as_bad (_("jump to misaligned address (0x%lx)"),
7623 (unsigned long) address_expr->X_add_number);
7624 ip->insn_opcode |=
7625 (((address_expr->X_add_number & 0x7c0000) << 3)
7626 | ((address_expr->X_add_number & 0xf800000) >> 7)
7627 | ((address_expr->X_add_number & 0x3fffc) >> 2));
7628 ip->complete_p = 1;
7629 break;
7630
7631 case BFD_RELOC_16_PCREL_S2:
7632 {
7633 int shift;
7634
7635 shift = mips_opts.micromips ? 1 : 2;
7636 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7637 as_bad (_("branch to misaligned address (0x%lx)"),
7638 (unsigned long) address_expr->X_add_number);
7639 if (!mips_relax_branch)
7640 {
7641 if ((address_expr->X_add_number + (1 << (shift + 15)))
7642 & ~((1 << (shift + 16)) - 1))
7643 as_bad (_("branch address range overflow (0x%lx)"),
7644 (unsigned long) address_expr->X_add_number);
7645 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7646 & 0xffff);
7647 }
7648 }
7649 break;
7650
7651 case BFD_RELOC_MIPS_21_PCREL_S2:
7652 {
7653 int shift;
7654
7655 shift = 2;
7656 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7657 as_bad (_("branch to misaligned address (0x%lx)"),
7658 (unsigned long) address_expr->X_add_number);
7659 if ((address_expr->X_add_number + (1 << (shift + 20)))
7660 & ~((1 << (shift + 21)) - 1))
7661 as_bad (_("branch address range overflow (0x%lx)"),
7662 (unsigned long) address_expr->X_add_number);
7663 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7664 & 0x1fffff);
7665 }
7666 break;
7667
7668 case BFD_RELOC_MIPS_26_PCREL_S2:
7669 {
7670 int shift;
7671
7672 shift = 2;
7673 if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
7674 as_bad (_("branch to misaligned address (0x%lx)"),
7675 (unsigned long) address_expr->X_add_number);
7676 if ((address_expr->X_add_number + (1 << (shift + 25)))
7677 & ~((1 << (shift + 26)) - 1))
7678 as_bad (_("branch address range overflow (0x%lx)"),
7679 (unsigned long) address_expr->X_add_number);
7680 ip->insn_opcode |= ((address_expr->X_add_number >> shift)
7681 & 0x3ffffff);
7682 }
7683 break;
7684
7685 default:
7686 {
7687 offsetT value;
7688
7689 if (calculate_reloc (*reloc_type, address_expr->X_add_number,
7690 &value))
7691 {
7692 ip->insn_opcode |= value & 0xffff;
7693 ip->complete_p = 1;
7694 }
7695 }
7696 break;
7697 }
7698 }
7699
7700 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
7701 {
7702 /* There are a lot of optimizations we could do that we don't.
7703 In particular, we do not, in general, reorder instructions.
7704 If you use gcc with optimization, it will reorder
7705 instructions and generally do much more optimization then we
7706 do here; repeating all that work in the assembler would only
7707 benefit hand written assembly code, and does not seem worth
7708 it. */
7709 int nops = (mips_optimize == 0
7710 ? nops_for_insn (0, history, NULL)
7711 : nops_for_insn_or_target (0, history, ip));
7712 if (nops > 0)
7713 {
7714 fragS *old_frag;
7715 unsigned long old_frag_offset;
7716 int i;
7717
7718 old_frag = frag_now;
7719 old_frag_offset = frag_now_fix ();
7720
7721 for (i = 0; i < nops; i++)
7722 add_fixed_insn (NOP_INSN);
7723 insert_into_history (0, nops, NOP_INSN);
7724
7725 if (listing)
7726 {
7727 listing_prev_line ();
7728 /* We may be at the start of a variant frag. In case we
7729 are, make sure there is enough space for the frag
7730 after the frags created by listing_prev_line. The
7731 argument to frag_grow here must be at least as large
7732 as the argument to all other calls to frag_grow in
7733 this file. We don't have to worry about being in the
7734 middle of a variant frag, because the variants insert
7735 all needed nop instructions themselves. */
7736 frag_grow (40);
7737 }
7738
7739 mips_move_text_labels ();
7740
7741 #ifndef NO_ECOFF_DEBUGGING
7742 if (ECOFF_DEBUGGING)
7743 ecoff_fix_loc (old_frag, old_frag_offset);
7744 #endif
7745 }
7746 }
7747 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
7748 {
7749 int nops;
7750
7751 /* Work out how many nops in prev_nop_frag are needed by IP,
7752 ignoring hazards generated by the first prev_nop_frag_since
7753 instructions. */
7754 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
7755 gas_assert (nops <= prev_nop_frag_holds);
7756
7757 /* Enforce NOPS as a minimum. */
7758 if (nops > prev_nop_frag_required)
7759 prev_nop_frag_required = nops;
7760
7761 if (prev_nop_frag_holds == prev_nop_frag_required)
7762 {
7763 /* Settle for the current number of nops. Update the history
7764 accordingly (for the benefit of any future .set reorder code). */
7765 prev_nop_frag = NULL;
7766 insert_into_history (prev_nop_frag_since,
7767 prev_nop_frag_holds, NOP_INSN);
7768 }
7769 else
7770 {
7771 /* Allow this instruction to replace one of the nops that was
7772 tentatively added to prev_nop_frag. */
7773 prev_nop_frag->fr_fix -= NOP_INSN_SIZE;
7774 prev_nop_frag_holds--;
7775 prev_nop_frag_since++;
7776 }
7777 }
7778
7779 method = get_append_method (ip, address_expr, reloc_type);
7780 branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
7781
7782 dwarf2_emit_insn (0);
7783 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7784 so "move" the instruction address accordingly.
7785
7786 Also, it doesn't seem appropriate for the assembler to reorder .loc
7787 entries. If this instruction is a branch that we are going to swap
7788 with the previous instruction, the two instructions should be
7789 treated as a unit, and the debug information for both instructions
7790 should refer to the start of the branch sequence. Using the
7791 current position is certainly wrong when swapping a 32-bit branch
7792 and a 16-bit delay slot, since the current position would then be
7793 in the middle of a branch. */
7794 dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
7795
7796 relax32 = (mips_relax_branch
7797 /* Don't try branch relaxation within .set nomacro, or within
7798 .set noat if we use $at for PIC computations. If it turns
7799 out that the branch was out-of-range, we'll get an error. */
7800 && !mips_opts.warn_about_macros
7801 && (mips_opts.at || mips_pic == NO_PIC)
7802 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7803 as they have no complementing branches. */
7804 && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
7805
7806 if (!HAVE_CODE_COMPRESSION
7807 && address_expr
7808 && relax32
7809 && *reloc_type == BFD_RELOC_16_PCREL_S2
7810 && delayed_branch_p (ip))
7811 {
7812 relaxed_branch = true;
7813 add_relaxed_insn (ip, (relaxed_branch_length
7814 (NULL, NULL,
7815 uncond_branch_p (ip) ? -1
7816 : branch_likely_p (ip) ? 1
7817 : 0)), 4,
7818 RELAX_BRANCH_ENCODE
7819 (AT, mips_pic != NO_PIC,
7820 uncond_branch_p (ip),
7821 branch_likely_p (ip),
7822 pinfo & INSN_WRITE_GPR_31,
7823 0),
7824 address_expr->X_add_symbol,
7825 address_expr->X_add_number);
7826 *reloc_type = BFD_RELOC_UNUSED;
7827 }
7828 else if (mips_opts.micromips
7829 && address_expr
7830 && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
7831 || *reloc_type > BFD_RELOC_UNUSED)
7832 && (delayed_branch_p (ip) || compact_branch_p (ip))
7833 /* Don't try branch relaxation when users specify
7834 16-bit/32-bit instructions. */
7835 && !forced_insn_length)
7836 {
7837 bool relax16 = (method != APPEND_ADD_COMPACT
7838 && *reloc_type > BFD_RELOC_UNUSED);
7839 int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0;
7840 int uncond = uncond_branch_p (ip) ? -1 : 0;
7841 int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT;
7842 int nods = method == APPEND_ADD_WITH_NOP;
7843 int al = pinfo & INSN_WRITE_GPR_31;
7844 int length32 = nods ? 8 : 4;
7845
7846 gas_assert (address_expr != NULL);
7847 gas_assert (!mips_relax.sequence);
7848
7849 relaxed_branch = true;
7850 if (nods)
7851 method = APPEND_ADD;
7852 if (relax32)
7853 length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond);
7854 add_relaxed_insn (ip, length32, relax16 ? 2 : 4,
7855 RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32,
7856 mips_pic != NO_PIC,
7857 uncond, compact, al, nods,
7858 relax32, 0, 0),
7859 address_expr->X_add_symbol,
7860 address_expr->X_add_number);
7861 *reloc_type = BFD_RELOC_UNUSED;
7862 }
7863 else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED)
7864 {
7865 bool require_unextended;
7866 bool require_extended;
7867 symbolS *symbol;
7868 offsetT offset;
7869
7870 if (forced_insn_length != 0)
7871 {
7872 require_unextended = forced_insn_length == 2;
7873 require_extended = forced_insn_length == 4;
7874 }
7875 else
7876 {
7877 require_unextended = (mips_opts.noautoextend
7878 && !mips_opcode_32bit_p (ip->insn_mo));
7879 require_extended = 0;
7880 }
7881
7882 /* We need to set up a variant frag. */
7883 gas_assert (address_expr != NULL);
7884 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7885 symbol created by `make_expr_symbol' may not get a necessary
7886 external relocation produced. */
7887 if (address_expr->X_op == O_symbol)
7888 {
7889 symbol = address_expr->X_add_symbol;
7890 offset = address_expr->X_add_number;
7891 }
7892 else
7893 {
7894 symbol = make_expr_symbol (address_expr);
7895 symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP);
7896 offset = 0;
7897 }
7898 add_relaxed_insn (ip, 12, 0,
7899 RELAX_MIPS16_ENCODE
7900 (*reloc_type - BFD_RELOC_UNUSED,
7901 mips_opts.ase & ASE_MIPS16E2,
7902 mips_pic != NO_PIC,
7903 HAVE_32BIT_SYMBOLS,
7904 mips_opts.warn_about_macros,
7905 require_unextended, require_extended,
7906 delayed_branch_p (&history[0]),
7907 history[0].mips16_absolute_jump_p),
7908 symbol, offset);
7909 }
7910 else if (mips_opts.mips16 && insn_length (ip) == 2)
7911 {
7912 if (!delayed_branch_p (ip))
7913 /* Make sure there is enough room to swap this instruction with
7914 a following jump instruction. */
7915 frag_grow (6);
7916 add_fixed_insn (ip);
7917 }
7918 else
7919 {
7920 if (mips_opts.mips16
7921 && mips_opts.noreorder
7922 && delayed_branch_p (&history[0]))
7923 as_warn (_("extended instruction in delay slot"));
7924
7925 if (mips_relax.sequence)
7926 {
7927 /* If we've reached the end of this frag, turn it into a variant
7928 frag and record the information for the instructions we've
7929 written so far. */
7930 if (frag_room () < 4)
7931 relax_close_frag ();
7932 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip);
7933 }
7934
7935 if (mips_relax.sequence != 2)
7936 {
7937 if (mips_macro_warning.first_insn_sizes[0] == 0)
7938 mips_macro_warning.first_insn_sizes[0] = insn_length (ip);
7939 mips_macro_warning.sizes[0] += insn_length (ip);
7940 mips_macro_warning.insns[0]++;
7941 }
7942 if (mips_relax.sequence != 1)
7943 {
7944 if (mips_macro_warning.first_insn_sizes[1] == 0)
7945 mips_macro_warning.first_insn_sizes[1] = insn_length (ip);
7946 mips_macro_warning.sizes[1] += insn_length (ip);
7947 mips_macro_warning.insns[1]++;
7948 }
7949
7950 if (mips_opts.mips16)
7951 {
7952 ip->fixed_p = 1;
7953 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
7954 }
7955 add_fixed_insn (ip);
7956 }
7957
7958 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
7959 {
7960 bfd_reloc_code_real_type final_type[3];
7961 reloc_howto_type *howto0;
7962 reloc_howto_type *howto;
7963 int i;
7964
7965 /* Perform any necessary conversion to microMIPS relocations
7966 and find out how many relocations there actually are. */
7967 for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++)
7968 final_type[i] = micromips_map_reloc (reloc_type[i]);
7969
7970 /* In a compound relocation, it is the final (outermost)
7971 operator that determines the relocated field. */
7972 howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]);
7973 if (!howto)
7974 abort ();
7975
7976 if (i > 1)
7977 howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]);
7978 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
7979 bfd_get_reloc_size (howto),
7980 address_expr,
7981 howto0 && howto0->pc_relative,
7982 final_type[0]);
7983 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7984 ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC;
7985
7986 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7987 if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy)
7988 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
7989
7990 /* These relocations can have an addend that won't fit in
7991 4 octets for 64bit assembly. */
7992 if (GPR_SIZE == 64
7993 && ! howto->partial_inplace
7994 && (reloc_type[0] == BFD_RELOC_16
7995 || reloc_type[0] == BFD_RELOC_32
7996 || reloc_type[0] == BFD_RELOC_MIPS_JMP
7997 || reloc_type[0] == BFD_RELOC_GPREL16
7998 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
7999 || reloc_type[0] == BFD_RELOC_GPREL32
8000 || reloc_type[0] == BFD_RELOC_64
8001 || reloc_type[0] == BFD_RELOC_CTOR
8002 || reloc_type[0] == BFD_RELOC_MIPS_SUB
8003 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
8004 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
8005 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
8006 || reloc_type[0] == BFD_RELOC_MIPS_16
8007 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
8008 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
8009 || hi16_reloc_p (reloc_type[0])
8010 || lo16_reloc_p (reloc_type[0])))
8011 ip->fixp[0]->fx_no_overflow = 1;
8012
8013 /* These relocations can have an addend that won't fit in 2 octets. */
8014 if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
8015 || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1)
8016 ip->fixp[0]->fx_no_overflow = 1;
8017
8018 if (mips_relax.sequence)
8019 {
8020 if (mips_relax.first_fixup == 0)
8021 mips_relax.first_fixup = ip->fixp[0];
8022 }
8023 else if (reloc_needs_lo_p (*reloc_type))
8024 {
8025 struct mips_hi_fixup *hi_fixup;
8026
8027 /* Reuse the last entry if it already has a matching %lo. */
8028 hi_fixup = mips_hi_fixup_list;
8029 if (hi_fixup == 0
8030 || !fixup_has_matching_lo_p (hi_fixup->fixp))
8031 {
8032 hi_fixup = XNEW (struct mips_hi_fixup);
8033 hi_fixup->next = mips_hi_fixup_list;
8034 mips_hi_fixup_list = hi_fixup;
8035 }
8036 hi_fixup->fixp = ip->fixp[0];
8037 hi_fixup->seg = now_seg;
8038 }
8039
8040 /* Add fixups for the second and third relocations, if given.
8041 Note that the ABI allows the second relocation to be
8042 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
8043 moment we only use RSS_UNDEF, but we could add support
8044 for the others if it ever becomes necessary. */
8045 for (i = 1; i < 3; i++)
8046 if (reloc_type[i] != BFD_RELOC_UNUSED)
8047 {
8048 ip->fixp[i] = fix_new (ip->frag, ip->where,
8049 ip->fixp[0]->fx_size, NULL, 0,
8050 false, final_type[i]);
8051
8052 /* Use fx_tcbit to mark compound relocs. */
8053 ip->fixp[0]->fx_tcbit = 1;
8054 ip->fixp[i]->fx_tcbit = 1;
8055 }
8056 }
8057
8058 /* Update the register mask information. */
8059 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
8060 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
8061
8062 switch (method)
8063 {
8064 case APPEND_ADD:
8065 insert_into_history (0, 1, ip);
8066 break;
8067
8068 case APPEND_ADD_WITH_NOP:
8069 {
8070 struct mips_cl_insn *nop;
8071
8072 insert_into_history (0, 1, ip);
8073 nop = get_delay_slot_nop (ip);
8074 add_fixed_insn (nop);
8075 insert_into_history (0, 1, nop);
8076 if (mips_relax.sequence)
8077 mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop);
8078 }
8079 break;
8080
8081 case APPEND_ADD_COMPACT:
8082 /* Convert MIPS16 jr/jalr into a "compact" jump. */
8083 if (mips_opts.mips16)
8084 {
8085 ip->insn_opcode |= 0x0080;
8086 find_altered_mips16_opcode (ip);
8087 }
8088 /* Convert microMIPS instructions. */
8089 else if (mips_opts.micromips)
8090 {
8091 /* jr16->jrc */
8092 if ((ip->insn_opcode & 0xffe0) == 0x4580)
8093 ip->insn_opcode |= 0x0020;
8094 /* b16->bc */
8095 else if ((ip->insn_opcode & 0xfc00) == 0xcc00)
8096 ip->insn_opcode = 0x40e00000;
8097 /* beqz16->beqzc, bnez16->bnezc */
8098 else if ((ip->insn_opcode & 0xdc00) == 0x8c00)
8099 {
8100 unsigned long regno;
8101
8102 regno = ip->insn_opcode >> MICROMIPSOP_SH_MD;
8103 regno &= MICROMIPSOP_MASK_MD;
8104 regno = micromips_to_32_reg_d_map[regno];
8105 ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000)
8106 | (regno << MICROMIPSOP_SH_RS)
8107 | 0x40a00000) ^ 0x00400000;
8108 }
8109 /* beqz->beqzc, bnez->bnezc */
8110 else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000)
8111 ip->insn_opcode = ((ip->insn_opcode & 0x001f0000)
8112 | ((ip->insn_opcode >> 7) & 0x00400000)
8113 | 0x40a00000) ^ 0x00400000;
8114 /* beq $0->beqzc, bne $0->bnezc */
8115 else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000)
8116 ip->insn_opcode = (((ip->insn_opcode >>
8117 (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS))
8118 & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS))
8119 | ((ip->insn_opcode >> 7) & 0x00400000)
8120 | 0x40a00000) ^ 0x00400000;
8121 else
8122 abort ();
8123 find_altered_micromips_opcode (ip);
8124 }
8125 else
8126 abort ();
8127 install_insn (ip);
8128 insert_into_history (0, 1, ip);
8129 break;
8130
8131 case APPEND_SWAP:
8132 {
8133 struct mips_cl_insn delay = history[0];
8134
8135 if (relaxed_branch || delay.frag != ip->frag)
8136 {
8137 /* Add the delay slot instruction to the end of the
8138 current frag and shrink the fixed part of the
8139 original frag. If the branch occupies the tail of
8140 the latter, move it backwards to cover the gap. */
8141 delay.frag->fr_fix -= branch_disp;
8142 if (delay.frag == ip->frag)
8143 move_insn (ip, ip->frag, ip->where - branch_disp);
8144 add_fixed_insn (&delay);
8145 }
8146 else
8147 {
8148 /* If this is not a relaxed branch and we are in the
8149 same frag, then just swap the instructions. */
8150 move_insn (ip, delay.frag, delay.where);
8151 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
8152 }
8153 history[0] = *ip;
8154 delay.fixed_p = 1;
8155 insert_into_history (0, 1, &delay);
8156 }
8157 break;
8158 }
8159
8160 /* If we have just completed an unconditional branch, clear the history. */
8161 if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1]))
8162 || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0])))
8163 {
8164 unsigned int i;
8165
8166 mips_no_prev_insn ();
8167
8168 for (i = 0; i < ARRAY_SIZE (history); i++)
8169 history[i].cleared_p = 1;
8170 }
8171
8172 /* We need to emit a label at the end of branch-likely macros. */
8173 if (emit_branch_likely_macro)
8174 {
8175 emit_branch_likely_macro = false;
8176 micromips_add_label ();
8177 }
8178
8179 /* We just output an insn, so the next one doesn't have a label. */
8180 mips_clear_insn_labels ();
8181 }
8182
8183 /* Forget that there was any previous instruction or label.
8184 When BRANCH is true, the branch history is also flushed. */
8185
8186 static void
mips_no_prev_insn(void)8187 mips_no_prev_insn (void)
8188 {
8189 prev_nop_frag = NULL;
8190 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
8191 mips_clear_insn_labels ();
8192 }
8193
8194 /* This function must be called before we emit something other than
8195 instructions. It is like mips_no_prev_insn except that it inserts
8196 any NOPS that might be needed by previous instructions. */
8197
8198 void
mips_emit_delays(void)8199 mips_emit_delays (void)
8200 {
8201 if (! mips_opts.noreorder)
8202 {
8203 int nops = nops_for_insn (0, history, NULL);
8204 if (nops > 0)
8205 {
8206 while (nops-- > 0)
8207 add_fixed_insn (NOP_INSN);
8208 mips_move_text_labels ();
8209 }
8210 }
8211 mips_no_prev_insn ();
8212 }
8213
8214 /* Start a (possibly nested) noreorder block. */
8215
8216 static void
start_noreorder(void)8217 start_noreorder (void)
8218 {
8219 if (mips_opts.noreorder == 0)
8220 {
8221 unsigned int i;
8222 int nops;
8223
8224 /* None of the instructions before the .set noreorder can be moved. */
8225 for (i = 0; i < ARRAY_SIZE (history); i++)
8226 history[i].fixed_p = 1;
8227
8228 /* Insert any nops that might be needed between the .set noreorder
8229 block and the previous instructions. We will later remove any
8230 nops that turn out not to be needed. */
8231 nops = nops_for_insn (0, history, NULL);
8232 if (nops > 0)
8233 {
8234 if (mips_optimize != 0)
8235 {
8236 /* Record the frag which holds the nop instructions, so
8237 that we can remove them if we don't need them. */
8238 frag_grow (nops * NOP_INSN_SIZE);
8239 prev_nop_frag = frag_now;
8240 prev_nop_frag_holds = nops;
8241 prev_nop_frag_required = 0;
8242 prev_nop_frag_since = 0;
8243 }
8244
8245 for (; nops > 0; --nops)
8246 add_fixed_insn (NOP_INSN);
8247
8248 /* Move on to a new frag, so that it is safe to simply
8249 decrease the size of prev_nop_frag. */
8250 frag_wane (frag_now);
8251 frag_new (0);
8252 mips_move_text_labels ();
8253 }
8254 mips_mark_labels ();
8255 mips_clear_insn_labels ();
8256 }
8257 mips_opts.noreorder++;
8258 mips_any_noreorder = 1;
8259 }
8260
8261 /* End a nested noreorder block. */
8262
8263 static void
end_noreorder(void)8264 end_noreorder (void)
8265 {
8266 mips_opts.noreorder--;
8267 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
8268 {
8269 /* Commit to inserting prev_nop_frag_required nops and go back to
8270 handling nop insertion the .set reorder way. */
8271 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
8272 * NOP_INSN_SIZE);
8273 insert_into_history (prev_nop_frag_since,
8274 prev_nop_frag_required, NOP_INSN);
8275 prev_nop_frag = NULL;
8276 }
8277 }
8278
8279 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8280 higher bits unset. */
8281
8282 static void
normalize_constant_expr(expressionS * ex)8283 normalize_constant_expr (expressionS *ex)
8284 {
8285 if (ex->X_op == O_constant
8286 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
8287 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
8288 - 0x80000000);
8289 }
8290
8291 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8292 all higher bits unset. */
8293
8294 static void
normalize_address_expr(expressionS * ex)8295 normalize_address_expr (expressionS *ex)
8296 {
8297 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
8298 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
8299 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
8300 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
8301 - 0x80000000);
8302 }
8303
8304 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8305 Return true if the match was successful.
8306
8307 OPCODE_EXTRA is a value that should be ORed into the opcode
8308 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8309 there are more alternatives after OPCODE and SOFT_MATCH is
8310 as for mips_arg_info. */
8311
8312 static bool
match_insn(struct mips_cl_insn * insn,const struct mips_opcode * opcode,struct mips_operand_token * tokens,unsigned int opcode_extra,bool lax_match,bool complete_p)8313 match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8314 struct mips_operand_token *tokens, unsigned int opcode_extra,
8315 bool lax_match, bool complete_p)
8316 {
8317 const char *args;
8318 struct mips_arg_info arg;
8319 const struct mips_operand *operand;
8320 char c;
8321
8322 imm_expr.X_op = O_absent;
8323 offset_expr.X_op = O_absent;
8324 offset_reloc[0] = BFD_RELOC_UNUSED;
8325 offset_reloc[1] = BFD_RELOC_UNUSED;
8326 offset_reloc[2] = BFD_RELOC_UNUSED;
8327
8328 create_insn (insn, opcode);
8329 /* When no opcode suffix is specified, assume ".xyzw". */
8330 if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0)
8331 insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb;
8332 else
8333 insn->insn_opcode |= opcode_extra;
8334 memset (&arg, 0, sizeof (arg));
8335 arg.insn = insn;
8336 arg.token = tokens;
8337 arg.argnum = 1;
8338 arg.last_regno = ILLEGAL_REG;
8339 arg.dest_regno = ILLEGAL_REG;
8340 arg.lax_match = lax_match;
8341 for (args = opcode->args;; ++args)
8342 {
8343 if (arg.token->type == OT_END)
8344 {
8345 /* Handle unary instructions in which only one operand is given.
8346 The source is then the same as the destination. */
8347 if (arg.opnum == 1 && *args == ',')
8348 {
8349 operand = (mips_opts.micromips
8350 ? decode_micromips_operand (args + 1)
8351 : decode_mips_operand (args + 1));
8352 if (operand && mips_optional_operand_p (operand))
8353 {
8354 arg.token = tokens;
8355 arg.argnum = 1;
8356 continue;
8357 }
8358 }
8359
8360 /* Treat elided base registers as $0. */
8361 if (strcmp (args, "(b)") == 0)
8362 args += 3;
8363
8364 if (args[0] == '+')
8365 switch (args[1])
8366 {
8367 case 'K':
8368 case 'N':
8369 /* The register suffix is optional. */
8370 args += 2;
8371 break;
8372 }
8373
8374 /* Fail the match if there were too few operands. */
8375 if (*args)
8376 return false;
8377
8378 /* Successful match. */
8379 if (!complete_p)
8380 return true;
8381 clear_insn_error ();
8382 if (arg.dest_regno == arg.last_regno
8383 && startswith (insn->insn_mo->name, "jalr"))
8384 {
8385 if (arg.opnum == 2)
8386 set_insn_error
8387 (0, _("source and destination must be different"));
8388 else if (arg.last_regno == 31)
8389 set_insn_error
8390 (0, _("a destination register must be supplied"));
8391 }
8392 else if (arg.last_regno == 31
8393 && (startswith (insn->insn_mo->name, "bltzal")
8394 || startswith (insn->insn_mo->name, "bgezal")))
8395 set_insn_error (0, _("the source register must not be $31"));
8396 check_completed_insn (&arg);
8397 return true;
8398 }
8399
8400 /* Fail the match if the line has too many operands. */
8401 if (*args == 0)
8402 return false;
8403
8404 /* Handle characters that need to match exactly. */
8405 if (*args == '(' || *args == ')' || *args == ',')
8406 {
8407 if (match_char (&arg, *args))
8408 continue;
8409 return false;
8410 }
8411 if (*args == '#')
8412 {
8413 ++args;
8414 if (arg.token->type == OT_DOUBLE_CHAR
8415 && arg.token->u.ch == *args)
8416 {
8417 ++arg.token;
8418 continue;
8419 }
8420 return false;
8421 }
8422
8423 /* Handle special macro operands. Work out the properties of
8424 other operands. */
8425 arg.opnum += 1;
8426 switch (*args)
8427 {
8428 case '-':
8429 switch (args[1])
8430 {
8431 case 'A':
8432 *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2;
8433 break;
8434
8435 case 'B':
8436 *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3;
8437 break;
8438 }
8439 break;
8440
8441 case '+':
8442 switch (args[1])
8443 {
8444 case 'i':
8445 *offset_reloc = BFD_RELOC_MIPS_JMP;
8446 break;
8447
8448 case '\'':
8449 *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2;
8450 break;
8451
8452 case '\"':
8453 *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2;
8454 break;
8455 }
8456 break;
8457
8458 case 'I':
8459 if (!match_const_int (&arg, &imm_expr.X_add_number))
8460 return false;
8461 imm_expr.X_op = O_constant;
8462 if (GPR_SIZE == 32)
8463 normalize_constant_expr (&imm_expr);
8464 continue;
8465
8466 case 'A':
8467 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8468 {
8469 /* Assume that the offset has been elided and that what
8470 we saw was a base register. The match will fail later
8471 if that assumption turns out to be wrong. */
8472 offset_expr.X_op = O_constant;
8473 offset_expr.X_add_number = 0;
8474 }
8475 else
8476 {
8477 if (!match_expression (&arg, &offset_expr, offset_reloc))
8478 return false;
8479 normalize_address_expr (&offset_expr);
8480 }
8481 continue;
8482
8483 case 'F':
8484 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8485 8, true))
8486 return false;
8487 continue;
8488
8489 case 'L':
8490 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8491 8, false))
8492 return false;
8493 continue;
8494
8495 case 'f':
8496 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8497 4, true))
8498 return false;
8499 continue;
8500
8501 case 'l':
8502 if (!match_float_constant (&arg, &imm_expr, &offset_expr,
8503 4, false))
8504 return false;
8505 continue;
8506
8507 case 'p':
8508 *offset_reloc = BFD_RELOC_16_PCREL_S2;
8509 break;
8510
8511 case 'a':
8512 *offset_reloc = BFD_RELOC_MIPS_JMP;
8513 break;
8514
8515 case 'm':
8516 gas_assert (mips_opts.micromips);
8517 c = args[1];
8518 switch (c)
8519 {
8520 case 'D':
8521 case 'E':
8522 if (!forced_insn_length)
8523 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
8524 else if (c == 'D')
8525 *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1;
8526 else
8527 *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1;
8528 break;
8529 }
8530 break;
8531 }
8532
8533 operand = (mips_opts.micromips
8534 ? decode_micromips_operand (args)
8535 : decode_mips_operand (args));
8536 if (!operand)
8537 abort ();
8538
8539 /* Skip prefixes. */
8540 if (*args == '+' || *args == 'm' || *args == '-')
8541 args++;
8542
8543 if (mips_optional_operand_p (operand)
8544 && args[1] == ','
8545 && (arg.token[0].type != OT_REG
8546 || arg.token[1].type == OT_END))
8547 {
8548 /* Assume that the register has been elided and is the
8549 same as the first operand. */
8550 arg.token = tokens;
8551 arg.argnum = 1;
8552 }
8553
8554 if (!match_operand (&arg, operand))
8555 return false;
8556 }
8557 }
8558
8559 /* Like match_insn, but for MIPS16. */
8560
8561 static bool
match_mips16_insn(struct mips_cl_insn * insn,const struct mips_opcode * opcode,struct mips_operand_token * tokens)8562 match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
8563 struct mips_operand_token *tokens)
8564 {
8565 const char *args;
8566 const struct mips_operand *operand;
8567 const struct mips_operand *ext_operand;
8568 bool pcrel = false;
8569 int required_insn_length;
8570 struct mips_arg_info arg;
8571 int relax_char;
8572
8573 if (forced_insn_length)
8574 required_insn_length = forced_insn_length;
8575 else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode))
8576 required_insn_length = 2;
8577 else
8578 required_insn_length = 0;
8579
8580 create_insn (insn, opcode);
8581 imm_expr.X_op = O_absent;
8582 offset_expr.X_op = O_absent;
8583 offset_reloc[0] = BFD_RELOC_UNUSED;
8584 offset_reloc[1] = BFD_RELOC_UNUSED;
8585 offset_reloc[2] = BFD_RELOC_UNUSED;
8586 relax_char = 0;
8587
8588 memset (&arg, 0, sizeof (arg));
8589 arg.insn = insn;
8590 arg.token = tokens;
8591 arg.argnum = 1;
8592 arg.last_regno = ILLEGAL_REG;
8593 arg.dest_regno = ILLEGAL_REG;
8594 relax_char = 0;
8595 for (args = opcode->args;; ++args)
8596 {
8597 int c;
8598
8599 if (arg.token->type == OT_END)
8600 {
8601 offsetT value;
8602
8603 /* Handle unary instructions in which only one operand is given.
8604 The source is then the same as the destination. */
8605 if (arg.opnum == 1 && *args == ',')
8606 {
8607 operand = decode_mips16_operand (args[1], false);
8608 if (operand && mips_optional_operand_p (operand))
8609 {
8610 arg.token = tokens;
8611 arg.argnum = 1;
8612 continue;
8613 }
8614 }
8615
8616 /* Fail the match if there were too few operands. */
8617 if (*args)
8618 return false;
8619
8620 /* Successful match. Stuff the immediate value in now, if
8621 we can. */
8622 clear_insn_error ();
8623 if (opcode->pinfo == INSN_MACRO)
8624 {
8625 gas_assert (relax_char == 0 || relax_char == 'p');
8626 gas_assert (*offset_reloc == BFD_RELOC_UNUSED);
8627 }
8628 else if (relax_char
8629 && offset_expr.X_op == O_constant
8630 && !pcrel
8631 && calculate_reloc (*offset_reloc,
8632 offset_expr.X_add_number,
8633 &value))
8634 {
8635 mips16_immed (NULL, 0, relax_char, *offset_reloc, value,
8636 required_insn_length, &insn->insn_opcode);
8637 offset_expr.X_op = O_absent;
8638 *offset_reloc = BFD_RELOC_UNUSED;
8639 }
8640 else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED)
8641 {
8642 if (required_insn_length == 2)
8643 set_insn_error (0, _("invalid unextended operand value"));
8644 else if (!mips_opcode_32bit_p (opcode))
8645 {
8646 forced_insn_length = 4;
8647 insn->insn_opcode |= MIPS16_EXTEND;
8648 }
8649 }
8650 else if (relax_char)
8651 *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char;
8652
8653 check_completed_insn (&arg);
8654 return true;
8655 }
8656
8657 /* Fail the match if the line has too many operands. */
8658 if (*args == 0)
8659 return false;
8660
8661 /* Handle characters that need to match exactly. */
8662 if (*args == '(' || *args == ')' || *args == ',')
8663 {
8664 if (match_char (&arg, *args))
8665 continue;
8666 return false;
8667 }
8668
8669 arg.opnum += 1;
8670 c = *args;
8671 switch (c)
8672 {
8673 case 'p':
8674 case 'q':
8675 case 'A':
8676 case 'B':
8677 case 'E':
8678 case 'V':
8679 case 'u':
8680 relax_char = c;
8681 break;
8682
8683 case 'I':
8684 if (!match_const_int (&arg, &imm_expr.X_add_number))
8685 return false;
8686 imm_expr.X_op = O_constant;
8687 if (GPR_SIZE == 32)
8688 normalize_constant_expr (&imm_expr);
8689 continue;
8690
8691 case 'a':
8692 case 'i':
8693 *offset_reloc = BFD_RELOC_MIPS16_JMP;
8694 break;
8695 }
8696
8697 operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode));
8698 if (!operand)
8699 abort ();
8700
8701 if (operand->type == OP_PCREL)
8702 pcrel = true;
8703 else
8704 {
8705 ext_operand = decode_mips16_operand (c, true);
8706 if (operand != ext_operand)
8707 {
8708 if (arg.token->type == OT_CHAR && arg.token->u.ch == '(')
8709 {
8710 offset_expr.X_op = O_constant;
8711 offset_expr.X_add_number = 0;
8712 relax_char = c;
8713 continue;
8714 }
8715
8716 if (!match_expression (&arg, &offset_expr, offset_reloc))
8717 return false;
8718
8719 /* '8' is used for SLTI(U) and has traditionally not
8720 been allowed to take relocation operators. */
8721 if (offset_reloc[0] != BFD_RELOC_UNUSED
8722 && (ext_operand->size != 16 || c == '8'))
8723 {
8724 match_not_constant (&arg);
8725 return false;
8726 }
8727
8728 if (offset_expr.X_op == O_big)
8729 {
8730 match_out_of_range (&arg);
8731 return false;
8732 }
8733
8734 relax_char = c;
8735 continue;
8736 }
8737 }
8738
8739 if (mips_optional_operand_p (operand)
8740 && args[1] == ','
8741 && (arg.token[0].type != OT_REG
8742 || arg.token[1].type == OT_END))
8743 {
8744 /* Assume that the register has been elided and is the
8745 same as the first operand. */
8746 arg.token = tokens;
8747 arg.argnum = 1;
8748 }
8749
8750 if (!match_operand (&arg, operand))
8751 return false;
8752 }
8753 }
8754
8755 /* Record that the current instruction is invalid for the current ISA. */
8756
8757 static void
match_invalid_for_isa(void)8758 match_invalid_for_isa (void)
8759 {
8760 set_insn_error_ss
8761 (0, _("opcode not supported on this processor: %s (%s)"),
8762 mips_cpu_info_from_arch (mips_opts.arch)->name,
8763 mips_cpu_info_from_isa (mips_opts.isa)->name);
8764 }
8765
8766 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8767 Return true if a definite match or failure was found, storing any match
8768 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8769 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8770 tried and failed to match under normal conditions and now want to try a
8771 more relaxed match. */
8772
8773 static bool
match_insns(struct mips_cl_insn * insn,const struct mips_opcode * first,const struct mips_opcode * past,struct mips_operand_token * tokens,int opcode_extra,bool lax_match)8774 match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8775 const struct mips_opcode *past, struct mips_operand_token *tokens,
8776 int opcode_extra, bool lax_match)
8777 {
8778 const struct mips_opcode *opcode;
8779 const struct mips_opcode *invalid_delay_slot;
8780 bool seen_valid_for_isa, seen_valid_for_size;
8781
8782 /* Search for a match, ignoring alternatives that don't satisfy the
8783 current ISA or forced_length. */
8784 invalid_delay_slot = 0;
8785 seen_valid_for_isa = false;
8786 seen_valid_for_size = false;
8787 opcode = first;
8788 do
8789 {
8790 gas_assert (strcmp (opcode->name, first->name) == 0);
8791 if (is_opcode_valid (opcode))
8792 {
8793 seen_valid_for_isa = true;
8794 if (is_size_valid (opcode))
8795 {
8796 bool delay_slot_ok;
8797
8798 seen_valid_for_size = true;
8799 delay_slot_ok = is_delay_slot_valid (opcode);
8800 if (match_insn (insn, opcode, tokens, opcode_extra,
8801 lax_match, delay_slot_ok))
8802 {
8803 if (!delay_slot_ok)
8804 {
8805 if (!invalid_delay_slot)
8806 invalid_delay_slot = opcode;
8807 }
8808 else
8809 return true;
8810 }
8811 }
8812 }
8813 ++opcode;
8814 }
8815 while (opcode < past && strcmp (opcode->name, first->name) == 0);
8816
8817 /* If the only matches we found had the wrong length for the delay slot,
8818 pick the first such match. We'll issue an appropriate warning later. */
8819 if (invalid_delay_slot)
8820 {
8821 if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra,
8822 lax_match, true))
8823 return true;
8824 abort ();
8825 }
8826
8827 /* Handle the case where we didn't try to match an instruction because
8828 all the alternatives were incompatible with the current ISA. */
8829 if (!seen_valid_for_isa)
8830 {
8831 match_invalid_for_isa ();
8832 return true;
8833 }
8834
8835 /* Handle the case where we didn't try to match an instruction because
8836 all the alternatives were of the wrong size. */
8837 if (!seen_valid_for_size)
8838 {
8839 if (mips_opts.insn32)
8840 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8841 else
8842 set_insn_error_i
8843 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8844 8 * forced_insn_length);
8845 return true;
8846 }
8847
8848 return false;
8849 }
8850
8851 /* Like match_insns, but for MIPS16. */
8852
8853 static bool
match_mips16_insns(struct mips_cl_insn * insn,const struct mips_opcode * first,struct mips_operand_token * tokens)8854 match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
8855 struct mips_operand_token *tokens)
8856 {
8857 const struct mips_opcode *opcode;
8858 bool seen_valid_for_isa;
8859 bool seen_valid_for_size;
8860
8861 /* Search for a match, ignoring alternatives that don't satisfy the
8862 current ISA. There are no separate entries for extended forms so
8863 we deal with forced_length later. */
8864 seen_valid_for_isa = false;
8865 seen_valid_for_size = false;
8866 opcode = first;
8867 do
8868 {
8869 gas_assert (strcmp (opcode->name, first->name) == 0);
8870 if (is_opcode_valid_16 (opcode))
8871 {
8872 seen_valid_for_isa = true;
8873 if (is_size_valid_16 (opcode))
8874 {
8875 seen_valid_for_size = true;
8876 if (match_mips16_insn (insn, opcode, tokens))
8877 return true;
8878 }
8879 }
8880 ++opcode;
8881 }
8882 while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes]
8883 && strcmp (opcode->name, first->name) == 0);
8884
8885 /* Handle the case where we didn't try to match an instruction because
8886 all the alternatives were incompatible with the current ISA. */
8887 if (!seen_valid_for_isa)
8888 {
8889 match_invalid_for_isa ();
8890 return true;
8891 }
8892
8893 /* Handle the case where we didn't try to match an instruction because
8894 all the alternatives were of the wrong size. */
8895 if (!seen_valid_for_size)
8896 {
8897 if (forced_insn_length == 2)
8898 set_insn_error
8899 (0, _("unrecognized unextended version of MIPS16 opcode"));
8900 else
8901 set_insn_error
8902 (0, _("unrecognized extended version of MIPS16 opcode"));
8903 return true;
8904 }
8905
8906 return false;
8907 }
8908
8909 /* Set up global variables for the start of a new macro. */
8910
8911 static void
macro_start(void)8912 macro_start (void)
8913 {
8914 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
8915 memset (&mips_macro_warning.first_insn_sizes, 0,
8916 sizeof (mips_macro_warning.first_insn_sizes));
8917 memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns));
8918 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
8919 && delayed_branch_p (&history[0]));
8920 if (history[0].frag
8921 && history[0].frag->fr_type == rs_machine_dependent
8922 && RELAX_MICROMIPS_P (history[0].frag->fr_subtype)
8923 && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype))
8924 mips_macro_warning.delay_slot_length = 0;
8925 else
8926 switch (history[0].insn_mo->pinfo2
8927 & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT))
8928 {
8929 case INSN2_BRANCH_DELAY_32BIT:
8930 mips_macro_warning.delay_slot_length = 4;
8931 break;
8932 case INSN2_BRANCH_DELAY_16BIT:
8933 mips_macro_warning.delay_slot_length = 2;
8934 break;
8935 default:
8936 mips_macro_warning.delay_slot_length = 0;
8937 break;
8938 }
8939 mips_macro_warning.first_frag = NULL;
8940 }
8941
8942 /* Given that a macro is longer than one instruction or of the wrong size,
8943 return the appropriate warning for it. Return null if no warning is
8944 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8945 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8946 and RELAX_NOMACRO. */
8947
8948 static const char *
macro_warning(relax_substateT subtype)8949 macro_warning (relax_substateT subtype)
8950 {
8951 if (subtype & RELAX_DELAY_SLOT)
8952 return _("macro instruction expanded into multiple instructions"
8953 " in a branch delay slot");
8954 else if (subtype & RELAX_NOMACRO)
8955 return _("macro instruction expanded into multiple instructions");
8956 else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
8957 | RELAX_DELAY_SLOT_SIZE_SECOND))
8958 return ((subtype & RELAX_DELAY_SLOT_16BIT)
8959 ? _("macro instruction expanded into a wrong size instruction"
8960 " in a 16-bit branch delay slot")
8961 : _("macro instruction expanded into a wrong size instruction"
8962 " in a 32-bit branch delay slot"));
8963 else
8964 return 0;
8965 }
8966
8967 /* Finish up a macro. Emit warnings as appropriate. */
8968
8969 static void
macro_end(void)8970 macro_end (void)
8971 {
8972 /* Relaxation warning flags. */
8973 relax_substateT subtype = 0;
8974
8975 /* Check delay slot size requirements. */
8976 if (mips_macro_warning.delay_slot_length == 2)
8977 subtype |= RELAX_DELAY_SLOT_16BIT;
8978 if (mips_macro_warning.delay_slot_length != 0)
8979 {
8980 if (mips_macro_warning.delay_slot_length
8981 != mips_macro_warning.first_insn_sizes[0])
8982 subtype |= RELAX_DELAY_SLOT_SIZE_FIRST;
8983 if (mips_macro_warning.delay_slot_length
8984 != mips_macro_warning.first_insn_sizes[1])
8985 subtype |= RELAX_DELAY_SLOT_SIZE_SECOND;
8986 }
8987
8988 /* Check instruction count requirements. */
8989 if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1)
8990 {
8991 if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0])
8992 subtype |= RELAX_SECOND_LONGER;
8993 if (mips_opts.warn_about_macros)
8994 subtype |= RELAX_NOMACRO;
8995 if (mips_macro_warning.delay_slot_p)
8996 subtype |= RELAX_DELAY_SLOT;
8997 }
8998
8999 /* If both alternatives fail to fill a delay slot correctly,
9000 emit the warning now. */
9001 if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0
9002 && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)
9003 {
9004 relax_substateT s;
9005 const char *msg;
9006
9007 s = subtype & (RELAX_DELAY_SLOT_16BIT
9008 | RELAX_DELAY_SLOT_SIZE_FIRST
9009 | RELAX_DELAY_SLOT_SIZE_SECOND);
9010 msg = macro_warning (s);
9011 if (msg != NULL)
9012 as_warn ("%s", msg);
9013 subtype &= ~s;
9014 }
9015
9016 /* If both implementations are longer than 1 instruction, then emit the
9017 warning now. */
9018 if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1)
9019 {
9020 relax_substateT s;
9021 const char *msg;
9022
9023 s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT);
9024 msg = macro_warning (s);
9025 if (msg != NULL)
9026 as_warn ("%s", msg);
9027 subtype &= ~s;
9028 }
9029
9030 /* If any flags still set, then one implementation might need a warning
9031 and the other either will need one of a different kind or none at all.
9032 Pass any remaining flags over to relaxation. */
9033 if (mips_macro_warning.first_frag != NULL)
9034 mips_macro_warning.first_frag->fr_subtype |= subtype;
9035 }
9036
9037 /* Instruction operand formats used in macros that vary between
9038 standard MIPS and microMIPS code. */
9039
9040 static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
9041 static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
9042 static const char * const jalr_fmt[2] = { "d,s", "t,s" };
9043 static const char * const lui_fmt[2] = { "t,u", "s,u" };
9044 static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
9045 static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
9046 static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
9047 static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
9048
9049 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
9050 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
9051 : cop12_fmt[mips_opts.micromips])
9052 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
9053 #define LUI_FMT (lui_fmt[mips_opts.micromips])
9054 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
9055 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
9056 : mem12_fmt[mips_opts.micromips])
9057 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
9058 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
9059 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
9060
9061 /* Read a macro's relocation codes from *ARGS and store them in *R.
9062 The first argument in *ARGS will be either the code for a single
9063 relocation or -1 followed by the three codes that make up a
9064 composite relocation. */
9065
9066 static void
macro_read_relocs(va_list * args,bfd_reloc_code_real_type * r)9067 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
9068 {
9069 int i, next;
9070
9071 next = va_arg (*args, int);
9072 if (next >= 0)
9073 r[0] = (bfd_reloc_code_real_type) next;
9074 else
9075 {
9076 for (i = 0; i < 3; i++)
9077 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
9078 /* This function is only used for 16-bit relocation fields.
9079 To make the macro code simpler, treat an unrelocated value
9080 in the same way as BFD_RELOC_LO16. */
9081 if (r[0] == BFD_RELOC_UNUSED)
9082 r[0] = BFD_RELOC_LO16;
9083 }
9084 }
9085
9086 /* Build an instruction created by a macro expansion. This is passed
9087 a pointer to the count of instructions created so far, an
9088 expression, the name of the instruction to build, an operand format
9089 string, and corresponding arguments. */
9090
9091 static void
macro_build(expressionS * ep,const char * name,const char * fmt,...)9092 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
9093 {
9094 const struct mips_opcode *mo = NULL;
9095 bfd_reloc_code_real_type r[3];
9096 const struct mips_opcode *amo;
9097 const struct mips_operand *operand;
9098 htab_t hash;
9099 struct mips_cl_insn insn;
9100 va_list args;
9101 unsigned int uval;
9102
9103 va_start (args, fmt);
9104
9105 if (mips_opts.mips16)
9106 {
9107 mips16_macro_build (ep, name, fmt, &args);
9108 va_end (args);
9109 return;
9110 }
9111
9112 r[0] = BFD_RELOC_UNUSED;
9113 r[1] = BFD_RELOC_UNUSED;
9114 r[2] = BFD_RELOC_UNUSED;
9115 hash = mips_opts.micromips ? micromips_op_hash : op_hash;
9116 amo = (struct mips_opcode *) str_hash_find (hash, name);
9117 gas_assert (amo);
9118 gas_assert (strcmp (name, amo->name) == 0);
9119
9120 do
9121 {
9122 /* Search until we get a match for NAME. It is assumed here that
9123 macros will never generate MDMX, MIPS-3D, or MT instructions.
9124 We try to match an instruction that fulfills the branch delay
9125 slot instruction length requirement (if any) of the previous
9126 instruction. While doing this we record the first instruction
9127 seen that matches all the other conditions and use it anyway
9128 if the requirement cannot be met; we will issue an appropriate
9129 warning later on. */
9130 if (strcmp (fmt, amo->args) == 0
9131 && amo->pinfo != INSN_MACRO
9132 && is_opcode_valid (amo)
9133 && is_size_valid (amo))
9134 {
9135 if (is_delay_slot_valid (amo))
9136 {
9137 mo = amo;
9138 break;
9139 }
9140 else if (!mo)
9141 mo = amo;
9142 }
9143
9144 ++amo;
9145 gas_assert (amo->name);
9146 }
9147 while (strcmp (name, amo->name) == 0);
9148
9149 gas_assert (mo);
9150 create_insn (&insn, mo);
9151 for (; *fmt; ++fmt)
9152 {
9153 switch (*fmt)
9154 {
9155 case ',':
9156 case '(':
9157 case ')':
9158 case 'z':
9159 break;
9160
9161 case 'i':
9162 case 'j':
9163 macro_read_relocs (&args, r);
9164 gas_assert (*r == BFD_RELOC_GPREL16
9165 || *r == BFD_RELOC_MIPS_HIGHER
9166 || *r == BFD_RELOC_HI16_S
9167 || *r == BFD_RELOC_LO16
9168 || *r == BFD_RELOC_MIPS_GOT_OFST
9169 || (mips_opts.micromips
9170 && (*r == BFD_RELOC_MIPS_16
9171 || *r == BFD_RELOC_MIPS_GOT16
9172 || *r == BFD_RELOC_MIPS_CALL16
9173 || *r == BFD_RELOC_MIPS_GOT_HI16
9174 || *r == BFD_RELOC_MIPS_GOT_LO16
9175 || *r == BFD_RELOC_MIPS_CALL_HI16
9176 || *r == BFD_RELOC_MIPS_CALL_LO16
9177 || *r == BFD_RELOC_MIPS_SUB
9178 || *r == BFD_RELOC_MIPS_GOT_PAGE
9179 || *r == BFD_RELOC_MIPS_HIGHEST
9180 || *r == BFD_RELOC_MIPS_GOT_DISP
9181 || *r == BFD_RELOC_MIPS_TLS_GD
9182 || *r == BFD_RELOC_MIPS_TLS_LDM
9183 || *r == BFD_RELOC_MIPS_TLS_DTPREL_HI16
9184 || *r == BFD_RELOC_MIPS_TLS_DTPREL_LO16
9185 || *r == BFD_RELOC_MIPS_TLS_GOTTPREL
9186 || *r == BFD_RELOC_MIPS_TLS_TPREL_HI16
9187 || *r == BFD_RELOC_MIPS_TLS_TPREL_LO16)));
9188 break;
9189
9190 case 'o':
9191 macro_read_relocs (&args, r);
9192 break;
9193
9194 case 'u':
9195 macro_read_relocs (&args, r);
9196 gas_assert (ep != NULL
9197 && (ep->X_op == O_constant
9198 || (ep->X_op == O_symbol
9199 && (*r == BFD_RELOC_MIPS_HIGHEST
9200 || *r == BFD_RELOC_HI16_S
9201 || *r == BFD_RELOC_HI16
9202 || *r == BFD_RELOC_GPREL16
9203 || *r == BFD_RELOC_MIPS_GOT_HI16
9204 || *r == BFD_RELOC_MIPS_CALL_HI16))));
9205 break;
9206
9207 case 'p':
9208 gas_assert (ep != NULL);
9209
9210 /*
9211 * This allows macro() to pass an immediate expression for
9212 * creating short branches without creating a symbol.
9213 *
9214 * We don't allow branch relaxation for these branches, as
9215 * they should only appear in ".set nomacro" anyway.
9216 */
9217 if (ep->X_op == O_constant)
9218 {
9219 /* For microMIPS we always use relocations for branches.
9220 So we should not resolve immediate values. */
9221 gas_assert (!mips_opts.micromips);
9222
9223 if ((ep->X_add_number & 3) != 0)
9224 as_bad (_("branch to misaligned address (0x%lx)"),
9225 (unsigned long) ep->X_add_number);
9226 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
9227 as_bad (_("branch address range overflow (0x%lx)"),
9228 (unsigned long) ep->X_add_number);
9229 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
9230 ep = NULL;
9231 }
9232 else
9233 *r = BFD_RELOC_16_PCREL_S2;
9234 break;
9235
9236 case 'a':
9237 gas_assert (ep != NULL);
9238 *r = BFD_RELOC_MIPS_JMP;
9239 break;
9240
9241 default:
9242 operand = (mips_opts.micromips
9243 ? decode_micromips_operand (fmt)
9244 : decode_mips_operand (fmt));
9245 if (!operand)
9246 abort ();
9247
9248 uval = va_arg (args, int);
9249 if (operand->type == OP_CLO_CLZ_DEST)
9250 uval |= (uval << 5);
9251 insn_insert_operand (&insn, operand, uval);
9252
9253 if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
9254 ++fmt;
9255 break;
9256 }
9257 }
9258 va_end (args);
9259 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
9260
9261 append_insn (&insn, ep, r, true);
9262 }
9263
9264 static void
mips16_macro_build(expressionS * ep,const char * name,const char * fmt,va_list * args)9265 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
9266 va_list *args)
9267 {
9268 struct mips_opcode *mo;
9269 struct mips_cl_insn insn;
9270 const struct mips_operand *operand;
9271 bfd_reloc_code_real_type r[3]
9272 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
9273
9274 mo = (struct mips_opcode *) str_hash_find (mips16_op_hash, name);
9275 gas_assert (mo);
9276 gas_assert (strcmp (name, mo->name) == 0);
9277
9278 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
9279 {
9280 ++mo;
9281 gas_assert (mo->name);
9282 gas_assert (strcmp (name, mo->name) == 0);
9283 }
9284
9285 create_insn (&insn, mo);
9286 for (; *fmt; ++fmt)
9287 {
9288 int c;
9289
9290 c = *fmt;
9291 switch (c)
9292 {
9293 case ',':
9294 case '(':
9295 case ')':
9296 break;
9297
9298 case '.':
9299 case 'S':
9300 case 'P':
9301 case 'R':
9302 break;
9303
9304 case '<':
9305 case '5':
9306 case 'F':
9307 case 'H':
9308 case 'W':
9309 case 'D':
9310 case 'j':
9311 case '8':
9312 case 'V':
9313 case 'C':
9314 case 'U':
9315 case 'k':
9316 case 'K':
9317 case 'p':
9318 case 'q':
9319 {
9320 offsetT value;
9321
9322 gas_assert (ep != NULL);
9323
9324 if (ep->X_op != O_constant)
9325 *r = (int) BFD_RELOC_UNUSED + c;
9326 else if (calculate_reloc (*r, ep->X_add_number, &value))
9327 {
9328 mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode);
9329 ep = NULL;
9330 *r = BFD_RELOC_UNUSED;
9331 }
9332 }
9333 break;
9334
9335 default:
9336 operand = decode_mips16_operand (c, false);
9337 if (!operand)
9338 abort ();
9339
9340 insn_insert_operand (&insn, operand, va_arg (*args, int));
9341 break;
9342 }
9343 }
9344
9345 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
9346
9347 append_insn (&insn, ep, r, true);
9348 }
9349
9350 /*
9351 * Generate a "jalr" instruction with a relocation hint to the called
9352 * function. This occurs in NewABI PIC code.
9353 */
9354 static void
macro_build_jalr(expressionS * ep,int cprestore)9355 macro_build_jalr (expressionS *ep, int cprestore)
9356 {
9357 static const bfd_reloc_code_real_type jalr_relocs[2]
9358 = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR };
9359 bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips];
9360 const char *jalr;
9361 char *f = NULL;
9362
9363 if (MIPS_JALR_HINT_P (ep))
9364 {
9365 frag_grow (8);
9366 f = frag_more (0);
9367 }
9368 if (mips_opts.micromips)
9369 {
9370 jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
9371 ? "jalr" : "jalrs");
9372 if (MIPS_JALR_HINT_P (ep)
9373 || mips_opts.insn32
9374 || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
9375 macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
9376 else
9377 macro_build (NULL, jalr, "mj", PIC_CALL_REG);
9378 }
9379 else
9380 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
9381 if (MIPS_JALR_HINT_P (ep))
9382 fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, false, jalr_reloc);
9383 }
9384
9385 /*
9386 * Generate a "lui" instruction.
9387 */
9388 static void
macro_build_lui(expressionS * ep,int regnum)9389 macro_build_lui (expressionS *ep, int regnum)
9390 {
9391 gas_assert (! mips_opts.mips16);
9392
9393 if (ep->X_op != O_constant)
9394 {
9395 gas_assert (ep->X_op == O_symbol);
9396 /* _gp_disp is a special case, used from s_cpload.
9397 __gnu_local_gp is used if mips_no_shared. */
9398 gas_assert (mips_pic == NO_PIC
9399 || (! HAVE_NEWABI
9400 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
9401 || (! mips_in_shared
9402 && strcmp (S_GET_NAME (ep->X_add_symbol),
9403 "__gnu_local_gp") == 0));
9404 }
9405
9406 macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S);
9407 }
9408
9409 /* Generate a sequence of instructions to do a load or store from a constant
9410 offset off of a base register (breg) into/from a target register (treg),
9411 using AT if necessary. */
9412 static void
macro_build_ldst_constoffset(expressionS * ep,const char * op,int treg,int breg,int dbl)9413 macro_build_ldst_constoffset (expressionS *ep, const char *op,
9414 int treg, int breg, int dbl)
9415 {
9416 gas_assert (ep->X_op == O_constant);
9417
9418 /* Sign-extending 32-bit constants makes their handling easier. */
9419 if (!dbl)
9420 normalize_constant_expr (ep);
9421
9422 /* Right now, this routine can only handle signed 32-bit constants. */
9423 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
9424 as_warn (_("operand overflow"));
9425
9426 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
9427 {
9428 /* Signed 16-bit offset will fit in the op. Easy! */
9429 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
9430 }
9431 else
9432 {
9433 /* 32-bit offset, need multiple instructions and AT, like:
9434 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9435 addu $tempreg,$tempreg,$breg
9436 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9437 to handle the complete offset. */
9438 macro_build_lui (ep, AT);
9439 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
9440 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
9441
9442 if (!mips_opts.at)
9443 as_bad (_("macro used $at after \".set noat\""));
9444 }
9445 }
9446
9447 /* set_at()
9448 * Generates code to set the $at register to true (one)
9449 * if reg is less than the immediate expression.
9450 */
9451 static void
set_at(int reg,int unsignedp)9452 set_at (int reg, int unsignedp)
9453 {
9454 if (imm_expr.X_add_number >= -0x8000
9455 && imm_expr.X_add_number < 0x8000)
9456 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
9457 AT, reg, BFD_RELOC_LO16);
9458 else
9459 {
9460 load_register (AT, &imm_expr, GPR_SIZE == 64);
9461 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
9462 }
9463 }
9464
9465 /* Count the leading zeroes by performing a binary chop. This is a
9466 bulky bit of source, but performance is a LOT better for the
9467 majority of values than a simple loop to count the bits:
9468 for (lcnt = 0; (lcnt < 32); lcnt++)
9469 if ((v) & (1 << (31 - lcnt)))
9470 break;
9471 However it is not code size friendly, and the gain will drop a bit
9472 on certain cached systems.
9473 */
9474 #define COUNT_TOP_ZEROES(v) \
9475 (((v) & ~0xffff) == 0 \
9476 ? ((v) & ~0xff) == 0 \
9477 ? ((v) & ~0xf) == 0 \
9478 ? ((v) & ~0x3) == 0 \
9479 ? ((v) & ~0x1) == 0 \
9480 ? !(v) \
9481 ? 32 \
9482 : 31 \
9483 : 30 \
9484 : ((v) & ~0x7) == 0 \
9485 ? 29 \
9486 : 28 \
9487 : ((v) & ~0x3f) == 0 \
9488 ? ((v) & ~0x1f) == 0 \
9489 ? 27 \
9490 : 26 \
9491 : ((v) & ~0x7f) == 0 \
9492 ? 25 \
9493 : 24 \
9494 : ((v) & ~0xfff) == 0 \
9495 ? ((v) & ~0x3ff) == 0 \
9496 ? ((v) & ~0x1ff) == 0 \
9497 ? 23 \
9498 : 22 \
9499 : ((v) & ~0x7ff) == 0 \
9500 ? 21 \
9501 : 20 \
9502 : ((v) & ~0x3fff) == 0 \
9503 ? ((v) & ~0x1fff) == 0 \
9504 ? 19 \
9505 : 18 \
9506 : ((v) & ~0x7fff) == 0 \
9507 ? 17 \
9508 : 16 \
9509 : ((v) & ~0xffffff) == 0 \
9510 ? ((v) & ~0xfffff) == 0 \
9511 ? ((v) & ~0x3ffff) == 0 \
9512 ? ((v) & ~0x1ffff) == 0 \
9513 ? 15 \
9514 : 14 \
9515 : ((v) & ~0x7ffff) == 0 \
9516 ? 13 \
9517 : 12 \
9518 : ((v) & ~0x3fffff) == 0 \
9519 ? ((v) & ~0x1fffff) == 0 \
9520 ? 11 \
9521 : 10 \
9522 : ((v) & ~0x7fffff) == 0 \
9523 ? 9 \
9524 : 8 \
9525 : ((v) & ~0xfffffff) == 0 \
9526 ? ((v) & ~0x3ffffff) == 0 \
9527 ? ((v) & ~0x1ffffff) == 0 \
9528 ? 7 \
9529 : 6 \
9530 : ((v) & ~0x7ffffff) == 0 \
9531 ? 5 \
9532 : 4 \
9533 : ((v) & ~0x3fffffff) == 0 \
9534 ? ((v) & ~0x1fffffff) == 0 \
9535 ? 3 \
9536 : 2 \
9537 : ((v) & ~0x7fffffff) == 0 \
9538 ? 1 \
9539 : 0)
9540
9541 /* load_register()
9542 * This routine generates the least number of instructions necessary to load
9543 * an absolute expression value into a register.
9544 */
9545 static void
load_register(int reg,expressionS * ep,int dbl)9546 load_register (int reg, expressionS *ep, int dbl)
9547 {
9548 int freg;
9549 expressionS hi32, lo32;
9550
9551 if (ep->X_op != O_big)
9552 {
9553 gas_assert (ep->X_op == O_constant);
9554
9555 /* Sign-extending 32-bit constants makes their handling easier. */
9556 if (!dbl)
9557 normalize_constant_expr (ep);
9558
9559 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
9560 {
9561 /* We can handle 16 bit signed values with an addiu to
9562 $zero. No need to ever use daddiu here, since $zero and
9563 the result are always correct in 32 bit mode. */
9564 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9565 return;
9566 }
9567 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
9568 {
9569 /* We can handle 16 bit unsigned values with an ori to
9570 $zero. */
9571 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9572 return;
9573 }
9574 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
9575 {
9576 /* 32 bit values require an lui. */
9577 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9578 if ((ep->X_add_number & 0xffff) != 0)
9579 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9580 return;
9581 }
9582 }
9583
9584 /* The value is larger than 32 bits. */
9585
9586 if (!dbl || GPR_SIZE == 32)
9587 {
9588 as_bad (_("number (0x%" PRIx64 ") larger than 32 bits"),
9589 ep->X_add_number);
9590 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9591 return;
9592 }
9593
9594 if (ep->X_op != O_big)
9595 {
9596 hi32 = *ep;
9597 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9598 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
9599 hi32.X_add_number &= 0xffffffff;
9600 lo32 = *ep;
9601 lo32.X_add_number &= 0xffffffff;
9602 }
9603 else
9604 {
9605 gas_assert (ep->X_add_number > 2);
9606 if (ep->X_add_number == 3)
9607 generic_bignum[3] = 0;
9608 else if (ep->X_add_number > 4)
9609 as_bad (_("number larger than 64 bits"));
9610 lo32.X_op = O_constant;
9611 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
9612 hi32.X_op = O_constant;
9613 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
9614 }
9615
9616 if (hi32.X_add_number == 0)
9617 freg = 0;
9618 else
9619 {
9620 int shift, bit;
9621 unsigned long hi, lo;
9622
9623 if (hi32.X_add_number == (offsetT) 0xffffffff)
9624 {
9625 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
9626 {
9627 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9628 return;
9629 }
9630 if (lo32.X_add_number & 0x80000000)
9631 {
9632 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9633 if (lo32.X_add_number & 0xffff)
9634 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
9635 return;
9636 }
9637 }
9638
9639 /* Check for 16bit shifted constant. We know that hi32 is
9640 non-zero, so start the mask on the first bit of the hi32
9641 value. */
9642 shift = 17;
9643 do
9644 {
9645 unsigned long himask, lomask;
9646
9647 if (shift < 32)
9648 {
9649 himask = 0xffff >> (32 - shift);
9650 lomask = (0xffffU << shift) & 0xffffffff;
9651 }
9652 else
9653 {
9654 himask = 0xffffU << (shift - 32);
9655 lomask = 0;
9656 }
9657 if ((hi32.X_add_number & ~(offsetT) himask) == 0
9658 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
9659 {
9660 expressionS tmp;
9661
9662 tmp.X_op = O_constant;
9663 if (shift < 32)
9664 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
9665 | (lo32.X_add_number >> shift));
9666 else
9667 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
9668 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
9669 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9670 reg, reg, (shift >= 32) ? shift - 32 : shift);
9671 return;
9672 }
9673 ++shift;
9674 }
9675 while (shift <= (64 - 16));
9676
9677 /* Find the bit number of the lowest one bit, and store the
9678 shifted value in hi/lo. */
9679 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
9680 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
9681 if (lo != 0)
9682 {
9683 bit = 0;
9684 while ((lo & 1) == 0)
9685 {
9686 lo >>= 1;
9687 ++bit;
9688 }
9689 if (bit != 0)
9690 {
9691 lo |= (hi & ((2UL << (bit - 1)) - 1)) << (32 - bit);
9692 hi >>= bit;
9693 }
9694 }
9695 else
9696 {
9697 bit = 32;
9698 while ((hi & 1) == 0)
9699 {
9700 hi >>= 1;
9701 ++bit;
9702 }
9703 lo = hi;
9704 hi = 0;
9705 }
9706
9707 /* Optimize if the shifted value is a (power of 2) - 1. */
9708 if ((hi == 0 && ((lo + 1) & lo) == 0)
9709 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
9710 {
9711 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
9712 if (shift != 0)
9713 {
9714 expressionS tmp;
9715
9716 /* This instruction will set the register to be all
9717 ones. */
9718 tmp.X_op = O_constant;
9719 tmp.X_add_number = (offsetT) -1;
9720 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
9721 if (bit != 0)
9722 {
9723 bit += shift;
9724 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT,
9725 reg, reg, (bit >= 32) ? bit - 32 : bit);
9726 }
9727 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT,
9728 reg, reg, (shift >= 32) ? shift - 32 : shift);
9729 return;
9730 }
9731 }
9732
9733 /* Sign extend hi32 before calling load_register, because we can
9734 generally get better code when we load a sign extended value. */
9735 if ((hi32.X_add_number & 0x80000000) != 0)
9736 hi32.X_add_number |= ~(offsetT) 0xffffffff;
9737 load_register (reg, &hi32, 0);
9738 freg = reg;
9739 }
9740 if ((lo32.X_add_number & 0xffff0000) == 0)
9741 {
9742 if (freg != 0)
9743 {
9744 macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0);
9745 freg = reg;
9746 }
9747 }
9748 else
9749 {
9750 expressionS mid16;
9751
9752 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
9753 {
9754 macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16);
9755 macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0);
9756 return;
9757 }
9758
9759 if (freg != 0)
9760 {
9761 macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16);
9762 freg = reg;
9763 }
9764 mid16 = lo32;
9765 mid16.X_add_number >>= 16;
9766 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9767 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9768 freg = reg;
9769 }
9770 if ((lo32.X_add_number & 0xffff) != 0)
9771 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
9772 }
9773
9774 static inline void
load_delay_nop(void)9775 load_delay_nop (void)
9776 {
9777 if (!gpr_interlocks)
9778 macro_build (NULL, "nop", "");
9779 }
9780
9781 /* Load an address into a register. */
9782
9783 static void
load_address(int reg,expressionS * ep,int * used_at)9784 load_address (int reg, expressionS *ep, int *used_at)
9785 {
9786 if (ep->X_op != O_constant
9787 && ep->X_op != O_symbol)
9788 {
9789 as_bad (_("expression too complex"));
9790 ep->X_op = O_constant;
9791 }
9792
9793 if (ep->X_op == O_constant)
9794 {
9795 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
9796 return;
9797 }
9798
9799 if (mips_pic == NO_PIC)
9800 {
9801 /* If this is a reference to a GP relative symbol, we want
9802 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9803 Otherwise we want
9804 lui $reg,<sym> (BFD_RELOC_HI16_S)
9805 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9806 If we have an addend, we always use the latter form.
9807
9808 With 64bit address space and a usable $at we want
9809 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9810 lui $at,<sym> (BFD_RELOC_HI16_S)
9811 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9812 daddiu $at,<sym> (BFD_RELOC_LO16)
9813 dsll32 $reg,0
9814 daddu $reg,$reg,$at
9815
9816 If $at is already in use, we use a path which is suboptimal
9817 on superscalar processors.
9818 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9819 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9820 dsll $reg,16
9821 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9822 dsll $reg,16
9823 daddiu $reg,<sym> (BFD_RELOC_LO16)
9824
9825 For GP relative symbols in 64bit address space we can use
9826 the same sequence as in 32bit address space. */
9827 if (HAVE_64BIT_SYMBOLS)
9828 {
9829 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9830 && !nopic_need_relax (ep->X_add_symbol, 1))
9831 {
9832 relax_start (ep->X_add_symbol);
9833 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9834 mips_gp_register, BFD_RELOC_GPREL16);
9835 relax_switch ();
9836 }
9837
9838 if (*used_at == 0 && mips_opts.at)
9839 {
9840 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9841 macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S);
9842 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9843 BFD_RELOC_MIPS_HIGHER);
9844 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
9845 macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0);
9846 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
9847 *used_at = 1;
9848 }
9849 else
9850 {
9851 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST);
9852 macro_build (ep, "daddiu", "t,r,j", reg, reg,
9853 BFD_RELOC_MIPS_HIGHER);
9854 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9855 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
9856 macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16);
9857 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
9858 }
9859
9860 if (mips_relax.sequence)
9861 relax_end ();
9862 }
9863 else
9864 {
9865 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
9866 && !nopic_need_relax (ep->X_add_symbol, 1))
9867 {
9868 relax_start (ep->X_add_symbol);
9869 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
9870 mips_gp_register, BFD_RELOC_GPREL16);
9871 relax_switch ();
9872 }
9873 macro_build_lui (ep, reg);
9874 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
9875 reg, reg, BFD_RELOC_LO16);
9876 if (mips_relax.sequence)
9877 relax_end ();
9878 }
9879 }
9880 else if (!mips_big_got)
9881 {
9882 expressionS ex;
9883
9884 /* If this is a reference to an external symbol, we want
9885 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9886 Otherwise we want
9887 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9888 nop
9889 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9890 If there is a constant, it must be added in after.
9891
9892 If we have NewABI, we want
9893 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9894 unless we're referencing a global symbol with a non-zero
9895 offset, in which case cst must be added separately. */
9896 if (HAVE_NEWABI)
9897 {
9898 if (ep->X_add_number)
9899 {
9900 ex.X_add_number = ep->X_add_number;
9901 ep->X_add_number = 0;
9902 relax_start (ep->X_add_symbol);
9903 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9904 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9905 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9906 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9907 ex.X_op = O_constant;
9908 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9909 reg, reg, BFD_RELOC_LO16);
9910 ep->X_add_number = ex.X_add_number;
9911 relax_switch ();
9912 }
9913 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9914 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
9915 if (mips_relax.sequence)
9916 relax_end ();
9917 }
9918 else
9919 {
9920 ex.X_add_number = ep->X_add_number;
9921 ep->X_add_number = 0;
9922 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9923 BFD_RELOC_MIPS_GOT16, mips_gp_register);
9924 load_delay_nop ();
9925 relax_start (ep->X_add_symbol);
9926 relax_switch ();
9927 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9928 BFD_RELOC_LO16);
9929 relax_end ();
9930
9931 if (ex.X_add_number != 0)
9932 {
9933 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9934 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9935 ex.X_op = O_constant;
9936 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
9937 reg, reg, BFD_RELOC_LO16);
9938 }
9939 }
9940 }
9941 else if (mips_big_got)
9942 {
9943 expressionS ex;
9944
9945 /* This is the large GOT case. If this is a reference to an
9946 external symbol, we want
9947 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9948 addu $reg,$reg,$gp
9949 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9950
9951 Otherwise, for a reference to a local symbol in old ABI, we want
9952 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9953 nop
9954 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9955 If there is a constant, it must be added in after.
9956
9957 In the NewABI, for local symbols, with or without offsets, we want:
9958 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9959 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9960 */
9961 if (HAVE_NEWABI)
9962 {
9963 ex.X_add_number = ep->X_add_number;
9964 ep->X_add_number = 0;
9965 relax_start (ep->X_add_symbol);
9966 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9967 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9968 reg, reg, mips_gp_register);
9969 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9970 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9971 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
9972 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9973 else if (ex.X_add_number)
9974 {
9975 ex.X_op = O_constant;
9976 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9977 BFD_RELOC_LO16);
9978 }
9979
9980 ep->X_add_number = ex.X_add_number;
9981 relax_switch ();
9982 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
9983 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
9984 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
9985 BFD_RELOC_MIPS_GOT_OFST);
9986 relax_end ();
9987 }
9988 else
9989 {
9990 ex.X_add_number = ep->X_add_number;
9991 ep->X_add_number = 0;
9992 relax_start (ep->X_add_symbol);
9993 macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16);
9994 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
9995 reg, reg, mips_gp_register);
9996 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
9997 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
9998 relax_switch ();
9999 if (reg_needs_delay (mips_gp_register))
10000 {
10001 /* We need a nop before loading from $gp. This special
10002 check is required because the lui which starts the main
10003 instruction stream does not refer to $gp, and so will not
10004 insert the nop which may be required. */
10005 macro_build (NULL, "nop", "");
10006 }
10007 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
10008 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10009 load_delay_nop ();
10010 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
10011 BFD_RELOC_LO16);
10012 relax_end ();
10013
10014 if (ex.X_add_number != 0)
10015 {
10016 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
10017 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
10018 ex.X_op = O_constant;
10019 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
10020 BFD_RELOC_LO16);
10021 }
10022 }
10023 }
10024 else
10025 abort ();
10026
10027 if (!mips_opts.at && *used_at == 1)
10028 as_bad (_("macro used $at after \".set noat\""));
10029 }
10030
10031 /* Move the contents of register SOURCE into register DEST. */
10032
10033 static void
move_register(int dest,int source)10034 move_register (int dest, int source)
10035 {
10036 /* Prefer to use a 16-bit microMIPS instruction unless the previous
10037 instruction specifically requires a 32-bit one. */
10038 if (mips_opts.micromips
10039 && !mips_opts.insn32
10040 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
10041 macro_build (NULL, "move", "mp,mj", dest, source);
10042 else
10043 macro_build (NULL, "or", "d,v,t", dest, source, 0);
10044 }
10045
10046 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
10047 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
10048 The two alternatives are:
10049
10050 Global symbol Local symbol
10051 ------------- ------------
10052 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
10053 ... ...
10054 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
10055
10056 load_got_offset emits the first instruction and add_got_offset
10057 emits the second for a 16-bit offset or add_got_offset_hilo emits
10058 a sequence to add a 32-bit offset using a scratch register. */
10059
10060 static void
load_got_offset(int dest,expressionS * local)10061 load_got_offset (int dest, expressionS *local)
10062 {
10063 expressionS global;
10064
10065 global = *local;
10066 global.X_add_number = 0;
10067
10068 relax_start (local->X_add_symbol);
10069 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
10070 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10071 relax_switch ();
10072 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
10073 BFD_RELOC_MIPS_GOT16, mips_gp_register);
10074 relax_end ();
10075 }
10076
10077 static void
add_got_offset(int dest,expressionS * local)10078 add_got_offset (int dest, expressionS *local)
10079 {
10080 expressionS global;
10081
10082 global.X_op = O_constant;
10083 global.X_op_symbol = NULL;
10084 global.X_add_symbol = NULL;
10085 global.X_add_number = local->X_add_number;
10086
10087 relax_start (local->X_add_symbol);
10088 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
10089 dest, dest, BFD_RELOC_LO16);
10090 relax_switch ();
10091 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
10092 relax_end ();
10093 }
10094
10095 static void
add_got_offset_hilo(int dest,expressionS * local,int tmp)10096 add_got_offset_hilo (int dest, expressionS *local, int tmp)
10097 {
10098 expressionS global;
10099 int hold_mips_optimize;
10100
10101 global.X_op = O_constant;
10102 global.X_op_symbol = NULL;
10103 global.X_add_symbol = NULL;
10104 global.X_add_number = local->X_add_number;
10105
10106 relax_start (local->X_add_symbol);
10107 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
10108 relax_switch ();
10109 /* Set mips_optimize around the lui instruction to avoid
10110 inserting an unnecessary nop after the lw. */
10111 hold_mips_optimize = mips_optimize;
10112 mips_optimize = 2;
10113 macro_build_lui (&global, tmp);
10114 mips_optimize = hold_mips_optimize;
10115 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
10116 relax_end ();
10117
10118 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
10119 }
10120
10121 /* Emit a sequence of instructions to emulate a branch likely operation.
10122 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10123 is its complementing branch with the original condition negated.
10124 CALL is set if the original branch specified the link operation.
10125 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10126
10127 Code like this is produced in the noreorder mode:
10128
10129 BRNEG <args>, 1f
10130 nop
10131 b <sym>
10132 delay slot (executed only if branch taken)
10133 1:
10134
10135 or, if CALL is set:
10136
10137 BRNEG <args>, 1f
10138 nop
10139 bal <sym>
10140 delay slot (executed only if branch taken)
10141 1:
10142
10143 In the reorder mode the delay slot would be filled with a nop anyway,
10144 so code produced is simply:
10145
10146 BR <args>, <sym>
10147 nop
10148
10149 This function is used when producing code for the microMIPS ASE that
10150 does not implement branch likely instructions in hardware. */
10151
10152 static void
macro_build_branch_likely(const char * br,const char * brneg,int call,expressionS * ep,const char * fmt,unsigned int sreg,unsigned int treg)10153 macro_build_branch_likely (const char *br, const char *brneg,
10154 int call, expressionS *ep, const char *fmt,
10155 unsigned int sreg, unsigned int treg)
10156 {
10157 int noreorder = mips_opts.noreorder;
10158 expressionS expr1;
10159
10160 gas_assert (mips_opts.micromips);
10161 start_noreorder ();
10162 if (noreorder)
10163 {
10164 micromips_label_expr (&expr1);
10165 macro_build (&expr1, brneg, fmt, sreg, treg);
10166 macro_build (NULL, "nop", "");
10167 macro_build (ep, call ? "bal" : "b", "p");
10168
10169 /* Set to true so that append_insn adds a label. */
10170 emit_branch_likely_macro = true;
10171 }
10172 else
10173 {
10174 macro_build (ep, br, fmt, sreg, treg);
10175 macro_build (NULL, "nop", "");
10176 }
10177 end_noreorder ();
10178 }
10179
10180 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10181 the condition code tested. EP specifies the branch target. */
10182
10183 static void
macro_build_branch_ccl(int type,expressionS * ep,unsigned int cc)10184 macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc)
10185 {
10186 const int call = 0;
10187 const char *brneg;
10188 const char *br;
10189
10190 switch (type)
10191 {
10192 case M_BC1FL:
10193 br = "bc1f";
10194 brneg = "bc1t";
10195 break;
10196 case M_BC1TL:
10197 br = "bc1t";
10198 brneg = "bc1f";
10199 break;
10200 case M_BC2FL:
10201 br = "bc2f";
10202 brneg = "bc2t";
10203 break;
10204 case M_BC2TL:
10205 br = "bc2t";
10206 brneg = "bc2f";
10207 break;
10208 default:
10209 abort ();
10210 }
10211 macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO);
10212 }
10213
10214 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10215 the register tested. EP specifies the branch target. */
10216
10217 static void
macro_build_branch_rs(int type,expressionS * ep,unsigned int sreg)10218 macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
10219 {
10220 const char *brneg = NULL;
10221 const char *br;
10222 int call = 0;
10223
10224 switch (type)
10225 {
10226 case M_BGEZ:
10227 br = "bgez";
10228 break;
10229 case M_BGEZL:
10230 br = mips_opts.micromips ? "bgez" : "bgezl";
10231 brneg = "bltz";
10232 break;
10233 case M_BGEZALL:
10234 gas_assert (mips_opts.micromips);
10235 br = mips_opts.insn32 ? "bgezal" : "bgezals";
10236 brneg = "bltz";
10237 call = 1;
10238 break;
10239 case M_BGTZ:
10240 br = "bgtz";
10241 break;
10242 case M_BGTZL:
10243 br = mips_opts.micromips ? "bgtz" : "bgtzl";
10244 brneg = "blez";
10245 break;
10246 case M_BLEZ:
10247 br = "blez";
10248 break;
10249 case M_BLEZL:
10250 br = mips_opts.micromips ? "blez" : "blezl";
10251 brneg = "bgtz";
10252 break;
10253 case M_BLTZ:
10254 br = "bltz";
10255 break;
10256 case M_BLTZL:
10257 br = mips_opts.micromips ? "bltz" : "bltzl";
10258 brneg = "bgez";
10259 break;
10260 case M_BLTZALL:
10261 gas_assert (mips_opts.micromips);
10262 br = mips_opts.insn32 ? "bltzal" : "bltzals";
10263 brneg = "bgez";
10264 call = 1;
10265 break;
10266 default:
10267 abort ();
10268 }
10269 if (mips_opts.micromips && brneg)
10270 macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
10271 else
10272 macro_build (ep, br, "s,p", sreg);
10273 }
10274
10275 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10276 TREG as the registers tested. EP specifies the branch target. */
10277
10278 static void
macro_build_branch_rsrt(int type,expressionS * ep,unsigned int sreg,unsigned int treg)10279 macro_build_branch_rsrt (int type, expressionS *ep,
10280 unsigned int sreg, unsigned int treg)
10281 {
10282 const char *brneg = NULL;
10283 const int call = 0;
10284 const char *br;
10285
10286 switch (type)
10287 {
10288 case M_BEQ:
10289 case M_BEQ_I:
10290 br = "beq";
10291 break;
10292 case M_BEQL:
10293 case M_BEQL_I:
10294 br = mips_opts.micromips ? "beq" : "beql";
10295 brneg = "bne";
10296 break;
10297 case M_BNE:
10298 case M_BNE_I:
10299 br = "bne";
10300 break;
10301 case M_BNEL:
10302 case M_BNEL_I:
10303 br = mips_opts.micromips ? "bne" : "bnel";
10304 brneg = "beq";
10305 break;
10306 default:
10307 abort ();
10308 }
10309 if (mips_opts.micromips && brneg)
10310 macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
10311 else
10312 macro_build (ep, br, "s,t,p", sreg, treg);
10313 }
10314
10315 /* Return the high part that should be loaded in order to make the low
10316 part of VALUE accessible using an offset of OFFBITS bits. */
10317
10318 static offsetT
offset_high_part(offsetT value,unsigned int offbits)10319 offset_high_part (offsetT value, unsigned int offbits)
10320 {
10321 offsetT bias;
10322 addressT low_mask;
10323
10324 if (offbits == 0)
10325 return value;
10326 bias = 1 << (offbits - 1);
10327 low_mask = bias * 2 - 1;
10328 return (value + bias) & ~low_mask;
10329 }
10330
10331 /* Return true if the value stored in offset_expr and offset_reloc
10332 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10333 amount that the caller wants to add without inducing overflow
10334 and ALIGN is the known alignment of the value in bytes. */
10335
10336 static bool
small_offset_p(unsigned int range,unsigned int align,unsigned int offbits)10337 small_offset_p (unsigned int range, unsigned int align, unsigned int offbits)
10338 {
10339 if (offbits == 16)
10340 {
10341 /* Accept any relocation operator if overflow isn't a concern. */
10342 if (range < align && *offset_reloc != BFD_RELOC_UNUSED)
10343 return true;
10344
10345 /* These relocations are guaranteed not to overflow in correct links. */
10346 if (*offset_reloc == BFD_RELOC_MIPS_LITERAL
10347 || gprel16_reloc_p (*offset_reloc))
10348 return true;
10349 }
10350 if (offset_expr.X_op == O_constant
10351 && offset_high_part (offset_expr.X_add_number, offbits) == 0
10352 && offset_high_part (offset_expr.X_add_number + range, offbits) == 0)
10353 return true;
10354 return false;
10355 }
10356
10357 /*
10358 * Build macros
10359 * This routine implements the seemingly endless macro or synthesized
10360 * instructions and addressing modes in the mips assembly language. Many
10361 * of these macros are simple and are similar to each other. These could
10362 * probably be handled by some kind of table or grammar approach instead of
10363 * this verbose method. Others are not simple macros but are more like
10364 * optimizing code generation.
10365 * One interesting optimization is when several store macros appear
10366 * consecutively that would load AT with the upper half of the same address.
10367 * The ensuing load upper instructions are omitted. This implies some kind
10368 * of global optimization. We currently only optimize within a single macro.
10369 * For many of the load and store macros if the address is specified as a
10370 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10371 * first load register 'at' with zero and use it as the base register. The
10372 * mips assembler simply uses register $zero. Just one tiny optimization
10373 * we're missing.
10374 */
10375 static void
macro(struct mips_cl_insn * ip,char * str)10376 macro (struct mips_cl_insn *ip, char *str)
10377 {
10378 const struct mips_operand_array *operands;
10379 unsigned int breg, i;
10380 unsigned int tempreg;
10381 int mask;
10382 int used_at = 0;
10383 expressionS label_expr;
10384 expressionS expr1;
10385 expressionS *ep;
10386 const char *s;
10387 const char *s2;
10388 const char *fmt;
10389 int likely = 0;
10390 int coproc = 0;
10391 int offbits = 16;
10392 int call = 0;
10393 int jals = 0;
10394 int dbl = 0;
10395 int imm = 0;
10396 int ust = 0;
10397 int lp = 0;
10398 int ll_sc_paired = 0;
10399 bool large_offset;
10400 int off;
10401 int hold_mips_optimize;
10402 unsigned int align;
10403 unsigned int op[MAX_OPERANDS];
10404
10405 gas_assert (! mips_opts.mips16);
10406
10407 operands = insn_operands (ip);
10408 for (i = 0; i < MAX_OPERANDS; i++)
10409 if (operands->operand[i])
10410 op[i] = insn_extract_operand (ip, operands->operand[i]);
10411 else
10412 op[i] = -1;
10413
10414 mask = ip->insn_mo->mask;
10415
10416 label_expr.X_op = O_constant;
10417 label_expr.X_op_symbol = NULL;
10418 label_expr.X_add_symbol = NULL;
10419 label_expr.X_add_number = 0;
10420
10421 expr1.X_op = O_constant;
10422 expr1.X_op_symbol = NULL;
10423 expr1.X_add_symbol = NULL;
10424 expr1.X_add_number = 1;
10425 align = 1;
10426
10427 switch (mask)
10428 {
10429 case M_DABS:
10430 dbl = 1;
10431 /* Fall through. */
10432 case M_ABS:
10433 /* bgez $a0,1f
10434 move v0,$a0
10435 sub v0,$zero,$a0
10436 1:
10437 */
10438
10439 start_noreorder ();
10440
10441 if (mips_opts.micromips)
10442 micromips_label_expr (&label_expr);
10443 else
10444 label_expr.X_add_number = 8;
10445 macro_build (&label_expr, "bgez", "s,p", op[1]);
10446 if (op[0] == op[1])
10447 macro_build (NULL, "nop", "");
10448 else
10449 move_register (op[0], op[1]);
10450 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
10451 if (mips_opts.micromips)
10452 micromips_add_label ();
10453
10454 end_noreorder ();
10455 break;
10456
10457 case M_ADD_I:
10458 s = "addi";
10459 s2 = "add";
10460 if (ISA_IS_R6 (mips_opts.isa))
10461 goto do_addi_i;
10462 else
10463 goto do_addi;
10464 case M_ADDU_I:
10465 s = "addiu";
10466 s2 = "addu";
10467 goto do_addi;
10468 case M_DADD_I:
10469 dbl = 1;
10470 s = "daddi";
10471 s2 = "dadd";
10472 if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa))
10473 goto do_addi;
10474 if (imm_expr.X_add_number >= -0x200
10475 && imm_expr.X_add_number < 0x200
10476 && !ISA_IS_R6 (mips_opts.isa))
10477 {
10478 macro_build (NULL, s, "t,r,.", op[0], op[1],
10479 (int) imm_expr.X_add_number);
10480 break;
10481 }
10482 goto do_addi_i;
10483 case M_DADDU_I:
10484 dbl = 1;
10485 s = "daddiu";
10486 s2 = "daddu";
10487 do_addi:
10488 if (imm_expr.X_add_number >= -0x8000
10489 && imm_expr.X_add_number < 0x8000)
10490 {
10491 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
10492 break;
10493 }
10494 do_addi_i:
10495 used_at = 1;
10496 load_register (AT, &imm_expr, dbl);
10497 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10498 break;
10499
10500 case M_AND_I:
10501 s = "andi";
10502 s2 = "and";
10503 goto do_bit;
10504 case M_OR_I:
10505 s = "ori";
10506 s2 = "or";
10507 goto do_bit;
10508 case M_NOR_I:
10509 s = "";
10510 s2 = "nor";
10511 goto do_bit;
10512 case M_XOR_I:
10513 s = "xori";
10514 s2 = "xor";
10515 do_bit:
10516 if (imm_expr.X_add_number >= 0
10517 && imm_expr.X_add_number < 0x10000)
10518 {
10519 if (mask != M_NOR_I)
10520 macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16);
10521 else
10522 {
10523 macro_build (&imm_expr, "ori", "t,r,i",
10524 op[0], op[1], BFD_RELOC_LO16);
10525 macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0);
10526 }
10527 break;
10528 }
10529
10530 used_at = 1;
10531 load_register (AT, &imm_expr, GPR_SIZE == 64);
10532 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
10533 break;
10534
10535 case M_BALIGN:
10536 switch (imm_expr.X_add_number)
10537 {
10538 case 0:
10539 macro_build (NULL, "nop", "");
10540 break;
10541 case 2:
10542 macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]);
10543 break;
10544 case 1:
10545 case 3:
10546 macro_build (NULL, "balign", "t,s,2", op[0], op[1],
10547 (int) imm_expr.X_add_number);
10548 break;
10549 default:
10550 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10551 (unsigned long) imm_expr.X_add_number);
10552 break;
10553 }
10554 break;
10555
10556 case M_BC1FL:
10557 case M_BC1TL:
10558 case M_BC2FL:
10559 case M_BC2TL:
10560 gas_assert (mips_opts.micromips);
10561 macro_build_branch_ccl (mask, &offset_expr,
10562 EXTRACT_OPERAND (1, BCC, *ip));
10563 break;
10564
10565 case M_BEQ_I:
10566 case M_BEQL_I:
10567 case M_BNE_I:
10568 case M_BNEL_I:
10569 if (imm_expr.X_add_number == 0)
10570 op[1] = 0;
10571 else
10572 {
10573 op[1] = AT;
10574 used_at = 1;
10575 load_register (op[1], &imm_expr, GPR_SIZE == 64);
10576 }
10577 /* Fall through. */
10578 case M_BEQL:
10579 case M_BNEL:
10580 macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]);
10581 break;
10582
10583 case M_BGEL:
10584 likely = 1;
10585 /* Fall through. */
10586 case M_BGE:
10587 if (op[1] == 0)
10588 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]);
10589 else if (op[0] == 0)
10590 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]);
10591 else
10592 {
10593 used_at = 1;
10594 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10595 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10596 &offset_expr, AT, ZERO);
10597 }
10598 break;
10599
10600 case M_BGEZL:
10601 case M_BGEZALL:
10602 case M_BGTZL:
10603 case M_BLEZL:
10604 case M_BLTZL:
10605 case M_BLTZALL:
10606 macro_build_branch_rs (mask, &offset_expr, op[0]);
10607 break;
10608
10609 case M_BGTL_I:
10610 likely = 1;
10611 /* Fall through. */
10612 case M_BGT_I:
10613 /* Check for > max integer. */
10614 if (imm_expr.X_add_number >= GPR_SMAX)
10615 {
10616 do_false:
10617 /* Result is always false. */
10618 if (! likely)
10619 macro_build (NULL, "nop", "");
10620 else
10621 macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO);
10622 break;
10623 }
10624 ++imm_expr.X_add_number;
10625 /* Fall through. */
10626 case M_BGE_I:
10627 case M_BGEL_I:
10628 if (mask == M_BGEL_I)
10629 likely = 1;
10630 if (imm_expr.X_add_number == 0)
10631 {
10632 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ,
10633 &offset_expr, op[0]);
10634 break;
10635 }
10636 if (imm_expr.X_add_number == 1)
10637 {
10638 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ,
10639 &offset_expr, op[0]);
10640 break;
10641 }
10642 if (imm_expr.X_add_number <= GPR_SMIN)
10643 {
10644 do_true:
10645 /* Result is always true. */
10646 as_warn (_("branch %s is always true"), ip->insn_mo->name);
10647 macro_build (&offset_expr, "b", "p");
10648 break;
10649 }
10650 used_at = 1;
10651 set_at (op[0], 0);
10652 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10653 &offset_expr, AT, ZERO);
10654 break;
10655
10656 case M_BGEUL:
10657 likely = 1;
10658 /* Fall through. */
10659 case M_BGEU:
10660 if (op[1] == 0)
10661 goto do_true;
10662 else if (op[0] == 0)
10663 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10664 &offset_expr, ZERO, op[1]);
10665 else
10666 {
10667 used_at = 1;
10668 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10669 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10670 &offset_expr, AT, ZERO);
10671 }
10672 break;
10673
10674 case M_BGTUL_I:
10675 likely = 1;
10676 /* Fall through. */
10677 case M_BGTU_I:
10678 if (op[0] == 0
10679 || (GPR_SIZE == 32
10680 && imm_expr.X_add_number == -1))
10681 goto do_false;
10682 ++imm_expr.X_add_number;
10683 /* Fall through. */
10684 case M_BGEU_I:
10685 case M_BGEUL_I:
10686 if (mask == M_BGEUL_I)
10687 likely = 1;
10688 if (imm_expr.X_add_number == 0)
10689 goto do_true;
10690 else if (imm_expr.X_add_number == 1)
10691 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10692 &offset_expr, op[0], ZERO);
10693 else
10694 {
10695 used_at = 1;
10696 set_at (op[0], 1);
10697 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10698 &offset_expr, AT, ZERO);
10699 }
10700 break;
10701
10702 case M_BGTL:
10703 likely = 1;
10704 /* Fall through. */
10705 case M_BGT:
10706 if (op[1] == 0)
10707 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]);
10708 else if (op[0] == 0)
10709 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]);
10710 else
10711 {
10712 used_at = 1;
10713 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10714 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10715 &offset_expr, AT, ZERO);
10716 }
10717 break;
10718
10719 case M_BGTUL:
10720 likely = 1;
10721 /* Fall through. */
10722 case M_BGTU:
10723 if (op[1] == 0)
10724 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10725 &offset_expr, op[0], ZERO);
10726 else if (op[0] == 0)
10727 goto do_false;
10728 else
10729 {
10730 used_at = 1;
10731 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10732 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10733 &offset_expr, AT, ZERO);
10734 }
10735 break;
10736
10737 case M_BLEL:
10738 likely = 1;
10739 /* Fall through. */
10740 case M_BLE:
10741 if (op[1] == 0)
10742 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10743 else if (op[0] == 0)
10744 macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]);
10745 else
10746 {
10747 used_at = 1;
10748 macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]);
10749 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10750 &offset_expr, AT, ZERO);
10751 }
10752 break;
10753
10754 case M_BLEL_I:
10755 likely = 1;
10756 /* Fall through. */
10757 case M_BLE_I:
10758 if (imm_expr.X_add_number >= GPR_SMAX)
10759 goto do_true;
10760 ++imm_expr.X_add_number;
10761 /* Fall through. */
10762 case M_BLT_I:
10763 case M_BLTL_I:
10764 if (mask == M_BLTL_I)
10765 likely = 1;
10766 if (imm_expr.X_add_number == 0)
10767 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10768 else if (imm_expr.X_add_number == 1)
10769 macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]);
10770 else
10771 {
10772 used_at = 1;
10773 set_at (op[0], 0);
10774 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10775 &offset_expr, AT, ZERO);
10776 }
10777 break;
10778
10779 case M_BLEUL:
10780 likely = 1;
10781 /* Fall through. */
10782 case M_BLEU:
10783 if (op[1] == 0)
10784 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10785 &offset_expr, op[0], ZERO);
10786 else if (op[0] == 0)
10787 goto do_true;
10788 else
10789 {
10790 used_at = 1;
10791 macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]);
10792 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10793 &offset_expr, AT, ZERO);
10794 }
10795 break;
10796
10797 case M_BLEUL_I:
10798 likely = 1;
10799 /* Fall through. */
10800 case M_BLEU_I:
10801 if (op[0] == 0
10802 || (GPR_SIZE == 32
10803 && imm_expr.X_add_number == -1))
10804 goto do_true;
10805 ++imm_expr.X_add_number;
10806 /* Fall through. */
10807 case M_BLTU_I:
10808 case M_BLTUL_I:
10809 if (mask == M_BLTUL_I)
10810 likely = 1;
10811 if (imm_expr.X_add_number == 0)
10812 goto do_false;
10813 else if (imm_expr.X_add_number == 1)
10814 macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ,
10815 &offset_expr, op[0], ZERO);
10816 else
10817 {
10818 used_at = 1;
10819 set_at (op[0], 1);
10820 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10821 &offset_expr, AT, ZERO);
10822 }
10823 break;
10824
10825 case M_BLTL:
10826 likely = 1;
10827 /* Fall through. */
10828 case M_BLT:
10829 if (op[1] == 0)
10830 macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]);
10831 else if (op[0] == 0)
10832 macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]);
10833 else
10834 {
10835 used_at = 1;
10836 macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]);
10837 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10838 &offset_expr, AT, ZERO);
10839 }
10840 break;
10841
10842 case M_BLTUL:
10843 likely = 1;
10844 /* Fall through. */
10845 case M_BLTU:
10846 if (op[1] == 0)
10847 goto do_false;
10848 else if (op[0] == 0)
10849 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10850 &offset_expr, ZERO, op[1]);
10851 else
10852 {
10853 used_at = 1;
10854 macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]);
10855 macro_build_branch_rsrt (likely ? M_BNEL : M_BNE,
10856 &offset_expr, AT, ZERO);
10857 }
10858 break;
10859
10860 case M_DDIV_3:
10861 dbl = 1;
10862 /* Fall through. */
10863 case M_DIV_3:
10864 s = "mflo";
10865 goto do_div3;
10866 case M_DREM_3:
10867 dbl = 1;
10868 /* Fall through. */
10869 case M_REM_3:
10870 s = "mfhi";
10871 do_div3:
10872 if (op[2] == 0)
10873 {
10874 as_warn (_("divide by zero"));
10875 if (mips_trap)
10876 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10877 else
10878 macro_build (NULL, "break", BRK_FMT, 7);
10879 break;
10880 }
10881
10882 start_noreorder ();
10883 if (mips_trap)
10884 {
10885 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
10886 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10887 }
10888 else
10889 {
10890 if (mips_opts.micromips)
10891 micromips_label_expr (&label_expr);
10892 else
10893 label_expr.X_add_number = 8;
10894 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
10895 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]);
10896 macro_build (NULL, "break", BRK_FMT, 7);
10897 if (mips_opts.micromips)
10898 micromips_add_label ();
10899 }
10900 expr1.X_add_number = -1;
10901 used_at = 1;
10902 load_register (AT, &expr1, dbl);
10903 if (mips_opts.micromips)
10904 micromips_label_expr (&label_expr);
10905 else
10906 label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
10907 macro_build (&label_expr, "bne", "s,t,p", op[2], AT);
10908 if (dbl)
10909 {
10910 expr1.X_add_number = 1;
10911 load_register (AT, &expr1, dbl);
10912 macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31);
10913 }
10914 else
10915 {
10916 expr1.X_add_number = 0x80000000;
10917 macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16);
10918 }
10919 if (mips_trap)
10920 {
10921 macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6);
10922 /* We want to close the noreorder block as soon as possible, so
10923 that later insns are available for delay slot filling. */
10924 end_noreorder ();
10925 }
10926 else
10927 {
10928 if (mips_opts.micromips)
10929 micromips_label_expr (&label_expr);
10930 else
10931 label_expr.X_add_number = 8;
10932 macro_build (&label_expr, "bne", "s,t,p", op[1], AT);
10933 macro_build (NULL, "nop", "");
10934
10935 /* We want to close the noreorder block as soon as possible, so
10936 that later insns are available for delay slot filling. */
10937 end_noreorder ();
10938
10939 macro_build (NULL, "break", BRK_FMT, 6);
10940 }
10941 if (mips_opts.micromips)
10942 micromips_add_label ();
10943 macro_build (NULL, s, MFHL_FMT, op[0]);
10944 break;
10945
10946 case M_DIV_3I:
10947 s = "div";
10948 s2 = "mflo";
10949 goto do_divi;
10950 case M_DIVU_3I:
10951 s = "divu";
10952 s2 = "mflo";
10953 goto do_divi;
10954 case M_REM_3I:
10955 s = "div";
10956 s2 = "mfhi";
10957 goto do_divi;
10958 case M_REMU_3I:
10959 s = "divu";
10960 s2 = "mfhi";
10961 goto do_divi;
10962 case M_DDIV_3I:
10963 dbl = 1;
10964 s = "ddiv";
10965 s2 = "mflo";
10966 goto do_divi;
10967 case M_DDIVU_3I:
10968 dbl = 1;
10969 s = "ddivu";
10970 s2 = "mflo";
10971 goto do_divi;
10972 case M_DREM_3I:
10973 dbl = 1;
10974 s = "ddiv";
10975 s2 = "mfhi";
10976 goto do_divi;
10977 case M_DREMU_3I:
10978 dbl = 1;
10979 s = "ddivu";
10980 s2 = "mfhi";
10981 do_divi:
10982 if (imm_expr.X_add_number == 0)
10983 {
10984 as_warn (_("divide by zero"));
10985 if (mips_trap)
10986 macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
10987 else
10988 macro_build (NULL, "break", BRK_FMT, 7);
10989 break;
10990 }
10991 if (imm_expr.X_add_number == 1)
10992 {
10993 if (strcmp (s2, "mflo") == 0)
10994 move_register (op[0], op[1]);
10995 else
10996 move_register (op[0], ZERO);
10997 break;
10998 }
10999 if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u')
11000 {
11001 if (strcmp (s2, "mflo") == 0)
11002 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]);
11003 else
11004 move_register (op[0], ZERO);
11005 break;
11006 }
11007
11008 used_at = 1;
11009 load_register (AT, &imm_expr, dbl);
11010 macro_build (NULL, s, "z,s,t", op[1], AT);
11011 macro_build (NULL, s2, MFHL_FMT, op[0]);
11012 break;
11013
11014 case M_DIVU_3:
11015 s = "divu";
11016 s2 = "mflo";
11017 goto do_divu3;
11018 case M_REMU_3:
11019 s = "divu";
11020 s2 = "mfhi";
11021 goto do_divu3;
11022 case M_DDIVU_3:
11023 s = "ddivu";
11024 s2 = "mflo";
11025 goto do_divu3;
11026 case M_DREMU_3:
11027 s = "ddivu";
11028 s2 = "mfhi";
11029 do_divu3:
11030 start_noreorder ();
11031 if (mips_trap)
11032 {
11033 macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7);
11034 macro_build (NULL, s, "z,s,t", op[1], op[2]);
11035 /* We want to close the noreorder block as soon as possible, so
11036 that later insns are available for delay slot filling. */
11037 end_noreorder ();
11038 }
11039 else
11040 {
11041 if (mips_opts.micromips)
11042 micromips_label_expr (&label_expr);
11043 else
11044 label_expr.X_add_number = 8;
11045 macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO);
11046 macro_build (NULL, s, "z,s,t", op[1], op[2]);
11047
11048 /* We want to close the noreorder block as soon as possible, so
11049 that later insns are available for delay slot filling. */
11050 end_noreorder ();
11051 macro_build (NULL, "break", BRK_FMT, 7);
11052 if (mips_opts.micromips)
11053 micromips_add_label ();
11054 }
11055 macro_build (NULL, s2, MFHL_FMT, op[0]);
11056 break;
11057
11058 case M_DLCA_AB:
11059 dbl = 1;
11060 /* Fall through. */
11061 case M_LCA_AB:
11062 call = 1;
11063 goto do_la;
11064 case M_DLA_AB:
11065 dbl = 1;
11066 /* Fall through. */
11067 case M_LA_AB:
11068 do_la:
11069 /* Load the address of a symbol into a register. If breg is not
11070 zero, we then add a base register to it. */
11071
11072 breg = op[2];
11073 if (dbl && GPR_SIZE == 32)
11074 as_warn (_("dla used to load 32-bit register; recommend using la "
11075 "instead"));
11076
11077 if (!dbl && HAVE_64BIT_OBJECTS)
11078 as_warn (_("la used to load 64-bit address; recommend using dla "
11079 "instead"));
11080
11081 if (small_offset_p (0, align, 16))
11082 {
11083 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg,
11084 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]);
11085 break;
11086 }
11087
11088 if (mips_opts.at && (op[0] == breg))
11089 {
11090 tempreg = AT;
11091 used_at = 1;
11092 }
11093 else
11094 tempreg = op[0];
11095
11096 if (offset_expr.X_op != O_symbol
11097 && offset_expr.X_op != O_constant)
11098 {
11099 as_bad (_("expression too complex"));
11100 offset_expr.X_op = O_constant;
11101 }
11102
11103 if (offset_expr.X_op == O_constant)
11104 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
11105 else if (mips_pic == NO_PIC)
11106 {
11107 /* If this is a reference to a GP relative symbol, we want
11108 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11109 Otherwise we want
11110 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11111 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11112 If we have a constant, we need two instructions anyhow,
11113 so we may as well always use the latter form.
11114
11115 With 64bit address space and a usable $at we want
11116 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11117 lui $at,<sym> (BFD_RELOC_HI16_S)
11118 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11119 daddiu $at,<sym> (BFD_RELOC_LO16)
11120 dsll32 $tempreg,0
11121 daddu $tempreg,$tempreg,$at
11122
11123 If $at is already in use, we use a path which is suboptimal
11124 on superscalar processors.
11125 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11126 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11127 dsll $tempreg,16
11128 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11129 dsll $tempreg,16
11130 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11131
11132 For GP relative symbols in 64bit address space we can use
11133 the same sequence as in 32bit address space. */
11134 if (HAVE_64BIT_SYMBOLS)
11135 {
11136 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11137 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11138 {
11139 relax_start (offset_expr.X_add_symbol);
11140 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11141 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
11142 relax_switch ();
11143 }
11144
11145 if (used_at == 0 && mips_opts.at)
11146 {
11147 macro_build (&offset_expr, "lui", LUI_FMT,
11148 tempreg, BFD_RELOC_MIPS_HIGHEST);
11149 macro_build (&offset_expr, "lui", LUI_FMT,
11150 AT, BFD_RELOC_HI16_S);
11151 macro_build (&offset_expr, "daddiu", "t,r,j",
11152 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
11153 macro_build (&offset_expr, "daddiu", "t,r,j",
11154 AT, AT, BFD_RELOC_LO16);
11155 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
11156 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
11157 used_at = 1;
11158 }
11159 else
11160 {
11161 macro_build (&offset_expr, "lui", LUI_FMT,
11162 tempreg, BFD_RELOC_MIPS_HIGHEST);
11163 macro_build (&offset_expr, "daddiu", "t,r,j",
11164 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
11165 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11166 macro_build (&offset_expr, "daddiu", "t,r,j",
11167 tempreg, tempreg, BFD_RELOC_HI16_S);
11168 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
11169 macro_build (&offset_expr, "daddiu", "t,r,j",
11170 tempreg, tempreg, BFD_RELOC_LO16);
11171 }
11172
11173 if (mips_relax.sequence)
11174 relax_end ();
11175 }
11176 else
11177 {
11178 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
11179 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
11180 {
11181 relax_start (offset_expr.X_add_symbol);
11182 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11183 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
11184 relax_switch ();
11185 }
11186 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
11187 as_bad (_("offset too large"));
11188 macro_build_lui (&offset_expr, tempreg);
11189 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11190 tempreg, tempreg, BFD_RELOC_LO16);
11191 if (mips_relax.sequence)
11192 relax_end ();
11193 }
11194 }
11195 else if (!mips_big_got && !HAVE_NEWABI)
11196 {
11197 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11198
11199 /* If this is a reference to an external symbol, and there
11200 is no constant, we want
11201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11202 or for lca or if tempreg is PIC_CALL_REG
11203 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11204 For a local symbol, we want
11205 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11206 nop
11207 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11208
11209 If we have a small constant, and this is a reference to
11210 an external symbol, we want
11211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11212 nop
11213 addiu $tempreg,$tempreg,<constant>
11214 For a local symbol, we want the same instruction
11215 sequence, but we output a BFD_RELOC_LO16 reloc on the
11216 addiu instruction.
11217
11218 If we have a large constant, and this is a reference to
11219 an external symbol, we want
11220 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11221 lui $at,<hiconstant>
11222 addiu $at,$at,<loconstant>
11223 addu $tempreg,$tempreg,$at
11224 For a local symbol, we want the same instruction
11225 sequence, but we output a BFD_RELOC_LO16 reloc on the
11226 addiu instruction.
11227 */
11228
11229 if (offset_expr.X_add_number == 0)
11230 {
11231 if (mips_pic == SVR4_PIC
11232 && breg == 0
11233 && (call || tempreg == PIC_CALL_REG))
11234 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
11235
11236 relax_start (offset_expr.X_add_symbol);
11237 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11238 lw_reloc_type, mips_gp_register);
11239 if (breg != 0)
11240 {
11241 /* We're going to put in an addu instruction using
11242 tempreg, so we may as well insert the nop right
11243 now. */
11244 load_delay_nop ();
11245 }
11246 relax_switch ();
11247 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11248 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
11249 load_delay_nop ();
11250 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11251 tempreg, tempreg, BFD_RELOC_LO16);
11252 relax_end ();
11253 /* FIXME: If breg == 0, and the next instruction uses
11254 $tempreg, then if this variant case is used an extra
11255 nop will be generated. */
11256 }
11257 else if (offset_expr.X_add_number >= -0x8000
11258 && offset_expr.X_add_number < 0x8000)
11259 {
11260 load_got_offset (tempreg, &offset_expr);
11261 load_delay_nop ();
11262 add_got_offset (tempreg, &offset_expr);
11263 }
11264 else
11265 {
11266 expr1.X_add_number = offset_expr.X_add_number;
11267 offset_expr.X_add_number =
11268 SEXT_16BIT (offset_expr.X_add_number);
11269 load_got_offset (tempreg, &offset_expr);
11270 offset_expr.X_add_number = expr1.X_add_number;
11271 /* If we are going to add in a base register, and the
11272 target register and the base register are the same,
11273 then we are using AT as a temporary register. Since
11274 we want to load the constant into AT, we add our
11275 current AT (from the global offset table) and the
11276 register into the register now, and pretend we were
11277 not using a base register. */
11278 if (breg == op[0])
11279 {
11280 load_delay_nop ();
11281 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11282 op[0], AT, breg);
11283 breg = 0;
11284 tempreg = op[0];
11285 }
11286 add_got_offset_hilo (tempreg, &offset_expr, AT);
11287 used_at = 1;
11288 }
11289 }
11290 else if (!mips_big_got && HAVE_NEWABI)
11291 {
11292 int add_breg_early = 0;
11293
11294 /* If this is a reference to an external, and there is no
11295 constant, or local symbol (*), with or without a
11296 constant, we want
11297 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11298 or for lca or if tempreg is PIC_CALL_REG
11299 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11300
11301 If we have a small constant, and this is a reference to
11302 an external symbol, we want
11303 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11304 addiu $tempreg,$tempreg,<constant>
11305
11306 If we have a large constant, and this is a reference to
11307 an external symbol, we want
11308 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11309 lui $at,<hiconstant>
11310 addiu $at,$at,<loconstant>
11311 addu $tempreg,$tempreg,$at
11312
11313 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11314 local symbols, even though it introduces an additional
11315 instruction. */
11316
11317 if (offset_expr.X_add_number)
11318 {
11319 expr1.X_add_number = offset_expr.X_add_number;
11320 offset_expr.X_add_number = 0;
11321
11322 relax_start (offset_expr.X_add_symbol);
11323 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11324 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11325
11326 if (expr1.X_add_number >= -0x8000
11327 && expr1.X_add_number < 0x8000)
11328 {
11329 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11330 tempreg, tempreg, BFD_RELOC_LO16);
11331 }
11332 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11333 {
11334 unsigned int dreg;
11335
11336 /* If we are going to add in a base register, and the
11337 target register and the base register are the same,
11338 then we are using AT as a temporary register. Since
11339 we want to load the constant into AT, we add our
11340 current AT (from the global offset table) and the
11341 register into the register now, and pretend we were
11342 not using a base register. */
11343 if (breg != op[0])
11344 dreg = tempreg;
11345 else
11346 {
11347 gas_assert (tempreg == AT);
11348 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11349 op[0], AT, breg);
11350 dreg = op[0];
11351 add_breg_early = 1;
11352 }
11353
11354 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11355 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11356 dreg, dreg, AT);
11357
11358 used_at = 1;
11359 }
11360 else
11361 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11362
11363 relax_switch ();
11364 offset_expr.X_add_number = expr1.X_add_number;
11365
11366 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11367 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11368 if (add_breg_early)
11369 {
11370 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11371 op[0], tempreg, breg);
11372 breg = 0;
11373 tempreg = op[0];
11374 }
11375 relax_end ();
11376 }
11377 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
11378 {
11379 relax_start (offset_expr.X_add_symbol);
11380 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11381 BFD_RELOC_MIPS_CALL16, mips_gp_register);
11382 relax_switch ();
11383 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11384 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11385 relax_end ();
11386 }
11387 else
11388 {
11389 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11390 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
11391 }
11392 }
11393 else if (mips_big_got && !HAVE_NEWABI)
11394 {
11395 int gpdelay;
11396 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11397 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11398 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
11399
11400 /* This is the large GOT case. If this is a reference to an
11401 external symbol, and there is no constant, we want
11402 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11403 addu $tempreg,$tempreg,$gp
11404 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11405 or for lca or if tempreg is PIC_CALL_REG
11406 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11407 addu $tempreg,$tempreg,$gp
11408 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11409 For a local symbol, we want
11410 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11411 nop
11412 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11413
11414 If we have a small constant, and this is a reference to
11415 an external symbol, we want
11416 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11417 addu $tempreg,$tempreg,$gp
11418 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11419 nop
11420 addiu $tempreg,$tempreg,<constant>
11421 For a local symbol, we want
11422 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11423 nop
11424 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11425
11426 If we have a large constant, and this is a reference to
11427 an external symbol, we want
11428 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11429 addu $tempreg,$tempreg,$gp
11430 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11431 lui $at,<hiconstant>
11432 addiu $at,$at,<loconstant>
11433 addu $tempreg,$tempreg,$at
11434 For a local symbol, we want
11435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11436 lui $at,<hiconstant>
11437 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11438 addu $tempreg,$tempreg,$at
11439 */
11440
11441 expr1.X_add_number = offset_expr.X_add_number;
11442 offset_expr.X_add_number = 0;
11443 relax_start (offset_expr.X_add_symbol);
11444 gpdelay = reg_needs_delay (mips_gp_register);
11445 if (expr1.X_add_number == 0 && breg == 0
11446 && (call || tempreg == PIC_CALL_REG))
11447 {
11448 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11449 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11450 }
11451 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11452 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11453 tempreg, tempreg, mips_gp_register);
11454 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11455 tempreg, lw_reloc_type, tempreg);
11456 if (expr1.X_add_number == 0)
11457 {
11458 if (breg != 0)
11459 {
11460 /* We're going to put in an addu instruction using
11461 tempreg, so we may as well insert the nop right
11462 now. */
11463 load_delay_nop ();
11464 }
11465 }
11466 else if (expr1.X_add_number >= -0x8000
11467 && expr1.X_add_number < 0x8000)
11468 {
11469 load_delay_nop ();
11470 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11471 tempreg, tempreg, BFD_RELOC_LO16);
11472 }
11473 else
11474 {
11475 unsigned int dreg;
11476
11477 /* If we are going to add in a base register, and the
11478 target register and the base register are the same,
11479 then we are using AT as a temporary register. Since
11480 we want to load the constant into AT, we add our
11481 current AT (from the global offset table) and the
11482 register into the register now, and pretend we were
11483 not using a base register. */
11484 if (breg != op[0])
11485 dreg = tempreg;
11486 else
11487 {
11488 gas_assert (tempreg == AT);
11489 load_delay_nop ();
11490 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11491 op[0], AT, breg);
11492 dreg = op[0];
11493 }
11494
11495 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11496 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11497
11498 used_at = 1;
11499 }
11500 offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number);
11501 relax_switch ();
11502
11503 if (gpdelay)
11504 {
11505 /* This is needed because this instruction uses $gp, but
11506 the first instruction on the main stream does not. */
11507 macro_build (NULL, "nop", "");
11508 }
11509
11510 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11511 local_reloc_type, mips_gp_register);
11512 if (expr1.X_add_number >= -0x8000
11513 && expr1.X_add_number < 0x8000)
11514 {
11515 load_delay_nop ();
11516 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11517 tempreg, tempreg, BFD_RELOC_LO16);
11518 /* FIXME: If add_number is 0, and there was no base
11519 register, the external symbol case ended with a load,
11520 so if the symbol turns out to not be external, and
11521 the next instruction uses tempreg, an unnecessary nop
11522 will be inserted. */
11523 }
11524 else
11525 {
11526 if (breg == op[0])
11527 {
11528 /* We must add in the base register now, as in the
11529 external symbol case. */
11530 gas_assert (tempreg == AT);
11531 load_delay_nop ();
11532 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11533 op[0], AT, breg);
11534 tempreg = op[0];
11535 /* We set breg to 0 because we have arranged to add
11536 it in in both cases. */
11537 breg = 0;
11538 }
11539
11540 macro_build_lui (&expr1, AT);
11541 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11542 AT, AT, BFD_RELOC_LO16);
11543 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11544 tempreg, tempreg, AT);
11545 used_at = 1;
11546 }
11547 relax_end ();
11548 }
11549 else if (mips_big_got && HAVE_NEWABI)
11550 {
11551 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
11552 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
11553 int add_breg_early = 0;
11554
11555 /* This is the large GOT case. If this is a reference to an
11556 external symbol, and there is no constant, we want
11557 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11558 add $tempreg,$tempreg,$gp
11559 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11560 or for lca or if tempreg is PIC_CALL_REG
11561 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11562 add $tempreg,$tempreg,$gp
11563 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11564
11565 If we have a small constant, and this is a reference to
11566 an external symbol, we want
11567 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11568 add $tempreg,$tempreg,$gp
11569 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11570 addi $tempreg,$tempreg,<constant>
11571
11572 If we have a large constant, and this is a reference to
11573 an external symbol, we want
11574 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11575 addu $tempreg,$tempreg,$gp
11576 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11577 lui $at,<hiconstant>
11578 addi $at,$at,<loconstant>
11579 add $tempreg,$tempreg,$at
11580
11581 If we have NewABI, and we know it's a local symbol, we want
11582 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11583 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11584 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11585
11586 relax_start (offset_expr.X_add_symbol);
11587
11588 expr1.X_add_number = offset_expr.X_add_number;
11589 offset_expr.X_add_number = 0;
11590
11591 if (expr1.X_add_number == 0 && breg == 0
11592 && (call || tempreg == PIC_CALL_REG))
11593 {
11594 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
11595 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
11596 }
11597 macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type);
11598 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11599 tempreg, tempreg, mips_gp_register);
11600 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11601 tempreg, lw_reloc_type, tempreg);
11602
11603 if (expr1.X_add_number == 0)
11604 ;
11605 else if (expr1.X_add_number >= -0x8000
11606 && expr1.X_add_number < 0x8000)
11607 {
11608 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
11609 tempreg, tempreg, BFD_RELOC_LO16);
11610 }
11611 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
11612 {
11613 unsigned int dreg;
11614
11615 /* If we are going to add in a base register, and the
11616 target register and the base register are the same,
11617 then we are using AT as a temporary register. Since
11618 we want to load the constant into AT, we add our
11619 current AT (from the global offset table) and the
11620 register into the register now, and pretend we were
11621 not using a base register. */
11622 if (breg != op[0])
11623 dreg = tempreg;
11624 else
11625 {
11626 gas_assert (tempreg == AT);
11627 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11628 op[0], AT, breg);
11629 dreg = op[0];
11630 add_breg_early = 1;
11631 }
11632
11633 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
11634 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
11635
11636 used_at = 1;
11637 }
11638 else
11639 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11640
11641 relax_switch ();
11642 offset_expr.X_add_number = expr1.X_add_number;
11643 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
11644 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
11645 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
11646 tempreg, BFD_RELOC_MIPS_GOT_OFST);
11647 if (add_breg_early)
11648 {
11649 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
11650 op[0], tempreg, breg);
11651 breg = 0;
11652 tempreg = op[0];
11653 }
11654 relax_end ();
11655 }
11656 else
11657 abort ();
11658
11659 if (breg != 0)
11660 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg);
11661 break;
11662
11663 case M_JR_S:
11664 macro_build_jrpatch (&expr1, op[2]);
11665 macro_build (NULL, "jr", "s", op[2]);
11666 return; /* didn't modify $at */
11667
11668 case M_J_S:
11669 macro_build_jrpatch (&expr1, op[2]);
11670 macro_build (NULL, "j", "s", op[2]);
11671 return; /* didn't modify $at */
11672
11673 case M_JALR_S:
11674 macro_build_jrpatch (&expr1, op[2]);
11675 macro_build (NULL, "jalr", "s", op[2]);
11676 return; /* didn't modify $at */
11677
11678 case M_JALR_DS:
11679 macro_build_jrpatch (&expr1, op[2]);
11680 macro_build (NULL, "jalr", "d,s", op[0], op[2]);
11681 return; /* didn't modify $at */
11682
11683 case M_MSGSND:
11684 gas_assert (!mips_opts.micromips);
11685 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01);
11686 break;
11687
11688 case M_MSGLD:
11689 gas_assert (!mips_opts.micromips);
11690 macro_build (NULL, "c2", "C", 0x02);
11691 break;
11692
11693 case M_MSGLD_T:
11694 gas_assert (!mips_opts.micromips);
11695 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02);
11696 break;
11697
11698 case M_MSGWAIT:
11699 gas_assert (!mips_opts.micromips);
11700 macro_build (NULL, "c2", "C", 3);
11701 break;
11702
11703 case M_MSGWAIT_T:
11704 gas_assert (!mips_opts.micromips);
11705 macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03);
11706 break;
11707
11708 case M_J_A:
11709 /* The j instruction may not be used in PIC code, since it
11710 requires an absolute address. We convert it to a b
11711 instruction. */
11712 if (mips_pic == NO_PIC)
11713 macro_build (&offset_expr, "j", "a");
11714 else
11715 macro_build (&offset_expr, "b", "p");
11716 break;
11717
11718 /* The jal instructions must be handled as macros because when
11719 generating PIC code they expand to multi-instruction
11720 sequences. Normally they are simple instructions. */
11721 case M_JALS_1:
11722 op[1] = op[0];
11723 op[0] = RA;
11724 /* Fall through. */
11725 case M_JALS_2:
11726 gas_assert (mips_opts.micromips);
11727 if (mips_opts.insn32)
11728 {
11729 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11730 break;
11731 }
11732 jals = 1;
11733 goto jal;
11734 case M_JAL_1:
11735 op[1] = op[0];
11736 op[0] = RA;
11737 /* Fall through. */
11738 case M_JAL_2:
11739 jal:
11740 if (mips_pic == NO_PIC)
11741 {
11742 s = jals ? "jalrs" : "jalr";
11743 if (mips_opts.micromips
11744 && !mips_opts.insn32
11745 && op[0] == RA
11746 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11747 macro_build (NULL, s, "mj", op[1]);
11748 else
11749 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11750 }
11751 else
11752 {
11753 int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI
11754 && mips_cprestore_offset >= 0);
11755
11756 if (op[1] != PIC_CALL_REG)
11757 as_warn (_("MIPS PIC call to register other than $25"));
11758
11759 s = ((mips_opts.micromips
11760 && !mips_opts.insn32
11761 && (!mips_opts.noreorder || cprestore))
11762 ? "jalrs" : "jalr");
11763 if (mips_opts.micromips
11764 && !mips_opts.insn32
11765 && op[0] == RA
11766 && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
11767 macro_build (NULL, s, "mj", op[1]);
11768 else
11769 macro_build (NULL, s, JALR_FMT, op[0], op[1]);
11770 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
11771 {
11772 if (mips_cprestore_offset < 0)
11773 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11774 else
11775 {
11776 if (!mips_frame_reg_valid)
11777 {
11778 as_warn (_("no .frame pseudo-op used in PIC code"));
11779 /* Quiet this warning. */
11780 mips_frame_reg_valid = 1;
11781 }
11782 if (!mips_cprestore_valid)
11783 {
11784 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11785 /* Quiet this warning. */
11786 mips_cprestore_valid = 1;
11787 }
11788 if (mips_opts.noreorder)
11789 macro_build (NULL, "nop", "");
11790 expr1.X_add_number = mips_cprestore_offset;
11791 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11792 mips_gp_register,
11793 mips_frame_reg,
11794 HAVE_64BIT_ADDRESSES);
11795 }
11796 }
11797 }
11798
11799 break;
11800
11801 case M_JALS_A:
11802 gas_assert (mips_opts.micromips);
11803 if (mips_opts.insn32)
11804 {
11805 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
11806 break;
11807 }
11808 jals = 1;
11809 /* Fall through. */
11810 case M_JAL_A:
11811 if (mips_pic == NO_PIC)
11812 macro_build (&offset_expr, jals ? "jals" : "jal", "a");
11813 else if (mips_pic == SVR4_PIC)
11814 {
11815 /* If this is a reference to an external symbol, and we are
11816 using a small GOT, we want
11817 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11818 nop
11819 jalr $ra,$25
11820 nop
11821 lw $gp,cprestore($sp)
11822 The cprestore value is set using the .cprestore
11823 pseudo-op. If we are using a big GOT, we want
11824 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11825 addu $25,$25,$gp
11826 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11827 nop
11828 jalr $ra,$25
11829 nop
11830 lw $gp,cprestore($sp)
11831 If the symbol is not external, we want
11832 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11833 nop
11834 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11835 jalr $ra,$25
11836 nop
11837 lw $gp,cprestore($sp)
11838
11839 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11840 sequences above, minus nops, unless the symbol is local,
11841 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11842 GOT_DISP. */
11843 if (HAVE_NEWABI)
11844 {
11845 if (!mips_big_got)
11846 {
11847 relax_start (offset_expr.X_add_symbol);
11848 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11849 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11850 mips_gp_register);
11851 relax_switch ();
11852 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11853 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
11854 mips_gp_register);
11855 relax_end ();
11856 }
11857 else
11858 {
11859 relax_start (offset_expr.X_add_symbol);
11860 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11861 BFD_RELOC_MIPS_CALL_HI16);
11862 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11863 PIC_CALL_REG, mips_gp_register);
11864 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11865 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11866 PIC_CALL_REG);
11867 relax_switch ();
11868 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11869 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
11870 mips_gp_register);
11871 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11872 PIC_CALL_REG, PIC_CALL_REG,
11873 BFD_RELOC_MIPS_GOT_OFST);
11874 relax_end ();
11875 }
11876
11877 macro_build_jalr (&offset_expr, 0);
11878 }
11879 else
11880 {
11881 relax_start (offset_expr.X_add_symbol);
11882 if (!mips_big_got)
11883 {
11884 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11885 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
11886 mips_gp_register);
11887 load_delay_nop ();
11888 relax_switch ();
11889 }
11890 else
11891 {
11892 int gpdelay;
11893
11894 gpdelay = reg_needs_delay (mips_gp_register);
11895 macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG,
11896 BFD_RELOC_MIPS_CALL_HI16);
11897 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
11898 PIC_CALL_REG, mips_gp_register);
11899 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11900 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
11901 PIC_CALL_REG);
11902 load_delay_nop ();
11903 relax_switch ();
11904 if (gpdelay)
11905 macro_build (NULL, "nop", "");
11906 }
11907 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
11908 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
11909 mips_gp_register);
11910 load_delay_nop ();
11911 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
11912 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
11913 relax_end ();
11914 macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
11915
11916 if (mips_cprestore_offset < 0)
11917 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11918 else
11919 {
11920 if (!mips_frame_reg_valid)
11921 {
11922 as_warn (_("no .frame pseudo-op used in PIC code"));
11923 /* Quiet this warning. */
11924 mips_frame_reg_valid = 1;
11925 }
11926 if (!mips_cprestore_valid)
11927 {
11928 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11929 /* Quiet this warning. */
11930 mips_cprestore_valid = 1;
11931 }
11932 if (mips_opts.noreorder)
11933 macro_build (NULL, "nop", "");
11934 expr1.X_add_number = mips_cprestore_offset;
11935 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
11936 mips_gp_register,
11937 mips_frame_reg,
11938 HAVE_64BIT_ADDRESSES);
11939 }
11940 }
11941 }
11942 else if (mips_pic == VXWORKS_PIC)
11943 as_bad (_("non-PIC jump used in PIC library"));
11944 else
11945 abort ();
11946
11947 break;
11948
11949 case M_LBUE_AB:
11950 s = "lbue";
11951 fmt = "t,+j(b)";
11952 offbits = 9;
11953 goto ld_st;
11954 case M_LHUE_AB:
11955 s = "lhue";
11956 fmt = "t,+j(b)";
11957 offbits = 9;
11958 goto ld_st;
11959 case M_LBE_AB:
11960 s = "lbe";
11961 fmt = "t,+j(b)";
11962 offbits = 9;
11963 goto ld_st;
11964 case M_LHE_AB:
11965 s = "lhe";
11966 fmt = "t,+j(b)";
11967 offbits = 9;
11968 goto ld_st;
11969 case M_LLE_AB:
11970 s = "lle";
11971 fmt = "t,+j(b)";
11972 offbits = 9;
11973 goto ld_st;
11974 case M_LWE_AB:
11975 s = "lwe";
11976 fmt = "t,+j(b)";
11977 offbits = 9;
11978 goto ld_st;
11979 case M_LWLE_AB:
11980 s = "lwle";
11981 fmt = "t,+j(b)";
11982 offbits = 9;
11983 goto ld_st;
11984 case M_LWRE_AB:
11985 s = "lwre";
11986 fmt = "t,+j(b)";
11987 offbits = 9;
11988 goto ld_st;
11989 case M_SBE_AB:
11990 s = "sbe";
11991 fmt = "t,+j(b)";
11992 offbits = 9;
11993 goto ld_st;
11994 case M_SCE_AB:
11995 s = "sce";
11996 fmt = "t,+j(b)";
11997 offbits = 9;
11998 goto ld_st;
11999 case M_SHE_AB:
12000 s = "she";
12001 fmt = "t,+j(b)";
12002 offbits = 9;
12003 goto ld_st;
12004 case M_SWE_AB:
12005 s = "swe";
12006 fmt = "t,+j(b)";
12007 offbits = 9;
12008 goto ld_st;
12009 case M_SWLE_AB:
12010 s = "swle";
12011 fmt = "t,+j(b)";
12012 offbits = 9;
12013 goto ld_st;
12014 case M_SWRE_AB:
12015 s = "swre";
12016 fmt = "t,+j(b)";
12017 offbits = 9;
12018 goto ld_st;
12019 case M_ACLR_AB:
12020 s = "aclr";
12021 fmt = "\\,~(b)";
12022 offbits = 12;
12023 goto ld_st;
12024 case M_ASET_AB:
12025 s = "aset";
12026 fmt = "\\,~(b)";
12027 offbits = 12;
12028 goto ld_st;
12029 case M_LB_AB:
12030 s = "lb";
12031 fmt = "t,o(b)";
12032 goto ld;
12033 case M_LBU_AB:
12034 s = "lbu";
12035 fmt = "t,o(b)";
12036 goto ld;
12037 case M_LH_AB:
12038 s = "lh";
12039 fmt = "t,o(b)";
12040 goto ld;
12041 case M_LHU_AB:
12042 s = "lhu";
12043 fmt = "t,o(b)";
12044 goto ld;
12045 case M_LW_AB:
12046 s = "lw";
12047 fmt = "t,o(b)";
12048 goto ld;
12049 case M_LWC0_AB:
12050 gas_assert (!mips_opts.micromips);
12051 s = "lwc0";
12052 fmt = "E,o(b)";
12053 /* Itbl support may require additional care here. */
12054 coproc = 1;
12055 goto ld_st;
12056 case M_LWC1_AB:
12057 s = "lwc1";
12058 fmt = "T,o(b)";
12059 /* Itbl support may require additional care here. */
12060 coproc = 1;
12061 goto ld_st;
12062 case M_LWC2_AB:
12063 s = "lwc2";
12064 fmt = COP12_FMT;
12065 offbits = (mips_opts.micromips ? 12
12066 : ISA_IS_R6 (mips_opts.isa) ? 11
12067 : 16);
12068 /* Itbl support may require additional care here. */
12069 coproc = 1;
12070 goto ld_st;
12071 case M_LWC3_AB:
12072 gas_assert (!mips_opts.micromips);
12073 s = "lwc3";
12074 fmt = "E,o(b)";
12075 /* Itbl support may require additional care here. */
12076 coproc = 1;
12077 goto ld_st;
12078 case M_LWL_AB:
12079 s = "lwl";
12080 fmt = MEM12_FMT;
12081 offbits = (mips_opts.micromips ? 12 : 16);
12082 goto ld_st;
12083 case M_LWR_AB:
12084 s = "lwr";
12085 fmt = MEM12_FMT;
12086 offbits = (mips_opts.micromips ? 12 : 16);
12087 goto ld_st;
12088 case M_LDC1_AB:
12089 s = "ldc1";
12090 fmt = "T,o(b)";
12091 /* Itbl support may require additional care here. */
12092 coproc = 1;
12093 goto ld_st;
12094 case M_LDC2_AB:
12095 s = "ldc2";
12096 fmt = COP12_FMT;
12097 offbits = (mips_opts.micromips ? 12
12098 : ISA_IS_R6 (mips_opts.isa) ? 11
12099 : 16);
12100 /* Itbl support may require additional care here. */
12101 coproc = 1;
12102 goto ld_st;
12103 case M_LQC2_AB:
12104 s = "lqc2";
12105 fmt = "+7,o(b)";
12106 /* Itbl support may require additional care here. */
12107 coproc = 1;
12108 goto ld_st;
12109 case M_LDC3_AB:
12110 s = "ldc3";
12111 fmt = "E,o(b)";
12112 /* Itbl support may require additional care here. */
12113 coproc = 1;
12114 goto ld_st;
12115 case M_LDL_AB:
12116 s = "ldl";
12117 fmt = MEM12_FMT;
12118 offbits = (mips_opts.micromips ? 12 : 16);
12119 goto ld_st;
12120 case M_LDR_AB:
12121 s = "ldr";
12122 fmt = MEM12_FMT;
12123 offbits = (mips_opts.micromips ? 12 : 16);
12124 goto ld_st;
12125 case M_LL_AB:
12126 s = "ll";
12127 fmt = LL_SC_FMT;
12128 offbits = (mips_opts.micromips ? 12
12129 : ISA_IS_R6 (mips_opts.isa) ? 9
12130 : 16);
12131 goto ld;
12132 case M_LLD_AB:
12133 s = "lld";
12134 fmt = LL_SC_FMT;
12135 offbits = (mips_opts.micromips ? 12
12136 : ISA_IS_R6 (mips_opts.isa) ? 9
12137 : 16);
12138 goto ld;
12139 case M_LWU_AB:
12140 s = "lwu";
12141 fmt = MEM12_FMT;
12142 offbits = (mips_opts.micromips ? 12 : 16);
12143 goto ld;
12144 case M_LWP_AB:
12145 gas_assert (mips_opts.micromips);
12146 s = "lwp";
12147 fmt = "t,~(b)";
12148 offbits = 12;
12149 lp = 1;
12150 goto ld;
12151 case M_LDP_AB:
12152 gas_assert (mips_opts.micromips);
12153 s = "ldp";
12154 fmt = "t,~(b)";
12155 offbits = 12;
12156 lp = 1;
12157 goto ld;
12158 case M_LLDP_AB:
12159 case M_LLWP_AB:
12160 case M_LLWPE_AB:
12161 s = ip->insn_mo->name;
12162 fmt = "t,d,s";
12163 ll_sc_paired = 1;
12164 offbits = 0;
12165 goto ld;
12166 case M_LWM_AB:
12167 gas_assert (mips_opts.micromips);
12168 s = "lwm";
12169 fmt = "n,~(b)";
12170 offbits = 12;
12171 goto ld_st;
12172 case M_LDM_AB:
12173 gas_assert (mips_opts.micromips);
12174 s = "ldm";
12175 fmt = "n,~(b)";
12176 offbits = 12;
12177 goto ld_st;
12178
12179 ld:
12180 /* Try to use one the the load registers to compute the base address.
12181 We don't want to use $0 as tempreg. */
12182 if (ll_sc_paired)
12183 {
12184 if ((op[0] == ZERO && op[3] == op[1])
12185 || (op[1] == ZERO && op[3] == op[0])
12186 || (op[0] == ZERO && op[1] == ZERO))
12187 goto ld_st;
12188 else if (op[0] != op[3] && op[0] != ZERO)
12189 tempreg = op[0];
12190 else
12191 tempreg = op[1];
12192 }
12193 else
12194 {
12195 if (op[2] == op[0] + lp || op[0] + lp == ZERO)
12196 goto ld_st;
12197 else
12198 tempreg = op[0] + lp;
12199 }
12200 goto ld_noat;
12201
12202 case M_SB_AB:
12203 s = "sb";
12204 fmt = "t,o(b)";
12205 goto ld_st;
12206 case M_SH_AB:
12207 s = "sh";
12208 fmt = "t,o(b)";
12209 goto ld_st;
12210 case M_SW_AB:
12211 s = "sw";
12212 fmt = "t,o(b)";
12213 goto ld_st;
12214 case M_SWC0_AB:
12215 gas_assert (!mips_opts.micromips);
12216 s = "swc0";
12217 fmt = "E,o(b)";
12218 /* Itbl support may require additional care here. */
12219 coproc = 1;
12220 goto ld_st;
12221 case M_SWC1_AB:
12222 s = "swc1";
12223 fmt = "T,o(b)";
12224 /* Itbl support may require additional care here. */
12225 coproc = 1;
12226 goto ld_st;
12227 case M_SWC2_AB:
12228 s = "swc2";
12229 fmt = COP12_FMT;
12230 offbits = (mips_opts.micromips ? 12
12231 : ISA_IS_R6 (mips_opts.isa) ? 11
12232 : 16);
12233 /* Itbl support may require additional care here. */
12234 coproc = 1;
12235 goto ld_st;
12236 case M_SWC3_AB:
12237 gas_assert (!mips_opts.micromips);
12238 s = "swc3";
12239 fmt = "E,o(b)";
12240 /* Itbl support may require additional care here. */
12241 coproc = 1;
12242 goto ld_st;
12243 case M_SWL_AB:
12244 s = "swl";
12245 fmt = MEM12_FMT;
12246 offbits = (mips_opts.micromips ? 12 : 16);
12247 goto ld_st;
12248 case M_SWR_AB:
12249 s = "swr";
12250 fmt = MEM12_FMT;
12251 offbits = (mips_opts.micromips ? 12 : 16);
12252 goto ld_st;
12253 case M_SC_AB:
12254 s = "sc";
12255 fmt = LL_SC_FMT;
12256 offbits = (mips_opts.micromips ? 12
12257 : ISA_IS_R6 (mips_opts.isa) ? 9
12258 : 16);
12259 goto ld_st;
12260 case M_SCD_AB:
12261 s = "scd";
12262 fmt = LL_SC_FMT;
12263 offbits = (mips_opts.micromips ? 12
12264 : ISA_IS_R6 (mips_opts.isa) ? 9
12265 : 16);
12266 goto ld_st;
12267 case M_SCDP_AB:
12268 case M_SCWP_AB:
12269 case M_SCWPE_AB:
12270 s = ip->insn_mo->name;
12271 fmt = "t,d,s";
12272 ll_sc_paired = 1;
12273 offbits = 0;
12274 goto ld_st;
12275 case M_CACHE_AB:
12276 s = "cache";
12277 fmt = (mips_opts.micromips ? "k,~(b)"
12278 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
12279 : "k,o(b)");
12280 offbits = (mips_opts.micromips ? 12
12281 : ISA_IS_R6 (mips_opts.isa) ? 9
12282 : 16);
12283 goto ld_st;
12284 case M_CACHEE_AB:
12285 s = "cachee";
12286 fmt = "k,+j(b)";
12287 offbits = 9;
12288 goto ld_st;
12289 case M_PREF_AB:
12290 s = "pref";
12291 fmt = (mips_opts.micromips ? "k,~(b)"
12292 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
12293 : "k,o(b)");
12294 offbits = (mips_opts.micromips ? 12
12295 : ISA_IS_R6 (mips_opts.isa) ? 9
12296 : 16);
12297 goto ld_st;
12298 case M_PREFE_AB:
12299 s = "prefe";
12300 fmt = "k,+j(b)";
12301 offbits = 9;
12302 goto ld_st;
12303 case M_SDC1_AB:
12304 s = "sdc1";
12305 fmt = "T,o(b)";
12306 coproc = 1;
12307 /* Itbl support may require additional care here. */
12308 goto ld_st;
12309 case M_SDC2_AB:
12310 s = "sdc2";
12311 fmt = COP12_FMT;
12312 offbits = (mips_opts.micromips ? 12
12313 : ISA_IS_R6 (mips_opts.isa) ? 11
12314 : 16);
12315 /* Itbl support may require additional care here. */
12316 coproc = 1;
12317 goto ld_st;
12318 case M_SQC2_AB:
12319 s = "sqc2";
12320 fmt = "+7,o(b)";
12321 /* Itbl support may require additional care here. */
12322 coproc = 1;
12323 goto ld_st;
12324 case M_SDC3_AB:
12325 gas_assert (!mips_opts.micromips);
12326 s = "sdc3";
12327 fmt = "E,o(b)";
12328 /* Itbl support may require additional care here. */
12329 coproc = 1;
12330 goto ld_st;
12331 case M_SDL_AB:
12332 s = "sdl";
12333 fmt = MEM12_FMT;
12334 offbits = (mips_opts.micromips ? 12 : 16);
12335 goto ld_st;
12336 case M_SDR_AB:
12337 s = "sdr";
12338 fmt = MEM12_FMT;
12339 offbits = (mips_opts.micromips ? 12 : 16);
12340 goto ld_st;
12341 case M_SWP_AB:
12342 gas_assert (mips_opts.micromips);
12343 s = "swp";
12344 fmt = "t,~(b)";
12345 offbits = 12;
12346 goto ld_st;
12347 case M_SDP_AB:
12348 gas_assert (mips_opts.micromips);
12349 s = "sdp";
12350 fmt = "t,~(b)";
12351 offbits = 12;
12352 goto ld_st;
12353 case M_SWM_AB:
12354 gas_assert (mips_opts.micromips);
12355 s = "swm";
12356 fmt = "n,~(b)";
12357 offbits = 12;
12358 goto ld_st;
12359 case M_SDM_AB:
12360 gas_assert (mips_opts.micromips);
12361 s = "sdm";
12362 fmt = "n,~(b)";
12363 offbits = 12;
12364
12365 ld_st:
12366 tempreg = AT;
12367 ld_noat:
12368 breg = ll_sc_paired ? op[3] : op[2];
12369 if (small_offset_p (0, align, 16))
12370 {
12371 /* The first case exists for M_LD_AB and M_SD_AB, which are
12372 macros for o32 but which should act like normal instructions
12373 otherwise. */
12374 if (offbits == 16)
12375 macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0],
12376 offset_reloc[1], offset_reloc[2], breg);
12377 else if (small_offset_p (0, align, offbits))
12378 {
12379 if (offbits == 0)
12380 {
12381 if (ll_sc_paired)
12382 macro_build (NULL, s, fmt, op[0], op[1], breg);
12383 else
12384 macro_build (NULL, s, fmt, op[0], breg);
12385 }
12386 else
12387 macro_build (NULL, s, fmt, op[0],
12388 (int) offset_expr.X_add_number, breg);
12389 }
12390 else
12391 {
12392 if (tempreg == AT)
12393 used_at = 1;
12394 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
12395 tempreg, breg, -1, offset_reloc[0],
12396 offset_reloc[1], offset_reloc[2]);
12397 if (offbits == 0)
12398 {
12399 if (ll_sc_paired)
12400 macro_build (NULL, s, fmt, op[0], op[1], tempreg);
12401 else
12402 macro_build (NULL, s, fmt, op[0], tempreg);
12403 }
12404 else
12405 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12406 }
12407 break;
12408 }
12409
12410 if (tempreg == AT)
12411 used_at = 1;
12412
12413 if (offset_expr.X_op != O_constant
12414 && offset_expr.X_op != O_symbol)
12415 {
12416 as_bad (_("expression too complex"));
12417 offset_expr.X_op = O_constant;
12418 }
12419
12420 if (HAVE_32BIT_ADDRESSES
12421 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
12422 {
12423 as_bad (_("number (0x%" PRIx64 ") larger than 32 bits"),
12424 offset_expr.X_add_number);
12425 }
12426
12427 /* A constant expression in PIC code can be handled just as it
12428 is in non PIC code. */
12429 if (offset_expr.X_op == O_constant)
12430 {
12431 expr1.X_add_number = offset_high_part (offset_expr.X_add_number,
12432 offbits == 0 ? 16 : offbits);
12433 offset_expr.X_add_number -= expr1.X_add_number;
12434
12435 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
12436 if (breg != 0)
12437 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12438 tempreg, tempreg, breg);
12439 if (offbits == 0)
12440 {
12441 if (offset_expr.X_add_number != 0)
12442 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
12443 "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
12444 if (ll_sc_paired)
12445 macro_build (NULL, s, fmt, op[0], op[1], tempreg);
12446 else
12447 macro_build (NULL, s, fmt, op[0], tempreg);
12448 }
12449 else if (offbits == 16)
12450 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12451 else
12452 macro_build (NULL, s, fmt, op[0],
12453 (int) offset_expr.X_add_number, tempreg);
12454 }
12455 else if (offbits != 16)
12456 {
12457 /* The offset field is too narrow to be used for a low-part
12458 relocation, so load the whole address into the auxiliary
12459 register. */
12460 load_address (tempreg, &offset_expr, &used_at);
12461 if (breg != 0)
12462 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12463 tempreg, tempreg, breg);
12464 if (offbits == 0)
12465 {
12466 if (ll_sc_paired)
12467 macro_build (NULL, s, fmt, op[0], op[1], tempreg);
12468 else
12469 macro_build (NULL, s, fmt, op[0], tempreg);
12470 }
12471 else
12472 macro_build (NULL, s, fmt, op[0], 0, tempreg);
12473 }
12474 else if (mips_pic == NO_PIC)
12475 {
12476 /* If this is a reference to a GP relative symbol, and there
12477 is no base register, we want
12478 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12479 Otherwise, if there is no base register, we want
12480 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12481 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12482 If we have a constant, we need two instructions anyhow,
12483 so we always use the latter form.
12484
12485 If we have a base register, and this is a reference to a
12486 GP relative symbol, we want
12487 addu $tempreg,$breg,$gp
12488 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12489 Otherwise we want
12490 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12491 addu $tempreg,$tempreg,$breg
12492 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12493 With a constant we always use the latter case.
12494
12495 With 64bit address space and no base register and $at usable,
12496 we want
12497 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12498 lui $at,<sym> (BFD_RELOC_HI16_S)
12499 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12500 dsll32 $tempreg,0
12501 daddu $tempreg,$at
12502 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12503 If we have a base register, we want
12504 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12505 lui $at,<sym> (BFD_RELOC_HI16_S)
12506 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12507 daddu $at,$breg
12508 dsll32 $tempreg,0
12509 daddu $tempreg,$at
12510 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12511
12512 Without $at we can't generate the optimal path for superscalar
12513 processors here since this would require two temporary registers.
12514 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12515 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12516 dsll $tempreg,16
12517 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12518 dsll $tempreg,16
12519 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12520 If we have a base register, we want
12521 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12522 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12523 dsll $tempreg,16
12524 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12525 dsll $tempreg,16
12526 daddu $tempreg,$tempreg,$breg
12527 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12528
12529 For GP relative symbols in 64bit address space we can use
12530 the same sequence as in 32bit address space. */
12531 if (HAVE_64BIT_SYMBOLS)
12532 {
12533 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12534 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12535 {
12536 relax_start (offset_expr.X_add_symbol);
12537 if (breg == 0)
12538 {
12539 macro_build (&offset_expr, s, fmt, op[0],
12540 BFD_RELOC_GPREL16, mips_gp_register);
12541 }
12542 else
12543 {
12544 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12545 tempreg, breg, mips_gp_register);
12546 macro_build (&offset_expr, s, fmt, op[0],
12547 BFD_RELOC_GPREL16, tempreg);
12548 }
12549 relax_switch ();
12550 }
12551
12552 if (used_at == 0 && mips_opts.at)
12553 {
12554 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12555 BFD_RELOC_MIPS_HIGHEST);
12556 macro_build (&offset_expr, "lui", LUI_FMT, AT,
12557 BFD_RELOC_HI16_S);
12558 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12559 tempreg, BFD_RELOC_MIPS_HIGHER);
12560 if (breg != 0)
12561 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
12562 macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0);
12563 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
12564 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16,
12565 tempreg);
12566 used_at = 1;
12567 }
12568 else
12569 {
12570 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12571 BFD_RELOC_MIPS_HIGHEST);
12572 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12573 tempreg, BFD_RELOC_MIPS_HIGHER);
12574 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12575 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
12576 tempreg, BFD_RELOC_HI16_S);
12577 macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16);
12578 if (breg != 0)
12579 macro_build (NULL, "daddu", "d,v,t",
12580 tempreg, tempreg, breg);
12581 macro_build (&offset_expr, s, fmt, op[0],
12582 BFD_RELOC_LO16, tempreg);
12583 }
12584
12585 if (mips_relax.sequence)
12586 relax_end ();
12587 break;
12588 }
12589
12590 if (breg == 0)
12591 {
12592 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12593 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12594 {
12595 relax_start (offset_expr.X_add_symbol);
12596 macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16,
12597 mips_gp_register);
12598 relax_switch ();
12599 }
12600 macro_build_lui (&offset_expr, tempreg);
12601 macro_build (&offset_expr, s, fmt, op[0],
12602 BFD_RELOC_LO16, tempreg);
12603 if (mips_relax.sequence)
12604 relax_end ();
12605 }
12606 else
12607 {
12608 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
12609 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
12610 {
12611 relax_start (offset_expr.X_add_symbol);
12612 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12613 tempreg, breg, mips_gp_register);
12614 macro_build (&offset_expr, s, fmt, op[0],
12615 BFD_RELOC_GPREL16, tempreg);
12616 relax_switch ();
12617 }
12618 macro_build_lui (&offset_expr, tempreg);
12619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12620 tempreg, tempreg, breg);
12621 macro_build (&offset_expr, s, fmt, op[0],
12622 BFD_RELOC_LO16, tempreg);
12623 if (mips_relax.sequence)
12624 relax_end ();
12625 }
12626 }
12627 else if (!mips_big_got)
12628 {
12629 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
12630
12631 /* If this is a reference to an external symbol, we want
12632 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12633 nop
12634 <op> op[0],0($tempreg)
12635 Otherwise we want
12636 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12637 nop
12638 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12639 <op> op[0],0($tempreg)
12640
12641 For NewABI, we want
12642 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12643 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12644
12645 If there is a base register, we add it to $tempreg before
12646 the <op>. If there is a constant, we stick it in the
12647 <op> instruction. We don't handle constants larger than
12648 16 bits, because we have no way to load the upper 16 bits
12649 (actually, we could handle them for the subset of cases
12650 in which we are not using $at). */
12651 gas_assert (offset_expr.X_op == O_symbol);
12652 if (HAVE_NEWABI)
12653 {
12654 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12655 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12656 if (breg != 0)
12657 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12658 tempreg, tempreg, breg);
12659 macro_build (&offset_expr, s, fmt, op[0],
12660 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12661 break;
12662 }
12663 expr1.X_add_number = offset_expr.X_add_number;
12664 offset_expr.X_add_number = 0;
12665 if (expr1.X_add_number < -0x8000
12666 || expr1.X_add_number >= 0x8000)
12667 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12668 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12669 lw_reloc_type, mips_gp_register);
12670 load_delay_nop ();
12671 relax_start (offset_expr.X_add_symbol);
12672 relax_switch ();
12673 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12674 tempreg, BFD_RELOC_LO16);
12675 relax_end ();
12676 if (breg != 0)
12677 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12678 tempreg, tempreg, breg);
12679 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12680 }
12681 else if (mips_big_got && !HAVE_NEWABI)
12682 {
12683 int gpdelay;
12684
12685 /* If this is a reference to an external symbol, we want
12686 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12687 addu $tempreg,$tempreg,$gp
12688 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12689 <op> op[0],0($tempreg)
12690 Otherwise we want
12691 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12692 nop
12693 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12694 <op> op[0],0($tempreg)
12695 If there is a base register, we add it to $tempreg before
12696 the <op>. If there is a constant, we stick it in the
12697 <op> instruction. We don't handle constants larger than
12698 16 bits, because we have no way to load the upper 16 bits
12699 (actually, we could handle them for the subset of cases
12700 in which we are not using $at). */
12701 gas_assert (offset_expr.X_op == O_symbol);
12702 expr1.X_add_number = offset_expr.X_add_number;
12703 offset_expr.X_add_number = 0;
12704 if (expr1.X_add_number < -0x8000
12705 || expr1.X_add_number >= 0x8000)
12706 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12707 gpdelay = reg_needs_delay (mips_gp_register);
12708 relax_start (offset_expr.X_add_symbol);
12709 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12710 BFD_RELOC_MIPS_GOT_HI16);
12711 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12712 mips_gp_register);
12713 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12714 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12715 relax_switch ();
12716 if (gpdelay)
12717 macro_build (NULL, "nop", "");
12718 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12719 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12720 load_delay_nop ();
12721 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
12722 tempreg, BFD_RELOC_LO16);
12723 relax_end ();
12724
12725 if (breg != 0)
12726 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12727 tempreg, tempreg, breg);
12728 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12729 }
12730 else if (mips_big_got && HAVE_NEWABI)
12731 {
12732 /* If this is a reference to an external symbol, we want
12733 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12734 add $tempreg,$tempreg,$gp
12735 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12736 <op> op[0],<ofst>($tempreg)
12737 Otherwise, for local symbols, we want:
12738 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12739 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12740 gas_assert (offset_expr.X_op == O_symbol);
12741 expr1.X_add_number = offset_expr.X_add_number;
12742 offset_expr.X_add_number = 0;
12743 if (expr1.X_add_number < -0x8000
12744 || expr1.X_add_number >= 0x8000)
12745 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12746 relax_start (offset_expr.X_add_symbol);
12747 macro_build (&offset_expr, "lui", LUI_FMT, tempreg,
12748 BFD_RELOC_MIPS_GOT_HI16);
12749 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
12750 mips_gp_register);
12751 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12752 BFD_RELOC_MIPS_GOT_LO16, tempreg);
12753 if (breg != 0)
12754 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12755 tempreg, tempreg, breg);
12756 macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg);
12757
12758 relax_switch ();
12759 offset_expr.X_add_number = expr1.X_add_number;
12760 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
12761 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
12762 if (breg != 0)
12763 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
12764 tempreg, tempreg, breg);
12765 macro_build (&offset_expr, s, fmt, op[0],
12766 BFD_RELOC_MIPS_GOT_OFST, tempreg);
12767 relax_end ();
12768 }
12769 else
12770 abort ();
12771
12772 break;
12773
12774 case M_JRADDIUSP:
12775 gas_assert (mips_opts.micromips);
12776 gas_assert (mips_opts.insn32);
12777 start_noreorder ();
12778 macro_build (NULL, "jr", "s", RA);
12779 expr1.X_add_number = op[0] << 2;
12780 macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
12781 end_noreorder ();
12782 break;
12783
12784 case M_JRC:
12785 gas_assert (mips_opts.micromips);
12786 gas_assert (mips_opts.insn32);
12787 macro_build (NULL, "jr", "s", op[0]);
12788 if (mips_opts.noreorder)
12789 macro_build (NULL, "nop", "");
12790 break;
12791
12792 case M_LI:
12793 case M_LI_S:
12794 load_register (op[0], &imm_expr, 0);
12795 break;
12796
12797 case M_DLI:
12798 load_register (op[0], &imm_expr, 1);
12799 break;
12800
12801 case M_LI_SS:
12802 if (imm_expr.X_op == O_constant)
12803 {
12804 used_at = 1;
12805 load_register (AT, &imm_expr, 0);
12806 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12807 break;
12808 }
12809 else
12810 {
12811 gas_assert (imm_expr.X_op == O_absent
12812 && offset_expr.X_op == O_symbol
12813 && strcmp (segment_name (S_GET_SEGMENT
12814 (offset_expr.X_add_symbol)),
12815 ".lit4") == 0
12816 && offset_expr.X_add_number == 0);
12817 macro_build (&offset_expr, "lwc1", "T,o(b)", op[0],
12818 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
12819 break;
12820 }
12821
12822 case M_LI_D:
12823 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12824 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12825 order 32 bits of the value and the low order 32 bits are either
12826 zero or in OFFSET_EXPR. */
12827 if (imm_expr.X_op == O_constant)
12828 {
12829 if (GPR_SIZE == 64)
12830 load_register (op[0], &imm_expr, 1);
12831 else
12832 {
12833 int hreg, lreg;
12834
12835 if (target_big_endian)
12836 {
12837 hreg = op[0];
12838 lreg = op[0] + 1;
12839 }
12840 else
12841 {
12842 hreg = op[0] + 1;
12843 lreg = op[0];
12844 }
12845
12846 if (hreg <= 31)
12847 load_register (hreg, &imm_expr, 0);
12848 if (lreg <= 31)
12849 {
12850 if (offset_expr.X_op == O_absent)
12851 move_register (lreg, 0);
12852 else
12853 {
12854 gas_assert (offset_expr.X_op == O_constant);
12855 load_register (lreg, &offset_expr, 0);
12856 }
12857 }
12858 }
12859 break;
12860 }
12861 gas_assert (imm_expr.X_op == O_absent);
12862
12863 /* We know that sym is in the .rdata section. First we get the
12864 upper 16 bits of the address. */
12865 if (mips_pic == NO_PIC)
12866 {
12867 macro_build_lui (&offset_expr, AT);
12868 used_at = 1;
12869 }
12870 else
12871 {
12872 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12873 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12874 used_at = 1;
12875 }
12876
12877 /* Now we load the register(s). */
12878 if (GPR_SIZE == 64)
12879 {
12880 used_at = 1;
12881 macro_build (&offset_expr, "ld", "t,o(b)", op[0],
12882 BFD_RELOC_LO16, AT);
12883 }
12884 else
12885 {
12886 used_at = 1;
12887 macro_build (&offset_expr, "lw", "t,o(b)", op[0],
12888 BFD_RELOC_LO16, AT);
12889 if (op[0] != RA)
12890 {
12891 /* FIXME: How in the world do we deal with the possible
12892 overflow here? */
12893 offset_expr.X_add_number += 4;
12894 macro_build (&offset_expr, "lw", "t,o(b)",
12895 op[0] + 1, BFD_RELOC_LO16, AT);
12896 }
12897 }
12898 break;
12899
12900 case M_LI_DD:
12901 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12902 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12903 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12904 the value and the low order 32 bits are either zero or in
12905 OFFSET_EXPR. */
12906 if (imm_expr.X_op == O_constant)
12907 {
12908 tempreg = ZERO;
12909 if (((FPR_SIZE == 64 && GPR_SIZE == 64)
12910 || !ISA_HAS_MXHC1 (mips_opts.isa))
12911 && imm_expr.X_add_number != 0)
12912 {
12913 used_at = 1;
12914 tempreg = AT;
12915 load_register (AT, &imm_expr, FPR_SIZE == 64);
12916 }
12917 if (FPR_SIZE == 64 && GPR_SIZE == 64)
12918 macro_build (NULL, "dmtc1", "t,S", tempreg, op[0]);
12919 else
12920 {
12921 if (!ISA_HAS_MXHC1 (mips_opts.isa))
12922 {
12923 if (FPR_SIZE != 32)
12924 as_bad (_("Unable to generate `%s' compliant code "
12925 "without mthc1"),
12926 (FPR_SIZE == 64) ? "fp64" : "fpxx");
12927 else
12928 macro_build (NULL, "mtc1", "t,G", tempreg, op[0] + 1);
12929 }
12930 if (offset_expr.X_op == O_absent)
12931 macro_build (NULL, "mtc1", "t,G", 0, op[0]);
12932 else
12933 {
12934 gas_assert (offset_expr.X_op == O_constant);
12935 load_register (AT, &offset_expr, 0);
12936 macro_build (NULL, "mtc1", "t,G", AT, op[0]);
12937 }
12938 if (ISA_HAS_MXHC1 (mips_opts.isa))
12939 {
12940 if (imm_expr.X_add_number != 0)
12941 {
12942 used_at = 1;
12943 tempreg = AT;
12944 load_register (AT, &imm_expr, 0);
12945 }
12946 macro_build (NULL, "mthc1", "t,G", tempreg, op[0]);
12947 }
12948 }
12949 break;
12950 }
12951
12952 gas_assert (imm_expr.X_op == O_absent
12953 && offset_expr.X_op == O_symbol
12954 && offset_expr.X_add_number == 0);
12955 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
12956 if (strcmp (s, ".lit8") == 0)
12957 {
12958 op[2] = mips_gp_register;
12959 offset_reloc[0] = BFD_RELOC_MIPS_LITERAL;
12960 offset_reloc[1] = BFD_RELOC_UNUSED;
12961 offset_reloc[2] = BFD_RELOC_UNUSED;
12962 }
12963 else
12964 {
12965 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
12966 used_at = 1;
12967 if (mips_pic != NO_PIC)
12968 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
12969 BFD_RELOC_MIPS_GOT16, mips_gp_register);
12970 else
12971 {
12972 /* FIXME: This won't work for a 64 bit address. */
12973 macro_build_lui (&offset_expr, AT);
12974 }
12975
12976 op[2] = AT;
12977 offset_reloc[0] = BFD_RELOC_LO16;
12978 offset_reloc[1] = BFD_RELOC_UNUSED;
12979 offset_reloc[2] = BFD_RELOC_UNUSED;
12980 }
12981 align = 8;
12982 /* Fall through. */
12983
12984 case M_L_DAB:
12985 /* The MIPS assembler seems to check for X_add_number not
12986 being double aligned and generating:
12987 lui at,%hi(foo+1)
12988 addu at,at,v1
12989 addiu at,at,%lo(foo+1)
12990 lwc1 f2,0(at)
12991 lwc1 f3,4(at)
12992 But, the resulting address is the same after relocation so why
12993 generate the extra instruction? */
12994 /* Itbl support may require additional care here. */
12995 coproc = 1;
12996 fmt = "T,o(b)";
12997 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
12998 {
12999 s = "ldc1";
13000 goto ld_st;
13001 }
13002 s = "lwc1";
13003 goto ldd_std;
13004
13005 case M_S_DAB:
13006 gas_assert (!mips_opts.micromips);
13007 /* Itbl support may require additional care here. */
13008 coproc = 1;
13009 fmt = "T,o(b)";
13010 if (CPU_HAS_LDC1_SDC1 (mips_opts.arch))
13011 {
13012 s = "sdc1";
13013 goto ld_st;
13014 }
13015 s = "swc1";
13016 goto ldd_std;
13017
13018 case M_LQ_AB:
13019 fmt = "t,o(b)";
13020 s = "lq";
13021 goto ld;
13022
13023 case M_SQ_AB:
13024 fmt = "t,o(b)";
13025 s = "sq";
13026 goto ld_st;
13027
13028 case M_LD_AB:
13029 fmt = "t,o(b)";
13030 if (GPR_SIZE == 64)
13031 {
13032 s = "ld";
13033 goto ld;
13034 }
13035 s = "lw";
13036 goto ldd_std;
13037
13038 case M_SD_AB:
13039 fmt = "t,o(b)";
13040 if (GPR_SIZE == 64)
13041 {
13042 s = "sd";
13043 goto ld_st;
13044 }
13045 s = "sw";
13046
13047 ldd_std:
13048 /* Even on a big endian machine $fn comes before $fn+1. We have
13049 to adjust when loading from memory. We set coproc if we must
13050 load $fn+1 first. */
13051 /* Itbl support may require additional care here. */
13052 if (!target_big_endian)
13053 coproc = 0;
13054
13055 breg = op[2];
13056 if (small_offset_p (0, align, 16))
13057 {
13058 ep = &offset_expr;
13059 if (!small_offset_p (4, align, 16))
13060 {
13061 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg,
13062 -1, offset_reloc[0], offset_reloc[1],
13063 offset_reloc[2]);
13064 expr1.X_add_number = 0;
13065 ep = &expr1;
13066 breg = AT;
13067 used_at = 1;
13068 offset_reloc[0] = BFD_RELOC_LO16;
13069 offset_reloc[1] = BFD_RELOC_UNUSED;
13070 offset_reloc[2] = BFD_RELOC_UNUSED;
13071 }
13072 if (strcmp (s, "lw") == 0 && op[0] == breg)
13073 {
13074 ep->X_add_number += 4;
13075 macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0],
13076 offset_reloc[1], offset_reloc[2], breg);
13077 ep->X_add_number -= 4;
13078 macro_build (ep, s, fmt, op[0], -1, offset_reloc[0],
13079 offset_reloc[1], offset_reloc[2], breg);
13080 }
13081 else
13082 {
13083 macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1,
13084 offset_reloc[0], offset_reloc[1], offset_reloc[2],
13085 breg);
13086 ep->X_add_number += 4;
13087 macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1,
13088 offset_reloc[0], offset_reloc[1], offset_reloc[2],
13089 breg);
13090 }
13091 break;
13092 }
13093
13094 if (offset_expr.X_op != O_symbol
13095 && offset_expr.X_op != O_constant)
13096 {
13097 as_bad (_("expression too complex"));
13098 offset_expr.X_op = O_constant;
13099 }
13100
13101 if (HAVE_32BIT_ADDRESSES
13102 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
13103 {
13104 as_bad (_("number (0x%" PRIx64 ") larger than 32 bits"),
13105 offset_expr.X_add_number);
13106 }
13107
13108 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
13109 {
13110 /* If this is a reference to a GP relative symbol, we want
13111 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
13112 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
13113 If we have a base register, we use this
13114 addu $at,$breg,$gp
13115 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
13116 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
13117 If this is not a GP relative symbol, we want
13118 lui $at,<sym> (BFD_RELOC_HI16_S)
13119 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13120 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13121 If there is a base register, we add it to $at after the
13122 lui instruction. If there is a constant, we always use
13123 the last case. */
13124 if (offset_expr.X_op == O_symbol
13125 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
13126 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
13127 {
13128 relax_start (offset_expr.X_add_symbol);
13129 if (breg == 0)
13130 {
13131 tempreg = mips_gp_register;
13132 }
13133 else
13134 {
13135 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13136 AT, breg, mips_gp_register);
13137 tempreg = AT;
13138 used_at = 1;
13139 }
13140
13141 /* Itbl support may require additional care here. */
13142 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
13143 BFD_RELOC_GPREL16, tempreg);
13144 offset_expr.X_add_number += 4;
13145
13146 /* Set mips_optimize to 2 to avoid inserting an
13147 undesired nop. */
13148 hold_mips_optimize = mips_optimize;
13149 mips_optimize = 2;
13150 /* Itbl support may require additional care here. */
13151 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
13152 BFD_RELOC_GPREL16, tempreg);
13153 mips_optimize = hold_mips_optimize;
13154
13155 relax_switch ();
13156
13157 offset_expr.X_add_number -= 4;
13158 }
13159 used_at = 1;
13160 if (offset_high_part (offset_expr.X_add_number, 16)
13161 != offset_high_part (offset_expr.X_add_number + 4, 16))
13162 {
13163 load_address (AT, &offset_expr, &used_at);
13164 offset_expr.X_op = O_constant;
13165 offset_expr.X_add_number = 0;
13166 }
13167 else
13168 macro_build_lui (&offset_expr, AT);
13169 if (breg != 0)
13170 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
13171 /* Itbl support may require additional care here. */
13172 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
13173 BFD_RELOC_LO16, AT);
13174 /* FIXME: How do we handle overflow here? */
13175 offset_expr.X_add_number += 4;
13176 /* Itbl support may require additional care here. */
13177 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
13178 BFD_RELOC_LO16, AT);
13179 if (mips_relax.sequence)
13180 relax_end ();
13181 }
13182 else if (!mips_big_got)
13183 {
13184 /* If this is a reference to an external symbol, we want
13185 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13186 nop
13187 <op> op[0],0($at)
13188 <op> op[0]+1,4($at)
13189 Otherwise we want
13190 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13191 nop
13192 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13193 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13194 If there is a base register we add it to $at before the
13195 lwc1 instructions. If there is a constant we include it
13196 in the lwc1 instructions. */
13197 used_at = 1;
13198 expr1.X_add_number = offset_expr.X_add_number;
13199 if (expr1.X_add_number < -0x8000
13200 || expr1.X_add_number >= 0x8000 - 4)
13201 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13202 load_got_offset (AT, &offset_expr);
13203 load_delay_nop ();
13204 if (breg != 0)
13205 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
13206
13207 /* Set mips_optimize to 2 to avoid inserting an undesired
13208 nop. */
13209 hold_mips_optimize = mips_optimize;
13210 mips_optimize = 2;
13211
13212 /* Itbl support may require additional care here. */
13213 relax_start (offset_expr.X_add_symbol);
13214 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
13215 BFD_RELOC_LO16, AT);
13216 expr1.X_add_number += 4;
13217 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
13218 BFD_RELOC_LO16, AT);
13219 relax_switch ();
13220 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
13221 BFD_RELOC_LO16, AT);
13222 offset_expr.X_add_number += 4;
13223 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
13224 BFD_RELOC_LO16, AT);
13225 relax_end ();
13226
13227 mips_optimize = hold_mips_optimize;
13228 }
13229 else if (mips_big_got)
13230 {
13231 int gpdelay;
13232
13233 /* If this is a reference to an external symbol, we want
13234 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13235 addu $at,$at,$gp
13236 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13237 nop
13238 <op> op[0],0($at)
13239 <op> op[0]+1,4($at)
13240 Otherwise we want
13241 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13242 nop
13243 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13244 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13245 If there is a base register we add it to $at before the
13246 lwc1 instructions. If there is a constant we include it
13247 in the lwc1 instructions. */
13248 used_at = 1;
13249 expr1.X_add_number = offset_expr.X_add_number;
13250 offset_expr.X_add_number = 0;
13251 if (expr1.X_add_number < -0x8000
13252 || expr1.X_add_number >= 0x8000 - 4)
13253 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13254 gpdelay = reg_needs_delay (mips_gp_register);
13255 relax_start (offset_expr.X_add_symbol);
13256 macro_build (&offset_expr, "lui", LUI_FMT,
13257 AT, BFD_RELOC_MIPS_GOT_HI16);
13258 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
13259 AT, AT, mips_gp_register);
13260 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
13261 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
13262 load_delay_nop ();
13263 if (breg != 0)
13264 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
13265 /* Itbl support may require additional care here. */
13266 macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0],
13267 BFD_RELOC_LO16, AT);
13268 expr1.X_add_number += 4;
13269
13270 /* Set mips_optimize to 2 to avoid inserting an undesired
13271 nop. */
13272 hold_mips_optimize = mips_optimize;
13273 mips_optimize = 2;
13274 /* Itbl support may require additional care here. */
13275 macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1,
13276 BFD_RELOC_LO16, AT);
13277 mips_optimize = hold_mips_optimize;
13278 expr1.X_add_number -= 4;
13279
13280 relax_switch ();
13281 offset_expr.X_add_number = expr1.X_add_number;
13282 if (gpdelay)
13283 macro_build (NULL, "nop", "");
13284 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
13285 BFD_RELOC_MIPS_GOT16, mips_gp_register);
13286 load_delay_nop ();
13287 if (breg != 0)
13288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
13289 /* Itbl support may require additional care here. */
13290 macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0],
13291 BFD_RELOC_LO16, AT);
13292 offset_expr.X_add_number += 4;
13293
13294 /* Set mips_optimize to 2 to avoid inserting an undesired
13295 nop. */
13296 hold_mips_optimize = mips_optimize;
13297 mips_optimize = 2;
13298 /* Itbl support may require additional care here. */
13299 macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1,
13300 BFD_RELOC_LO16, AT);
13301 mips_optimize = hold_mips_optimize;
13302 relax_end ();
13303 }
13304 else
13305 abort ();
13306
13307 break;
13308
13309 case M_SAA_AB:
13310 s = "saa";
13311 goto saa_saad;
13312 case M_SAAD_AB:
13313 s = "saad";
13314 saa_saad:
13315 gas_assert (!mips_opts.micromips);
13316 offbits = 0;
13317 fmt = "t,(b)";
13318 goto ld_st;
13319
13320 /* New code added to support COPZ instructions.
13321 This code builds table entries out of the macros in mip_opcodes.
13322 R4000 uses interlocks to handle coproc delays.
13323 Other chips (like the R3000) require nops to be inserted for delays.
13324
13325 FIXME: Currently, we require that the user handle delays.
13326 In order to fill delay slots for non-interlocked chips,
13327 we must have a way to specify delays based on the coprocessor.
13328 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13329 What are the side-effects of the cop instruction?
13330 What cache support might we have and what are its effects?
13331 Both coprocessor & memory require delays. how long???
13332 What registers are read/set/modified?
13333
13334 If an itbl is provided to interpret cop instructions,
13335 this knowledge can be encoded in the itbl spec. */
13336
13337 case M_COP0:
13338 s = "c0";
13339 goto copz;
13340 case M_COP1:
13341 s = "c1";
13342 goto copz;
13343 case M_COP2:
13344 s = "c2";
13345 goto copz;
13346 case M_COP3:
13347 s = "c3";
13348 copz:
13349 gas_assert (!mips_opts.micromips);
13350 /* For now we just do C (same as Cz). The parameter will be
13351 stored in insn_opcode by mips_ip. */
13352 macro_build (NULL, s, "C", (int) ip->insn_opcode);
13353 break;
13354
13355 case M_MOVE:
13356 move_register (op[0], op[1]);
13357 break;
13358
13359 case M_MOVEP:
13360 gas_assert (mips_opts.micromips);
13361 gas_assert (mips_opts.insn32);
13362 move_register (micromips_to_32_reg_h_map1[op[0]],
13363 micromips_to_32_reg_m_map[op[1]]);
13364 move_register (micromips_to_32_reg_h_map2[op[0]],
13365 micromips_to_32_reg_n_map[op[2]]);
13366 break;
13367
13368 case M_DMUL:
13369 dbl = 1;
13370 /* Fall through. */
13371 case M_MUL:
13372 if (mips_opts.arch == CPU_R5900)
13373 macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1],
13374 op[2]);
13375 else
13376 {
13377 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]);
13378 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13379 }
13380 break;
13381
13382 case M_DMUL_I:
13383 dbl = 1;
13384 /* Fall through. */
13385 case M_MUL_I:
13386 /* The MIPS assembler some times generates shifts and adds. I'm
13387 not trying to be that fancy. GCC should do this for us
13388 anyway. */
13389 used_at = 1;
13390 load_register (AT, &imm_expr, dbl);
13391 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT);
13392 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13393 break;
13394
13395 case M_DMULO_I:
13396 dbl = 1;
13397 /* Fall through. */
13398 case M_MULO_I:
13399 imm = 1;
13400 goto do_mulo;
13401
13402 case M_DMULO:
13403 dbl = 1;
13404 /* Fall through. */
13405 case M_MULO:
13406 do_mulo:
13407 start_noreorder ();
13408 used_at = 1;
13409 if (imm)
13410 load_register (AT, &imm_expr, dbl);
13411 macro_build (NULL, dbl ? "dmult" : "mult", "s,t",
13412 op[1], imm ? AT : op[2]);
13413 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13414 macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31);
13415 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13416 if (mips_trap)
13417 macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6);
13418 else
13419 {
13420 if (mips_opts.micromips)
13421 micromips_label_expr (&label_expr);
13422 else
13423 label_expr.X_add_number = 8;
13424 macro_build (&label_expr, "beq", "s,t,p", op[0], AT);
13425 macro_build (NULL, "nop", "");
13426 macro_build (NULL, "break", BRK_FMT, 6);
13427 if (mips_opts.micromips)
13428 micromips_add_label ();
13429 }
13430 end_noreorder ();
13431 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13432 break;
13433
13434 case M_DMULOU_I:
13435 dbl = 1;
13436 /* Fall through. */
13437 case M_MULOU_I:
13438 imm = 1;
13439 goto do_mulou;
13440
13441 case M_DMULOU:
13442 dbl = 1;
13443 /* Fall through. */
13444 case M_MULOU:
13445 do_mulou:
13446 start_noreorder ();
13447 used_at = 1;
13448 if (imm)
13449 load_register (AT, &imm_expr, dbl);
13450 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
13451 op[1], imm ? AT : op[2]);
13452 macro_build (NULL, "mfhi", MFHL_FMT, AT);
13453 macro_build (NULL, "mflo", MFHL_FMT, op[0]);
13454 if (mips_trap)
13455 macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6);
13456 else
13457 {
13458 if (mips_opts.micromips)
13459 micromips_label_expr (&label_expr);
13460 else
13461 label_expr.X_add_number = 8;
13462 macro_build (&label_expr, "beq", "s,t,p", AT, ZERO);
13463 macro_build (NULL, "nop", "");
13464 macro_build (NULL, "break", BRK_FMT, 6);
13465 if (mips_opts.micromips)
13466 micromips_add_label ();
13467 }
13468 end_noreorder ();
13469 break;
13470
13471 case M_DROL:
13472 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13473 {
13474 if (op[0] == op[1])
13475 {
13476 tempreg = AT;
13477 used_at = 1;
13478 }
13479 else
13480 tempreg = op[0];
13481 macro_build (NULL, "dnegu", "d,w", tempreg, op[2]);
13482 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg);
13483 break;
13484 }
13485 used_at = 1;
13486 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13487 macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT);
13488 macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]);
13489 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13490 break;
13491
13492 case M_ROL:
13493 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13494 {
13495 if (op[0] == op[1])
13496 {
13497 tempreg = AT;
13498 used_at = 1;
13499 }
13500 else
13501 tempreg = op[0];
13502 macro_build (NULL, "negu", "d,w", tempreg, op[2]);
13503 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg);
13504 break;
13505 }
13506 used_at = 1;
13507 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13508 macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT);
13509 macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]);
13510 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13511 break;
13512
13513 case M_DROL_I:
13514 {
13515 unsigned int rot;
13516 const char *l;
13517 const char *rr;
13518
13519 rot = imm_expr.X_add_number & 0x3f;
13520 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13521 {
13522 rot = (64 - rot) & 0x3f;
13523 if (rot >= 32)
13524 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13525 else
13526 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13527 break;
13528 }
13529 if (rot == 0)
13530 {
13531 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13532 break;
13533 }
13534 l = (rot < 0x20) ? "dsll" : "dsll32";
13535 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
13536 rot &= 0x1f;
13537 used_at = 1;
13538 macro_build (NULL, l, SHFT_FMT, AT, op[1], rot);
13539 macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13540 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13541 }
13542 break;
13543
13544 case M_ROL_I:
13545 {
13546 unsigned int rot;
13547
13548 rot = imm_expr.X_add_number & 0x1f;
13549 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13550 {
13551 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1],
13552 (32 - rot) & 0x1f);
13553 break;
13554 }
13555 if (rot == 0)
13556 {
13557 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13558 break;
13559 }
13560 used_at = 1;
13561 macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot);
13562 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13563 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13564 }
13565 break;
13566
13567 case M_DROR:
13568 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13569 {
13570 macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]);
13571 break;
13572 }
13573 used_at = 1;
13574 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]);
13575 macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT);
13576 macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]);
13577 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13578 break;
13579
13580 case M_ROR:
13581 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13582 {
13583 macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]);
13584 break;
13585 }
13586 used_at = 1;
13587 macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]);
13588 macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT);
13589 macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]);
13590 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13591 break;
13592
13593 case M_DROR_I:
13594 {
13595 unsigned int rot;
13596 const char *l;
13597 const char *rr;
13598
13599 rot = imm_expr.X_add_number & 0x3f;
13600 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
13601 {
13602 if (rot >= 32)
13603 macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32);
13604 else
13605 macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot);
13606 break;
13607 }
13608 if (rot == 0)
13609 {
13610 macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0);
13611 break;
13612 }
13613 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
13614 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
13615 rot &= 0x1f;
13616 used_at = 1;
13617 macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot);
13618 macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13619 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13620 }
13621 break;
13622
13623 case M_ROR_I:
13624 {
13625 unsigned int rot;
13626
13627 rot = imm_expr.X_add_number & 0x1f;
13628 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13629 {
13630 macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot);
13631 break;
13632 }
13633 if (rot == 0)
13634 {
13635 macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0);
13636 break;
13637 }
13638 used_at = 1;
13639 macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot);
13640 macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f);
13641 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
13642 }
13643 break;
13644
13645 case M_SEQ:
13646 if (op[1] == 0)
13647 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16);
13648 else if (op[2] == 0)
13649 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13650 else
13651 {
13652 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13653 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13654 }
13655 break;
13656
13657 case M_SEQ_I:
13658 if (imm_expr.X_add_number == 0)
13659 {
13660 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13661 break;
13662 }
13663 if (op[1] == 0)
13664 {
13665 as_warn (_("instruction %s: result is always false"),
13666 ip->insn_mo->name);
13667 move_register (op[0], 0);
13668 break;
13669 }
13670 if (CPU_HAS_SEQ (mips_opts.arch)
13671 && -512 <= imm_expr.X_add_number
13672 && imm_expr.X_add_number < 512)
13673 {
13674 macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1],
13675 (int) imm_expr.X_add_number);
13676 break;
13677 }
13678 if (imm_expr.X_add_number >= 0
13679 && imm_expr.X_add_number < 0x10000)
13680 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16);
13681 else if (imm_expr.X_add_number > -0x8000
13682 && imm_expr.X_add_number < 0)
13683 {
13684 imm_expr.X_add_number = -imm_expr.X_add_number;
13685 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13686 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13687 }
13688 else if (CPU_HAS_SEQ (mips_opts.arch))
13689 {
13690 used_at = 1;
13691 load_register (AT, &imm_expr, GPR_SIZE == 64);
13692 macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT);
13693 break;
13694 }
13695 else
13696 {
13697 load_register (AT, &imm_expr, GPR_SIZE == 64);
13698 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13699 used_at = 1;
13700 }
13701 macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16);
13702 break;
13703
13704 case M_SGE: /* X >= Y <==> not (X < Y) */
13705 s = "slt";
13706 goto sge;
13707 case M_SGEU:
13708 s = "sltu";
13709 sge:
13710 macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]);
13711 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13712 break;
13713
13714 case M_SGE_I: /* X >= I <==> not (X < I). */
13715 case M_SGEU_I:
13716 if (imm_expr.X_add_number >= -0x8000
13717 && imm_expr.X_add_number < 0x8000)
13718 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
13719 op[0], op[1], BFD_RELOC_LO16);
13720 else
13721 {
13722 load_register (AT, &imm_expr, GPR_SIZE == 64);
13723 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
13724 op[0], op[1], AT);
13725 used_at = 1;
13726 }
13727 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13728 break;
13729
13730 case M_SGT: /* X > Y <==> Y < X. */
13731 s = "slt";
13732 goto sgt;
13733 case M_SGTU:
13734 s = "sltu";
13735 sgt:
13736 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13737 break;
13738
13739 case M_SGT_I: /* X > I <==> I < X. */
13740 s = "slt";
13741 goto sgti;
13742 case M_SGTU_I:
13743 s = "sltu";
13744 sgti:
13745 used_at = 1;
13746 load_register (AT, &imm_expr, GPR_SIZE == 64);
13747 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13748 break;
13749
13750 case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X). */
13751 s = "slt";
13752 goto sle;
13753 case M_SLEU:
13754 s = "sltu";
13755 sle:
13756 macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]);
13757 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13758 break;
13759
13760 case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */
13761 s = "slt";
13762 goto slei;
13763 case M_SLEU_I:
13764 s = "sltu";
13765 slei:
13766 used_at = 1;
13767 load_register (AT, &imm_expr, GPR_SIZE == 64);
13768 macro_build (NULL, s, "d,v,t", op[0], AT, op[1]);
13769 macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16);
13770 break;
13771
13772 case M_SLT_I:
13773 if (imm_expr.X_add_number >= -0x8000
13774 && imm_expr.X_add_number < 0x8000)
13775 {
13776 macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1],
13777 BFD_RELOC_LO16);
13778 break;
13779 }
13780 used_at = 1;
13781 load_register (AT, &imm_expr, GPR_SIZE == 64);
13782 macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT);
13783 break;
13784
13785 case M_SLTU_I:
13786 if (imm_expr.X_add_number >= -0x8000
13787 && imm_expr.X_add_number < 0x8000)
13788 {
13789 macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1],
13790 BFD_RELOC_LO16);
13791 break;
13792 }
13793 used_at = 1;
13794 load_register (AT, &imm_expr, GPR_SIZE == 64);
13795 macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT);
13796 break;
13797
13798 case M_SNE:
13799 if (op[1] == 0)
13800 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]);
13801 else if (op[2] == 0)
13802 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13803 else
13804 {
13805 macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]);
13806 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13807 }
13808 break;
13809
13810 case M_SNE_I:
13811 if (imm_expr.X_add_number == 0)
13812 {
13813 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]);
13814 break;
13815 }
13816 if (op[1] == 0)
13817 {
13818 as_warn (_("instruction %s: result is always true"),
13819 ip->insn_mo->name);
13820 macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j",
13821 op[0], 0, BFD_RELOC_LO16);
13822 break;
13823 }
13824 if (CPU_HAS_SEQ (mips_opts.arch)
13825 && -512 <= imm_expr.X_add_number
13826 && imm_expr.X_add_number < 512)
13827 {
13828 macro_build (NULL, "snei", "t,r,+Q", op[0], op[1],
13829 (int) imm_expr.X_add_number);
13830 break;
13831 }
13832 if (imm_expr.X_add_number >= 0
13833 && imm_expr.X_add_number < 0x10000)
13834 {
13835 macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1],
13836 BFD_RELOC_LO16);
13837 }
13838 else if (imm_expr.X_add_number > -0x8000
13839 && imm_expr.X_add_number < 0)
13840 {
13841 imm_expr.X_add_number = -imm_expr.X_add_number;
13842 macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu",
13843 "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13844 }
13845 else if (CPU_HAS_SEQ (mips_opts.arch))
13846 {
13847 used_at = 1;
13848 load_register (AT, &imm_expr, GPR_SIZE == 64);
13849 macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT);
13850 break;
13851 }
13852 else
13853 {
13854 load_register (AT, &imm_expr, GPR_SIZE == 64);
13855 macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT);
13856 used_at = 1;
13857 }
13858 macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]);
13859 break;
13860
13861 case M_SUB_I:
13862 s = "addi";
13863 s2 = "sub";
13864 if (ISA_IS_R6 (mips_opts.isa))
13865 goto do_subi_i;
13866 else
13867 goto do_subi;
13868 case M_SUBU_I:
13869 s = "addiu";
13870 s2 = "subu";
13871 goto do_subi;
13872 case M_DSUB_I:
13873 dbl = 1;
13874 s = "daddi";
13875 s2 = "dsub";
13876 if (!mips_opts.micromips && !ISA_IS_R6 (mips_opts.isa))
13877 goto do_subi;
13878 if (imm_expr.X_add_number > -0x200
13879 && imm_expr.X_add_number <= 0x200
13880 && !ISA_IS_R6 (mips_opts.isa))
13881 {
13882 macro_build (NULL, s, "t,r,.", op[0], op[1],
13883 (int) -imm_expr.X_add_number);
13884 break;
13885 }
13886 goto do_subi_i;
13887 case M_DSUBU_I:
13888 dbl = 1;
13889 s = "daddiu";
13890 s2 = "dsubu";
13891 do_subi:
13892 if (imm_expr.X_add_number > -0x8000
13893 && imm_expr.X_add_number <= 0x8000)
13894 {
13895 imm_expr.X_add_number = -imm_expr.X_add_number;
13896 macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16);
13897 break;
13898 }
13899 do_subi_i:
13900 used_at = 1;
13901 load_register (AT, &imm_expr, dbl);
13902 macro_build (NULL, s2, "d,v,t", op[0], op[1], AT);
13903 break;
13904
13905 case M_TEQ_I:
13906 s = "teq";
13907 goto trap;
13908 case M_TGE_I:
13909 s = "tge";
13910 goto trap;
13911 case M_TGEU_I:
13912 s = "tgeu";
13913 goto trap;
13914 case M_TLT_I:
13915 s = "tlt";
13916 goto trap;
13917 case M_TLTU_I:
13918 s = "tltu";
13919 goto trap;
13920 case M_TNE_I:
13921 s = "tne";
13922 trap:
13923 used_at = 1;
13924 load_register (AT, &imm_expr, GPR_SIZE == 64);
13925 macro_build (NULL, s, "s,t", op[0], AT);
13926 break;
13927
13928 case M_TRUNCWS:
13929 case M_TRUNCWD:
13930 gas_assert (!mips_opts.micromips);
13931 gas_assert (mips_opts.isa == ISA_MIPS1);
13932 used_at = 1;
13933
13934 /*
13935 * Is the double cfc1 instruction a bug in the mips assembler;
13936 * or is there a reason for it?
13937 */
13938 start_noreorder ();
13939 macro_build (NULL, "cfc1", "t,g", op[2], FCSR);
13940 macro_build (NULL, "cfc1", "t,g", op[2], FCSR);
13941 macro_build (NULL, "nop", "");
13942 expr1.X_add_number = 3;
13943 macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
13944 expr1.X_add_number = 2;
13945 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
13946 macro_build (NULL, "ctc1", "t,g", AT, FCSR);
13947 macro_build (NULL, "nop", "");
13948 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
13949 op[0], op[1]);
13950 macro_build (NULL, "ctc1", "t,g", op[2], FCSR);
13951 macro_build (NULL, "nop", "");
13952 end_noreorder ();
13953 break;
13954
13955 case M_ULH_AB:
13956 s = "lb";
13957 s2 = "lbu";
13958 off = 1;
13959 goto uld_st;
13960 case M_ULHU_AB:
13961 s = "lbu";
13962 s2 = "lbu";
13963 off = 1;
13964 goto uld_st;
13965 case M_ULW_AB:
13966 s = "lwl";
13967 s2 = "lwr";
13968 offbits = (mips_opts.micromips ? 12 : 16);
13969 off = 3;
13970 goto uld_st;
13971 case M_ULD_AB:
13972 s = "ldl";
13973 s2 = "ldr";
13974 offbits = (mips_opts.micromips ? 12 : 16);
13975 off = 7;
13976 goto uld_st;
13977 case M_USH_AB:
13978 s = "sb";
13979 s2 = "sb";
13980 off = 1;
13981 ust = 1;
13982 goto uld_st;
13983 case M_USW_AB:
13984 s = "swl";
13985 s2 = "swr";
13986 offbits = (mips_opts.micromips ? 12 : 16);
13987 off = 3;
13988 ust = 1;
13989 goto uld_st;
13990 case M_USD_AB:
13991 s = "sdl";
13992 s2 = "sdr";
13993 offbits = (mips_opts.micromips ? 12 : 16);
13994 off = 7;
13995 ust = 1;
13996
13997 uld_st:
13998 breg = op[2];
13999 large_offset = !small_offset_p (off, align, offbits);
14000 ep = &offset_expr;
14001 expr1.X_add_number = 0;
14002 if (large_offset)
14003 {
14004 used_at = 1;
14005 tempreg = AT;
14006 if (small_offset_p (0, align, 16))
14007 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1,
14008 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
14009 else
14010 {
14011 load_address (tempreg, ep, &used_at);
14012 if (breg != 0)
14013 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
14014 tempreg, tempreg, breg);
14015 }
14016 offset_reloc[0] = BFD_RELOC_LO16;
14017 offset_reloc[1] = BFD_RELOC_UNUSED;
14018 offset_reloc[2] = BFD_RELOC_UNUSED;
14019 breg = tempreg;
14020 tempreg = op[0];
14021 ep = &expr1;
14022 }
14023 else if (!ust && op[0] == breg)
14024 {
14025 used_at = 1;
14026 tempreg = AT;
14027 }
14028 else
14029 tempreg = op[0];
14030
14031 if (off == 1)
14032 goto ulh_sh;
14033
14034 if (!target_big_endian)
14035 ep->X_add_number += off;
14036 if (offbits == 12)
14037 macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg);
14038 else
14039 macro_build (ep, s, "t,o(b)", tempreg, -1,
14040 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
14041
14042 if (!target_big_endian)
14043 ep->X_add_number -= off;
14044 else
14045 ep->X_add_number += off;
14046 if (offbits == 12)
14047 macro_build (NULL, s2, "t,~(b)",
14048 tempreg, (int) ep->X_add_number, breg);
14049 else
14050 macro_build (ep, s2, "t,o(b)", tempreg, -1,
14051 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
14052
14053 /* If necessary, move the result in tempreg to the final destination. */
14054 if (!ust && op[0] != tempreg)
14055 {
14056 /* Protect second load's delay slot. */
14057 load_delay_nop ();
14058 move_register (op[0], tempreg);
14059 }
14060 break;
14061
14062 ulh_sh:
14063 used_at = 1;
14064 if (target_big_endian == ust)
14065 ep->X_add_number += off;
14066 tempreg = ust || large_offset ? op[0] : AT;
14067 macro_build (ep, s, "t,o(b)", tempreg, -1,
14068 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
14069
14070 /* For halfword transfers we need a temporary register to shuffle
14071 bytes. Unfortunately for M_USH_A we have none available before
14072 the next store as AT holds the base address. We deal with this
14073 case by clobbering TREG and then restoring it as with ULH. */
14074 tempreg = ust == large_offset ? op[0] : AT;
14075 if (ust)
14076 macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8);
14077
14078 if (target_big_endian == ust)
14079 ep->X_add_number -= off;
14080 else
14081 ep->X_add_number += off;
14082 macro_build (ep, s2, "t,o(b)", tempreg, -1,
14083 offset_reloc[0], offset_reloc[1], offset_reloc[2], breg);
14084
14085 /* For M_USH_A re-retrieve the LSB. */
14086 if (ust && large_offset)
14087 {
14088 if (target_big_endian)
14089 ep->X_add_number += off;
14090 else
14091 ep->X_add_number -= off;
14092 macro_build (&expr1, "lbu", "t,o(b)", AT, -1,
14093 offset_reloc[0], offset_reloc[1], offset_reloc[2], AT);
14094 }
14095 /* For ULH and M_USH_A OR the LSB in. */
14096 if (!ust || large_offset)
14097 {
14098 tempreg = !large_offset ? AT : op[0];
14099 macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8);
14100 macro_build (NULL, "or", "d,v,t", op[0], op[0], AT);
14101 }
14102 break;
14103
14104 default:
14105 /* FIXME: Check if this is one of the itbl macros, since they
14106 are added dynamically. */
14107 as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
14108 break;
14109 }
14110 if (!mips_opts.at && used_at)
14111 as_bad (_("macro used $at after \".set noat\""));
14112 }
14113
14114 /* Implement macros in mips16 mode. */
14115
14116 static void
mips16_macro(struct mips_cl_insn * ip)14117 mips16_macro (struct mips_cl_insn *ip)
14118 {
14119 const struct mips_operand_array *operands;
14120 int mask;
14121 int tmp;
14122 expressionS expr1;
14123 int dbl;
14124 const char *s, *s2, *s3;
14125 unsigned int op[MAX_OPERANDS];
14126 unsigned int i;
14127
14128 mask = ip->insn_mo->mask;
14129
14130 operands = insn_operands (ip);
14131 for (i = 0; i < MAX_OPERANDS; i++)
14132 if (operands->operand[i])
14133 op[i] = insn_extract_operand (ip, operands->operand[i]);
14134 else
14135 op[i] = -1;
14136
14137 expr1.X_op = O_constant;
14138 expr1.X_op_symbol = NULL;
14139 expr1.X_add_symbol = NULL;
14140 expr1.X_add_number = 1;
14141
14142 dbl = 0;
14143
14144 switch (mask)
14145 {
14146 default:
14147 abort ();
14148
14149 case M_DDIV_3:
14150 dbl = 1;
14151 /* Fall through. */
14152 case M_DIV_3:
14153 s = "mflo";
14154 goto do_div3;
14155 case M_DREM_3:
14156 dbl = 1;
14157 /* Fall through. */
14158 case M_REM_3:
14159 s = "mfhi";
14160 do_div3:
14161 start_noreorder ();
14162 macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]);
14163 expr1.X_add_number = 2;
14164 macro_build (&expr1, "bnez", "x,p", op[2]);
14165 macro_build (NULL, "break", "6", 7);
14166
14167 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14168 since that causes an overflow. We should do that as well,
14169 but I don't see how to do the comparisons without a temporary
14170 register. */
14171 end_noreorder ();
14172 macro_build (NULL, s, "x", op[0]);
14173 break;
14174
14175 case M_DIVU_3:
14176 s = "divu";
14177 s2 = "mflo";
14178 goto do_divu3;
14179 case M_REMU_3:
14180 s = "divu";
14181 s2 = "mfhi";
14182 goto do_divu3;
14183 case M_DDIVU_3:
14184 s = "ddivu";
14185 s2 = "mflo";
14186 goto do_divu3;
14187 case M_DREMU_3:
14188 s = "ddivu";
14189 s2 = "mfhi";
14190 do_divu3:
14191 start_noreorder ();
14192 macro_build (NULL, s, ".,x,y", op[1], op[2]);
14193 expr1.X_add_number = 2;
14194 macro_build (&expr1, "bnez", "x,p", op[2]);
14195 macro_build (NULL, "break", "6", 7);
14196 end_noreorder ();
14197 macro_build (NULL, s2, "x", op[0]);
14198 break;
14199
14200 case M_DMUL:
14201 dbl = 1;
14202 /* Fall through. */
14203 case M_MUL:
14204 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]);
14205 macro_build (NULL, "mflo", "x", op[0]);
14206 break;
14207
14208 case M_DSUBU_I:
14209 dbl = 1;
14210 goto do_subu;
14211 case M_SUBU_I:
14212 do_subu:
14213 imm_expr.X_add_number = -imm_expr.X_add_number;
14214 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]);
14215 break;
14216
14217 case M_SUBU_I_2:
14218 imm_expr.X_add_number = -imm_expr.X_add_number;
14219 macro_build (&imm_expr, "addiu", "x,k", op[0]);
14220 break;
14221
14222 case M_DSUBU_I_2:
14223 imm_expr.X_add_number = -imm_expr.X_add_number;
14224 macro_build (&imm_expr, "daddiu", "y,j", op[0]);
14225 break;
14226
14227 case M_BEQ:
14228 s = "cmp";
14229 s2 = "bteqz";
14230 goto do_branch;
14231 case M_BNE:
14232 s = "cmp";
14233 s2 = "btnez";
14234 goto do_branch;
14235 case M_BLT:
14236 s = "slt";
14237 s2 = "btnez";
14238 goto do_branch;
14239 case M_BLTU:
14240 s = "sltu";
14241 s2 = "btnez";
14242 goto do_branch;
14243 case M_BLE:
14244 s = "slt";
14245 s2 = "bteqz";
14246 goto do_reverse_branch;
14247 case M_BLEU:
14248 s = "sltu";
14249 s2 = "bteqz";
14250 goto do_reverse_branch;
14251 case M_BGE:
14252 s = "slt";
14253 s2 = "bteqz";
14254 goto do_branch;
14255 case M_BGEU:
14256 s = "sltu";
14257 s2 = "bteqz";
14258 goto do_branch;
14259 case M_BGT:
14260 s = "slt";
14261 s2 = "btnez";
14262 goto do_reverse_branch;
14263 case M_BGTU:
14264 s = "sltu";
14265 s2 = "btnez";
14266
14267 do_reverse_branch:
14268 tmp = op[1];
14269 op[1] = op[0];
14270 op[0] = tmp;
14271
14272 do_branch:
14273 macro_build (NULL, s, "x,y", op[0], op[1]);
14274 macro_build (&offset_expr, s2, "p");
14275 break;
14276
14277 case M_BEQ_I:
14278 s = "cmpi";
14279 s2 = "bteqz";
14280 s3 = "x,U";
14281 goto do_branch_i;
14282 case M_BNE_I:
14283 s = "cmpi";
14284 s2 = "btnez";
14285 s3 = "x,U";
14286 goto do_branch_i;
14287 case M_BLT_I:
14288 s = "slti";
14289 s2 = "btnez";
14290 s3 = "x,8";
14291 goto do_branch_i;
14292 case M_BLTU_I:
14293 s = "sltiu";
14294 s2 = "btnez";
14295 s3 = "x,8";
14296 goto do_branch_i;
14297 case M_BLE_I:
14298 s = "slti";
14299 s2 = "btnez";
14300 s3 = "x,8";
14301 goto do_addone_branch_i;
14302 case M_BLEU_I:
14303 s = "sltiu";
14304 s2 = "btnez";
14305 s3 = "x,8";
14306 goto do_addone_branch_i;
14307 case M_BGE_I:
14308 s = "slti";
14309 s2 = "bteqz";
14310 s3 = "x,8";
14311 goto do_branch_i;
14312 case M_BGEU_I:
14313 s = "sltiu";
14314 s2 = "bteqz";
14315 s3 = "x,8";
14316 goto do_branch_i;
14317 case M_BGT_I:
14318 s = "slti";
14319 s2 = "bteqz";
14320 s3 = "x,8";
14321 goto do_addone_branch_i;
14322 case M_BGTU_I:
14323 s = "sltiu";
14324 s2 = "bteqz";
14325 s3 = "x,8";
14326
14327 do_addone_branch_i:
14328 ++imm_expr.X_add_number;
14329
14330 do_branch_i:
14331 macro_build (&imm_expr, s, s3, op[0]);
14332 macro_build (&offset_expr, s2, "p");
14333 break;
14334
14335 case M_ABS:
14336 expr1.X_add_number = 0;
14337 macro_build (&expr1, "slti", "x,8", op[1]);
14338 if (op[0] != op[1])
14339 macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]);
14340 expr1.X_add_number = 2;
14341 macro_build (&expr1, "bteqz", "p");
14342 macro_build (NULL, "neg", "x,w", op[0], op[0]);
14343 break;
14344 }
14345 }
14346
14347 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14348 opcode bits in *OPCODE_EXTRA. */
14349
14350 static struct mips_opcode *
mips_lookup_insn(htab_t hash,const char * start,ssize_t length,unsigned int * opcode_extra)14351 mips_lookup_insn (htab_t hash, const char *start,
14352 ssize_t length, unsigned int *opcode_extra)
14353 {
14354 char *name, *dot, *p;
14355 unsigned int mask, suffix;
14356 ssize_t opend;
14357 struct mips_opcode *insn;
14358
14359 /* Make a copy of the instruction so that we can fiddle with it. */
14360 name = xstrndup (start, length);
14361
14362 /* Look up the instruction as-is. */
14363 insn = (struct mips_opcode *) str_hash_find (hash, name);
14364 if (insn)
14365 goto end;
14366
14367 dot = strchr (name, '.');
14368 if (dot && dot[1])
14369 {
14370 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14371 p = mips_parse_vu0_channels (dot + 1, &mask);
14372 if (*p == 0 && mask != 0)
14373 {
14374 *dot = 0;
14375 insn = (struct mips_opcode *) str_hash_find (hash, name);
14376 *dot = '.';
14377 if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
14378 {
14379 *opcode_extra |= mask << mips_vu0_channel_mask.lsb;
14380 goto end;
14381 }
14382 }
14383 }
14384
14385 if (mips_opts.micromips)
14386 {
14387 /* See if there's an instruction size override suffix,
14388 either `16' or `32', at the end of the mnemonic proper,
14389 that defines the operation, i.e. before the first `.'
14390 character if any. Strip it and retry. */
14391 opend = dot != NULL ? dot - name : length;
14392 if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
14393 suffix = 2;
14394 else if (opend >= 2 && name[opend - 2] == '3' && name[opend - 1] == '2')
14395 suffix = 4;
14396 else
14397 suffix = 0;
14398 if (suffix)
14399 {
14400 memmove (name + opend - 2, name + opend, length - opend + 1);
14401 insn = (struct mips_opcode *) str_hash_find (hash, name);
14402 if (insn)
14403 {
14404 forced_insn_length = suffix;
14405 goto end;
14406 }
14407 }
14408 }
14409
14410 insn = NULL;
14411 end:
14412 free (name);
14413 return insn;
14414 }
14415
14416 /* Assemble an instruction into its binary format. If the instruction
14417 is a macro, set imm_expr and offset_expr to the values associated
14418 with "I" and "A" operands respectively. Otherwise store the value
14419 of the relocatable field (if any) in offset_expr. In both cases
14420 set offset_reloc to the relocation operators applied to offset_expr. */
14421
14422 static void
mips_ip(char * str,struct mips_cl_insn * insn)14423 mips_ip (char *str, struct mips_cl_insn *insn)
14424 {
14425 const struct mips_opcode *first, *past;
14426 htab_t hash;
14427 char format;
14428 size_t end;
14429 struct mips_operand_token *tokens;
14430 unsigned int opcode_extra;
14431
14432 if (mips_opts.micromips)
14433 {
14434 hash = micromips_op_hash;
14435 past = µmips_opcodes[bfd_micromips_num_opcodes];
14436 }
14437 else
14438 {
14439 hash = op_hash;
14440 past = &mips_opcodes[NUMOPCODES];
14441 }
14442 forced_insn_length = 0;
14443 opcode_extra = 0;
14444
14445 /* We first try to match an instruction up to a space or to the end. */
14446 for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
14447 continue;
14448
14449 first = mips_lookup_insn (hash, str, end, &opcode_extra);
14450 if (first == NULL)
14451 {
14452 set_insn_error (0, _("unrecognized opcode"));
14453 return;
14454 }
14455
14456 if (strcmp (first->name, "li.s") == 0)
14457 format = 'f';
14458 else if (strcmp (first->name, "li.d") == 0)
14459 format = 'd';
14460 else
14461 format = 0;
14462 tokens = mips_parse_arguments (str + end, format);
14463 if (!tokens)
14464 return;
14465
14466 if (!match_insns (insn, first, past, tokens, opcode_extra, false)
14467 && !match_insns (insn, first, past, tokens, opcode_extra, true))
14468 set_insn_error (0, _("invalid operands"));
14469
14470 obstack_free (&mips_operand_tokens, tokens);
14471 }
14472
14473 /* As for mips_ip, but used when assembling MIPS16 code.
14474 Also set forced_insn_length to the resulting instruction size in
14475 bytes if the user explicitly requested a small or extended instruction. */
14476
14477 static void
mips16_ip(char * str,struct mips_cl_insn * insn)14478 mips16_ip (char *str, struct mips_cl_insn *insn)
14479 {
14480 char *end, *s, c;
14481 struct mips_opcode *first;
14482 struct mips_operand_token *tokens;
14483 unsigned int l;
14484
14485 for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s)
14486 ;
14487 end = s;
14488 c = *end;
14489
14490 l = 0;
14491 switch (c)
14492 {
14493 case '\0':
14494 break;
14495
14496 case ' ':
14497 s++;
14498 break;
14499
14500 case '.':
14501 s++;
14502 if (*s == 't')
14503 {
14504 l = 2;
14505 s++;
14506 }
14507 else if (*s == 'e')
14508 {
14509 l = 4;
14510 s++;
14511 }
14512 if (*s == '\0')
14513 break;
14514 else if (*s++ == ' ')
14515 break;
14516 set_insn_error (0, _("unrecognized opcode"));
14517 return;
14518 }
14519 forced_insn_length = l;
14520
14521 *end = 0;
14522 first = (struct mips_opcode *) str_hash_find (mips16_op_hash, str);
14523 *end = c;
14524
14525 if (!first)
14526 {
14527 set_insn_error (0, _("unrecognized opcode"));
14528 return;
14529 }
14530
14531 tokens = mips_parse_arguments (s, 0);
14532 if (!tokens)
14533 return;
14534
14535 if (!match_mips16_insns (insn, first, tokens))
14536 set_insn_error (0, _("invalid operands"));
14537
14538 obstack_free (&mips_operand_tokens, tokens);
14539 }
14540
14541 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14542 NBITS is the number of significant bits in VAL. */
14543
14544 static unsigned long
mips16_immed_extend(offsetT val,unsigned int nbits)14545 mips16_immed_extend (offsetT val, unsigned int nbits)
14546 {
14547 int extval;
14548
14549 extval = 0;
14550 val &= (1U << nbits) - 1;
14551 if (nbits == 16 || nbits == 9)
14552 {
14553 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
14554 val &= 0x1f;
14555 }
14556 else if (nbits == 15)
14557 {
14558 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
14559 val &= 0xf;
14560 }
14561 else if (nbits == 6)
14562 {
14563 extval = ((val & 0x1f) << 6) | (val & 0x20);
14564 val = 0;
14565 }
14566 return (extval << 16) | val;
14567 }
14568
14569 /* Like decode_mips16_operand, but require the operand to be defined and
14570 require it to be an integer. */
14571
14572 static const struct mips_int_operand *
mips16_immed_operand(int type,bool extended_p)14573 mips16_immed_operand (int type, bool extended_p)
14574 {
14575 const struct mips_operand *operand;
14576
14577 operand = decode_mips16_operand (type, extended_p);
14578 if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL))
14579 abort ();
14580 return (const struct mips_int_operand *) operand;
14581 }
14582
14583 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14584
14585 static bool
mips16_immed_in_range_p(const struct mips_int_operand * operand,bfd_reloc_code_real_type reloc,offsetT sval)14586 mips16_immed_in_range_p (const struct mips_int_operand *operand,
14587 bfd_reloc_code_real_type reloc, offsetT sval)
14588 {
14589 int min_val, max_val;
14590
14591 min_val = mips_int_operand_min (operand);
14592 max_val = mips_int_operand_max (operand);
14593 if (reloc != BFD_RELOC_UNUSED)
14594 {
14595 if (min_val < 0)
14596 sval = SEXT_16BIT (sval);
14597 else
14598 sval &= 0xffff;
14599 }
14600
14601 return (sval >= min_val
14602 && sval <= max_val
14603 && (sval & ((1 << operand->shift) - 1)) == 0);
14604 }
14605
14606 /* Install immediate value VAL into MIPS16 instruction *INSN,
14607 extending it if necessary. The instruction in *INSN may
14608 already be extended.
14609
14610 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14611 if none. In the former case, VAL is a 16-bit number with no
14612 defined signedness.
14613
14614 TYPE is the type of the immediate field. USER_INSN_LENGTH
14615 is the length that the user requested, or 0 if none. */
14616
14617 static void
mips16_immed(const char * file,unsigned int line,int type,bfd_reloc_code_real_type reloc,offsetT val,unsigned int user_insn_length,unsigned long * insn)14618 mips16_immed (const char *file, unsigned int line, int type,
14619 bfd_reloc_code_real_type reloc, offsetT val,
14620 unsigned int user_insn_length, unsigned long *insn)
14621 {
14622 const struct mips_int_operand *operand;
14623 unsigned int uval, length;
14624
14625 operand = mips16_immed_operand (type, false);
14626 if (!mips16_immed_in_range_p (operand, reloc, val))
14627 {
14628 /* We need an extended instruction. */
14629 if (user_insn_length == 2)
14630 as_bad_where (file, line, _("invalid unextended operand value"));
14631 else
14632 *insn |= MIPS16_EXTEND;
14633 }
14634 else if (user_insn_length == 4)
14635 {
14636 /* The operand doesn't force an unextended instruction to be extended.
14637 Warn if the user wanted an extended instruction anyway. */
14638 *insn |= MIPS16_EXTEND;
14639 as_warn_where (file, line,
14640 _("extended operand requested but not required"));
14641 }
14642
14643 length = mips16_opcode_length (*insn);
14644 if (length == 4)
14645 {
14646 operand = mips16_immed_operand (type, true);
14647 if (!mips16_immed_in_range_p (operand, reloc, val))
14648 as_bad_where (file, line,
14649 _("operand value out of range for instruction"));
14650 }
14651 uval = ((unsigned int) val >> operand->shift) - operand->bias;
14652 if (length == 2 || operand->root.lsb != 0)
14653 *insn = mips_insert_operand (&operand->root, *insn, uval);
14654 else
14655 *insn |= mips16_immed_extend (uval, operand->root.size);
14656 }
14657
14658 struct percent_op_match
14659 {
14660 const char *str;
14661 bfd_reloc_code_real_type reloc;
14662 };
14663
14664 static const struct percent_op_match mips_percent_op[] =
14665 {
14666 {"%lo", BFD_RELOC_LO16},
14667 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
14668 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
14669 {"%call16", BFD_RELOC_MIPS_CALL16},
14670 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
14671 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
14672 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
14673 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
14674 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
14675 {"%got", BFD_RELOC_MIPS_GOT16},
14676 {"%gp_rel", BFD_RELOC_GPREL16},
14677 {"%gprel", BFD_RELOC_GPREL16},
14678 {"%half", BFD_RELOC_MIPS_16},
14679 {"%highest", BFD_RELOC_MIPS_HIGHEST},
14680 {"%higher", BFD_RELOC_MIPS_HIGHER},
14681 {"%neg", BFD_RELOC_MIPS_SUB},
14682 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
14683 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
14684 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
14685 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
14686 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
14687 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
14688 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
14689 {"%hi", BFD_RELOC_HI16_S},
14690 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL},
14691 {"%pcrel_lo", BFD_RELOC_LO16_PCREL}
14692 };
14693
14694 static const struct percent_op_match mips16_percent_op[] =
14695 {
14696 {"%lo", BFD_RELOC_MIPS16_LO16},
14697 {"%gp_rel", BFD_RELOC_MIPS16_GPREL},
14698 {"%gprel", BFD_RELOC_MIPS16_GPREL},
14699 {"%got", BFD_RELOC_MIPS16_GOT16},
14700 {"%call16", BFD_RELOC_MIPS16_CALL16},
14701 {"%hi", BFD_RELOC_MIPS16_HI16_S},
14702 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD},
14703 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM},
14704 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16},
14705 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16},
14706 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16},
14707 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16},
14708 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL}
14709 };
14710
14711
14712 /* Return true if *STR points to a relocation operator. When returning true,
14713 move *STR over the operator and store its relocation code in *RELOC.
14714 Leave both *STR and *RELOC alone when returning false. */
14715
14716 static bool
parse_relocation(char ** str,bfd_reloc_code_real_type * reloc)14717 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
14718 {
14719 const struct percent_op_match *percent_op;
14720 size_t limit, i;
14721
14722 if (mips_opts.mips16)
14723 {
14724 percent_op = mips16_percent_op;
14725 limit = ARRAY_SIZE (mips16_percent_op);
14726 }
14727 else
14728 {
14729 percent_op = mips_percent_op;
14730 limit = ARRAY_SIZE (mips_percent_op);
14731 }
14732
14733 for (i = 0; i < limit; i++)
14734 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
14735 {
14736 int len = strlen (percent_op[i].str);
14737
14738 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
14739 continue;
14740
14741 *str += strlen (percent_op[i].str);
14742 *reloc = percent_op[i].reloc;
14743
14744 /* Check whether the output BFD supports this relocation.
14745 If not, issue an error and fall back on something safe. */
14746 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
14747 {
14748 as_bad (_("relocation %s isn't supported by the current ABI"),
14749 percent_op[i].str);
14750 *reloc = BFD_RELOC_UNUSED;
14751 }
14752 return true;
14753 }
14754 return false;
14755 }
14756
14757
14758 /* Parse string STR as a 16-bit relocatable operand. Store the
14759 expression in *EP and the relocations in the array starting
14760 at RELOC. Return the number of relocation operators used.
14761
14762 On exit, EXPR_PARSE_END points to the first character after the
14763 expression. */
14764
14765 static size_t
my_getSmallExpression(expressionS * ep,bfd_reloc_code_real_type * reloc,char * str)14766 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
14767 char *str)
14768 {
14769 bfd_reloc_code_real_type reversed_reloc[3];
14770 size_t reloc_index, i;
14771 int crux_depth, str_depth;
14772 char *crux;
14773
14774 /* Search for the start of the main expression, recoding relocations
14775 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14776 of the main expression and with CRUX_DEPTH containing the number
14777 of open brackets at that point. */
14778 reloc_index = -1;
14779 str_depth = 0;
14780 do
14781 {
14782 reloc_index++;
14783 crux = str;
14784 crux_depth = str_depth;
14785
14786 /* Skip over whitespace and brackets, keeping count of the number
14787 of brackets. */
14788 while (*str == ' ' || *str == '\t' || *str == '(')
14789 if (*str++ == '(')
14790 str_depth++;
14791 }
14792 while (*str == '%'
14793 && reloc_index < (HAVE_NEWABI ? 3 : 1)
14794 && parse_relocation (&str, &reversed_reloc[reloc_index]));
14795
14796 my_getExpression (ep, crux);
14797 str = expr_parse_end;
14798
14799 /* Match every open bracket. */
14800 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
14801 if (*str++ == ')')
14802 crux_depth--;
14803
14804 if (crux_depth > 0)
14805 as_bad (_("unclosed '('"));
14806
14807 expr_parse_end = str;
14808
14809 for (i = 0; i < reloc_index; i++)
14810 reloc[i] = reversed_reloc[reloc_index - 1 - i];
14811
14812 return reloc_index;
14813 }
14814
14815 static void
my_getExpression(expressionS * ep,char * str)14816 my_getExpression (expressionS *ep, char *str)
14817 {
14818 char *save_in;
14819
14820 save_in = input_line_pointer;
14821 input_line_pointer = str;
14822 expression (ep);
14823 expr_parse_end = input_line_pointer;
14824 input_line_pointer = save_in;
14825 }
14826
14827 const char *
md_atof(int type,char * litP,int * sizeP)14828 md_atof (int type, char *litP, int *sizeP)
14829 {
14830 return ieee_md_atof (type, litP, sizeP, target_big_endian);
14831 }
14832
14833 void
md_number_to_chars(char * buf,valueT val,int n)14834 md_number_to_chars (char *buf, valueT val, int n)
14835 {
14836 if (target_big_endian)
14837 number_to_chars_bigendian (buf, val, n);
14838 else
14839 number_to_chars_littleendian (buf, val, n);
14840 }
14841
support_64bit_objects(void)14842 static int support_64bit_objects(void)
14843 {
14844 const char **list, **l;
14845 int yes;
14846
14847 list = bfd_target_list ();
14848 for (l = list; *l != NULL; l++)
14849 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
14850 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
14851 break;
14852 yes = (*l != NULL);
14853 free (list);
14854 return yes;
14855 }
14856
14857 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14858 NEW_VALUE. Warn if another value was already specified. Note:
14859 we have to defer parsing the -march and -mtune arguments in order
14860 to handle 'from-abi' correctly, since the ABI might be specified
14861 in a later argument. */
14862
14863 static void
mips_set_option_string(const char ** string_ptr,const char * new_value)14864 mips_set_option_string (const char **string_ptr, const char *new_value)
14865 {
14866 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
14867 as_warn (_("a different %s was already specified, is now %s"),
14868 string_ptr == &mips_arch_string ? "-march" : "-mtune",
14869 new_value);
14870
14871 *string_ptr = new_value;
14872 }
14873
14874 int
md_parse_option(int c,const char * arg)14875 md_parse_option (int c, const char *arg)
14876 {
14877 unsigned int i;
14878
14879 for (i = 0; i < ARRAY_SIZE (mips_ases); i++)
14880 if (c == mips_ases[i].option_on || c == mips_ases[i].option_off)
14881 {
14882 file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts,
14883 c == mips_ases[i].option_on);
14884 return 1;
14885 }
14886
14887 switch (c)
14888 {
14889 case OPTION_CONSTRUCT_FLOATS:
14890 mips_disable_float_construction = 0;
14891 break;
14892
14893 case OPTION_NO_CONSTRUCT_FLOATS:
14894 mips_disable_float_construction = 1;
14895 break;
14896
14897 case OPTION_TRAP:
14898 mips_trap = 1;
14899 break;
14900
14901 case OPTION_BREAK:
14902 mips_trap = 0;
14903 break;
14904
14905 case OPTION_EB:
14906 target_big_endian = 1;
14907 break;
14908
14909 case OPTION_EL:
14910 target_big_endian = 0;
14911 break;
14912
14913 case 'O':
14914 if (arg == NULL)
14915 mips_optimize = 1;
14916 else if (arg[0] == '0')
14917 mips_optimize = 0;
14918 else if (arg[0] == '1')
14919 mips_optimize = 1;
14920 else
14921 mips_optimize = 2;
14922 break;
14923
14924 case 'g':
14925 if (arg == NULL)
14926 mips_debug = 2;
14927 else
14928 mips_debug = atoi (arg);
14929 break;
14930
14931 case OPTION_MIPS1:
14932 file_mips_opts.isa = ISA_MIPS1;
14933 break;
14934
14935 case OPTION_MIPS2:
14936 file_mips_opts.isa = ISA_MIPS2;
14937 break;
14938
14939 case OPTION_MIPS3:
14940 file_mips_opts.isa = ISA_MIPS3;
14941 break;
14942
14943 case OPTION_MIPS4:
14944 file_mips_opts.isa = ISA_MIPS4;
14945 break;
14946
14947 case OPTION_MIPS5:
14948 file_mips_opts.isa = ISA_MIPS5;
14949 break;
14950
14951 case OPTION_MIPS32:
14952 file_mips_opts.isa = ISA_MIPS32;
14953 break;
14954
14955 case OPTION_MIPS32R2:
14956 file_mips_opts.isa = ISA_MIPS32R2;
14957 break;
14958
14959 case OPTION_MIPS32R3:
14960 file_mips_opts.isa = ISA_MIPS32R3;
14961 break;
14962
14963 case OPTION_MIPS32R5:
14964 file_mips_opts.isa = ISA_MIPS32R5;
14965 break;
14966
14967 case OPTION_MIPS32R6:
14968 file_mips_opts.isa = ISA_MIPS32R6;
14969 break;
14970
14971 case OPTION_MIPS64R2:
14972 file_mips_opts.isa = ISA_MIPS64R2;
14973 break;
14974
14975 case OPTION_MIPS64R3:
14976 file_mips_opts.isa = ISA_MIPS64R3;
14977 break;
14978
14979 case OPTION_MIPS64R5:
14980 file_mips_opts.isa = ISA_MIPS64R5;
14981 break;
14982
14983 case OPTION_MIPS64R6:
14984 file_mips_opts.isa = ISA_MIPS64R6;
14985 break;
14986
14987 case OPTION_MIPS64:
14988 file_mips_opts.isa = ISA_MIPS64;
14989 break;
14990
14991 case OPTION_MTUNE:
14992 mips_set_option_string (&mips_tune_string, arg);
14993 break;
14994
14995 case OPTION_MARCH:
14996 mips_set_option_string (&mips_arch_string, arg);
14997 break;
14998
14999 case OPTION_M4650:
15000 mips_set_option_string (&mips_arch_string, "4650");
15001 mips_set_option_string (&mips_tune_string, "4650");
15002 break;
15003
15004 case OPTION_NO_M4650:
15005 break;
15006
15007 case OPTION_M4010:
15008 mips_set_option_string (&mips_arch_string, "4010");
15009 mips_set_option_string (&mips_tune_string, "4010");
15010 break;
15011
15012 case OPTION_NO_M4010:
15013 break;
15014
15015 case OPTION_M4100:
15016 mips_set_option_string (&mips_arch_string, "4100");
15017 mips_set_option_string (&mips_tune_string, "4100");
15018 break;
15019
15020 case OPTION_NO_M4100:
15021 break;
15022
15023 case OPTION_M3900:
15024 mips_set_option_string (&mips_arch_string, "3900");
15025 mips_set_option_string (&mips_tune_string, "3900");
15026 break;
15027
15028 case OPTION_NO_M3900:
15029 break;
15030
15031 case OPTION_MICROMIPS:
15032 if (file_mips_opts.mips16 == 1)
15033 {
15034 as_bad (_("-mmicromips cannot be used with -mips16"));
15035 return 0;
15036 }
15037 file_mips_opts.micromips = 1;
15038 mips_no_prev_insn ();
15039 break;
15040
15041 case OPTION_NO_MICROMIPS:
15042 file_mips_opts.micromips = 0;
15043 mips_no_prev_insn ();
15044 break;
15045
15046 case OPTION_MIPS16:
15047 if (file_mips_opts.micromips == 1)
15048 {
15049 as_bad (_("-mips16 cannot be used with -micromips"));
15050 return 0;
15051 }
15052 file_mips_opts.mips16 = 1;
15053 mips_no_prev_insn ();
15054 break;
15055
15056 case OPTION_NO_MIPS16:
15057 file_mips_opts.mips16 = 0;
15058 mips_no_prev_insn ();
15059 break;
15060
15061 case OPTION_FIX_24K:
15062 mips_fix_24k = 1;
15063 break;
15064
15065 case OPTION_NO_FIX_24K:
15066 mips_fix_24k = 0;
15067 break;
15068
15069 case OPTION_FIX_RM7000:
15070 mips_fix_rm7000 = 1;
15071 break;
15072
15073 case OPTION_NO_FIX_RM7000:
15074 mips_fix_rm7000 = 0;
15075 break;
15076
15077 case OPTION_FIX_LOONGSON3_LLSC:
15078 mips_fix_loongson3_llsc = true;
15079 break;
15080
15081 case OPTION_NO_FIX_LOONGSON3_LLSC:
15082 mips_fix_loongson3_llsc = false;
15083 break;
15084
15085 case OPTION_FIX_LOONGSON2F_JUMP:
15086 mips_fix_loongson2f_jump = true;
15087 break;
15088
15089 case OPTION_NO_FIX_LOONGSON2F_JUMP:
15090 mips_fix_loongson2f_jump = false;
15091 break;
15092
15093 case OPTION_FIX_LOONGSON2F_NOP:
15094 mips_fix_loongson2f_nop = true;
15095 break;
15096
15097 case OPTION_NO_FIX_LOONGSON2F_NOP:
15098 mips_fix_loongson2f_nop = false;
15099 break;
15100
15101 case OPTION_FIX_VR4120:
15102 mips_fix_vr4120 = 1;
15103 break;
15104
15105 case OPTION_NO_FIX_VR4120:
15106 mips_fix_vr4120 = 0;
15107 break;
15108
15109 case OPTION_FIX_VR4130:
15110 mips_fix_vr4130 = 1;
15111 break;
15112
15113 case OPTION_NO_FIX_VR4130:
15114 mips_fix_vr4130 = 0;
15115 break;
15116
15117 case OPTION_FIX_LOONGSON2F_BTB:
15118 mips_fix_loongson2f_btb = 1;
15119 break;
15120
15121 case OPTION_NO_FIX_LOONGSON2F_BTB:
15122 mips_fix_loongson2f_btb = 0;
15123 break;
15124
15125 case OPTION_FIX_CN63XXP1:
15126 mips_fix_cn63xxp1 = true;
15127 break;
15128
15129 case OPTION_NO_FIX_CN63XXP1:
15130 mips_fix_cn63xxp1 = false;
15131 break;
15132
15133 case OPTION_FIX_R5900:
15134 mips_fix_r5900 = true;
15135 mips_fix_r5900_explicit = true;
15136 break;
15137
15138 case OPTION_NO_FIX_R5900:
15139 mips_fix_r5900 = false;
15140 mips_fix_r5900_explicit = true;
15141 break;
15142
15143 case OPTION_RELAX_BRANCH:
15144 mips_relax_branch = 1;
15145 break;
15146
15147 case OPTION_NO_RELAX_BRANCH:
15148 mips_relax_branch = 0;
15149 break;
15150
15151 case OPTION_IGNORE_BRANCH_ISA:
15152 mips_ignore_branch_isa = true;
15153 break;
15154
15155 case OPTION_NO_IGNORE_BRANCH_ISA:
15156 mips_ignore_branch_isa = false;
15157 break;
15158
15159 case OPTION_INSN32:
15160 file_mips_opts.insn32 = true;
15161 break;
15162
15163 case OPTION_NO_INSN32:
15164 file_mips_opts.insn32 = false;
15165 break;
15166
15167 case OPTION_MSHARED:
15168 mips_in_shared = true;
15169 break;
15170
15171 case OPTION_MNO_SHARED:
15172 mips_in_shared = false;
15173 break;
15174
15175 case OPTION_MSYM32:
15176 file_mips_opts.sym32 = true;
15177 break;
15178
15179 case OPTION_MNO_SYM32:
15180 file_mips_opts.sym32 = false;
15181 break;
15182
15183 /* When generating ELF code, we permit -KPIC and -call_shared to
15184 select SVR4_PIC, and -non_shared to select no PIC. This is
15185 intended to be compatible with Irix 5. */
15186 case OPTION_CALL_SHARED:
15187 mips_pic = SVR4_PIC;
15188 mips_abicalls = true;
15189 break;
15190
15191 case OPTION_CALL_NONPIC:
15192 mips_pic = NO_PIC;
15193 mips_abicalls = true;
15194 break;
15195
15196 case OPTION_NON_SHARED:
15197 mips_pic = NO_PIC;
15198 mips_abicalls = false;
15199 break;
15200
15201 /* The -xgot option tells the assembler to use 32 bit offsets
15202 when accessing the got in SVR4_PIC mode. It is for Irix
15203 compatibility. */
15204 case OPTION_XGOT:
15205 mips_big_got = 1;
15206 break;
15207
15208 case 'G':
15209 g_switch_value = atoi (arg);
15210 g_switch_seen = 1;
15211 break;
15212
15213 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15214 and -mabi=64. */
15215 case OPTION_32:
15216 mips_abi = O32_ABI;
15217 break;
15218
15219 case OPTION_N32:
15220 mips_abi = N32_ABI;
15221 break;
15222
15223 case OPTION_64:
15224 mips_abi = N64_ABI;
15225 if (!support_64bit_objects())
15226 as_fatal (_("no compiled in support for 64 bit object file format"));
15227 break;
15228
15229 case OPTION_GP32:
15230 file_mips_opts.gp = 32;
15231 break;
15232
15233 case OPTION_GP64:
15234 file_mips_opts.gp = 64;
15235 break;
15236
15237 case OPTION_FP32:
15238 file_mips_opts.fp = 32;
15239 break;
15240
15241 case OPTION_FPXX:
15242 file_mips_opts.fp = 0;
15243 break;
15244
15245 case OPTION_FP64:
15246 file_mips_opts.fp = 64;
15247 break;
15248
15249 case OPTION_ODD_SPREG:
15250 file_mips_opts.oddspreg = 1;
15251 break;
15252
15253 case OPTION_NO_ODD_SPREG:
15254 file_mips_opts.oddspreg = 0;
15255 break;
15256
15257 case OPTION_SINGLE_FLOAT:
15258 file_mips_opts.single_float = 1;
15259 break;
15260
15261 case OPTION_DOUBLE_FLOAT:
15262 file_mips_opts.single_float = 0;
15263 break;
15264
15265 case OPTION_SOFT_FLOAT:
15266 file_mips_opts.soft_float = 1;
15267 break;
15268
15269 case OPTION_HARD_FLOAT:
15270 file_mips_opts.soft_float = 0;
15271 break;
15272
15273 case OPTION_MABI:
15274 if (strcmp (arg, "32") == 0)
15275 mips_abi = O32_ABI;
15276 else if (strcmp (arg, "o64") == 0)
15277 mips_abi = O64_ABI;
15278 else if (strcmp (arg, "n32") == 0)
15279 mips_abi = N32_ABI;
15280 else if (strcmp (arg, "64") == 0)
15281 {
15282 mips_abi = N64_ABI;
15283 if (! support_64bit_objects())
15284 as_fatal (_("no compiled in support for 64 bit object file "
15285 "format"));
15286 }
15287 else if (strcmp (arg, "eabi") == 0)
15288 mips_abi = EABI_ABI;
15289 else
15290 {
15291 as_fatal (_("invalid abi -mabi=%s"), arg);
15292 return 0;
15293 }
15294 break;
15295
15296 case OPTION_M7000_HILO_FIX:
15297 mips_7000_hilo_fix = true;
15298 break;
15299
15300 case OPTION_MNO_7000_HILO_FIX:
15301 mips_7000_hilo_fix = false;
15302 break;
15303
15304 case OPTION_MDEBUG:
15305 mips_flag_mdebug = true;
15306 break;
15307
15308 case OPTION_NO_MDEBUG:
15309 mips_flag_mdebug = false;
15310 break;
15311
15312 case OPTION_PDR:
15313 mips_flag_pdr = true;
15314 break;
15315
15316 case OPTION_NO_PDR:
15317 mips_flag_pdr = false;
15318 break;
15319
15320 case OPTION_MVXWORKS_PIC:
15321 mips_pic = VXWORKS_PIC;
15322 break;
15323
15324 case OPTION_NAN:
15325 if (strcmp (arg, "2008") == 0)
15326 mips_nan2008 = 1;
15327 else if (strcmp (arg, "legacy") == 0)
15328 mips_nan2008 = 0;
15329 else
15330 {
15331 as_fatal (_("invalid NaN setting -mnan=%s"), arg);
15332 return 0;
15333 }
15334 break;
15335
15336 default:
15337 return 0;
15338 }
15339
15340 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
15341
15342 return 1;
15343 }
15344
15345 /* Set up globals to tune for the ISA or processor described by INFO. */
15346
15347 static void
mips_set_tune(const struct mips_cpu_info * info)15348 mips_set_tune (const struct mips_cpu_info *info)
15349 {
15350 if (info != 0)
15351 mips_tune = info->cpu;
15352 }
15353
15354
15355 void
mips_after_parse_args(void)15356 mips_after_parse_args (void)
15357 {
15358 const struct mips_cpu_info *arch_info = 0;
15359 const struct mips_cpu_info *tune_info = 0;
15360
15361 /* GP relative stuff not working for PE. */
15362 if (startswith (TARGET_OS, "pe"))
15363 {
15364 if (g_switch_seen && g_switch_value != 0)
15365 as_bad (_("-G not supported in this configuration"));
15366 g_switch_value = 0;
15367 }
15368
15369 if (mips_abi == NO_ABI)
15370 mips_abi = MIPS_DEFAULT_ABI;
15371
15372 /* The following code determines the architecture.
15373 Similar code was added to GCC 3.3 (see override_options() in
15374 config/mips/mips.c). The GAS and GCC code should be kept in sync
15375 as much as possible. */
15376
15377 if (mips_arch_string != 0)
15378 arch_info = mips_parse_cpu ("-march", mips_arch_string);
15379
15380 if (file_mips_opts.isa != ISA_UNKNOWN)
15381 {
15382 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15383 ISA level specified by -mipsN, while arch_info->isa contains
15384 the -march selection (if any). */
15385 if (arch_info != 0)
15386 {
15387 /* -march takes precedence over -mipsN, since it is more descriptive.
15388 There's no harm in specifying both as long as the ISA levels
15389 are the same. */
15390 if (file_mips_opts.isa != arch_info->isa)
15391 as_bad (_("-%s conflicts with the other architecture options,"
15392 " which imply -%s"),
15393 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
15394 mips_cpu_info_from_isa (arch_info->isa)->name);
15395 }
15396 else
15397 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
15398 }
15399
15400 if (arch_info == 0)
15401 {
15402 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
15403 gas_assert (arch_info);
15404 }
15405
15406 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
15407 as_bad (_("-march=%s is not compatible with the selected ABI"),
15408 arch_info->name);
15409
15410 file_mips_opts.arch = arch_info->cpu;
15411 file_mips_opts.isa = arch_info->isa;
15412 file_mips_opts.init_ase = arch_info->ase;
15413
15414 /* The EVA Extension has instructions which are only valid when the R6 ISA
15415 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15416 present. */
15417 if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa))
15418 file_mips_opts.ase |= ASE_EVA_R6;
15419
15420 /* Set up initial mips_opts state. */
15421 mips_opts = file_mips_opts;
15422
15423 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15424 if (!mips_fix_r5900_explicit)
15425 mips_fix_r5900 = file_mips_opts.arch == CPU_R5900;
15426
15427 /* The register size inference code is now placed in
15428 file_mips_check_options. */
15429
15430 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15431 processor. */
15432 if (mips_tune_string != 0)
15433 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
15434
15435 if (tune_info == 0)
15436 mips_set_tune (arch_info);
15437 else
15438 mips_set_tune (tune_info);
15439
15440 if (mips_flag_mdebug < 0)
15441 mips_flag_mdebug = 0;
15442 }
15443
15444 void
mips_init_after_args(void)15445 mips_init_after_args (void)
15446 {
15447 /* Initialize opcodes. */
15448 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
15449 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
15450 }
15451
15452 long
md_pcrel_from(fixS * fixP)15453 md_pcrel_from (fixS *fixP)
15454 {
15455 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
15456
15457 switch (fixP->fx_r_type)
15458 {
15459 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15460 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15461 /* Return the address of the delay slot. */
15462 return addr + 2;
15463
15464 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15465 case BFD_RELOC_MICROMIPS_JMP:
15466 case BFD_RELOC_MIPS16_16_PCREL_S1:
15467 case BFD_RELOC_16_PCREL_S2:
15468 case BFD_RELOC_MIPS_21_PCREL_S2:
15469 case BFD_RELOC_MIPS_26_PCREL_S2:
15470 case BFD_RELOC_MIPS_JMP:
15471 /* Return the address of the delay slot. */
15472 return addr + 4;
15473
15474 case BFD_RELOC_MIPS_18_PCREL_S3:
15475 /* Return the aligned address of the doubleword containing
15476 the instruction. */
15477 return addr & ~7;
15478
15479 default:
15480 return addr;
15481 }
15482 }
15483
15484 /* This is called before the symbol table is processed. In order to
15485 work with gcc when using mips-tfile, we must keep all local labels.
15486 However, in other cases, we want to discard them. If we were
15487 called with -g, but we didn't see any debugging information, it may
15488 mean that gcc is smuggling debugging information through to
15489 mips-tfile, in which case we must generate all local labels. */
15490
15491 void
mips_frob_file_before_adjust(void)15492 mips_frob_file_before_adjust (void)
15493 {
15494 #ifndef NO_ECOFF_DEBUGGING
15495 if (ECOFF_DEBUGGING
15496 && mips_debug != 0
15497 && ! ecoff_debugging_seen)
15498 flag_keep_locals = 1;
15499 #endif
15500 }
15501
15502 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15503 the corresponding LO16 reloc. This is called before md_apply_fix and
15504 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15505 relocation operators.
15506
15507 For our purposes, a %lo() expression matches a %got() or %hi()
15508 expression if:
15509
15510 (a) it refers to the same symbol; and
15511 (b) the offset applied in the %lo() expression is no lower than
15512 the offset applied in the %got() or %hi().
15513
15514 (b) allows us to cope with code like:
15515
15516 lui $4,%hi(foo)
15517 lh $4,%lo(foo+2)($4)
15518
15519 ...which is legal on RELA targets, and has a well-defined behaviour
15520 if the user knows that adding 2 to "foo" will not induce a carry to
15521 the high 16 bits.
15522
15523 When several %lo()s match a particular %got() or %hi(), we use the
15524 following rules to distinguish them:
15525
15526 (1) %lo()s with smaller offsets are a better match than %lo()s with
15527 higher offsets.
15528
15529 (2) %lo()s with no matching %got() or %hi() are better than those
15530 that already have a matching %got() or %hi().
15531
15532 (3) later %lo()s are better than earlier %lo()s.
15533
15534 These rules are applied in order.
15535
15536 (1) means, among other things, that %lo()s with identical offsets are
15537 chosen if they exist.
15538
15539 (2) means that we won't associate several high-part relocations with
15540 the same low-part relocation unless there's no alternative. Having
15541 several high parts for the same low part is a GNU extension; this rule
15542 allows careful users to avoid it.
15543
15544 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15545 with the last high-part relocation being at the front of the list.
15546 It therefore makes sense to choose the last matching low-part
15547 relocation, all other things being equal. It's also easier
15548 to code that way. */
15549
15550 void
mips_frob_file(void)15551 mips_frob_file (void)
15552 {
15553 struct mips_hi_fixup *l;
15554 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
15555
15556 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
15557 {
15558 segment_info_type *seginfo;
15559 bool matched_lo_p;
15560 fixS **hi_pos, **lo_pos, **pos;
15561
15562 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
15563
15564 /* If a GOT16 relocation turns out to be against a global symbol,
15565 there isn't supposed to be a matching LO. Ignore %gots against
15566 constants; we'll report an error for those later. */
15567 if (got16_reloc_p (l->fixp->fx_r_type)
15568 && !pic_need_relax (l->fixp->fx_addsy))
15569 continue;
15570
15571 /* Check quickly whether the next fixup happens to be a matching %lo. */
15572 if (fixup_has_matching_lo_p (l->fixp))
15573 continue;
15574
15575 seginfo = seg_info (l->seg);
15576
15577 /* Set HI_POS to the position of this relocation in the chain.
15578 Set LO_POS to the position of the chosen low-part relocation.
15579 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15580 relocation that matches an immediately-preceding high-part
15581 relocation. */
15582 hi_pos = NULL;
15583 lo_pos = NULL;
15584 matched_lo_p = false;
15585 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
15586
15587 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
15588 {
15589 if (*pos == l->fixp)
15590 hi_pos = pos;
15591
15592 if ((*pos)->fx_r_type == looking_for_rtype
15593 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
15594 && (*pos)->fx_offset >= l->fixp->fx_offset
15595 && (lo_pos == NULL
15596 || (*pos)->fx_offset < (*lo_pos)->fx_offset
15597 || (!matched_lo_p
15598 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
15599 lo_pos = pos;
15600
15601 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
15602 && fixup_has_matching_lo_p (*pos));
15603 }
15604
15605 /* If we found a match, remove the high-part relocation from its
15606 current position and insert it before the low-part relocation.
15607 Make the offsets match so that fixup_has_matching_lo_p()
15608 will return true.
15609
15610 We don't warn about unmatched high-part relocations since some
15611 versions of gcc have been known to emit dead "lui ...%hi(...)"
15612 instructions. */
15613 if (lo_pos != NULL)
15614 {
15615 l->fixp->fx_offset = (*lo_pos)->fx_offset;
15616 if (l->fixp->fx_next != *lo_pos)
15617 {
15618 *hi_pos = l->fixp->fx_next;
15619 l->fixp->fx_next = *lo_pos;
15620 *lo_pos = l->fixp;
15621 }
15622 }
15623 }
15624 }
15625
15626 int
mips_force_relocation(fixS * fixp)15627 mips_force_relocation (fixS *fixp)
15628 {
15629 if (generic_force_reloc (fixp))
15630 return 1;
15631
15632 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15633 so that the linker relaxation can update targets. */
15634 if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
15635 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
15636 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1)
15637 return 1;
15638
15639 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15640 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15641 microMIPS symbols so that we can do cross-mode branch diagnostics
15642 and BAL to JALX conversion by the linker. */
15643 if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15644 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15645 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2)
15646 && fixp->fx_addsy
15647 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy)))
15648 return 1;
15649
15650 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15651 if (ISA_IS_R6 (file_mips_opts.isa)
15652 && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
15653 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
15654 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
15655 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
15656 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
15657 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
15658 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL))
15659 return 1;
15660
15661 return 0;
15662 }
15663
15664 /* Implement TC_FORCE_RELOCATION_ABS. */
15665
15666 bool
mips_force_relocation_abs(fixS * fixp)15667 mips_force_relocation_abs (fixS *fixp)
15668 {
15669 if (generic_force_reloc (fixp))
15670 return true;
15671
15672 /* These relocations do not have enough bits in the in-place addend
15673 to hold an arbitrary absolute section's offset. */
15674 if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type))
15675 return true;
15676
15677 return false;
15678 }
15679
15680 /* Read the instruction associated with RELOC from BUF. */
15681
15682 static unsigned int
read_reloc_insn(char * buf,bfd_reloc_code_real_type reloc)15683 read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc)
15684 {
15685 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15686 return read_compressed_insn (buf, 4);
15687 else
15688 return read_insn (buf);
15689 }
15690
15691 /* Write instruction INSN to BUF, given that it has been relocated
15692 by RELOC. */
15693
15694 static void
write_reloc_insn(char * buf,bfd_reloc_code_real_type reloc,unsigned long insn)15695 write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc,
15696 unsigned long insn)
15697 {
15698 if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc))
15699 write_compressed_insn (buf, insn, 4);
15700 else
15701 write_insn (buf, insn);
15702 }
15703
15704 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15705 to a symbol in another ISA mode, which cannot be converted to JALX. */
15706
15707 static bool
fix_bad_cross_mode_jump_p(fixS * fixP)15708 fix_bad_cross_mode_jump_p (fixS *fixP)
15709 {
15710 unsigned long opcode;
15711 int other;
15712 char *buf;
15713
15714 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
15715 return false;
15716
15717 other = S_GET_OTHER (fixP->fx_addsy);
15718 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15719 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15720 switch (fixP->fx_r_type)
15721 {
15722 case BFD_RELOC_MIPS_JMP:
15723 return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other);
15724 case BFD_RELOC_MICROMIPS_JMP:
15725 return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other);
15726 default:
15727 return false;
15728 }
15729 }
15730
15731 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15732 jump to a symbol in the same ISA mode. */
15733
15734 static bool
fix_bad_same_mode_jalx_p(fixS * fixP)15735 fix_bad_same_mode_jalx_p (fixS *fixP)
15736 {
15737 unsigned long opcode;
15738 int other;
15739 char *buf;
15740
15741 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
15742 return false;
15743
15744 other = S_GET_OTHER (fixP->fx_addsy);
15745 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15746 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26;
15747 switch (fixP->fx_r_type)
15748 {
15749 case BFD_RELOC_MIPS_JMP:
15750 return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other);
15751 case BFD_RELOC_MIPS16_JMP:
15752 return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other);
15753 case BFD_RELOC_MICROMIPS_JMP:
15754 return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other);
15755 default:
15756 return false;
15757 }
15758 }
15759
15760 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15761 to a symbol whose value plus addend is not aligned according to the
15762 ultimate (after linker relaxation) jump instruction's immediate field
15763 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15764 regular MIPS code, to (1 << 2). */
15765
15766 static bool
fix_bad_misaligned_jump_p(fixS * fixP,int shift)15767 fix_bad_misaligned_jump_p (fixS *fixP, int shift)
15768 {
15769 bool micro_to_mips_p;
15770 valueT val;
15771 int other;
15772
15773 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
15774 return false;
15775
15776 other = S_GET_OTHER (fixP->fx_addsy);
15777 val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other);
15778 val += fixP->fx_offset;
15779 micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
15780 && !ELF_ST_IS_MICROMIPS (other));
15781 return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1))
15782 != ELF_ST_IS_COMPRESSED (other));
15783 }
15784
15785 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15786 to a symbol whose annotation indicates another ISA mode. For absolute
15787 symbols check the ISA bit instead.
15788
15789 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15790 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15791 MIPS symbols and associated with BAL instructions as these instructions
15792 may be converted to JALX by the linker. */
15793
15794 static bool
fix_bad_cross_mode_branch_p(fixS * fixP)15795 fix_bad_cross_mode_branch_p (fixS *fixP)
15796 {
15797 bool absolute_p;
15798 unsigned long opcode;
15799 asection *symsec;
15800 valueT val;
15801 int other;
15802 char *buf;
15803
15804 if (mips_ignore_branch_isa)
15805 return false;
15806
15807 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
15808 return false;
15809
15810 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15811 absolute_p = bfd_is_abs_section (symsec);
15812
15813 val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
15814 other = S_GET_OTHER (fixP->fx_addsy);
15815
15816 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15817 opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16;
15818 switch (fixP->fx_r_type)
15819 {
15820 case BFD_RELOC_16_PCREL_S2:
15821 return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other))
15822 && opcode != 0x0411);
15823 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15824 return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
15825 && opcode != 0x4060);
15826 case BFD_RELOC_MIPS_21_PCREL_S2:
15827 case BFD_RELOC_MIPS_26_PCREL_S2:
15828 return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
15829 case BFD_RELOC_MIPS16_16_PCREL_S1:
15830 return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other);
15831 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15832 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15833 return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
15834 default:
15835 abort ();
15836 }
15837 }
15838
15839 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15840 branch instruction pointed to by FIXP is not aligned according to the
15841 branch instruction's immediate field requirement. We need the addend
15842 to preserve the ISA bit and also the sum must not have bit 2 set. We
15843 must explicitly OR in the ISA bit from symbol annotation as the bit
15844 won't be set in the symbol's value then. */
15845
15846 static bool
fix_bad_misaligned_branch_p(fixS * fixP)15847 fix_bad_misaligned_branch_p (fixS *fixP)
15848 {
15849 bool absolute_p;
15850 asection *symsec;
15851 valueT isa_bit;
15852 valueT val;
15853 valueT off;
15854 int other;
15855
15856 if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, true))
15857 return false;
15858
15859 symsec = S_GET_SEGMENT (fixP->fx_addsy);
15860 absolute_p = bfd_is_abs_section (symsec);
15861
15862 val = S_GET_VALUE (fixP->fx_addsy);
15863 other = S_GET_OTHER (fixP->fx_addsy);
15864 off = fixP->fx_offset;
15865
15866 isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other);
15867 val |= ELF_ST_IS_COMPRESSED (other);
15868 val += off;
15869 return (val & 0x3) != isa_bit;
15870 }
15871
15872 /* Calculate the relocation target by masking off ISA mode bit before
15873 combining symbol and addend. */
15874
15875 static valueT
fix_bad_misaligned_address(fixS * fixP)15876 fix_bad_misaligned_address (fixS *fixP)
15877 {
15878 valueT val;
15879 valueT off;
15880 unsigned isa_mode;
15881 gas_assert (fixP != NULL && fixP->fx_addsy != NULL);
15882 val = S_GET_VALUE (fixP->fx_addsy);
15883 off = fixP->fx_offset;
15884 isa_mode = (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP->fx_addsy))
15885 ? 1 : 0);
15886
15887 return ((val & ~isa_mode) + off);
15888 }
15889
15890 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15891 and its calculated value VAL. */
15892
15893 static void
fix_validate_branch(fixS * fixP,valueT val)15894 fix_validate_branch (fixS *fixP, valueT val)
15895 {
15896 if (fixP->fx_done && (val & 0x3) != 0)
15897 as_bad_where (fixP->fx_file, fixP->fx_line,
15898 _("branch to misaligned address (0x%lx)"),
15899 (long) (val + md_pcrel_from (fixP)));
15900 else if (fix_bad_cross_mode_branch_p (fixP))
15901 as_bad_where (fixP->fx_file, fixP->fx_line,
15902 _("branch to a symbol in another ISA mode"));
15903 else if (fix_bad_misaligned_branch_p (fixP))
15904 as_bad_where (fixP->fx_file, fixP->fx_line,
15905 _("branch to misaligned address (0x%lx)"),
15906 (long) fix_bad_misaligned_address (fixP));
15907 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0)
15908 as_bad_where (fixP->fx_file, fixP->fx_line,
15909 _("cannot encode misaligned addend "
15910 "in the relocatable field (0x%lx)"),
15911 (long) fixP->fx_offset);
15912 }
15913
15914 /* Apply a fixup to the object file. */
15915
15916 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg ATTRIBUTE_UNUSED)15917 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15918 {
15919 char *buf;
15920 unsigned long insn;
15921 reloc_howto_type *howto;
15922
15923 if (fixP->fx_pcrel)
15924 switch (fixP->fx_r_type)
15925 {
15926 case BFD_RELOC_16_PCREL_S2:
15927 case BFD_RELOC_MIPS16_16_PCREL_S1:
15928 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
15929 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
15930 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
15931 case BFD_RELOC_32_PCREL:
15932 case BFD_RELOC_MIPS_21_PCREL_S2:
15933 case BFD_RELOC_MIPS_26_PCREL_S2:
15934 case BFD_RELOC_MIPS_18_PCREL_S3:
15935 case BFD_RELOC_MIPS_19_PCREL_S2:
15936 case BFD_RELOC_HI16_S_PCREL:
15937 case BFD_RELOC_LO16_PCREL:
15938 break;
15939
15940 case BFD_RELOC_32:
15941 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15942 break;
15943
15944 default:
15945 as_bad_where (fixP->fx_file, fixP->fx_line,
15946 _("PC-relative reference to a different section"));
15947 break;
15948 }
15949
15950 /* Handle BFD_RELOC_8 and BFD_RELOC_16. Punt on other bfd
15951 relocations that have no MIPS ELF equivalent. */
15952 if (fixP->fx_r_type != BFD_RELOC_8
15953 && fixP->fx_r_type != BFD_RELOC_16)
15954 {
15955 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
15956 if (!howto)
15957 return;
15958 }
15959
15960 gas_assert (fixP->fx_size == 2
15961 || fixP->fx_size == 4
15962 || fixP->fx_r_type == BFD_RELOC_8
15963 || fixP->fx_r_type == BFD_RELOC_64
15964 || fixP->fx_r_type == BFD_RELOC_CTOR
15965 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
15966 || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB
15967 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
15968 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
15969 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64
15970 || fixP->fx_r_type == BFD_RELOC_NONE);
15971
15972 buf = fixP->fx_frag->fr_literal + fixP->fx_where;
15973
15974 /* Don't treat parts of a composite relocation as done. There are two
15975 reasons for this:
15976
15977 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15978 should nevertheless be emitted if the first part is.
15979
15980 (2) In normal usage, composite relocations are never assembly-time
15981 constants. The easiest way of dealing with the pathological
15982 exceptions is to generate a relocation against STN_UNDEF and
15983 leave everything up to the linker. */
15984 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
15985 fixP->fx_done = 1;
15986
15987 switch (fixP->fx_r_type)
15988 {
15989 case BFD_RELOC_MIPS_TLS_GD:
15990 case BFD_RELOC_MIPS_TLS_LDM:
15991 case BFD_RELOC_MIPS_TLS_DTPREL32:
15992 case BFD_RELOC_MIPS_TLS_DTPREL64:
15993 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
15994 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
15995 case BFD_RELOC_MIPS_TLS_GOTTPREL:
15996 case BFD_RELOC_MIPS_TLS_TPREL32:
15997 case BFD_RELOC_MIPS_TLS_TPREL64:
15998 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
15999 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
16000 case BFD_RELOC_MICROMIPS_TLS_GD:
16001 case BFD_RELOC_MICROMIPS_TLS_LDM:
16002 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16:
16003 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16:
16004 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL:
16005 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16:
16006 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16:
16007 case BFD_RELOC_MIPS16_TLS_GD:
16008 case BFD_RELOC_MIPS16_TLS_LDM:
16009 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16:
16010 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16:
16011 case BFD_RELOC_MIPS16_TLS_GOTTPREL:
16012 case BFD_RELOC_MIPS16_TLS_TPREL_HI16:
16013 case BFD_RELOC_MIPS16_TLS_TPREL_LO16:
16014 if (fixP->fx_addsy)
16015 S_SET_THREAD_LOCAL (fixP->fx_addsy);
16016 else
16017 as_bad_where (fixP->fx_file, fixP->fx_line,
16018 _("TLS relocation against a constant"));
16019 break;
16020
16021 case BFD_RELOC_MIPS_JMP:
16022 case BFD_RELOC_MIPS16_JMP:
16023 case BFD_RELOC_MICROMIPS_JMP:
16024 {
16025 int shift;
16026
16027 gas_assert (!fixP->fx_done);
16028
16029 /* Shift is 2, unusually, for microMIPS JALX. */
16030 if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP
16031 && (read_compressed_insn (buf, 4) >> 26) != 0x3c)
16032 shift = 1;
16033 else
16034 shift = 2;
16035
16036 if (fix_bad_cross_mode_jump_p (fixP))
16037 as_bad_where (fixP->fx_file, fixP->fx_line,
16038 _("jump to a symbol in another ISA mode"));
16039 else if (fix_bad_same_mode_jalx_p (fixP))
16040 as_bad_where (fixP->fx_file, fixP->fx_line,
16041 _("JALX to a symbol in the same ISA mode"));
16042 else if (fix_bad_misaligned_jump_p (fixP, shift))
16043 as_bad_where (fixP->fx_file, fixP->fx_line,
16044 _("jump to misaligned address (0x%lx)"),
16045 (long) fix_bad_misaligned_address (fixP));
16046 else if (HAVE_IN_PLACE_ADDENDS
16047 && (fixP->fx_offset & ((1 << shift) - 1)) != 0)
16048 as_bad_where (fixP->fx_file, fixP->fx_line,
16049 _("cannot encode misaligned addend "
16050 "in the relocatable field (0x%lx)"),
16051 (long) fixP->fx_offset);
16052 }
16053 /* Fall through. */
16054
16055 case BFD_RELOC_MIPS_SHIFT5:
16056 case BFD_RELOC_MIPS_SHIFT6:
16057 case BFD_RELOC_MIPS_GOT_DISP:
16058 case BFD_RELOC_MIPS_GOT_PAGE:
16059 case BFD_RELOC_MIPS_GOT_OFST:
16060 case BFD_RELOC_MIPS_SUB:
16061 case BFD_RELOC_MIPS_INSERT_A:
16062 case BFD_RELOC_MIPS_INSERT_B:
16063 case BFD_RELOC_MIPS_DELETE:
16064 case BFD_RELOC_MIPS_HIGHEST:
16065 case BFD_RELOC_MIPS_HIGHER:
16066 case BFD_RELOC_MIPS_SCN_DISP:
16067 case BFD_RELOC_MIPS_RELGOT:
16068 case BFD_RELOC_MIPS_JALR:
16069 case BFD_RELOC_HI16:
16070 case BFD_RELOC_HI16_S:
16071 case BFD_RELOC_LO16:
16072 case BFD_RELOC_GPREL16:
16073 case BFD_RELOC_MIPS_LITERAL:
16074 case BFD_RELOC_MIPS_CALL16:
16075 case BFD_RELOC_MIPS_GOT16:
16076 case BFD_RELOC_GPREL32:
16077 case BFD_RELOC_MIPS_GOT_HI16:
16078 case BFD_RELOC_MIPS_GOT_LO16:
16079 case BFD_RELOC_MIPS_CALL_HI16:
16080 case BFD_RELOC_MIPS_CALL_LO16:
16081 case BFD_RELOC_HI16_S_PCREL:
16082 case BFD_RELOC_LO16_PCREL:
16083 case BFD_RELOC_MIPS16_GPREL:
16084 case BFD_RELOC_MIPS16_GOT16:
16085 case BFD_RELOC_MIPS16_CALL16:
16086 case BFD_RELOC_MIPS16_HI16:
16087 case BFD_RELOC_MIPS16_HI16_S:
16088 case BFD_RELOC_MIPS16_LO16:
16089 case BFD_RELOC_MICROMIPS_GOT_DISP:
16090 case BFD_RELOC_MICROMIPS_GOT_PAGE:
16091 case BFD_RELOC_MICROMIPS_GOT_OFST:
16092 case BFD_RELOC_MICROMIPS_SUB:
16093 case BFD_RELOC_MICROMIPS_HIGHEST:
16094 case BFD_RELOC_MICROMIPS_HIGHER:
16095 case BFD_RELOC_MICROMIPS_SCN_DISP:
16096 case BFD_RELOC_MICROMIPS_JALR:
16097 case BFD_RELOC_MICROMIPS_HI16:
16098 case BFD_RELOC_MICROMIPS_HI16_S:
16099 case BFD_RELOC_MICROMIPS_LO16:
16100 case BFD_RELOC_MICROMIPS_GPREL16:
16101 case BFD_RELOC_MICROMIPS_LITERAL:
16102 case BFD_RELOC_MICROMIPS_CALL16:
16103 case BFD_RELOC_MICROMIPS_GOT16:
16104 case BFD_RELOC_MICROMIPS_GOT_HI16:
16105 case BFD_RELOC_MICROMIPS_GOT_LO16:
16106 case BFD_RELOC_MICROMIPS_CALL_HI16:
16107 case BFD_RELOC_MICROMIPS_CALL_LO16:
16108 case BFD_RELOC_MIPS_EH:
16109 if (fixP->fx_done)
16110 {
16111 offsetT value;
16112
16113 if (calculate_reloc (fixP->fx_r_type, *valP, &value))
16114 {
16115 insn = read_reloc_insn (buf, fixP->fx_r_type);
16116 if (mips16_reloc_p (fixP->fx_r_type))
16117 insn |= mips16_immed_extend (value, 16);
16118 else
16119 insn |= (value & 0xffff);
16120 write_reloc_insn (buf, fixP->fx_r_type, insn);
16121 }
16122 else
16123 as_bad_where (fixP->fx_file, fixP->fx_line,
16124 _("unsupported constant in relocation"));
16125 }
16126 break;
16127
16128 case BFD_RELOC_64:
16129 /* This is handled like BFD_RELOC_32, but we output a sign
16130 extended value if we are only 32 bits. */
16131 if (fixP->fx_done)
16132 {
16133 if (8 <= sizeof (valueT))
16134 md_number_to_chars (buf, *valP, 8);
16135 else
16136 {
16137 valueT hiv;
16138
16139 if ((*valP & 0x80000000) != 0)
16140 hiv = 0xffffffff;
16141 else
16142 hiv = 0;
16143 md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4);
16144 md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4);
16145 }
16146 }
16147 break;
16148
16149 case BFD_RELOC_RVA:
16150 case BFD_RELOC_32:
16151 case BFD_RELOC_32_PCREL:
16152 case BFD_RELOC_MIPS_16:
16153 case BFD_RELOC_16:
16154 case BFD_RELOC_8:
16155 /* If we are deleting this reloc entry, we must fill in the
16156 value now. This can happen if we have a .word which is not
16157 resolved when it appears but is later defined. */
16158 if (fixP->fx_done)
16159 md_number_to_chars (buf, *valP, fixP->fx_size);
16160 break;
16161
16162 case BFD_RELOC_MIPS_21_PCREL_S2:
16163 fix_validate_branch (fixP, *valP);
16164 if (!fixP->fx_done)
16165 break;
16166
16167 if (*valP + 0x400000 <= 0x7fffff)
16168 {
16169 insn = read_insn (buf);
16170 insn |= (*valP >> 2) & 0x1fffff;
16171 write_insn (buf, insn);
16172 }
16173 else
16174 as_bad_where (fixP->fx_file, fixP->fx_line,
16175 _("branch out of range"));
16176 break;
16177
16178 case BFD_RELOC_MIPS_26_PCREL_S2:
16179 fix_validate_branch (fixP, *valP);
16180 if (!fixP->fx_done)
16181 break;
16182
16183 if (*valP + 0x8000000 <= 0xfffffff)
16184 {
16185 insn = read_insn (buf);
16186 insn |= (*valP >> 2) & 0x3ffffff;
16187 write_insn (buf, insn);
16188 }
16189 else
16190 as_bad_where (fixP->fx_file, fixP->fx_line,
16191 _("branch out of range"));
16192 break;
16193
16194 case BFD_RELOC_MIPS_18_PCREL_S3:
16195 if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
16196 as_bad_where (fixP->fx_file, fixP->fx_line,
16197 _("PC-relative access using misaligned symbol (%lx)"),
16198 (long) S_GET_VALUE (fixP->fx_addsy));
16199 if ((fixP->fx_offset & 0x7) != 0)
16200 as_bad_where (fixP->fx_file, fixP->fx_line,
16201 _("PC-relative access using misaligned offset (%lx)"),
16202 (long) fixP->fx_offset);
16203 if (!fixP->fx_done)
16204 break;
16205
16206 if (*valP + 0x100000 <= 0x1fffff)
16207 {
16208 insn = read_insn (buf);
16209 insn |= (*valP >> 3) & 0x3ffff;
16210 write_insn (buf, insn);
16211 }
16212 else
16213 as_bad_where (fixP->fx_file, fixP->fx_line,
16214 _("PC-relative access out of range"));
16215 break;
16216
16217 case BFD_RELOC_MIPS_19_PCREL_S2:
16218 if ((*valP & 0x3) != 0)
16219 as_bad_where (fixP->fx_file, fixP->fx_line,
16220 _("PC-relative access to misaligned address (%lx)"),
16221 (long) *valP);
16222 if (!fixP->fx_done)
16223 break;
16224
16225 if (*valP + 0x100000 <= 0x1fffff)
16226 {
16227 insn = read_insn (buf);
16228 insn |= (*valP >> 2) & 0x7ffff;
16229 write_insn (buf, insn);
16230 }
16231 else
16232 as_bad_where (fixP->fx_file, fixP->fx_line,
16233 _("PC-relative access out of range"));
16234 break;
16235
16236 case BFD_RELOC_16_PCREL_S2:
16237 fix_validate_branch (fixP, *valP);
16238
16239 /* We need to save the bits in the instruction since fixup_segment()
16240 might be deleting the relocation entry (i.e., a branch within
16241 the current segment). */
16242 if (! fixP->fx_done)
16243 break;
16244
16245 /* Update old instruction data. */
16246 insn = read_insn (buf);
16247
16248 if (*valP + 0x20000 <= 0x3ffff)
16249 {
16250 insn |= (*valP >> 2) & 0xffff;
16251 write_insn (buf, insn);
16252 }
16253 else if (fixP->fx_tcbit2
16254 && fixP->fx_done
16255 && fixP->fx_frag->fr_address >= text_section->vma
16256 && (fixP->fx_frag->fr_address
16257 < text_section->vma + bfd_section_size (text_section))
16258 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
16259 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
16260 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
16261 {
16262 /* The branch offset is too large. If this is an
16263 unconditional branch, and we are not generating PIC code,
16264 we can convert it to an absolute jump instruction. */
16265 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
16266 insn = 0x0c000000; /* jal */
16267 else
16268 insn = 0x08000000; /* j */
16269 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
16270 fixP->fx_done = 0;
16271 fixP->fx_addsy = section_symbol (text_section);
16272 *valP += md_pcrel_from (fixP);
16273 write_insn (buf, insn);
16274 }
16275 else
16276 {
16277 /* If we got here, we have branch-relaxation disabled,
16278 and there's nothing we can do to fix this instruction
16279 without turning it into a longer sequence. */
16280 as_bad_where (fixP->fx_file, fixP->fx_line,
16281 _("branch out of range"));
16282 }
16283 break;
16284
16285 case BFD_RELOC_MIPS16_16_PCREL_S1:
16286 case BFD_RELOC_MICROMIPS_7_PCREL_S1:
16287 case BFD_RELOC_MICROMIPS_10_PCREL_S1:
16288 case BFD_RELOC_MICROMIPS_16_PCREL_S1:
16289 gas_assert (!fixP->fx_done);
16290 if (fix_bad_cross_mode_branch_p (fixP))
16291 as_bad_where (fixP->fx_file, fixP->fx_line,
16292 _("branch to a symbol in another ISA mode"));
16293 else if (fixP->fx_addsy
16294 && !S_FORCE_RELOC (fixP->fx_addsy, true)
16295 && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy))
16296 && (fixP->fx_offset & 0x1) != 0)
16297 as_bad_where (fixP->fx_file, fixP->fx_line,
16298 _("branch to misaligned address (0x%lx)"),
16299 (long) fix_bad_misaligned_address (fixP));
16300 else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0)
16301 as_bad_where (fixP->fx_file, fixP->fx_line,
16302 _("cannot encode misaligned addend "
16303 "in the relocatable field (0x%lx)"),
16304 (long) fixP->fx_offset);
16305 break;
16306
16307 case BFD_RELOC_VTABLE_INHERIT:
16308 fixP->fx_done = 0;
16309 if (fixP->fx_addsy
16310 && !S_IS_DEFINED (fixP->fx_addsy)
16311 && !S_IS_WEAK (fixP->fx_addsy))
16312 S_SET_WEAK (fixP->fx_addsy);
16313 break;
16314
16315 case BFD_RELOC_NONE:
16316 case BFD_RELOC_VTABLE_ENTRY:
16317 fixP->fx_done = 0;
16318 break;
16319
16320 default:
16321 abort ();
16322 }
16323
16324 /* Remember value for tc_gen_reloc. */
16325 fixP->fx_addnumber = *valP;
16326 }
16327
16328 static symbolS *
get_symbol(void)16329 get_symbol (void)
16330 {
16331 int c;
16332 char *name;
16333 symbolS *p;
16334
16335 c = get_symbol_name (&name);
16336 p = (symbolS *) symbol_find_or_make (name);
16337 (void) restore_line_pointer (c);
16338 return p;
16339 }
16340
16341 /* Align the current frag to a given power of two. If a particular
16342 fill byte should be used, FILL points to an integer that contains
16343 that byte, otherwise FILL is null.
16344
16345 This function used to have the comment:
16346
16347 The MIPS assembler also automatically adjusts any preceding label.
16348
16349 The implementation therefore applied the adjustment to a maximum of
16350 one label. However, other label adjustments are applied to batches
16351 of labels, and adjusting just one caused problems when new labels
16352 were added for the sake of debugging or unwind information.
16353 We therefore adjust all preceding labels (given as LABELS) instead. */
16354
16355 static void
mips_align(int to,int * fill,struct insn_label_list * labels)16356 mips_align (int to, int *fill, struct insn_label_list *labels)
16357 {
16358 mips_emit_delays ();
16359 mips_record_compressed_mode ();
16360 if (fill == NULL && subseg_text_p (now_seg))
16361 frag_align_code (to, 0);
16362 else
16363 frag_align (to, fill ? *fill : 0, 0);
16364 record_alignment (now_seg, to);
16365 mips_move_labels (labels, subseg_text_p (now_seg));
16366 }
16367
16368 /* Align to a given power of two. .align 0 turns off the automatic
16369 alignment used by the data creating pseudo-ops. */
16370
16371 static void
s_align(int x ATTRIBUTE_UNUSED)16372 s_align (int x ATTRIBUTE_UNUSED)
16373 {
16374 int temp, fill_value, *fill_ptr;
16375 long max_alignment = 28;
16376
16377 file_mips_check_options ();
16378
16379 /* o Note that the assembler pulls down any immediately preceding label
16380 to the aligned address.
16381 o It's not documented but auto alignment is reinstated by
16382 a .align pseudo instruction.
16383 o Note also that after auto alignment is turned off the mips assembler
16384 issues an error on attempt to assemble an improperly aligned data item.
16385 We don't. */
16386
16387 temp = get_absolute_expression ();
16388 if (temp > max_alignment)
16389 as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
16390 else if (temp < 0)
16391 {
16392 as_warn (_("alignment negative, 0 assumed"));
16393 temp = 0;
16394 }
16395 if (*input_line_pointer == ',')
16396 {
16397 ++input_line_pointer;
16398 fill_value = get_absolute_expression ();
16399 fill_ptr = &fill_value;
16400 }
16401 else
16402 fill_ptr = 0;
16403
16404 mips_mark_labels ();
16405
16406 if (temp)
16407 {
16408 segment_info_type *si = seg_info (now_seg);
16409 struct insn_label_list *l = si->label_list;
16410 /* Auto alignment should be switched on by next section change. */
16411 auto_align = 1;
16412 mips_align (temp, fill_ptr, l);
16413 }
16414 else
16415 {
16416 auto_align = 0;
16417 }
16418
16419 demand_empty_rest_of_line ();
16420 }
16421
16422 static void
s_change_sec(int sec)16423 s_change_sec (int sec)
16424 {
16425 segT seg;
16426
16427 /* The ELF backend needs to know that we are changing sections, so
16428 that .previous works correctly. We could do something like check
16429 for an obj_section_change_hook macro, but that might be confusing
16430 as it would not be appropriate to use it in the section changing
16431 functions in read.c, since obj-elf.c intercepts those. FIXME:
16432 This should be cleaner, somehow. */
16433 obj_elf_section_change_hook ();
16434
16435 mips_emit_delays ();
16436
16437 switch (sec)
16438 {
16439 case 't':
16440 s_text (0);
16441 break;
16442 case 'd':
16443 s_data (0);
16444 break;
16445 case 'b':
16446 subseg_set (bss_section, (subsegT) get_absolute_expression ());
16447 demand_empty_rest_of_line ();
16448 break;
16449
16450 case 'r':
16451 seg = subseg_new (RDATA_SECTION_NAME,
16452 (subsegT) get_absolute_expression ());
16453 bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD | SEC_READONLY
16454 | SEC_RELOC | SEC_DATA));
16455 if (!startswith (TARGET_OS, "elf"))
16456 record_alignment (seg, 4);
16457 demand_empty_rest_of_line ();
16458 break;
16459
16460 case 's':
16461 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
16462 bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD | SEC_RELOC
16463 | SEC_DATA | SEC_SMALL_DATA));
16464 if (!startswith (TARGET_OS, "elf"))
16465 record_alignment (seg, 4);
16466 demand_empty_rest_of_line ();
16467 break;
16468
16469 case 'B':
16470 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
16471 bfd_set_section_flags (seg, SEC_ALLOC | SEC_SMALL_DATA);
16472 if (!startswith (TARGET_OS, "elf"))
16473 record_alignment (seg, 4);
16474 demand_empty_rest_of_line ();
16475 break;
16476 }
16477
16478 auto_align = 1;
16479 }
16480
16481 void
s_change_section(int ignore ATTRIBUTE_UNUSED)16482 s_change_section (int ignore ATTRIBUTE_UNUSED)
16483 {
16484 char *saved_ilp;
16485 const char *section_name;
16486 char c, next_c = 0;
16487 int section_type;
16488 int section_flag;
16489 int section_entry_size;
16490 int section_alignment;
16491
16492 saved_ilp = input_line_pointer;
16493 section_name = obj_elf_section_name ();
16494 if (section_name == NULL)
16495 return;
16496 c = input_line_pointer[0];
16497 if (c)
16498 next_c = input_line_pointer[1];
16499
16500 /* Do we have .section Name<,"flags">? */
16501 if (c != ',' || (c == ',' && next_c == '"'))
16502 {
16503 input_line_pointer = saved_ilp;
16504 obj_elf_section (ignore);
16505 return;
16506 }
16507
16508 input_line_pointer++;
16509
16510 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16511 if (c == ',')
16512 section_type = get_absolute_expression ();
16513 else
16514 section_type = 0;
16515
16516 if (*input_line_pointer++ == ',')
16517 section_flag = get_absolute_expression ();
16518 else
16519 section_flag = 0;
16520
16521 if (*input_line_pointer++ == ',')
16522 section_entry_size = get_absolute_expression ();
16523 else
16524 section_entry_size = 0;
16525
16526 if (*input_line_pointer++ == ',')
16527 section_alignment = get_absolute_expression ();
16528 else
16529 section_alignment = 0;
16530
16531 /* FIXME: really ignore? */
16532 (void) section_alignment;
16533
16534 /* When using the generic form of .section (as implemented by obj-elf.c),
16535 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16536 traditionally had to fall back on the more common @progbits instead.
16537
16538 There's nothing really harmful in this, since bfd will correct
16539 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16540 means that, for backwards compatibility, the special_section entries
16541 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16542
16543 Even so, we shouldn't force users of the MIPS .section syntax to
16544 incorrectly label the sections as SHT_PROGBITS. The best compromise
16545 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16546 generic type-checking code. */
16547 if (section_type == SHT_MIPS_DWARF)
16548 section_type = SHT_PROGBITS;
16549
16550 obj_elf_change_section (section_name, section_type, section_flag,
16551 section_entry_size, 0, false);
16552 }
16553
16554 void
mips_enable_auto_align(void)16555 mips_enable_auto_align (void)
16556 {
16557 auto_align = 1;
16558 }
16559
16560 static void
s_cons(int log_size)16561 s_cons (int log_size)
16562 {
16563 segment_info_type *si = seg_info (now_seg);
16564 struct insn_label_list *l = si->label_list;
16565
16566 mips_emit_delays ();
16567 if (log_size > 0 && auto_align)
16568 mips_align (log_size, 0, l);
16569 cons (1 << log_size);
16570 mips_clear_insn_labels ();
16571 }
16572
16573 static void
s_float_cons(int type)16574 s_float_cons (int type)
16575 {
16576 segment_info_type *si = seg_info (now_seg);
16577 struct insn_label_list *l = si->label_list;
16578
16579 mips_emit_delays ();
16580
16581 if (auto_align)
16582 {
16583 if (type == 'd')
16584 mips_align (3, 0, l);
16585 else
16586 mips_align (2, 0, l);
16587 }
16588
16589 float_cons (type);
16590 mips_clear_insn_labels ();
16591 }
16592
16593 /* Handle .globl. We need to override it because on Irix 5 you are
16594 permitted to say
16595 .globl foo .text
16596 where foo is an undefined symbol, to mean that foo should be
16597 considered to be the address of a function. */
16598
16599 static void
s_mips_globl(int x ATTRIBUTE_UNUSED)16600 s_mips_globl (int x ATTRIBUTE_UNUSED)
16601 {
16602 char *name;
16603 int c;
16604 symbolS *symbolP;
16605
16606 do
16607 {
16608 c = get_symbol_name (&name);
16609 symbolP = symbol_find_or_make (name);
16610 S_SET_EXTERNAL (symbolP);
16611
16612 *input_line_pointer = c;
16613 SKIP_WHITESPACE_AFTER_NAME ();
16614
16615 if (!is_end_of_line[(unsigned char) *input_line_pointer]
16616 && (*input_line_pointer != ','))
16617 {
16618 char *secname;
16619 asection *sec;
16620
16621 c = get_symbol_name (&secname);
16622 sec = bfd_get_section_by_name (stdoutput, secname);
16623 if (sec == NULL)
16624 as_bad (_("%s: no such section"), secname);
16625 (void) restore_line_pointer (c);
16626
16627 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
16628 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
16629 }
16630
16631 c = *input_line_pointer;
16632 if (c == ',')
16633 {
16634 input_line_pointer++;
16635 SKIP_WHITESPACE ();
16636 if (is_end_of_line[(unsigned char) *input_line_pointer])
16637 c = '\n';
16638 }
16639 }
16640 while (c == ',');
16641
16642 demand_empty_rest_of_line ();
16643 }
16644
16645 #ifdef TE_IRIX
16646 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16647 any undefined non-function symbol to STT_OBJECT. We try to be
16648 compatible, since newer Irix 5 and 6 linkers care. */
16649
16650 void
mips_frob_symbol(symbolS * symp ATTRIBUTE_UNUSED)16651 mips_frob_symbol (symbolS *symp ATTRIBUTE_UNUSED)
16652 {
16653 /* This late in assembly we can set BSF_OBJECT indiscriminately
16654 and let elf.c:swap_out_syms sort out the symbol type. */
16655 flagword *flags = &symbol_get_bfdsym (symp)->flags;
16656 if ((*flags & (BSF_GLOBAL | BSF_WEAK)) != 0
16657 || !S_IS_DEFINED (symp))
16658 *flags |= BSF_OBJECT;
16659 }
16660 #endif
16661
16662 static void
s_option(int x ATTRIBUTE_UNUSED)16663 s_option (int x ATTRIBUTE_UNUSED)
16664 {
16665 char *opt;
16666 char c;
16667
16668 c = get_symbol_name (&opt);
16669
16670 if (*opt == 'O')
16671 {
16672 /* FIXME: What does this mean? */
16673 }
16674 else if (startswith (opt, "pic") && ISDIGIT (opt[3]) && opt[4] == '\0')
16675 {
16676 int i;
16677
16678 i = atoi (opt + 3);
16679 if (i != 0 && i != 2)
16680 as_bad (_(".option pic%d not supported"), i);
16681 else if (mips_pic == VXWORKS_PIC)
16682 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i);
16683 else if (i == 0)
16684 mips_pic = NO_PIC;
16685 else if (i == 2)
16686 {
16687 mips_pic = SVR4_PIC;
16688 mips_abicalls = true;
16689 }
16690
16691 if (mips_pic == SVR4_PIC)
16692 {
16693 if (g_switch_seen && g_switch_value != 0)
16694 as_warn (_("-G may not be used with SVR4 PIC code"));
16695 g_switch_value = 0;
16696 bfd_set_gp_size (stdoutput, 0);
16697 }
16698 }
16699 else
16700 as_warn (_("unrecognized option \"%s\""), opt);
16701
16702 (void) restore_line_pointer (c);
16703 demand_empty_rest_of_line ();
16704 }
16705
16706 /* This structure is used to hold a stack of .set values. */
16707
16708 struct mips_option_stack
16709 {
16710 struct mips_option_stack *next;
16711 struct mips_set_options options;
16712 };
16713
16714 static struct mips_option_stack *mips_opts_stack;
16715
16716 /* Return status for .set/.module option handling. */
16717
16718 enum code_option_type
16719 {
16720 /* Unrecognized option. */
16721 OPTION_TYPE_BAD = -1,
16722
16723 /* Ordinary option. */
16724 OPTION_TYPE_NORMAL,
16725
16726 /* ISA changing option. */
16727 OPTION_TYPE_ISA
16728 };
16729
16730 /* Handle common .set/.module options. Return status indicating option
16731 type. */
16732
16733 static enum code_option_type
parse_code_option(char * name)16734 parse_code_option (char * name)
16735 {
16736 bool isa_set = false;
16737 const struct mips_ase *ase;
16738
16739 if (startswith (name, "at="))
16740 {
16741 char *s = name + 3;
16742
16743 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
16744 as_bad (_("unrecognized register name `%s'"), s);
16745 }
16746 else if (strcmp (name, "at") == 0)
16747 mips_opts.at = ATREG;
16748 else if (strcmp (name, "noat") == 0)
16749 mips_opts.at = ZERO;
16750 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
16751 mips_opts.nomove = 0;
16752 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
16753 mips_opts.nomove = 1;
16754 else if (strcmp (name, "bopt") == 0)
16755 mips_opts.nobopt = 0;
16756 else if (strcmp (name, "nobopt") == 0)
16757 mips_opts.nobopt = 1;
16758 else if (strcmp (name, "gp=32") == 0)
16759 mips_opts.gp = 32;
16760 else if (strcmp (name, "gp=64") == 0)
16761 mips_opts.gp = 64;
16762 else if (strcmp (name, "fp=32") == 0)
16763 mips_opts.fp = 32;
16764 else if (strcmp (name, "fp=xx") == 0)
16765 mips_opts.fp = 0;
16766 else if (strcmp (name, "fp=64") == 0)
16767 mips_opts.fp = 64;
16768 else if (strcmp (name, "softfloat") == 0)
16769 mips_opts.soft_float = 1;
16770 else if (strcmp (name, "hardfloat") == 0)
16771 mips_opts.soft_float = 0;
16772 else if (strcmp (name, "singlefloat") == 0)
16773 mips_opts.single_float = 1;
16774 else if (strcmp (name, "doublefloat") == 0)
16775 mips_opts.single_float = 0;
16776 else if (strcmp (name, "nooddspreg") == 0)
16777 mips_opts.oddspreg = 0;
16778 else if (strcmp (name, "oddspreg") == 0)
16779 mips_opts.oddspreg = 1;
16780 else if (strcmp (name, "mips16") == 0
16781 || strcmp (name, "MIPS-16") == 0)
16782 mips_opts.mips16 = 1;
16783 else if (strcmp (name, "nomips16") == 0
16784 || strcmp (name, "noMIPS-16") == 0)
16785 mips_opts.mips16 = 0;
16786 else if (strcmp (name, "micromips") == 0)
16787 mips_opts.micromips = 1;
16788 else if (strcmp (name, "nomicromips") == 0)
16789 mips_opts.micromips = 0;
16790 else if (name[0] == 'n'
16791 && name[1] == 'o'
16792 && (ase = mips_lookup_ase (name + 2)))
16793 mips_set_ase (ase, &mips_opts, false);
16794 else if ((ase = mips_lookup_ase (name)))
16795 mips_set_ase (ase, &mips_opts, true);
16796 else if (startswith (name, "mips") || startswith (name, "arch="))
16797 {
16798 /* Permit the user to change the ISA and architecture on the fly.
16799 Needless to say, misuse can cause serious problems. */
16800 if (startswith (name, "arch="))
16801 {
16802 const struct mips_cpu_info *p;
16803
16804 p = mips_parse_cpu ("internal use", name + 5);
16805 if (!p)
16806 as_bad (_("unknown architecture %s"), name + 5);
16807 else
16808 {
16809 mips_opts.arch = p->cpu;
16810 mips_opts.isa = p->isa;
16811 isa_set = true;
16812 mips_opts.init_ase = p->ase;
16813 }
16814 }
16815 else if (startswith (name, "mips"))
16816 {
16817 const struct mips_cpu_info *p;
16818
16819 p = mips_parse_cpu ("internal use", name);
16820 if (!p)
16821 as_bad (_("unknown ISA level %s"), name + 4);
16822 else
16823 {
16824 mips_opts.arch = p->cpu;
16825 mips_opts.isa = p->isa;
16826 isa_set = true;
16827 mips_opts.init_ase = p->ase;
16828 }
16829 }
16830 else
16831 as_bad (_("unknown ISA or architecture %s"), name);
16832 }
16833 else if (strcmp (name, "autoextend") == 0)
16834 mips_opts.noautoextend = 0;
16835 else if (strcmp (name, "noautoextend") == 0)
16836 mips_opts.noautoextend = 1;
16837 else if (strcmp (name, "insn32") == 0)
16838 mips_opts.insn32 = true;
16839 else if (strcmp (name, "noinsn32") == 0)
16840 mips_opts.insn32 = false;
16841 else if (strcmp (name, "sym32") == 0)
16842 mips_opts.sym32 = true;
16843 else if (strcmp (name, "nosym32") == 0)
16844 mips_opts.sym32 = false;
16845 else
16846 return OPTION_TYPE_BAD;
16847
16848 return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL;
16849 }
16850
16851 /* Handle the .set pseudo-op. */
16852
16853 static void
s_mipsset(int x ATTRIBUTE_UNUSED)16854 s_mipsset (int x ATTRIBUTE_UNUSED)
16855 {
16856 enum code_option_type type = OPTION_TYPE_NORMAL;
16857 char *name = input_line_pointer, ch;
16858
16859 file_mips_check_options ();
16860
16861 while (!is_end_of_line[(unsigned char) *input_line_pointer])
16862 ++input_line_pointer;
16863 ch = *input_line_pointer;
16864 *input_line_pointer = '\0';
16865
16866 if (strchr (name, ','))
16867 {
16868 /* Generic ".set" directive; use the generic handler. */
16869 *input_line_pointer = ch;
16870 input_line_pointer = name;
16871 s_set (0);
16872 return;
16873 }
16874
16875 if (strcmp (name, "reorder") == 0)
16876 {
16877 if (mips_opts.noreorder)
16878 end_noreorder ();
16879 }
16880 else if (strcmp (name, "noreorder") == 0)
16881 {
16882 if (!mips_opts.noreorder)
16883 start_noreorder ();
16884 }
16885 else if (strcmp (name, "macro") == 0)
16886 mips_opts.warn_about_macros = 0;
16887 else if (strcmp (name, "nomacro") == 0)
16888 {
16889 if (mips_opts.noreorder == 0)
16890 as_bad (_("`noreorder' must be set before `nomacro'"));
16891 mips_opts.warn_about_macros = 1;
16892 }
16893 else if (strcmp (name, "gp=default") == 0)
16894 mips_opts.gp = file_mips_opts.gp;
16895 else if (strcmp (name, "fp=default") == 0)
16896 mips_opts.fp = file_mips_opts.fp;
16897 else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
16898 {
16899 mips_opts.isa = file_mips_opts.isa;
16900 mips_opts.arch = file_mips_opts.arch;
16901 mips_opts.init_ase = file_mips_opts.init_ase;
16902 mips_opts.gp = file_mips_opts.gp;
16903 mips_opts.fp = file_mips_opts.fp;
16904 }
16905 else if (strcmp (name, "push") == 0)
16906 {
16907 struct mips_option_stack *s;
16908
16909 s = XNEW (struct mips_option_stack);
16910 s->next = mips_opts_stack;
16911 s->options = mips_opts;
16912 mips_opts_stack = s;
16913 }
16914 else if (strcmp (name, "pop") == 0)
16915 {
16916 struct mips_option_stack *s;
16917
16918 s = mips_opts_stack;
16919 if (s == NULL)
16920 as_bad (_(".set pop with no .set push"));
16921 else
16922 {
16923 /* If we're changing the reorder mode we need to handle
16924 delay slots correctly. */
16925 if (s->options.noreorder && ! mips_opts.noreorder)
16926 start_noreorder ();
16927 else if (! s->options.noreorder && mips_opts.noreorder)
16928 end_noreorder ();
16929
16930 mips_opts = s->options;
16931 mips_opts_stack = s->next;
16932 free (s);
16933 }
16934 }
16935 else
16936 {
16937 type = parse_code_option (name);
16938 if (type == OPTION_TYPE_BAD)
16939 as_warn (_("tried to set unrecognized symbol: %s\n"), name);
16940 }
16941
16942 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16943 registers based on what is supported by the arch/cpu. */
16944 if (type == OPTION_TYPE_ISA)
16945 {
16946 switch (mips_opts.isa)
16947 {
16948 case 0:
16949 break;
16950 case ISA_MIPS1:
16951 /* MIPS I cannot support FPXX. */
16952 mips_opts.fp = 32;
16953 /* fall-through. */
16954 case ISA_MIPS2:
16955 case ISA_MIPS32:
16956 case ISA_MIPS32R2:
16957 case ISA_MIPS32R3:
16958 case ISA_MIPS32R5:
16959 mips_opts.gp = 32;
16960 if (mips_opts.fp != 0)
16961 mips_opts.fp = 32;
16962 break;
16963 case ISA_MIPS32R6:
16964 mips_opts.gp = 32;
16965 mips_opts.fp = 64;
16966 break;
16967 case ISA_MIPS3:
16968 case ISA_MIPS4:
16969 case ISA_MIPS5:
16970 case ISA_MIPS64:
16971 case ISA_MIPS64R2:
16972 case ISA_MIPS64R3:
16973 case ISA_MIPS64R5:
16974 case ISA_MIPS64R6:
16975 mips_opts.gp = 64;
16976 if (mips_opts.fp != 0)
16977 {
16978 if (mips_opts.arch == CPU_R5900)
16979 mips_opts.fp = 32;
16980 else
16981 mips_opts.fp = 64;
16982 }
16983 break;
16984 default:
16985 as_bad (_("unknown ISA level %s"), name + 4);
16986 break;
16987 }
16988 }
16989
16990 mips_check_options (&mips_opts, false);
16991
16992 mips_check_isa_supports_ases ();
16993 *input_line_pointer = ch;
16994 demand_empty_rest_of_line ();
16995 }
16996
16997 /* Handle the .module pseudo-op. */
16998
16999 static void
s_module(int ignore ATTRIBUTE_UNUSED)17000 s_module (int ignore ATTRIBUTE_UNUSED)
17001 {
17002 char *name = input_line_pointer, ch;
17003
17004 while (!is_end_of_line[(unsigned char) *input_line_pointer])
17005 ++input_line_pointer;
17006 ch = *input_line_pointer;
17007 *input_line_pointer = '\0';
17008
17009 if (!file_mips_opts_checked)
17010 {
17011 if (parse_code_option (name) == OPTION_TYPE_BAD)
17012 as_bad (_(".module used with unrecognized symbol: %s\n"), name);
17013
17014 /* Update module level settings from mips_opts. */
17015 file_mips_opts = mips_opts;
17016 }
17017 else
17018 as_bad (_(".module is not permitted after generating code"));
17019
17020 *input_line_pointer = ch;
17021 demand_empty_rest_of_line ();
17022 }
17023
17024 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
17025 .option pic2. It means to generate SVR4 PIC calls. */
17026
17027 static void
s_abicalls(int ignore ATTRIBUTE_UNUSED)17028 s_abicalls (int ignore ATTRIBUTE_UNUSED)
17029 {
17030 mips_pic = SVR4_PIC;
17031 mips_abicalls = true;
17032
17033 if (g_switch_seen && g_switch_value != 0)
17034 as_warn (_("-G may not be used with SVR4 PIC code"));
17035 g_switch_value = 0;
17036
17037 bfd_set_gp_size (stdoutput, 0);
17038 demand_empty_rest_of_line ();
17039 }
17040
17041 /* Handle the .cpload pseudo-op. This is used when generating SVR4
17042 PIC code. It sets the $gp register for the function based on the
17043 function address, which is in the register named in the argument.
17044 This uses a relocation against _gp_disp, which is handled specially
17045 by the linker. The result is:
17046 lui $gp,%hi(_gp_disp)
17047 addiu $gp,$gp,%lo(_gp_disp)
17048 addu $gp,$gp,.cpload argument
17049 The .cpload argument is normally $25 == $t9.
17050
17051 The -mno-shared option changes this to:
17052 lui $gp,%hi(__gnu_local_gp)
17053 addiu $gp,$gp,%lo(__gnu_local_gp)
17054 and the argument is ignored. This saves an instruction, but the
17055 resulting code is not position independent; it uses an absolute
17056 address for __gnu_local_gp. Thus code assembled with -mno-shared
17057 can go into an ordinary executable, but not into a shared library. */
17058
17059 static void
s_cpload(int ignore ATTRIBUTE_UNUSED)17060 s_cpload (int ignore ATTRIBUTE_UNUSED)
17061 {
17062 expressionS ex;
17063 int reg;
17064 int in_shared;
17065
17066 file_mips_check_options ();
17067
17068 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17069 .cpload is ignored. */
17070 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
17071 {
17072 s_ignore (0);
17073 return;
17074 }
17075
17076 if (mips_opts.mips16)
17077 {
17078 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
17079 ignore_rest_of_line ();
17080 return;
17081 }
17082
17083 /* .cpload should be in a .set noreorder section. */
17084 if (mips_opts.noreorder == 0)
17085 as_warn (_(".cpload not in noreorder section"));
17086
17087 reg = tc_get_register (0);
17088
17089 /* If we need to produce a 64-bit address, we are better off using
17090 the default instruction sequence. */
17091 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
17092
17093 ex.X_op = O_symbol;
17094 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
17095 "__gnu_local_gp");
17096 ex.X_op_symbol = NULL;
17097 ex.X_add_number = 0;
17098
17099 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17100 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
17101
17102 mips_mark_labels ();
17103 mips_assembling_insn = true;
17104
17105 macro_start ();
17106 macro_build_lui (&ex, mips_gp_register);
17107 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17108 mips_gp_register, BFD_RELOC_LO16);
17109 if (in_shared)
17110 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
17111 mips_gp_register, reg);
17112 macro_end ();
17113
17114 mips_assembling_insn = false;
17115 demand_empty_rest_of_line ();
17116 }
17117
17118 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17119 .cpsetup $reg1, offset|$reg2, label
17120
17121 If offset is given, this results in:
17122 sd $gp, offset($sp)
17123 lui $gp, %hi(%neg(%gp_rel(label)))
17124 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17125 daddu $gp, $gp, $reg1
17126
17127 If $reg2 is given, this results in:
17128 or $reg2, $gp, $0
17129 lui $gp, %hi(%neg(%gp_rel(label)))
17130 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17131 daddu $gp, $gp, $reg1
17132 $reg1 is normally $25 == $t9.
17133
17134 The -mno-shared option replaces the last three instructions with
17135 lui $gp,%hi(_gp)
17136 addiu $gp,$gp,%lo(_gp) */
17137
17138 static void
s_cpsetup(int ignore ATTRIBUTE_UNUSED)17139 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
17140 {
17141 expressionS ex_off;
17142 expressionS ex_sym;
17143 int reg1;
17144
17145 file_mips_check_options ();
17146
17147 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17148 We also need NewABI support. */
17149 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17150 {
17151 s_ignore (0);
17152 return;
17153 }
17154
17155 if (mips_opts.mips16)
17156 {
17157 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17158 ignore_rest_of_line ();
17159 return;
17160 }
17161
17162 reg1 = tc_get_register (0);
17163 SKIP_WHITESPACE ();
17164 if (*input_line_pointer != ',')
17165 {
17166 as_bad (_("missing argument separator ',' for .cpsetup"));
17167 return;
17168 }
17169 else
17170 ++input_line_pointer;
17171 SKIP_WHITESPACE ();
17172 if (*input_line_pointer == '$')
17173 {
17174 mips_cpreturn_register = tc_get_register (0);
17175 mips_cpreturn_offset = -1;
17176 }
17177 else
17178 {
17179 mips_cpreturn_offset = get_absolute_expression ();
17180 mips_cpreturn_register = -1;
17181 }
17182 SKIP_WHITESPACE ();
17183 if (*input_line_pointer != ',')
17184 {
17185 as_bad (_("missing argument separator ',' for .cpsetup"));
17186 return;
17187 }
17188 else
17189 ++input_line_pointer;
17190 SKIP_WHITESPACE ();
17191 expression (&ex_sym);
17192
17193 mips_mark_labels ();
17194 mips_assembling_insn = true;
17195
17196 macro_start ();
17197 if (mips_cpreturn_register == -1)
17198 {
17199 ex_off.X_op = O_constant;
17200 ex_off.X_add_symbol = NULL;
17201 ex_off.X_op_symbol = NULL;
17202 ex_off.X_add_number = mips_cpreturn_offset;
17203
17204 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
17205 BFD_RELOC_LO16, SP);
17206 }
17207 else
17208 move_register (mips_cpreturn_register, mips_gp_register);
17209
17210 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
17211 {
17212 macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register,
17213 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
17214 BFD_RELOC_HI16_S);
17215
17216 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
17217 mips_gp_register, -1, BFD_RELOC_GPREL16,
17218 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
17219
17220 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
17221 mips_gp_register, reg1);
17222 }
17223 else
17224 {
17225 expressionS ex;
17226
17227 ex.X_op = O_symbol;
17228 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
17229 ex.X_op_symbol = NULL;
17230 ex.X_add_number = 0;
17231
17232 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17233 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
17234
17235 macro_build_lui (&ex, mips_gp_register);
17236 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
17237 mips_gp_register, BFD_RELOC_LO16);
17238 }
17239
17240 macro_end ();
17241
17242 mips_assembling_insn = false;
17243 demand_empty_rest_of_line ();
17244 }
17245
17246 static void
s_cplocal(int ignore ATTRIBUTE_UNUSED)17247 s_cplocal (int ignore ATTRIBUTE_UNUSED)
17248 {
17249 file_mips_check_options ();
17250
17251 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17252 .cplocal is ignored. */
17253 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17254 {
17255 s_ignore (0);
17256 return;
17257 }
17258
17259 if (mips_opts.mips16)
17260 {
17261 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17262 ignore_rest_of_line ();
17263 return;
17264 }
17265
17266 mips_gp_register = tc_get_register (0);
17267 demand_empty_rest_of_line ();
17268 }
17269
17270 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17271 offset from $sp. The offset is remembered, and after making a PIC
17272 call $gp is restored from that location. */
17273
17274 static void
s_cprestore(int ignore ATTRIBUTE_UNUSED)17275 s_cprestore (int ignore ATTRIBUTE_UNUSED)
17276 {
17277 expressionS ex;
17278
17279 file_mips_check_options ();
17280
17281 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17282 .cprestore is ignored. */
17283 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
17284 {
17285 s_ignore (0);
17286 return;
17287 }
17288
17289 if (mips_opts.mips16)
17290 {
17291 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17292 ignore_rest_of_line ();
17293 return;
17294 }
17295
17296 mips_cprestore_offset = get_absolute_expression ();
17297 mips_cprestore_valid = 1;
17298
17299 ex.X_op = O_constant;
17300 ex.X_add_symbol = NULL;
17301 ex.X_op_symbol = NULL;
17302 ex.X_add_number = mips_cprestore_offset;
17303
17304 mips_mark_labels ();
17305 mips_assembling_insn = true;
17306
17307 macro_start ();
17308 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
17309 SP, HAVE_64BIT_ADDRESSES);
17310 macro_end ();
17311
17312 mips_assembling_insn = false;
17313 demand_empty_rest_of_line ();
17314 }
17315
17316 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17317 was given in the preceding .cpsetup, it results in:
17318 ld $gp, offset($sp)
17319
17320 If a register $reg2 was given there, it results in:
17321 or $gp, $reg2, $0 */
17322
17323 static void
s_cpreturn(int ignore ATTRIBUTE_UNUSED)17324 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
17325 {
17326 expressionS ex;
17327
17328 file_mips_check_options ();
17329
17330 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17331 We also need NewABI support. */
17332 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17333 {
17334 s_ignore (0);
17335 return;
17336 }
17337
17338 if (mips_opts.mips16)
17339 {
17340 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17341 ignore_rest_of_line ();
17342 return;
17343 }
17344
17345 mips_mark_labels ();
17346 mips_assembling_insn = true;
17347
17348 macro_start ();
17349 if (mips_cpreturn_register == -1)
17350 {
17351 ex.X_op = O_constant;
17352 ex.X_add_symbol = NULL;
17353 ex.X_op_symbol = NULL;
17354 ex.X_add_number = mips_cpreturn_offset;
17355
17356 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
17357 }
17358 else
17359 move_register (mips_gp_register, mips_cpreturn_register);
17360
17361 macro_end ();
17362
17363 mips_assembling_insn = false;
17364 demand_empty_rest_of_line ();
17365 }
17366
17367 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17368 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17369 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17370 debug information or MIPS16 TLS. */
17371
17372 static void
s_tls_rel_directive(const size_t bytes,const char * dirstr,bfd_reloc_code_real_type rtype)17373 s_tls_rel_directive (const size_t bytes, const char *dirstr,
17374 bfd_reloc_code_real_type rtype)
17375 {
17376 expressionS ex;
17377 char *p;
17378
17379 expression (&ex);
17380
17381 if (ex.X_op != O_symbol)
17382 {
17383 as_bad (_("unsupported use of %s"), dirstr);
17384 ignore_rest_of_line ();
17385 }
17386
17387 p = frag_more (bytes);
17388 md_number_to_chars (p, 0, bytes);
17389 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false, rtype);
17390 demand_empty_rest_of_line ();
17391 mips_clear_insn_labels ();
17392 }
17393
17394 /* Handle .dtprelword. */
17395
17396 static void
s_dtprelword(int ignore ATTRIBUTE_UNUSED)17397 s_dtprelword (int ignore ATTRIBUTE_UNUSED)
17398 {
17399 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32);
17400 }
17401
17402 /* Handle .dtpreldword. */
17403
17404 static void
s_dtpreldword(int ignore ATTRIBUTE_UNUSED)17405 s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
17406 {
17407 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64);
17408 }
17409
17410 /* Handle .tprelword. */
17411
17412 static void
s_tprelword(int ignore ATTRIBUTE_UNUSED)17413 s_tprelword (int ignore ATTRIBUTE_UNUSED)
17414 {
17415 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32);
17416 }
17417
17418 /* Handle .tpreldword. */
17419
17420 static void
s_tpreldword(int ignore ATTRIBUTE_UNUSED)17421 s_tpreldword (int ignore ATTRIBUTE_UNUSED)
17422 {
17423 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64);
17424 }
17425
17426 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17427 code. It sets the offset to use in gp_rel relocations. */
17428
17429 static void
s_gpvalue(int ignore ATTRIBUTE_UNUSED)17430 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
17431 {
17432 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17433 We also need NewABI support. */
17434 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
17435 {
17436 s_ignore (0);
17437 return;
17438 }
17439
17440 mips_gprel_offset = get_absolute_expression ();
17441
17442 demand_empty_rest_of_line ();
17443 }
17444
17445 /* Handle the .gpword pseudo-op. This is used when generating PIC
17446 code. It generates a 32 bit GP relative reloc. */
17447
17448 static void
s_gpword(int ignore ATTRIBUTE_UNUSED)17449 s_gpword (int ignore ATTRIBUTE_UNUSED)
17450 {
17451 segment_info_type *si;
17452 struct insn_label_list *l;
17453 expressionS ex;
17454 char *p;
17455
17456 /* When not generating PIC code, this is treated as .word. */
17457 if (mips_pic != SVR4_PIC)
17458 {
17459 s_cons (2);
17460 return;
17461 }
17462
17463 si = seg_info (now_seg);
17464 l = si->label_list;
17465 mips_emit_delays ();
17466 if (auto_align)
17467 mips_align (2, 0, l);
17468
17469 expression (&ex);
17470 mips_clear_insn_labels ();
17471
17472 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17473 {
17474 as_bad (_("unsupported use of .gpword"));
17475 ignore_rest_of_line ();
17476 }
17477
17478 p = frag_more (4);
17479 md_number_to_chars (p, 0, 4);
17480 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
17481 BFD_RELOC_GPREL32);
17482
17483 demand_empty_rest_of_line ();
17484 }
17485
17486 static void
s_gpdword(int ignore ATTRIBUTE_UNUSED)17487 s_gpdword (int ignore ATTRIBUTE_UNUSED)
17488 {
17489 segment_info_type *si;
17490 struct insn_label_list *l;
17491 expressionS ex;
17492 char *p;
17493
17494 /* When not generating PIC code, this is treated as .dword. */
17495 if (mips_pic != SVR4_PIC)
17496 {
17497 s_cons (3);
17498 return;
17499 }
17500
17501 si = seg_info (now_seg);
17502 l = si->label_list;
17503 mips_emit_delays ();
17504 if (auto_align)
17505 mips_align (3, 0, l);
17506
17507 expression (&ex);
17508 mips_clear_insn_labels ();
17509
17510 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17511 {
17512 as_bad (_("unsupported use of .gpdword"));
17513 ignore_rest_of_line ();
17514 }
17515
17516 p = frag_more (8);
17517 md_number_to_chars (p, 0, 8);
17518 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
17519 BFD_RELOC_GPREL32)->fx_tcbit = 1;
17520
17521 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17522 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
17523 false, BFD_RELOC_64)->fx_tcbit = 1;
17524
17525 demand_empty_rest_of_line ();
17526 }
17527
17528 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17529 tables. It generates a R_MIPS_EH reloc. */
17530
17531 static void
s_ehword(int ignore ATTRIBUTE_UNUSED)17532 s_ehword (int ignore ATTRIBUTE_UNUSED)
17533 {
17534 expressionS ex;
17535 char *p;
17536
17537 mips_emit_delays ();
17538
17539 expression (&ex);
17540 mips_clear_insn_labels ();
17541
17542 if (ex.X_op != O_symbol || ex.X_add_number != 0)
17543 {
17544 as_bad (_("unsupported use of .ehword"));
17545 ignore_rest_of_line ();
17546 }
17547
17548 p = frag_more (4);
17549 md_number_to_chars (p, 0, 4);
17550 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false,
17551 BFD_RELOC_32_PCREL);
17552
17553 demand_empty_rest_of_line ();
17554 }
17555
17556 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17557 tables in SVR4 PIC code. */
17558
17559 static void
s_cpadd(int ignore ATTRIBUTE_UNUSED)17560 s_cpadd (int ignore ATTRIBUTE_UNUSED)
17561 {
17562 int reg;
17563
17564 file_mips_check_options ();
17565
17566 /* This is ignored when not generating SVR4 PIC code. */
17567 if (mips_pic != SVR4_PIC)
17568 {
17569 s_ignore (0);
17570 return;
17571 }
17572
17573 mips_mark_labels ();
17574 mips_assembling_insn = true;
17575
17576 /* Add $gp to the register named as an argument. */
17577 macro_start ();
17578 reg = tc_get_register (0);
17579 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
17580 macro_end ();
17581
17582 mips_assembling_insn = false;
17583 demand_empty_rest_of_line ();
17584 }
17585
17586 /* Handle the .insn pseudo-op. This marks instruction labels in
17587 mips16/micromips mode. This permits the linker to handle them specially,
17588 such as generating jalx instructions when needed. We also make
17589 them odd for the duration of the assembly, in order to generate the
17590 right sort of code. We will make them even in the adjust_symtab
17591 routine, while leaving them marked. This is convenient for the
17592 debugger and the disassembler. The linker knows to make them odd
17593 again. */
17594
17595 static void
s_insn(int ignore ATTRIBUTE_UNUSED)17596 s_insn (int ignore ATTRIBUTE_UNUSED)
17597 {
17598 file_mips_check_options ();
17599 file_ase_mips16 |= mips_opts.mips16;
17600 file_ase_micromips |= mips_opts.micromips;
17601
17602 mips_mark_labels ();
17603
17604 demand_empty_rest_of_line ();
17605 }
17606
17607 /* Handle the .nan pseudo-op. */
17608
17609 static void
s_nan(int ignore ATTRIBUTE_UNUSED)17610 s_nan (int ignore ATTRIBUTE_UNUSED)
17611 {
17612 static const char str_legacy[] = "legacy";
17613 static const char str_2008[] = "2008";
17614 size_t i;
17615
17616 for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++);
17617
17618 if (i == sizeof (str_2008) - 1
17619 && memcmp (input_line_pointer, str_2008, i) == 0)
17620 mips_nan2008 = 1;
17621 else if (i == sizeof (str_legacy) - 1
17622 && memcmp (input_line_pointer, str_legacy, i) == 0)
17623 {
17624 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
17625 mips_nan2008 = 0;
17626 else
17627 as_bad (_("`%s' does not support legacy NaN"),
17628 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
17629 }
17630 else
17631 as_bad (_("bad .nan directive"));
17632
17633 input_line_pointer += i;
17634 demand_empty_rest_of_line ();
17635 }
17636
17637 /* Handle a .stab[snd] directive. Ideally these directives would be
17638 implemented in a transparent way, so that removing them would not
17639 have any effect on the generated instructions. However, s_stab
17640 internally changes the section, so in practice we need to decide
17641 now whether the preceding label marks compressed code. We do not
17642 support changing the compression mode of a label after a .stab*
17643 directive, such as in:
17644
17645 foo:
17646 .stabs ...
17647 .set mips16
17648
17649 so the current mode wins. */
17650
17651 static void
s_mips_stab(int type)17652 s_mips_stab (int type)
17653 {
17654 file_mips_check_options ();
17655 mips_mark_labels ();
17656 s_stab (type);
17657 }
17658
17659 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17660
17661 static void
s_mips_weakext(int ignore ATTRIBUTE_UNUSED)17662 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
17663 {
17664 char *name;
17665 int c;
17666 symbolS *symbolP;
17667 expressionS exp;
17668
17669 c = get_symbol_name (&name);
17670 symbolP = symbol_find_or_make (name);
17671 S_SET_WEAK (symbolP);
17672 *input_line_pointer = c;
17673
17674 SKIP_WHITESPACE_AFTER_NAME ();
17675
17676 if (! is_end_of_line[(unsigned char) *input_line_pointer])
17677 {
17678 if (S_IS_DEFINED (symbolP))
17679 {
17680 as_bad (_("ignoring attempt to redefine symbol %s"),
17681 S_GET_NAME (symbolP));
17682 ignore_rest_of_line ();
17683 return;
17684 }
17685
17686 if (*input_line_pointer == ',')
17687 {
17688 ++input_line_pointer;
17689 SKIP_WHITESPACE ();
17690 }
17691
17692 expression (&exp);
17693 if (exp.X_op != O_symbol)
17694 {
17695 as_bad (_("bad .weakext directive"));
17696 ignore_rest_of_line ();
17697 return;
17698 }
17699 symbol_set_value_expression (symbolP, &exp);
17700 }
17701
17702 demand_empty_rest_of_line ();
17703 }
17704
17705 /* Parse a register string into a number. Called from the ECOFF code
17706 to parse .frame. The argument is non-zero if this is the frame
17707 register, so that we can record it in mips_frame_reg. */
17708
17709 int
tc_get_register(int frame)17710 tc_get_register (int frame)
17711 {
17712 unsigned int reg;
17713
17714 SKIP_WHITESPACE ();
17715 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®))
17716 reg = 0;
17717 if (frame)
17718 {
17719 mips_frame_reg = reg != 0 ? reg : SP;
17720 mips_frame_reg_valid = 1;
17721 mips_cprestore_valid = 0;
17722 }
17723 return reg;
17724 }
17725
17726 valueT
md_section_align(asection * seg,valueT addr)17727 md_section_align (asection *seg, valueT addr)
17728 {
17729 int align = bfd_section_alignment (seg);
17730
17731 /* We don't need to align ELF sections to the full alignment.
17732 However, Irix 5 may prefer that we align them at least to a 16
17733 byte boundary. We don't bother to align the sections if we
17734 are targeted for an embedded system. */
17735 if (startswith (TARGET_OS, "elf"))
17736 return addr;
17737 if (align > 4)
17738 align = 4;
17739
17740 return ((addr + (1 << align) - 1) & -(1 << align));
17741 }
17742
17743 /* Utility routine, called from above as well. If called while the
17744 input file is still being read, it's only an approximation. (For
17745 example, a symbol may later become defined which appeared to be
17746 undefined earlier.) */
17747
17748 static int
nopic_need_relax(symbolS * sym,int before_relaxing)17749 nopic_need_relax (symbolS *sym, int before_relaxing)
17750 {
17751 if (sym == 0)
17752 return 0;
17753
17754 if (g_switch_value > 0)
17755 {
17756 const char *symname;
17757 int change;
17758
17759 /* Find out whether this symbol can be referenced off the $gp
17760 register. It can be if it is smaller than the -G size or if
17761 it is in the .sdata or .sbss section. Certain symbols can
17762 not be referenced off the $gp, although it appears as though
17763 they can. */
17764 symname = S_GET_NAME (sym);
17765 if (symname != (const char *) NULL
17766 && (strcmp (symname, "eprol") == 0
17767 || strcmp (symname, "etext") == 0
17768 || strcmp (symname, "_gp") == 0
17769 || strcmp (symname, "edata") == 0
17770 || strcmp (symname, "_fbss") == 0
17771 || strcmp (symname, "_fdata") == 0
17772 || strcmp (symname, "_ftext") == 0
17773 || strcmp (symname, "end") == 0
17774 || strcmp (symname, "_gp_disp") == 0))
17775 change = 1;
17776 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
17777 && (0
17778 #ifndef NO_ECOFF_DEBUGGING
17779 || (symbol_get_obj (sym)->ecoff_extern_size != 0
17780 && (symbol_get_obj (sym)->ecoff_extern_size
17781 <= g_switch_value))
17782 #endif
17783 /* We must defer this decision until after the whole
17784 file has been read, since there might be a .extern
17785 after the first use of this symbol. */
17786 || (before_relaxing
17787 #ifndef NO_ECOFF_DEBUGGING
17788 && symbol_get_obj (sym)->ecoff_extern_size == 0
17789 #endif
17790 && S_GET_VALUE (sym) == 0)
17791 || (S_GET_VALUE (sym) != 0
17792 && S_GET_VALUE (sym) <= g_switch_value)))
17793 change = 0;
17794 else
17795 {
17796 const char *segname;
17797
17798 segname = segment_name (S_GET_SEGMENT (sym));
17799 gas_assert (strcmp (segname, ".lit8") != 0
17800 && strcmp (segname, ".lit4") != 0);
17801 change = (strcmp (segname, ".sdata") != 0
17802 && strcmp (segname, ".sbss") != 0
17803 && !startswith (segname, ".sdata.")
17804 && !startswith (segname, ".sbss.")
17805 && !startswith (segname, ".gnu.linkonce.sb.")
17806 && !startswith (segname, ".gnu.linkonce.s."));
17807 }
17808 return change;
17809 }
17810 else
17811 /* We are not optimizing for the $gp register. */
17812 return 1;
17813 }
17814
17815
17816 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17817
17818 static bool
pic_need_relax(symbolS * sym)17819 pic_need_relax (symbolS *sym)
17820 {
17821 asection *symsec;
17822
17823 if (!sym)
17824 return false;
17825
17826 /* Handle the case of a symbol equated to another symbol. */
17827 while (symbol_equated_reloc_p (sym))
17828 {
17829 symbolS *n;
17830
17831 /* It's possible to get a loop here in a badly written program. */
17832 n = symbol_get_value_expression (sym)->X_add_symbol;
17833 if (n == sym)
17834 break;
17835 sym = n;
17836 }
17837
17838 if (symbol_section_p (sym))
17839 return true;
17840
17841 symsec = S_GET_SEGMENT (sym);
17842
17843 /* This must duplicate the test in adjust_reloc_syms. */
17844 return (!bfd_is_und_section (symsec)
17845 && !bfd_is_abs_section (symsec)
17846 && !bfd_is_com_section (symsec)
17847 /* A global or weak symbol is treated as external. */
17848 && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym)));
17849 }
17850
17851 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17852 convert a section-relative value VAL to the equivalent PC-relative
17853 value. */
17854
17855 static offsetT
mips16_pcrel_val(fragS * fragp,const struct mips_pcrel_operand * pcrel_op,offsetT val,long stretch)17856 mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op,
17857 offsetT val, long stretch)
17858 {
17859 fragS *sym_frag;
17860 addressT addr;
17861
17862 gas_assert (pcrel_op->root.root.type == OP_PCREL);
17863
17864 sym_frag = symbol_get_frag (fragp->fr_symbol);
17865
17866 /* If the relax_marker of the symbol fragment differs from the
17867 relax_marker of this fragment, we have not yet adjusted the
17868 symbol fragment fr_address. We want to add in STRETCH in
17869 order to get a better estimate of the address. This
17870 particularly matters because of the shift bits. */
17871 if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker)
17872 {
17873 fragS *f;
17874
17875 /* Adjust stretch for any alignment frag. Note that if have
17876 been expanding the earlier code, the symbol may be
17877 defined in what appears to be an earlier frag. FIXME:
17878 This doesn't handle the fr_subtype field, which specifies
17879 a maximum number of bytes to skip when doing an
17880 alignment. */
17881 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
17882 {
17883 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
17884 {
17885 if (stretch < 0)
17886 stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1));
17887 else
17888 stretch &= ~((1 << (int) f->fr_offset) - 1);
17889 if (stretch == 0)
17890 break;
17891 }
17892 }
17893 if (f != NULL)
17894 val += stretch;
17895 }
17896
17897 addr = fragp->fr_address + fragp->fr_fix;
17898
17899 /* The base address rules are complicated. The base address of
17900 a branch is the following instruction. The base address of a
17901 PC relative load or add is the instruction itself, but if it
17902 is in a delay slot (in which case it can not be extended) use
17903 the address of the instruction whose delay slot it is in. */
17904 if (pcrel_op->include_isa_bit)
17905 {
17906 addr += 2;
17907
17908 /* If we are currently assuming that this frag should be
17909 extended, then the current address is two bytes higher. */
17910 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17911 addr += 2;
17912
17913 /* Ignore the low bit in the target, since it will be set
17914 for a text label. */
17915 val &= -2;
17916 }
17917 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
17918 addr -= 4;
17919 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
17920 addr -= 2;
17921
17922 val -= addr & -(1 << pcrel_op->align_log2);
17923
17924 return val;
17925 }
17926
17927 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17928 extended opcode. SEC is the section the frag is in. */
17929
17930 static int
mips16_extended_frag(fragS * fragp,asection * sec,long stretch)17931 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
17932 {
17933 const struct mips_int_operand *operand;
17934 offsetT val;
17935 segT symsec;
17936 int type;
17937
17938 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
17939 return 0;
17940 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
17941 return 1;
17942
17943 symsec = S_GET_SEGMENT (fragp->fr_symbol);
17944 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
17945 operand = mips16_immed_operand (type, false);
17946 if (S_FORCE_RELOC (fragp->fr_symbol, true)
17947 || (operand->root.type == OP_PCREL
17948 ? sec != symsec
17949 : !bfd_is_abs_section (symsec)))
17950 return 1;
17951
17952 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
17953
17954 if (operand->root.type == OP_PCREL)
17955 {
17956 const struct mips_pcrel_operand *pcrel_op;
17957 offsetT maxtiny;
17958
17959 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype))
17960 return 1;
17961
17962 pcrel_op = (const struct mips_pcrel_operand *) operand;
17963 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
17964
17965 /* If any of the shifted bits are set, we must use an extended
17966 opcode. If the address depends on the size of this
17967 instruction, this can lead to a loop, so we arrange to always
17968 use an extended opcode. */
17969 if ((val & ((1 << operand->shift) - 1)) != 0)
17970 {
17971 fragp->fr_subtype =
17972 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17973 return 1;
17974 }
17975
17976 /* If we are about to mark a frag as extended because the value
17977 is precisely the next value above maxtiny, then there is a
17978 chance of an infinite loop as in the following code:
17979 la $4,foo
17980 .skip 1020
17981 .align 2
17982 foo:
17983 In this case when the la is extended, foo is 0x3fc bytes
17984 away, so the la can be shrunk, but then foo is 0x400 away, so
17985 the la must be extended. To avoid this loop, we mark the
17986 frag as extended if it was small, and is about to become
17987 extended with the next value above maxtiny. */
17988 maxtiny = mips_int_operand_max (operand);
17989 if (val == maxtiny + (1 << operand->shift)
17990 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
17991 {
17992 fragp->fr_subtype =
17993 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype);
17994 return 1;
17995 }
17996 }
17997
17998 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
17999 }
18000
18001 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
18002 macro expansion. SEC is the section the frag is in. We only
18003 support PC-relative instructions (LA, DLA, LW, LD) here, in
18004 non-PIC code using 32-bit addressing. */
18005
18006 static int
mips16_macro_frag(fragS * fragp,asection * sec,long stretch)18007 mips16_macro_frag (fragS *fragp, asection *sec, long stretch)
18008 {
18009 const struct mips_pcrel_operand *pcrel_op;
18010 const struct mips_int_operand *operand;
18011 offsetT val;
18012 segT symsec;
18013 int type;
18014
18015 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype));
18016
18017 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
18018 return 0;
18019 if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype))
18020 return 0;
18021
18022 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
18023 switch (type)
18024 {
18025 case 'A':
18026 case 'B':
18027 case 'E':
18028 symsec = S_GET_SEGMENT (fragp->fr_symbol);
18029 if (bfd_is_abs_section (symsec))
18030 return 1;
18031 if (RELAX_MIPS16_PIC (fragp->fr_subtype))
18032 return 0;
18033 if (S_FORCE_RELOC (fragp->fr_symbol, true) || sec != symsec)
18034 return 1;
18035
18036 operand = mips16_immed_operand (type, true);
18037 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
18038 pcrel_op = (const struct mips_pcrel_operand *) operand;
18039 val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
18040
18041 return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
18042
18043 default:
18044 return 0;
18045 }
18046 }
18047
18048 /* Compute the length of a branch sequence, and adjust the
18049 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
18050 worst-case length is computed, with UPDATE being used to indicate
18051 whether an unconditional (-1), branch-likely (+1) or regular (0)
18052 branch is to be computed. */
18053 static int
relaxed_branch_length(fragS * fragp,asection * sec,int update)18054 relaxed_branch_length (fragS *fragp, asection *sec, int update)
18055 {
18056 bool toofar;
18057 int length;
18058
18059 if (fragp
18060 && S_IS_DEFINED (fragp->fr_symbol)
18061 && !S_IS_WEAK (fragp->fr_symbol)
18062 && sec == S_GET_SEGMENT (fragp->fr_symbol))
18063 {
18064 addressT addr;
18065 offsetT val;
18066
18067 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
18068
18069 addr = fragp->fr_address + fragp->fr_fix + 4;
18070
18071 val -= addr;
18072
18073 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
18074 }
18075 else
18076 /* If the symbol is not defined or it's in a different segment,
18077 we emit the long sequence. */
18078 toofar = true;
18079
18080 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18081 fragp->fr_subtype
18082 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
18083 RELAX_BRANCH_PIC (fragp->fr_subtype),
18084 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
18085 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
18086 RELAX_BRANCH_LINK (fragp->fr_subtype),
18087 toofar);
18088
18089 length = 4;
18090 if (toofar)
18091 {
18092 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
18093 length += 8;
18094
18095 if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype))
18096 {
18097 /* Additional space for PIC loading of target address. */
18098 length += 8;
18099 if (mips_opts.isa == ISA_MIPS1)
18100 /* Additional space for $at-stabilizing nop. */
18101 length += 4;
18102 }
18103
18104 /* If branch is conditional. */
18105 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
18106 length += 8;
18107 }
18108
18109 return length;
18110 }
18111
18112 /* Get a FRAG's branch instruction delay slot size, either from the
18113 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
18114 or SHORT_INSN_SIZE otherwise. */
18115
18116 static int
frag_branch_delay_slot_size(fragS * fragp,bool al,int short_insn_size)18117 frag_branch_delay_slot_size (fragS *fragp, bool al, int short_insn_size)
18118 {
18119 char *buf = fragp->fr_literal + fragp->fr_fix;
18120
18121 if (al)
18122 return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4;
18123 else
18124 return short_insn_size;
18125 }
18126
18127 /* Compute the length of a branch sequence, and adjust the
18128 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18129 worst-case length is computed, with UPDATE being used to indicate
18130 whether an unconditional (-1), or regular (0) branch is to be
18131 computed. */
18132
18133 static int
relaxed_micromips_32bit_branch_length(fragS * fragp,asection * sec,int update)18134 relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
18135 {
18136 bool insn32 = true;
18137 bool nods = true;
18138 bool pic = true;
18139 bool al = true;
18140 int short_insn_size;
18141 bool toofar;
18142 int length;
18143
18144 if (fragp)
18145 {
18146 insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18147 nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18148 pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
18149 al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18150 }
18151 short_insn_size = insn32 ? 4 : 2;
18152
18153 if (fragp
18154 && S_IS_DEFINED (fragp->fr_symbol)
18155 && !S_IS_WEAK (fragp->fr_symbol)
18156 && sec == S_GET_SEGMENT (fragp->fr_symbol))
18157 {
18158 addressT addr;
18159 offsetT val;
18160
18161 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
18162 /* Ignore the low bit in the target, since it will be set
18163 for a text label. */
18164 if ((val & 1) != 0)
18165 --val;
18166
18167 addr = fragp->fr_address + fragp->fr_fix + 4;
18168
18169 val -= addr;
18170
18171 toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
18172 }
18173 else
18174 /* If the symbol is not defined or it's in a different segment,
18175 we emit the long sequence. */
18176 toofar = true;
18177
18178 if (fragp && update
18179 && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18180 fragp->fr_subtype = (toofar
18181 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype)
18182 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype));
18183
18184 length = 4;
18185 if (toofar)
18186 {
18187 bool compact_known = fragp != NULL;
18188 bool compact = false;
18189 bool uncond;
18190
18191 if (fragp)
18192 {
18193 compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18194 uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype);
18195 }
18196 else
18197 uncond = update < 0;
18198
18199 /* If label is out of range, we turn branch <br>:
18200
18201 <br> label # 4 bytes
18202 0:
18203
18204 into:
18205
18206 j label # 4 bytes
18207 nop # 2/4 bytes if
18208 # compact && (!PIC || insn32)
18209 0:
18210 */
18211 if ((!pic || insn32) && (!compact_known || compact))
18212 length += short_insn_size;
18213
18214 /* If assembling PIC code, we further turn:
18215
18216 j label # 4 bytes
18217
18218 into:
18219
18220 lw/ld at, %got(label)(gp) # 4 bytes
18221 d/addiu at, %lo(label) # 4 bytes
18222 jr/c at # 2/4 bytes
18223 */
18224 if (pic)
18225 length += 4 + short_insn_size;
18226
18227 /* Add an extra nop if the jump has no compact form and we need
18228 to fill the delay slot. */
18229 if ((!pic || al) && nods)
18230 length += (fragp
18231 ? frag_branch_delay_slot_size (fragp, al, short_insn_size)
18232 : short_insn_size);
18233
18234 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18235
18236 <brneg> 0f # 4 bytes
18237 nop # 2/4 bytes if !compact
18238 */
18239 if (!uncond)
18240 length += (compact_known && compact) ? 4 : 4 + short_insn_size;
18241 }
18242 else if (nods)
18243 {
18244 /* Add an extra nop to fill the delay slot. */
18245 gas_assert (fragp);
18246 length += frag_branch_delay_slot_size (fragp, al, short_insn_size);
18247 }
18248
18249 return length;
18250 }
18251
18252 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18253 bit accordingly. */
18254
18255 static int
relaxed_micromips_16bit_branch_length(fragS * fragp,asection * sec,int update)18256 relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
18257 {
18258 bool toofar;
18259
18260 if (fragp
18261 && S_IS_DEFINED (fragp->fr_symbol)
18262 && !S_IS_WEAK (fragp->fr_symbol)
18263 && sec == S_GET_SEGMENT (fragp->fr_symbol))
18264 {
18265 addressT addr;
18266 offsetT val;
18267 int type;
18268
18269 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
18270 /* Ignore the low bit in the target, since it will be set
18271 for a text label. */
18272 if ((val & 1) != 0)
18273 --val;
18274
18275 /* Assume this is a 2-byte branch. */
18276 addr = fragp->fr_address + fragp->fr_fix + 2;
18277
18278 /* We try to avoid the infinite loop by not adding 2 more bytes for
18279 long branches. */
18280
18281 val -= addr;
18282
18283 type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18284 if (type == 'D')
18285 toofar = val < - (0x200 << 1) || val >= (0x200 << 1);
18286 else if (type == 'E')
18287 toofar = val < - (0x40 << 1) || val >= (0x40 << 1);
18288 else
18289 abort ();
18290 }
18291 else
18292 /* If the symbol is not defined or it's in a different segment,
18293 we emit a normal 32-bit branch. */
18294 toofar = true;
18295
18296 if (fragp && update
18297 && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18298 fragp->fr_subtype
18299 = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype)
18300 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype);
18301
18302 if (toofar)
18303 return 4;
18304
18305 return 2;
18306 }
18307
18308 /* Estimate the size of a frag before relaxing. Unless this is the
18309 mips16, we are not really relaxing here, and the final size is
18310 encoded in the subtype information. For the mips16, we have to
18311 decide whether we are using an extended opcode or not. */
18312
18313 int
md_estimate_size_before_relax(fragS * fragp,asection * segtype)18314 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
18315 {
18316 int change;
18317
18318 if (RELAX_BRANCH_P (fragp->fr_subtype))
18319 {
18320
18321 fragp->fr_var = relaxed_branch_length (fragp, segtype, false);
18322
18323 return fragp->fr_var;
18324 }
18325
18326 if (RELAX_MIPS16_P (fragp->fr_subtype))
18327 {
18328 /* We don't want to modify the EXTENDED bit here; it might get us
18329 into infinite loops. We change it only in mips_relax_frag(). */
18330 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18331 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12;
18332 else
18333 return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2;
18334 }
18335
18336 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18337 {
18338 int length = 4;
18339
18340 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18341 length = relaxed_micromips_16bit_branch_length (fragp, segtype, false);
18342 if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18343 length = relaxed_micromips_32bit_branch_length (fragp, segtype, false);
18344 fragp->fr_var = length;
18345
18346 return length;
18347 }
18348
18349 if (mips_pic == VXWORKS_PIC)
18350 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18351 change = 0;
18352 else if (RELAX_PIC (fragp->fr_subtype))
18353 change = pic_need_relax (fragp->fr_symbol);
18354 else
18355 change = nopic_need_relax (fragp->fr_symbol, 0);
18356
18357 if (change)
18358 {
18359 fragp->fr_subtype |= RELAX_USE_SECOND;
18360 return -RELAX_FIRST (fragp->fr_subtype);
18361 }
18362 else
18363 return -RELAX_SECOND (fragp->fr_subtype);
18364 }
18365
18366 /* This is called to see whether a reloc against a defined symbol
18367 should be converted into a reloc against a section. */
18368
18369 int
mips_fix_adjustable(fixS * fixp)18370 mips_fix_adjustable (fixS *fixp)
18371 {
18372 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
18373 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18374 return 0;
18375
18376 if (fixp->fx_addsy == NULL)
18377 return 1;
18378
18379 /* Allow relocs used for EH tables. */
18380 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
18381 return 1;
18382
18383 /* If symbol SYM is in a mergeable section, relocations of the form
18384 SYM + 0 can usually be made section-relative. The mergeable data
18385 is then identified by the section offset rather than by the symbol.
18386
18387 However, if we're generating REL LO16 relocations, the offset is split
18388 between the LO16 and partnering high part relocation. The linker will
18389 need to recalculate the complete offset in order to correctly identify
18390 the merge data.
18391
18392 The linker has traditionally not looked for the partnering high part
18393 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18394 placed anywhere. Rather than break backwards compatibility by changing
18395 this, it seems better not to force the issue, and instead keep the
18396 original symbol. This will work with either linker behavior. */
18397 if ((lo16_reloc_p (fixp->fx_r_type)
18398 || reloc_needs_lo_p (fixp->fx_r_type))
18399 && HAVE_IN_PLACE_ADDENDS
18400 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
18401 return 0;
18402
18403 /* There is no place to store an in-place offset for JALR relocations. */
18404 if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS)
18405 return 0;
18406
18407 /* Likewise an in-range offset of limited PC-relative relocations may
18408 overflow the in-place relocatable field if recalculated against the
18409 start address of the symbol's containing section.
18410
18411 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18412 section relative to allow linker relaxations to be performed later on. */
18413 if (limited_pcrel_reloc_p (fixp->fx_r_type)
18414 && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa)))
18415 return 0;
18416
18417 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18418 to a floating-point stub. The same is true for non-R_MIPS16_26
18419 relocations against MIPS16 functions; in this case, the stub becomes
18420 the function's canonical address.
18421
18422 Floating-point stubs are stored in unique .mips16.call.* or
18423 .mips16.fn.* sections. If a stub T for function F is in section S,
18424 the first relocation in section S must be against F; this is how the
18425 linker determines the target function. All relocations that might
18426 resolve to T must also be against F. We therefore have the following
18427 restrictions, which are given in an intentionally-redundant way:
18428
18429 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18430 symbols.
18431
18432 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18433 if that stub might be used.
18434
18435 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18436 symbols.
18437
18438 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18439 that stub might be used.
18440
18441 There is a further restriction:
18442
18443 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18444 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18445 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18446 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18447 against MIPS16 or microMIPS symbols because we need to keep the
18448 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18449 detection and JAL or BAL to JALX instruction conversion in the
18450 linker.
18451
18452 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18453 against a MIPS16 symbol. We deal with (5) by additionally leaving
18454 alone any jump and branch relocations against a microMIPS symbol.
18455
18456 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18457 relocation against some symbol R, no relocation against R may be
18458 reduced. (Note that this deals with (2) as well as (1) because
18459 relocations against global symbols will never be reduced on ELF
18460 targets.) This approach is a little simpler than trying to detect
18461 stub sections, and gives the "all or nothing" per-symbol consistency
18462 that we have for MIPS16 symbols. */
18463 if (fixp->fx_subsy == NULL
18464 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
18465 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy))
18466 && (jmp_reloc_p (fixp->fx_r_type)
18467 || b_reloc_p (fixp->fx_r_type)))
18468 || *symbol_get_tc (fixp->fx_addsy)))
18469 return 0;
18470
18471 return 1;
18472 }
18473
18474 /* Translate internal representation of relocation info to BFD target
18475 format. */
18476
18477 arelent **
tc_gen_reloc(asection * section ATTRIBUTE_UNUSED,fixS * fixp)18478 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
18479 {
18480 static arelent *retval[4];
18481 arelent *reloc;
18482 bfd_reloc_code_real_type code;
18483
18484 memset (retval, 0, sizeof(retval));
18485 reloc = retval[0] = XCNEW (arelent);
18486 reloc->sym_ptr_ptr = XNEW (asymbol *);
18487 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
18488 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
18489
18490 if (fixp->fx_pcrel)
18491 {
18492 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
18493 || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1
18494 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
18495 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
18496 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
18497 || fixp->fx_r_type == BFD_RELOC_32_PCREL
18498 || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
18499 || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
18500 || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
18501 || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2
18502 || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL
18503 || fixp->fx_r_type == BFD_RELOC_LO16_PCREL);
18504
18505 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18506 Relocations want only the symbol offset. */
18507 switch (fixp->fx_r_type)
18508 {
18509 case BFD_RELOC_MIPS_18_PCREL_S3:
18510 reloc->addend = fixp->fx_addnumber + (reloc->address & ~7);
18511 break;
18512 default:
18513 reloc->addend = fixp->fx_addnumber + reloc->address;
18514 break;
18515 }
18516 }
18517 else if (HAVE_IN_PLACE_ADDENDS
18518 && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP
18519 && (read_compressed_insn (fixp->fx_frag->fr_literal
18520 + fixp->fx_where, 4) >> 26) == 0x3c)
18521 {
18522 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18523 addend accordingly. */
18524 reloc->addend = fixp->fx_addnumber >> 1;
18525 }
18526 else
18527 reloc->addend = fixp->fx_addnumber;
18528
18529 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18530 entry to be used in the relocation's section offset. */
18531 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
18532 {
18533 reloc->address = reloc->addend;
18534 reloc->addend = 0;
18535 }
18536
18537 code = fixp->fx_r_type;
18538
18539 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
18540 if (reloc->howto == NULL)
18541 {
18542 as_bad_where (fixp->fx_file, fixp->fx_line,
18543 _("cannot represent %s relocation in this object file"
18544 " format"),
18545 bfd_get_reloc_code_name (code));
18546 retval[0] = NULL;
18547 }
18548
18549 return retval;
18550 }
18551
18552 /* Relax a machine dependent frag. This returns the amount by which
18553 the current size of the frag should change. */
18554
18555 int
mips_relax_frag(asection * sec,fragS * fragp,long stretch)18556 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
18557 {
18558 if (RELAX_BRANCH_P (fragp->fr_subtype))
18559 {
18560 offsetT old_var = fragp->fr_var;
18561
18562 fragp->fr_var = relaxed_branch_length (fragp, sec, true);
18563
18564 return fragp->fr_var - old_var;
18565 }
18566
18567 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18568 {
18569 offsetT old_var = fragp->fr_var;
18570 offsetT new_var = 4;
18571
18572 if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0)
18573 new_var = relaxed_micromips_16bit_branch_length (fragp, sec, true);
18574 if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype))
18575 new_var = relaxed_micromips_32bit_branch_length (fragp, sec, true);
18576 fragp->fr_var = new_var;
18577
18578 return new_var - old_var;
18579 }
18580
18581 if (! RELAX_MIPS16_P (fragp->fr_subtype))
18582 return 0;
18583
18584 if (!mips16_extended_frag (fragp, sec, stretch))
18585 {
18586 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18587 {
18588 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18589 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10;
18590 }
18591 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18592 {
18593 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18594 return -2;
18595 }
18596 else
18597 return 0;
18598 }
18599 else if (!mips16_macro_frag (fragp, sec, stretch))
18600 {
18601 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18602 {
18603 fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
18604 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18605 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8;
18606 }
18607 else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18608 {
18609 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
18610 return 2;
18611 }
18612 else
18613 return 0;
18614 }
18615 else
18616 {
18617 if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
18618 return 0;
18619 else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
18620 {
18621 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
18622 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18623 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8;
18624 }
18625 else
18626 {
18627 fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
18628 return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10;
18629 }
18630 }
18631
18632 return 0;
18633 }
18634
18635 /* Convert a machine dependent frag. */
18636
18637 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT asec,fragS * fragp)18638 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
18639 {
18640 if (RELAX_BRANCH_P (fragp->fr_subtype))
18641 {
18642 char *buf;
18643 unsigned long insn;
18644 fixS *fixp;
18645
18646 buf = fragp->fr_literal + fragp->fr_fix;
18647 insn = read_insn (buf);
18648
18649 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
18650 {
18651 /* We generate a fixup instead of applying it right now
18652 because, if there are linker relaxations, we're going to
18653 need the relocations. */
18654 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18655 fragp->fr_symbol, fragp->fr_offset,
18656 true, BFD_RELOC_16_PCREL_S2);
18657 fixp->fx_file = fragp->fr_file;
18658 fixp->fx_line = fragp->fr_line;
18659
18660 buf = write_insn (buf, insn);
18661 }
18662 else
18663 {
18664 int i;
18665
18666 as_warn_where (fragp->fr_file, fragp->fr_line,
18667 _("relaxed out-of-range branch into a jump"));
18668
18669 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
18670 goto uncond;
18671
18672 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18673 {
18674 /* Reverse the branch. */
18675 switch ((insn >> 28) & 0xf)
18676 {
18677 case 4:
18678 if ((insn & 0xff000000) == 0x47000000
18679 || (insn & 0xff600000) == 0x45600000)
18680 {
18681 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18682 reversed by tweaking bit 23. */
18683 insn ^= 0x00800000;
18684 }
18685 else
18686 {
18687 /* bc[0-3][tf]l? instructions can have the condition
18688 reversed by tweaking a single TF bit, and their
18689 opcodes all have 0x4???????. */
18690 gas_assert ((insn & 0xf3e00000) == 0x41000000);
18691 insn ^= 0x00010000;
18692 }
18693 break;
18694
18695 case 0:
18696 /* bltz 0x04000000 bgez 0x04010000
18697 bltzal 0x04100000 bgezal 0x04110000 */
18698 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
18699 insn ^= 0x00010000;
18700 break;
18701
18702 case 1:
18703 /* beq 0x10000000 bne 0x14000000
18704 blez 0x18000000 bgtz 0x1c000000 */
18705 insn ^= 0x04000000;
18706 break;
18707
18708 default:
18709 abort ();
18710 }
18711 }
18712
18713 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18714 {
18715 /* Clear the and-link bit. */
18716 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
18717
18718 /* bltzal 0x04100000 bgezal 0x04110000
18719 bltzall 0x04120000 bgezall 0x04130000 */
18720 insn &= ~0x00100000;
18721 }
18722
18723 /* Branch over the branch (if the branch was likely) or the
18724 full jump (not likely case). Compute the offset from the
18725 current instruction to branch to. */
18726 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18727 i = 16;
18728 else
18729 {
18730 /* How many bytes in instructions we've already emitted? */
18731 i = buf - fragp->fr_literal - fragp->fr_fix;
18732 /* How many bytes in instructions from here to the end? */
18733 i = fragp->fr_var - i;
18734 }
18735 /* Convert to instruction count. */
18736 i >>= 2;
18737 /* Branch counts from the next instruction. */
18738 i--;
18739 insn |= i;
18740 /* Branch over the jump. */
18741 buf = write_insn (buf, insn);
18742
18743 /* nop */
18744 buf = write_insn (buf, 0);
18745
18746 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
18747 {
18748 /* beql $0, $0, 2f */
18749 insn = 0x50000000;
18750 /* Compute the PC offset from the current instruction to
18751 the end of the variable frag. */
18752 /* How many bytes in instructions we've already emitted? */
18753 i = buf - fragp->fr_literal - fragp->fr_fix;
18754 /* How many bytes in instructions from here to the end? */
18755 i = fragp->fr_var - i;
18756 /* Convert to instruction count. */
18757 i >>= 2;
18758 /* Don't decrement i, because we want to branch over the
18759 delay slot. */
18760 insn |= i;
18761
18762 buf = write_insn (buf, insn);
18763 buf = write_insn (buf, 0);
18764 }
18765
18766 uncond:
18767 if (!RELAX_BRANCH_PIC (fragp->fr_subtype))
18768 {
18769 /* j or jal. */
18770 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
18771 ? 0x0c000000 : 0x08000000);
18772
18773 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18774 fragp->fr_symbol, fragp->fr_offset,
18775 false, BFD_RELOC_MIPS_JMP);
18776 fixp->fx_file = fragp->fr_file;
18777 fixp->fx_line = fragp->fr_line;
18778
18779 buf = write_insn (buf, insn);
18780 }
18781 else
18782 {
18783 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
18784
18785 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18786 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
18787 insn |= at << OP_SH_RT;
18788
18789 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18790 fragp->fr_symbol, fragp->fr_offset,
18791 false, BFD_RELOC_MIPS_GOT16);
18792 fixp->fx_file = fragp->fr_file;
18793 fixp->fx_line = fragp->fr_line;
18794
18795 buf = write_insn (buf, insn);
18796
18797 if (mips_opts.isa == ISA_MIPS1)
18798 /* nop */
18799 buf = write_insn (buf, 0);
18800
18801 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18802 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
18803 insn |= at << OP_SH_RS | at << OP_SH_RT;
18804
18805 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18806 fragp->fr_symbol, fragp->fr_offset,
18807 false, BFD_RELOC_LO16);
18808 fixp->fx_file = fragp->fr_file;
18809 fixp->fx_line = fragp->fr_line;
18810
18811 buf = write_insn (buf, insn);
18812
18813 /* j(al)r $at. */
18814 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
18815 insn = 0x0000f809;
18816 else
18817 insn = 0x00000008;
18818 insn |= at << OP_SH_RS;
18819
18820 buf = write_insn (buf, insn);
18821 }
18822 }
18823
18824 fragp->fr_fix += fragp->fr_var;
18825 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18826 return;
18827 }
18828
18829 /* Relax microMIPS branches. */
18830 if (RELAX_MICROMIPS_P (fragp->fr_subtype))
18831 {
18832 char *buf = fragp->fr_literal + fragp->fr_fix;
18833 bool compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype);
18834 bool insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype);
18835 bool nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype);
18836 bool pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype);
18837 bool al = RELAX_MICROMIPS_LINK (fragp->fr_subtype);
18838 int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype);
18839 bool short_ds;
18840 unsigned long insn;
18841 fixS *fixp;
18842
18843 fragp->fr_fix += fragp->fr_var;
18844
18845 /* Handle 16-bit branches that fit or are forced to fit. */
18846 if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype))
18847 {
18848 /* We generate a fixup instead of applying it right now,
18849 because if there is linker relaxation, we're going to
18850 need the relocations. */
18851 switch (type)
18852 {
18853 case 'D':
18854 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18855 fragp->fr_symbol, fragp->fr_offset,
18856 true, BFD_RELOC_MICROMIPS_10_PCREL_S1);
18857 break;
18858 case 'E':
18859 fixp = fix_new (fragp, buf - fragp->fr_literal, 2,
18860 fragp->fr_symbol, fragp->fr_offset,
18861 true, BFD_RELOC_MICROMIPS_7_PCREL_S1);
18862 break;
18863 default:
18864 abort ();
18865 }
18866
18867 fixp->fx_file = fragp->fr_file;
18868 fixp->fx_line = fragp->fr_line;
18869
18870 /* These relocations can have an addend that won't fit in
18871 2 octets. */
18872 fixp->fx_no_overflow = 1;
18873
18874 return;
18875 }
18876
18877 /* Handle 32-bit branches that fit or are forced to fit. */
18878 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18879 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18880 {
18881 /* We generate a fixup instead of applying it right now,
18882 because if there is linker relaxation, we're going to
18883 need the relocations. */
18884 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
18885 fragp->fr_symbol, fragp->fr_offset,
18886 true, BFD_RELOC_MICROMIPS_16_PCREL_S1);
18887 fixp->fx_file = fragp->fr_file;
18888 fixp->fx_line = fragp->fr_line;
18889
18890 if (type == 0)
18891 {
18892 insn = read_compressed_insn (buf, 4);
18893 buf += 4;
18894
18895 if (nods)
18896 {
18897 /* Check the short-delay-slot bit. */
18898 if (!al || (insn & 0x02000000) != 0)
18899 buf = write_compressed_insn (buf, 0x0c00, 2);
18900 else
18901 buf = write_compressed_insn (buf, 0x00000000, 4);
18902 }
18903
18904 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18905 return;
18906 }
18907 }
18908
18909 /* Relax 16-bit branches to 32-bit branches. */
18910 if (type != 0)
18911 {
18912 insn = read_compressed_insn (buf, 2);
18913
18914 if ((insn & 0xfc00) == 0xcc00) /* b16 */
18915 insn = 0x94000000; /* beq */
18916 else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18917 {
18918 unsigned long regno;
18919
18920 regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
18921 regno = micromips_to_32_reg_d_map [regno];
18922 insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
18923 insn |= regno << MICROMIPSOP_SH_RS;
18924 }
18925 else
18926 abort ();
18927
18928 /* Nothing else to do, just write it out. */
18929 if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)
18930 || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype))
18931 {
18932 buf = write_compressed_insn (buf, insn, 4);
18933 if (nods)
18934 buf = write_compressed_insn (buf, 0x0c00, 2);
18935 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
18936 return;
18937 }
18938 }
18939 else
18940 insn = read_compressed_insn (buf, 4);
18941
18942 /* Relax 32-bit branches to a sequence of instructions. */
18943 as_warn_where (fragp->fr_file, fragp->fr_line,
18944 _("relaxed out-of-range branch into a jump"));
18945
18946 /* Set the short-delay-slot bit. */
18947 short_ds = !al || (insn & 0x02000000) != 0;
18948
18949 if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype))
18950 {
18951 symbolS *l;
18952
18953 /* Reverse the branch. */
18954 if ((insn & 0xfc000000) == 0x94000000 /* beq */
18955 || (insn & 0xfc000000) == 0xb4000000) /* bne */
18956 insn ^= 0x20000000;
18957 else if ((insn & 0xffe00000) == 0x40000000 /* bltz */
18958 || (insn & 0xffe00000) == 0x40400000 /* bgez */
18959 || (insn & 0xffe00000) == 0x40800000 /* blez */
18960 || (insn & 0xffe00000) == 0x40c00000 /* bgtz */
18961 || (insn & 0xffe00000) == 0x40a00000 /* bnezc */
18962 || (insn & 0xffe00000) == 0x40e00000 /* beqzc */
18963 || (insn & 0xffe00000) == 0x40200000 /* bltzal */
18964 || (insn & 0xffe00000) == 0x40600000 /* bgezal */
18965 || (insn & 0xffe00000) == 0x42200000 /* bltzals */
18966 || (insn & 0xffe00000) == 0x42600000) /* bgezals */
18967 insn ^= 0x00400000;
18968 else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */
18969 || (insn & 0xffe30000) == 0x43a00000 /* bc1t */
18970 || (insn & 0xffe30000) == 0x42800000 /* bc2f */
18971 || (insn & 0xffe30000) == 0x42a00000) /* bc2t */
18972 insn ^= 0x00200000;
18973 else if ((insn & 0xff000000) == 0x83000000 /* BZ.df
18974 BNZ.df */
18975 || (insn & 0xff600000) == 0x81600000) /* BZ.V
18976 BNZ.V */
18977 insn ^= 0x00800000;
18978 else
18979 abort ();
18980
18981 if (al)
18982 {
18983 /* Clear the and-link and short-delay-slot bits. */
18984 gas_assert ((insn & 0xfda00000) == 0x40200000);
18985
18986 /* bltzal 0x40200000 bgezal 0x40600000 */
18987 /* bltzals 0x42200000 bgezals 0x42600000 */
18988 insn &= ~0x02200000;
18989 }
18990
18991 /* Make a label at the end for use with the branch. */
18992 l = symbol_new (micromips_label_name (), asec, fragp, fragp->fr_fix);
18993 micromips_label_inc ();
18994 S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l)));
18995
18996 /* Refer to it. */
18997 fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, true,
18998 BFD_RELOC_MICROMIPS_16_PCREL_S1);
18999 fixp->fx_file = fragp->fr_file;
19000 fixp->fx_line = fragp->fr_line;
19001
19002 /* Branch over the jump. */
19003 buf = write_compressed_insn (buf, insn, 4);
19004
19005 if (!compact)
19006 {
19007 /* nop */
19008 if (insn32)
19009 buf = write_compressed_insn (buf, 0x00000000, 4);
19010 else
19011 buf = write_compressed_insn (buf, 0x0c00, 2);
19012 }
19013 }
19014
19015 if (!pic)
19016 {
19017 unsigned long jal = (short_ds || nods
19018 ? 0x74000000 : 0xf4000000); /* jal/s */
19019
19020 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
19021 insn = al ? jal : 0xd4000000;
19022
19023 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
19024 fragp->fr_symbol, fragp->fr_offset,
19025 false, BFD_RELOC_MICROMIPS_JMP);
19026 fixp->fx_file = fragp->fr_file;
19027 fixp->fx_line = fragp->fr_line;
19028
19029 buf = write_compressed_insn (buf, insn, 4);
19030
19031 if (compact || nods)
19032 {
19033 /* nop */
19034 if (insn32)
19035 buf = write_compressed_insn (buf, 0x00000000, 4);
19036 else
19037 buf = write_compressed_insn (buf, 0x0c00, 2);
19038 }
19039 }
19040 else
19041 {
19042 unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype);
19043
19044 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
19045 insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000;
19046 insn |= at << MICROMIPSOP_SH_RT;
19047
19048 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
19049 fragp->fr_symbol, fragp->fr_offset,
19050 false, BFD_RELOC_MICROMIPS_GOT16);
19051 fixp->fx_file = fragp->fr_file;
19052 fixp->fx_line = fragp->fr_line;
19053
19054 buf = write_compressed_insn (buf, insn, 4);
19055
19056 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
19057 insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000;
19058 insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS;
19059
19060 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
19061 fragp->fr_symbol, fragp->fr_offset,
19062 false, BFD_RELOC_MICROMIPS_LO16);
19063 fixp->fx_file = fragp->fr_file;
19064 fixp->fx_line = fragp->fr_line;
19065
19066 buf = write_compressed_insn (buf, insn, 4);
19067
19068 if (insn32)
19069 {
19070 /* jr/jalr $at */
19071 insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT;
19072 insn |= at << MICROMIPSOP_SH_RS;
19073
19074 buf = write_compressed_insn (buf, insn, 4);
19075
19076 if (compact || nods)
19077 /* nop */
19078 buf = write_compressed_insn (buf, 0x00000000, 4);
19079 }
19080 else
19081 {
19082 /* jr/jrc/jalr/jalrs $at */
19083 unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */
19084 unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */
19085
19086 insn = al ? jalr : jr;
19087 insn |= at << MICROMIPSOP_SH_MJ;
19088
19089 buf = write_compressed_insn (buf, insn, 2);
19090 if (al && nods)
19091 {
19092 /* nop */
19093 if (short_ds)
19094 buf = write_compressed_insn (buf, 0x0c00, 2);
19095 else
19096 buf = write_compressed_insn (buf, 0x00000000, 4);
19097 }
19098 }
19099 }
19100
19101 gas_assert (buf == fragp->fr_literal + fragp->fr_fix);
19102 return;
19103 }
19104
19105 if (RELAX_MIPS16_P (fragp->fr_subtype))
19106 {
19107 int type;
19108 const struct mips_int_operand *operand;
19109 offsetT val;
19110 char *buf;
19111 unsigned int user_length;
19112 bool need_reloc;
19113 unsigned long insn;
19114 bool mac;
19115 bool ext;
19116 segT symsec;
19117
19118 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
19119 operand = mips16_immed_operand (type, false);
19120
19121 mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
19122 ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
19123 val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
19124
19125 symsec = S_GET_SEGMENT (fragp->fr_symbol);
19126 need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, true)
19127 || (operand->root.type == OP_PCREL && !mac
19128 ? asec != symsec
19129 : !bfd_is_abs_section (symsec)));
19130
19131 if (operand->root.type == OP_PCREL && !mac)
19132 {
19133 const struct mips_pcrel_operand *pcrel_op;
19134
19135 pcrel_op = (const struct mips_pcrel_operand *) operand;
19136
19137 if (pcrel_op->include_isa_bit && !need_reloc)
19138 {
19139 if (!mips_ignore_branch_isa
19140 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol)))
19141 as_bad_where (fragp->fr_file, fragp->fr_line,
19142 _("branch to a symbol in another ISA mode"));
19143 else if ((fragp->fr_offset & 0x1) != 0)
19144 as_bad_where (fragp->fr_file, fragp->fr_line,
19145 _("branch to misaligned address (0x%lx)"),
19146 (long) (resolve_symbol_value (fragp->fr_symbol)
19147 + (fragp->fr_offset & ~1)));
19148 }
19149
19150 val = mips16_pcrel_val (fragp, pcrel_op, val, 0);
19151
19152 /* Make sure the section winds up with the alignment we have
19153 assumed. */
19154 if (operand->shift > 0)
19155 record_alignment (asec, operand->shift);
19156 }
19157
19158 if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
19159 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))
19160 {
19161 if (mac)
19162 as_warn_where (fragp->fr_file, fragp->fr_line,
19163 _("macro instruction expanded into multiple "
19164 "instructions in a branch delay slot"));
19165 else if (ext)
19166 as_warn_where (fragp->fr_file, fragp->fr_line,
19167 _("extended instruction in a branch delay slot"));
19168 }
19169 else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac)
19170 as_warn_where (fragp->fr_file, fragp->fr_line,
19171 _("macro instruction expanded into multiple "
19172 "instructions"));
19173
19174 buf = fragp->fr_literal + fragp->fr_fix;
19175
19176 insn = read_compressed_insn (buf, 2);
19177 if (ext)
19178 insn |= MIPS16_EXTEND;
19179
19180 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
19181 user_length = 4;
19182 else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
19183 user_length = 2;
19184 else
19185 user_length = 0;
19186
19187 if (mac)
19188 {
19189 unsigned long reg;
19190 unsigned long new;
19191 unsigned long op;
19192 bool e2;
19193
19194 gas_assert (type == 'A' || type == 'B' || type == 'E');
19195 gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
19196
19197 e2 = RELAX_MIPS16_E2 (fragp->fr_subtype);
19198
19199 if (need_reloc)
19200 {
19201 fixS *fixp;
19202
19203 gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype));
19204
19205 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
19206 fragp->fr_symbol, fragp->fr_offset,
19207 false, BFD_RELOC_MIPS16_HI16_S);
19208 fixp->fx_file = fragp->fr_file;
19209 fixp->fx_line = fragp->fr_line;
19210
19211 fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4,
19212 fragp->fr_symbol, fragp->fr_offset,
19213 false, BFD_RELOC_MIPS16_LO16);
19214 fixp->fx_file = fragp->fr_file;
19215 fixp->fx_line = fragp->fr_line;
19216
19217 val = 0;
19218 }
19219
19220 switch (insn & 0xf800)
19221 {
19222 case 0x0800: /* ADDIU */
19223 reg = (insn >> 8) & 0x7;
19224 op = 0xf0004800 | (reg << 8);
19225 break;
19226 case 0xb000: /* LW */
19227 reg = (insn >> 8) & 0x7;
19228 op = 0xf0009800 | (reg << 8) | (reg << 5);
19229 break;
19230 case 0xf800: /* I64 */
19231 reg = (insn >> 5) & 0x7;
19232 switch (insn & 0x0700)
19233 {
19234 case 0x0400: /* LD */
19235 op = 0xf0003800 | (reg << 8) | (reg << 5);
19236 break;
19237 case 0x0600: /* DADDIU */
19238 op = 0xf000fd00 | (reg << 5);
19239 break;
19240 default:
19241 abort ();
19242 }
19243 break;
19244 default:
19245 abort ();
19246 }
19247
19248 new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */
19249 new |= mips16_immed_extend ((val + 0x8000) >> 16, 16);
19250 buf = write_compressed_insn (buf, new, 4);
19251 if (!e2)
19252 {
19253 new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */
19254 buf = write_compressed_insn (buf, new, 4);
19255 }
19256 op |= mips16_immed_extend (val, 16);
19257 buf = write_compressed_insn (buf, op, 4);
19258
19259 fragp->fr_fix += e2 ? 8 : 12;
19260 }
19261 else
19262 {
19263 unsigned int length = ext ? 4 : 2;
19264
19265 if (need_reloc)
19266 {
19267 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
19268 fixS *fixp;
19269
19270 switch (type)
19271 {
19272 case 'p':
19273 case 'q':
19274 reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
19275 break;
19276 default:
19277 break;
19278 }
19279 if (mac || reloc == BFD_RELOC_NONE)
19280 as_bad_where (fragp->fr_file, fragp->fr_line,
19281 _("unsupported relocation"));
19282 else if (ext)
19283 {
19284 fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
19285 fragp->fr_symbol, fragp->fr_offset,
19286 true, reloc);
19287 fixp->fx_file = fragp->fr_file;
19288 fixp->fx_line = fragp->fr_line;
19289 }
19290 else
19291 as_bad_where (fragp->fr_file, fragp->fr_line,
19292 _("invalid unextended operand value"));
19293 }
19294 else
19295 mips16_immed (fragp->fr_file, fragp->fr_line, type,
19296 BFD_RELOC_UNUSED, val, user_length, &insn);
19297
19298 gas_assert (mips16_opcode_length (insn) == length);
19299 write_compressed_insn (buf, insn, length);
19300 fragp->fr_fix += length;
19301 }
19302 }
19303 else
19304 {
19305 relax_substateT subtype = fragp->fr_subtype;
19306 bool second_longer = (subtype & RELAX_SECOND_LONGER) != 0;
19307 bool use_second = (subtype & RELAX_USE_SECOND) != 0;
19308 unsigned int first, second;
19309 fixS *fixp;
19310
19311 first = RELAX_FIRST (subtype);
19312 second = RELAX_SECOND (subtype);
19313 fixp = (fixS *) fragp->fr_opcode;
19314
19315 /* If the delay slot chosen does not match the size of the instruction,
19316 then emit a warning. */
19317 if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0)
19318 || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0))
19319 {
19320 relax_substateT s;
19321 const char *msg;
19322
19323 s = subtype & (RELAX_DELAY_SLOT_16BIT
19324 | RELAX_DELAY_SLOT_SIZE_FIRST
19325 | RELAX_DELAY_SLOT_SIZE_SECOND);
19326 msg = macro_warning (s);
19327 if (msg != NULL)
19328 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
19329 subtype &= ~s;
19330 }
19331
19332 /* Possibly emit a warning if we've chosen the longer option. */
19333 if (use_second == second_longer)
19334 {
19335 relax_substateT s;
19336 const char *msg;
19337
19338 s = (subtype
19339 & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT));
19340 msg = macro_warning (s);
19341 if (msg != NULL)
19342 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
19343 subtype &= ~s;
19344 }
19345
19346 /* Go through all the fixups for the first sequence. Disable them
19347 (by marking them as done) if we're going to use the second
19348 sequence instead. */
19349 while (fixp
19350 && fixp->fx_frag == fragp
19351 && fixp->fx_where + second < fragp->fr_fix)
19352 {
19353 if (subtype & RELAX_USE_SECOND)
19354 fixp->fx_done = 1;
19355 fixp = fixp->fx_next;
19356 }
19357
19358 /* Go through the fixups for the second sequence. Disable them if
19359 we're going to use the first sequence, otherwise adjust their
19360 addresses to account for the relaxation. */
19361 while (fixp && fixp->fx_frag == fragp)
19362 {
19363 if (subtype & RELAX_USE_SECOND)
19364 fixp->fx_where -= first;
19365 else
19366 fixp->fx_done = 1;
19367 fixp = fixp->fx_next;
19368 }
19369
19370 /* Now modify the frag contents. */
19371 if (subtype & RELAX_USE_SECOND)
19372 {
19373 char *start;
19374
19375 start = fragp->fr_literal + fragp->fr_fix - first - second;
19376 memmove (start, start + first, second);
19377 fragp->fr_fix -= first;
19378 }
19379 else
19380 fragp->fr_fix -= second;
19381 }
19382 }
19383
19384 /* This function is called after the relocs have been generated.
19385 We've been storing mips16 text labels as odd. Here we convert them
19386 back to even for the convenience of the debugger. */
19387
19388 void
mips_frob_file_after_relocs(void)19389 mips_frob_file_after_relocs (void)
19390 {
19391 asymbol **syms;
19392 unsigned int count, i;
19393
19394 syms = bfd_get_outsymbols (stdoutput);
19395 count = bfd_get_symcount (stdoutput);
19396 for (i = 0; i < count; i++, syms++)
19397 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other)
19398 && ((*syms)->value & 1) != 0)
19399 {
19400 (*syms)->value &= ~1;
19401 /* If the symbol has an odd size, it was probably computed
19402 incorrectly, so adjust that as well. */
19403 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
19404 ++elf_symbol (*syms)->internal_elf_sym.st_size;
19405 }
19406 }
19407
19408 /* This function is called whenever a label is defined, including fake
19409 labels instantiated off the dot special symbol. It is used when
19410 handling branch delays; if a branch has a label, we assume we cannot
19411 move it. This also bumps the value of the symbol by 1 in compressed
19412 code. */
19413
19414 static void
mips_record_label(symbolS * sym)19415 mips_record_label (symbolS *sym)
19416 {
19417 segment_info_type *si = seg_info (now_seg);
19418 struct insn_label_list *l;
19419
19420 if (free_insn_labels == NULL)
19421 l = XNEW (struct insn_label_list);
19422 else
19423 {
19424 l = free_insn_labels;
19425 free_insn_labels = l->next;
19426 }
19427
19428 l->label = sym;
19429 l->next = si->label_list;
19430 si->label_list = l;
19431 }
19432
19433 /* This function is called as tc_frob_label() whenever a label is defined
19434 and adds a DWARF-2 record we only want for true labels. */
19435
19436 void
mips_define_label(symbolS * sym)19437 mips_define_label (symbolS *sym)
19438 {
19439 mips_record_label (sym);
19440 dwarf2_emit_label (sym);
19441 }
19442
19443 /* This function is called by tc_new_dot_label whenever a new dot symbol
19444 is defined. */
19445
19446 void
mips_add_dot_label(symbolS * sym)19447 mips_add_dot_label (symbolS *sym)
19448 {
19449 mips_record_label (sym);
19450 if (mips_assembling_insn && HAVE_CODE_COMPRESSION)
19451 mips_compressed_mark_label (sym);
19452 }
19453
19454 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19455 static unsigned int
mips_convert_ase_flags(int ase)19456 mips_convert_ase_flags (int ase)
19457 {
19458 unsigned int ext_ases = 0;
19459
19460 if (ase & ASE_DSP)
19461 ext_ases |= AFL_ASE_DSP;
19462 if (ase & ASE_DSPR2)
19463 ext_ases |= AFL_ASE_DSPR2;
19464 if (ase & ASE_DSPR3)
19465 ext_ases |= AFL_ASE_DSPR3;
19466 if (ase & ASE_EVA)
19467 ext_ases |= AFL_ASE_EVA;
19468 if (ase & ASE_MCU)
19469 ext_ases |= AFL_ASE_MCU;
19470 if (ase & ASE_MDMX)
19471 ext_ases |= AFL_ASE_MDMX;
19472 if (ase & ASE_MIPS3D)
19473 ext_ases |= AFL_ASE_MIPS3D;
19474 if (ase & ASE_MT)
19475 ext_ases |= AFL_ASE_MT;
19476 if (ase & ASE_SMARTMIPS)
19477 ext_ases |= AFL_ASE_SMARTMIPS;
19478 if (ase & ASE_VIRT)
19479 ext_ases |= AFL_ASE_VIRT;
19480 if (ase & ASE_MSA)
19481 ext_ases |= AFL_ASE_MSA;
19482 if (ase & ASE_XPA)
19483 ext_ases |= AFL_ASE_XPA;
19484 if (ase & ASE_MIPS16E2)
19485 ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0;
19486 if (ase & ASE_CRC)
19487 ext_ases |= AFL_ASE_CRC;
19488 if (ase & ASE_GINV)
19489 ext_ases |= AFL_ASE_GINV;
19490 if (ase & ASE_LOONGSON_MMI)
19491 ext_ases |= AFL_ASE_LOONGSON_MMI;
19492 if (ase & ASE_LOONGSON_CAM)
19493 ext_ases |= AFL_ASE_LOONGSON_CAM;
19494 if (ase & ASE_LOONGSON_EXT)
19495 ext_ases |= AFL_ASE_LOONGSON_EXT;
19496 if (ase & ASE_LOONGSON_EXT2)
19497 ext_ases |= AFL_ASE_LOONGSON_EXT2;
19498
19499 return ext_ases;
19500 }
19501 /* Some special processing for a MIPS ELF file. */
19502
19503 void
mips_elf_final_processing(void)19504 mips_elf_final_processing (void)
19505 {
19506 int fpabi;
19507 Elf_Internal_ABIFlags_v0 flags;
19508
19509 flags.version = 0;
19510 flags.isa_rev = 0;
19511 switch (file_mips_opts.isa)
19512 {
19513 case INSN_ISA1:
19514 flags.isa_level = 1;
19515 break;
19516 case INSN_ISA2:
19517 flags.isa_level = 2;
19518 break;
19519 case INSN_ISA3:
19520 flags.isa_level = 3;
19521 break;
19522 case INSN_ISA4:
19523 flags.isa_level = 4;
19524 break;
19525 case INSN_ISA5:
19526 flags.isa_level = 5;
19527 break;
19528 case INSN_ISA32:
19529 flags.isa_level = 32;
19530 flags.isa_rev = 1;
19531 break;
19532 case INSN_ISA32R2:
19533 flags.isa_level = 32;
19534 flags.isa_rev = 2;
19535 break;
19536 case INSN_ISA32R3:
19537 flags.isa_level = 32;
19538 flags.isa_rev = 3;
19539 break;
19540 case INSN_ISA32R5:
19541 flags.isa_level = 32;
19542 flags.isa_rev = 5;
19543 break;
19544 case INSN_ISA32R6:
19545 flags.isa_level = 32;
19546 flags.isa_rev = 6;
19547 break;
19548 case INSN_ISA64:
19549 flags.isa_level = 64;
19550 flags.isa_rev = 1;
19551 break;
19552 case INSN_ISA64R2:
19553 flags.isa_level = 64;
19554 flags.isa_rev = 2;
19555 break;
19556 case INSN_ISA64R3:
19557 flags.isa_level = 64;
19558 flags.isa_rev = 3;
19559 break;
19560 case INSN_ISA64R5:
19561 flags.isa_level = 64;
19562 flags.isa_rev = 5;
19563 break;
19564 case INSN_ISA64R6:
19565 flags.isa_level = 64;
19566 flags.isa_rev = 6;
19567 break;
19568 }
19569
19570 flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64;
19571 flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE
19572 : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128
19573 : (file_mips_opts.fp == 64) ? AFL_REG_64
19574 : AFL_REG_32;
19575 flags.cpr2_size = AFL_REG_NONE;
19576 flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19577 Tag_GNU_MIPS_ABI_FP);
19578 flags.isa_ext = bfd_mips_isa_ext (stdoutput);
19579 flags.ases = mips_convert_ase_flags (file_mips_opts.ase);
19580 if (file_ase_mips16)
19581 flags.ases |= AFL_ASE_MIPS16;
19582 if (file_ase_micromips)
19583 flags.ases |= AFL_ASE_MICROMIPS;
19584 flags.flags1 = 0;
19585 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
19586 || file_mips_opts.fp == 64)
19587 && file_mips_opts.oddspreg)
19588 flags.flags1 |= AFL_FLAGS1_ODDSPREG;
19589 flags.flags2 = 0;
19590
19591 bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags,
19592 ((Elf_External_ABIFlags_v0 *)
19593 mips_flags_frag));
19594
19595 /* Write out the register information. */
19596 if (mips_abi != N64_ABI)
19597 {
19598 Elf32_RegInfo s;
19599
19600 s.ri_gprmask = mips_gprmask;
19601 s.ri_cprmask[0] = mips_cprmask[0];
19602 s.ri_cprmask[1] = mips_cprmask[1];
19603 s.ri_cprmask[2] = mips_cprmask[2];
19604 s.ri_cprmask[3] = mips_cprmask[3];
19605 /* The gp_value field is set by the MIPS ELF backend. */
19606
19607 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
19608 ((Elf32_External_RegInfo *)
19609 mips_regmask_frag));
19610 }
19611 else
19612 {
19613 Elf64_Internal_RegInfo s;
19614
19615 s.ri_gprmask = mips_gprmask;
19616 s.ri_pad = 0;
19617 s.ri_cprmask[0] = mips_cprmask[0];
19618 s.ri_cprmask[1] = mips_cprmask[1];
19619 s.ri_cprmask[2] = mips_cprmask[2];
19620 s.ri_cprmask[3] = mips_cprmask[3];
19621 /* The gp_value field is set by the MIPS ELF backend. */
19622
19623 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
19624 ((Elf64_External_RegInfo *)
19625 mips_regmask_frag));
19626 }
19627
19628 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19629 sort of BFD interface for this. */
19630 if (mips_any_noreorder)
19631 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
19632 if (mips_pic != NO_PIC)
19633 {
19634 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
19635 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19636 }
19637 if (mips_abicalls)
19638 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
19639
19640 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19641 defined at present; this might need to change in future. */
19642 if (file_ase_mips16)
19643 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
19644 if (file_ase_micromips)
19645 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
19646 if (file_mips_opts.ase & ASE_MDMX)
19647 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
19648
19649 /* Set the MIPS ELF ABI flags. */
19650 if (mips_abi == O32_ABI && USE_EF_MIPS_ABI_O32)
19651 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_O32;
19652 else if (mips_abi == O64_ABI)
19653 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_O64;
19654 else if (mips_abi == EABI_ABI)
19655 {
19656 if (file_mips_opts.gp == 64)
19657 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_EABI64;
19658 else
19659 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_EABI32;
19660 }
19661
19662 /* Nothing to do for N32_ABI or N64_ABI. */
19663
19664 if (mips_32bitmode)
19665 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
19666
19667 if (mips_nan2008 == 1)
19668 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008;
19669
19670 /* 32 bit code with 64 bit FP registers. */
19671 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
19672 Tag_GNU_MIPS_ABI_FP);
19673 if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64)
19674 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64;
19675 }
19676
19677 typedef struct proc {
19678 symbolS *func_sym;
19679 symbolS *func_end_sym;
19680 unsigned long reg_mask;
19681 unsigned long reg_offset;
19682 unsigned long fpreg_mask;
19683 unsigned long fpreg_offset;
19684 unsigned long frame_offset;
19685 unsigned long frame_reg;
19686 unsigned long pc_reg;
19687 } procS;
19688
19689 static procS cur_proc;
19690 static procS *cur_proc_ptr;
19691 static int numprocs;
19692
19693 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19694 as "2", and a normal nop as "0". */
19695
19696 #define NOP_OPCODE_MIPS 0
19697 #define NOP_OPCODE_MIPS16 1
19698 #define NOP_OPCODE_MICROMIPS 2
19699
19700 char
mips_nop_opcode(void)19701 mips_nop_opcode (void)
19702 {
19703 if (seg_info (now_seg)->tc_segment_info_data.micromips)
19704 return NOP_OPCODE_MICROMIPS;
19705 else if (seg_info (now_seg)->tc_segment_info_data.mips16)
19706 return NOP_OPCODE_MIPS16;
19707 else
19708 return NOP_OPCODE_MIPS;
19709 }
19710
19711 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19712 32-bit microMIPS NOPs here (if applicable). */
19713
19714 void
mips_handle_align(fragS * fragp)19715 mips_handle_align (fragS *fragp)
19716 {
19717 char nop_opcode;
19718 char *p;
19719 int bytes, size, excess;
19720 valueT opcode;
19721
19722 if (fragp->fr_type != rs_align_code)
19723 return;
19724
19725 p = fragp->fr_literal + fragp->fr_fix;
19726 nop_opcode = *p;
19727 switch (nop_opcode)
19728 {
19729 case NOP_OPCODE_MICROMIPS:
19730 opcode = micromips_nop32_insn.insn_opcode;
19731 size = 4;
19732 break;
19733 case NOP_OPCODE_MIPS16:
19734 opcode = mips16_nop_insn.insn_opcode;
19735 size = 2;
19736 break;
19737 case NOP_OPCODE_MIPS:
19738 default:
19739 opcode = nop_insn.insn_opcode;
19740 size = 4;
19741 break;
19742 }
19743
19744 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
19745 excess = bytes % size;
19746
19747 /* Handle the leading part if we're not inserting a whole number of
19748 instructions, and make it the end of the fixed part of the frag.
19749 Try to fit in a short microMIPS NOP if applicable and possible,
19750 and use zeroes otherwise. */
19751 gas_assert (excess < 4);
19752 fragp->fr_fix += excess;
19753 switch (excess)
19754 {
19755 case 3:
19756 *p++ = '\0';
19757 /* Fall through. */
19758 case 2:
19759 if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32)
19760 {
19761 p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2);
19762 break;
19763 }
19764 *p++ = '\0';
19765 /* Fall through. */
19766 case 1:
19767 *p++ = '\0';
19768 /* Fall through. */
19769 case 0:
19770 break;
19771 }
19772
19773 md_number_to_chars (p, opcode, size);
19774 fragp->fr_var = size;
19775 }
19776
19777 static long
get_number(void)19778 get_number (void)
19779 {
19780 int negative = 0;
19781 long val = 0;
19782
19783 if (*input_line_pointer == '-')
19784 {
19785 ++input_line_pointer;
19786 negative = 1;
19787 }
19788 if (!ISDIGIT (*input_line_pointer))
19789 as_bad (_("expected simple number"));
19790 if (input_line_pointer[0] == '0')
19791 {
19792 if (input_line_pointer[1] == 'x')
19793 {
19794 input_line_pointer += 2;
19795 while (ISXDIGIT (*input_line_pointer))
19796 {
19797 val <<= 4;
19798 val |= hex_value (*input_line_pointer++);
19799 }
19800 return negative ? -val : val;
19801 }
19802 else
19803 {
19804 ++input_line_pointer;
19805 while (ISDIGIT (*input_line_pointer))
19806 {
19807 val <<= 3;
19808 val |= *input_line_pointer++ - '0';
19809 }
19810 return negative ? -val : val;
19811 }
19812 }
19813 if (!ISDIGIT (*input_line_pointer))
19814 {
19815 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19816 *input_line_pointer, *input_line_pointer);
19817 as_warn (_("invalid number"));
19818 return -1;
19819 }
19820 while (ISDIGIT (*input_line_pointer))
19821 {
19822 val *= 10;
19823 val += *input_line_pointer++ - '0';
19824 }
19825 return negative ? -val : val;
19826 }
19827
19828 /* The .file directive; just like the usual .file directive, but there
19829 is an initial number which is the ECOFF file index. In the non-ECOFF
19830 case .file implies DWARF-2. */
19831
19832 static void
s_mips_file(int x ATTRIBUTE_UNUSED)19833 s_mips_file (int x ATTRIBUTE_UNUSED)
19834 {
19835 static int first_file_directive = 0;
19836
19837 if (ECOFF_DEBUGGING)
19838 {
19839 get_number ();
19840 s_file (0);
19841 }
19842 else
19843 {
19844 char *filename;
19845
19846 filename = dwarf2_directive_filename ();
19847
19848 /* Versions of GCC up to 3.1 start files with a ".file"
19849 directive even for stabs output. Make sure that this
19850 ".file" is handled. Note that you need a version of GCC
19851 after 3.1 in order to support DWARF-2 on MIPS. */
19852 if (filename != NULL && ! first_file_directive)
19853 {
19854 new_logical_line (filename, -1);
19855 s_file_string (filename);
19856 }
19857 first_file_directive = 1;
19858 }
19859 }
19860
19861 /* The .loc directive, implying DWARF-2. */
19862
19863 static void
s_mips_loc(int x ATTRIBUTE_UNUSED)19864 s_mips_loc (int x ATTRIBUTE_UNUSED)
19865 {
19866 if (!ECOFF_DEBUGGING)
19867 dwarf2_directive_loc (0);
19868 }
19869
19870 /* The .end directive. */
19871
19872 static void
s_mips_end(int x ATTRIBUTE_UNUSED)19873 s_mips_end (int x ATTRIBUTE_UNUSED)
19874 {
19875 symbolS *p;
19876
19877 /* Following functions need their own .frame and .cprestore directives. */
19878 mips_frame_reg_valid = 0;
19879 mips_cprestore_valid = 0;
19880
19881 if (!is_end_of_line[(unsigned char) *input_line_pointer])
19882 {
19883 p = get_symbol ();
19884 demand_empty_rest_of_line ();
19885 }
19886 else
19887 p = NULL;
19888
19889 if ((bfd_section_flags (now_seg) & SEC_CODE) == 0)
19890 as_warn (_(".end not in text section"));
19891
19892 if (!cur_proc_ptr)
19893 {
19894 as_warn (_(".end directive without a preceding .ent directive"));
19895 demand_empty_rest_of_line ();
19896 return;
19897 }
19898
19899 if (p != NULL)
19900 {
19901 gas_assert (S_GET_NAME (p));
19902 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
19903 as_warn (_(".end symbol does not match .ent symbol"));
19904
19905 if (debug_type == DEBUG_STABS)
19906 stabs_generate_asm_endfunc (S_GET_NAME (p),
19907 S_GET_NAME (p));
19908 }
19909 else
19910 as_warn (_(".end directive missing or unknown symbol"));
19911
19912 /* Create an expression to calculate the size of the function. */
19913 if (p && cur_proc_ptr)
19914 {
19915 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
19916 expressionS *exp = XNEW (expressionS);
19917
19918 obj->size = exp;
19919 exp->X_op = O_subtract;
19920 exp->X_add_symbol = symbol_temp_new_now ();
19921 exp->X_op_symbol = p;
19922 exp->X_add_number = 0;
19923
19924 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
19925 }
19926
19927 #ifdef md_flush_pending_output
19928 md_flush_pending_output ();
19929 #endif
19930
19931 /* Generate a .pdr section. */
19932 if (!ECOFF_DEBUGGING && mips_flag_pdr)
19933 {
19934 segT saved_seg = now_seg;
19935 subsegT saved_subseg = now_subseg;
19936 expressionS exp;
19937 char *fragp;
19938
19939 gas_assert (pdr_seg);
19940 subseg_set (pdr_seg, 0);
19941
19942 /* Write the symbol. */
19943 exp.X_op = O_symbol;
19944 exp.X_add_symbol = p;
19945 exp.X_add_number = 0;
19946 emit_expr (&exp, 4);
19947
19948 fragp = frag_more (7 * 4);
19949
19950 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
19951 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
19952 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
19953 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
19954 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
19955 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
19956 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
19957
19958 subseg_set (saved_seg, saved_subseg);
19959 }
19960
19961 cur_proc_ptr = NULL;
19962 }
19963
19964 /* The .aent and .ent directives. */
19965
19966 static void
s_mips_ent(int aent)19967 s_mips_ent (int aent)
19968 {
19969 symbolS *symbolP;
19970
19971 symbolP = get_symbol ();
19972 if (*input_line_pointer == ',')
19973 ++input_line_pointer;
19974 SKIP_WHITESPACE ();
19975 if (ISDIGIT (*input_line_pointer)
19976 || *input_line_pointer == '-')
19977 get_number ();
19978
19979 if ((bfd_section_flags (now_seg) & SEC_CODE) == 0)
19980 as_warn (_(".ent or .aent not in text section"));
19981
19982 if (!aent && cur_proc_ptr)
19983 as_warn (_("missing .end"));
19984
19985 if (!aent)
19986 {
19987 /* This function needs its own .frame and .cprestore directives. */
19988 mips_frame_reg_valid = 0;
19989 mips_cprestore_valid = 0;
19990
19991 cur_proc_ptr = &cur_proc;
19992 memset (cur_proc_ptr, '\0', sizeof (procS));
19993
19994 cur_proc_ptr->func_sym = symbolP;
19995
19996 ++numprocs;
19997
19998 if (debug_type == DEBUG_STABS)
19999 stabs_generate_asm_func (S_GET_NAME (symbolP),
20000 S_GET_NAME (symbolP));
20001 }
20002
20003 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
20004
20005 demand_empty_rest_of_line ();
20006 }
20007
20008 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
20009 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
20010 s_mips_frame is used so that we can set the PDR information correctly.
20011 We can't use the ecoff routines because they make reference to the ecoff
20012 symbol table (in the mdebug section). */
20013
20014 static void
s_mips_frame(int ignore ATTRIBUTE_UNUSED)20015 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
20016 {
20017 if (ECOFF_DEBUGGING)
20018 s_ignore (ignore);
20019 else
20020 {
20021 long val;
20022
20023 if (cur_proc_ptr == (procS *) NULL)
20024 {
20025 as_warn (_(".frame outside of .ent"));
20026 demand_empty_rest_of_line ();
20027 return;
20028 }
20029
20030 cur_proc_ptr->frame_reg = tc_get_register (1);
20031
20032 SKIP_WHITESPACE ();
20033 if (*input_line_pointer++ != ','
20034 || get_absolute_expression_and_terminator (&val) != ',')
20035 {
20036 as_warn (_("bad .frame directive"));
20037 --input_line_pointer;
20038 demand_empty_rest_of_line ();
20039 return;
20040 }
20041
20042 cur_proc_ptr->frame_offset = val;
20043 cur_proc_ptr->pc_reg = tc_get_register (0);
20044
20045 demand_empty_rest_of_line ();
20046 }
20047 }
20048
20049 /* The .fmask and .mask directives. If the mdebug section is present
20050 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
20051 embedded targets, s_mips_mask is used so that we can set the PDR
20052 information correctly. We can't use the ecoff routines because they
20053 make reference to the ecoff symbol table (in the mdebug section). */
20054
20055 static void
s_mips_mask(int reg_type)20056 s_mips_mask (int reg_type)
20057 {
20058 if (ECOFF_DEBUGGING)
20059 s_ignore (reg_type);
20060 else
20061 {
20062 long mask, off;
20063
20064 if (cur_proc_ptr == (procS *) NULL)
20065 {
20066 as_warn (_(".mask/.fmask outside of .ent"));
20067 demand_empty_rest_of_line ();
20068 return;
20069 }
20070
20071 if (get_absolute_expression_and_terminator (&mask) != ',')
20072 {
20073 as_warn (_("bad .mask/.fmask directive"));
20074 --input_line_pointer;
20075 demand_empty_rest_of_line ();
20076 return;
20077 }
20078
20079 off = get_absolute_expression ();
20080
20081 if (reg_type == 'F')
20082 {
20083 cur_proc_ptr->fpreg_mask = mask;
20084 cur_proc_ptr->fpreg_offset = off;
20085 }
20086 else
20087 {
20088 cur_proc_ptr->reg_mask = mask;
20089 cur_proc_ptr->reg_offset = off;
20090 }
20091
20092 demand_empty_rest_of_line ();
20093 }
20094 }
20095
20096 /* A table describing all the processors gas knows about. Names are
20097 matched in the order listed.
20098
20099 To ease comparison, please keep this table in the same order as
20100 gcc's mips_cpu_info_table[]. */
20101 static const struct mips_cpu_info mips_cpu_info_table[] =
20102 {
20103 /* Entries for generic ISAs. */
20104 { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
20105 { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
20106 { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
20107 { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
20108 { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
20109 { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
20110 { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20111 { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 },
20112 { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 },
20113 { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 },
20114 { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
20115 { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
20116 { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 },
20117 { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 },
20118 { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 },
20119
20120 /* MIPS I */
20121 { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
20122 { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
20123 { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
20124
20125 /* MIPS II */
20126 { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
20127 { "allegrex", 0, 0, ISA_MIPS2, CPU_ALLEGREX },
20128
20129 /* MIPS III */
20130 { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
20131 { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
20132 { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
20133 { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
20134 { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
20135 { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
20136 { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
20137 { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
20138 { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
20139 { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
20140 { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
20141 { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
20142 { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
20143 /* ST Microelectronics Loongson 2E and 2F cores. */
20144 { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
20145 { "loongson2f", 0, ASE_LOONGSON_MMI, ISA_MIPS3, CPU_LOONGSON_2F },
20146
20147 /* MIPS IV */
20148 { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
20149 { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
20150 { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
20151 { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
20152 { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
20153 { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
20154 { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
20155 { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
20156 { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
20157 { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
20158 { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
20159 { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
20160 { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
20161 { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
20162 { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
20163
20164 /* MIPS 32 */
20165 { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
20166 { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
20167 { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
20168 { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
20169
20170 /* MIPS 32 Release 2 */
20171 { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20172 { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20173 { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20174 { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
20175 { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20176 { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20177 { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
20178 { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
20179 { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
20180 ISA_MIPS32R2, CPU_MIPS32R2 },
20181 { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
20182 ISA_MIPS32R2, CPU_MIPS32R2 },
20183 { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20184 { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20185 { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20186 { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20187 /* Deprecated forms of the above. */
20188 { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20189 { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
20190 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20191 { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
20192 { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
20193 { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
20194 { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
20195 /* Deprecated forms of the above. */
20196 { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
20197 { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
20198 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20199 { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20200 { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20201 { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20202 { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20203 /* Deprecated forms of the above. */
20204 { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20205 { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20206 /* 34Kn is a 34kc without DSP. */
20207 { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20208 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20209 { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20210 { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20211 { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20212 { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20213 { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20214 /* Deprecated forms of the above. */
20215 { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20216 { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
20217 /* 1004K cores are multiprocessor versions of the 34K. */
20218 { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20219 { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20220 { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20221 { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20222 /* interaptiv is the new name for 1004kf. */
20223 { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
20224 { "interaptiv-mr2", 0,
20225 ASE_DSP | ASE_EVA | ASE_MT | ASE_MIPS16E2 | ASE_MIPS16E2_MT,
20226 ISA_MIPS32R3, CPU_INTERAPTIV_MR2 },
20227 /* M5100 family. */
20228 { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
20229 { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
20230 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20231 { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },
20232
20233 /* MIPS 64 */
20234 { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
20235 { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
20236 { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
20237 { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
20238
20239 /* Broadcom SB-1 CPU core. */
20240 { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
20241 /* Broadcom SB-1A CPU core. */
20242 { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
20243
20244 /* MIPS 64 Release 2. */
20245 /* Loongson CPU core. */
20246 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20247 { "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
20248 ISA_MIPS64R2, CPU_GS464 },
20249 { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
20250 ISA_MIPS64R2, CPU_GS464 },
20251 { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
20252 | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E },
20253 { "gs264e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
20254 | ASE_LOONGSON_EXT2 | ASE_MSA | ASE_MSA64, ISA_MIPS64R2, CPU_GS264E },
20255
20256 /* Cavium Networks Octeon CPU core. */
20257 { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
20258 { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
20259 { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
20260 { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 },
20261
20262 /* RMI Xlr */
20263 { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
20264
20265 /* Broadcom XLP.
20266 XLP is mostly like XLR, with the prominent exception that it is
20267 MIPS64R2 rather than MIPS64. */
20268 { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
20269
20270 /* MIPS 64 Release 6. */
20271 { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
20272 { "i6500", 0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV,
20273 ISA_MIPS64R6, CPU_MIPS64R6},
20274 { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
20275
20276 /* End marker. */
20277 { NULL, 0, 0, 0, 0 }
20278 };
20279
20280
20281 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20282 with a final "000" replaced by "k". Ignore case.
20283
20284 Note: this function is shared between GCC and GAS. */
20285
20286 static bool
mips_strict_matching_cpu_name_p(const char * canonical,const char * given)20287 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
20288 {
20289 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
20290 given++, canonical++;
20291
20292 return ((*given == 0 && *canonical == 0)
20293 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
20294 }
20295
20296
20297 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20298 CPU name. We've traditionally allowed a lot of variation here.
20299
20300 Note: this function is shared between GCC and GAS. */
20301
20302 static bool
mips_matching_cpu_name_p(const char * canonical,const char * given)20303 mips_matching_cpu_name_p (const char *canonical, const char *given)
20304 {
20305 /* First see if the name matches exactly, or with a final "000"
20306 turned into "k". */
20307 if (mips_strict_matching_cpu_name_p (canonical, given))
20308 return true;
20309
20310 /* If not, try comparing based on numerical designation alone.
20311 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20312 if (TOLOWER (*given) == 'r')
20313 given++;
20314 if (!ISDIGIT (*given))
20315 return false;
20316
20317 /* Skip over some well-known prefixes in the canonical name,
20318 hoping to find a number there too. */
20319 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
20320 canonical += 2;
20321 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
20322 canonical += 2;
20323 else if (TOLOWER (canonical[0]) == 'r')
20324 canonical += 1;
20325
20326 return mips_strict_matching_cpu_name_p (canonical, given);
20327 }
20328
20329
20330 /* Parse an option that takes the name of a processor as its argument.
20331 OPTION is the name of the option and CPU_STRING is the argument.
20332 Return the corresponding processor enumeration if the CPU_STRING is
20333 recognized, otherwise report an error and return null.
20334
20335 A similar function exists in GCC. */
20336
20337 static const struct mips_cpu_info *
mips_parse_cpu(const char * option,const char * cpu_string)20338 mips_parse_cpu (const char *option, const char *cpu_string)
20339 {
20340 const struct mips_cpu_info *p;
20341
20342 /* 'from-abi' selects the most compatible architecture for the given
20343 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20344 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20345 version. Look first at the -mgp options, if given, otherwise base
20346 the choice on MIPS_DEFAULT_64BIT.
20347
20348 Treat NO_ABI like the EABIs. One reason to do this is that the
20349 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20350 architecture. This code picks MIPS I for 'mips' and MIPS III for
20351 'mips64', just as we did in the days before 'from-abi'. */
20352 if (strcasecmp (cpu_string, "from-abi") == 0)
20353 {
20354 if (ABI_NEEDS_32BIT_REGS (mips_abi))
20355 return mips_cpu_info_from_isa (ISA_MIPS1);
20356
20357 if (ABI_NEEDS_64BIT_REGS (mips_abi))
20358 return mips_cpu_info_from_isa (ISA_MIPS3);
20359
20360 if (file_mips_opts.gp >= 0)
20361 return mips_cpu_info_from_isa (file_mips_opts.gp == 32
20362 ? ISA_MIPS1 : ISA_MIPS3);
20363
20364 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20365 ? ISA_MIPS3
20366 : ISA_MIPS1);
20367 }
20368
20369 /* 'default' has traditionally been a no-op. Probably not very useful. */
20370 if (strcasecmp (cpu_string, "default") == 0)
20371 return 0;
20372
20373 for (p = mips_cpu_info_table; p->name != 0; p++)
20374 if (mips_matching_cpu_name_p (p->name, cpu_string))
20375 return p;
20376
20377 as_bad (_("bad value (%s) for %s"), cpu_string, option);
20378 return 0;
20379 }
20380
20381 /* Return the canonical processor information for ISA (a member of the
20382 ISA_MIPS* enumeration). */
20383
20384 static const struct mips_cpu_info *
mips_cpu_info_from_isa(int isa)20385 mips_cpu_info_from_isa (int isa)
20386 {
20387 int i;
20388
20389 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
20390 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
20391 && isa == mips_cpu_info_table[i].isa)
20392 return (&mips_cpu_info_table[i]);
20393
20394 return NULL;
20395 }
20396
20397 static const struct mips_cpu_info *
mips_cpu_info_from_arch(int arch)20398 mips_cpu_info_from_arch (int arch)
20399 {
20400 int i;
20401
20402 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
20403 if (arch == mips_cpu_info_table[i].cpu)
20404 return (&mips_cpu_info_table[i]);
20405
20406 return NULL;
20407 }
20408
20409 static void
show(FILE * stream,const char * string,int * col_p,int * first_p)20410 show (FILE *stream, const char *string, int *col_p, int *first_p)
20411 {
20412 if (*first_p)
20413 {
20414 fprintf (stream, "%24s", "");
20415 *col_p = 24;
20416 }
20417 else
20418 {
20419 fprintf (stream, ", ");
20420 *col_p += 2;
20421 }
20422
20423 if (*col_p + strlen (string) > 72)
20424 {
20425 fprintf (stream, "\n%24s", "");
20426 *col_p = 24;
20427 }
20428
20429 fprintf (stream, "%s", string);
20430 *col_p += strlen (string);
20431
20432 *first_p = 0;
20433 }
20434
20435 void
md_show_usage(FILE * stream)20436 md_show_usage (FILE *stream)
20437 {
20438 int column, first;
20439 size_t i;
20440
20441 fprintf (stream, _("\
20442 MIPS options:\n\
20443 -EB generate big endian output\n\
20444 -EL generate little endian output\n\
20445 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20446 -G NUM allow referencing objects up to NUM bytes\n\
20447 implicitly with the gp register [default 8]\n"));
20448 fprintf (stream, _("\
20449 -mips1 generate MIPS ISA I instructions\n\
20450 -mips2 generate MIPS ISA II instructions\n\
20451 -mips3 generate MIPS ISA III instructions\n\
20452 -mips4 generate MIPS ISA IV instructions\n\
20453 -mips5 generate MIPS ISA V instructions\n\
20454 -mips32 generate MIPS32 ISA instructions\n\
20455 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20456 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20457 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20458 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20459 -mips64 generate MIPS64 ISA instructions\n\
20460 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20461 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20462 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20463 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20464 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20465
20466 first = 1;
20467
20468 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
20469 show (stream, mips_cpu_info_table[i].name, &column, &first);
20470 show (stream, "from-abi", &column, &first);
20471 fputc ('\n', stream);
20472
20473 fprintf (stream, _("\
20474 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20475 -no-mCPU don't generate code specific to CPU.\n\
20476 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20477
20478 first = 1;
20479
20480 show (stream, "3900", &column, &first);
20481 show (stream, "4010", &column, &first);
20482 show (stream, "4100", &column, &first);
20483 show (stream, "4650", &column, &first);
20484 fputc ('\n', stream);
20485
20486 fprintf (stream, _("\
20487 -mips16 generate mips16 instructions\n\
20488 -no-mips16 do not generate mips16 instructions\n"));
20489 fprintf (stream, _("\
20490 -mmips16e2 generate MIPS16e2 instructions\n\
20491 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20492 fprintf (stream, _("\
20493 -mmicromips generate microMIPS instructions\n\
20494 -mno-micromips do not generate microMIPS instructions\n"));
20495 fprintf (stream, _("\
20496 -msmartmips generate smartmips instructions\n\
20497 -mno-smartmips do not generate smartmips instructions\n"));
20498 fprintf (stream, _("\
20499 -mdsp generate DSP instructions\n\
20500 -mno-dsp do not generate DSP instructions\n"));
20501 fprintf (stream, _("\
20502 -mdspr2 generate DSP R2 instructions\n\
20503 -mno-dspr2 do not generate DSP R2 instructions\n"));
20504 fprintf (stream, _("\
20505 -mdspr3 generate DSP R3 instructions\n\
20506 -mno-dspr3 do not generate DSP R3 instructions\n"));
20507 fprintf (stream, _("\
20508 -mmt generate MT instructions\n\
20509 -mno-mt do not generate MT instructions\n"));
20510 fprintf (stream, _("\
20511 -mmcu generate MCU instructions\n\
20512 -mno-mcu do not generate MCU instructions\n"));
20513 fprintf (stream, _("\
20514 -mmsa generate MSA instructions\n\
20515 -mno-msa do not generate MSA instructions\n"));
20516 fprintf (stream, _("\
20517 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20518 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20519 fprintf (stream, _("\
20520 -mvirt generate Virtualization instructions\n\
20521 -mno-virt do not generate Virtualization instructions\n"));
20522 fprintf (stream, _("\
20523 -mcrc generate CRC instructions\n\
20524 -mno-crc do not generate CRC instructions\n"));
20525 fprintf (stream, _("\
20526 -mginv generate Global INValidate (GINV) instructions\n\
20527 -mno-ginv do not generate Global INValidate instructions\n"));
20528 fprintf (stream, _("\
20529 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20530 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20531 fprintf (stream, _("\
20532 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20533 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20534 fprintf (stream, _("\
20535 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20536 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20537 fprintf (stream, _("\
20538 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20539 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20540 fprintf (stream, _("\
20541 -minsn32 only generate 32-bit microMIPS instructions\n\
20542 -mno-insn32 generate all microMIPS instructions\n"));
20543 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20544 fprintf (stream, _("\
20545 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20546 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20547 #else
20548 fprintf (stream, _("\
20549 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20550 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20551 #endif
20552 fprintf (stream, _("\
20553 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20554 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20555 -mfix-loongson2f-btb work around Loongson2F BTB errata\n\
20556 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20557 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20558 -mfix-vr4120 work around certain VR4120 errata\n\
20559 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20560 -mfix-24k insert a nop after ERET and DERET instructions\n\
20561 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20562 -mfix-r5900 work around R5900 short loop errata\n\
20563 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20564 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20565 -msym32 assume all symbols have 32-bit values\n\
20566 -O0 do not remove unneeded NOPs, do not swap branches\n\
20567 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20568 -O2 remove unneeded NOPs and swap branches\n\
20569 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20570 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20571 fprintf (stream, _("\
20572 -mhard-float allow floating-point instructions\n\
20573 -msoft-float do not allow floating-point instructions\n\
20574 -msingle-float only allow 32-bit floating-point operations\n\
20575 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20576 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20577 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20578 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20579 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20580 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20581
20582 first = 1;
20583
20584 show (stream, "legacy", &column, &first);
20585 show (stream, "2008", &column, &first);
20586
20587 fputc ('\n', stream);
20588
20589 fprintf (stream, _("\
20590 -KPIC, -call_shared generate SVR4 position independent code\n\
20591 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20592 -mvxworks-pic generate VxWorks position independent code\n\
20593 -non_shared do not generate code that can operate with DSOs\n\
20594 -xgot assume a 32 bit GOT\n\
20595 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20596 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20597 position dependent (non shared) code\n\
20598 -mabi=ABI create ABI conformant object file for:\n"));
20599
20600 first = 1;
20601
20602 show (stream, "32", &column, &first);
20603 show (stream, "o64", &column, &first);
20604 show (stream, "n32", &column, &first);
20605 show (stream, "64", &column, &first);
20606 show (stream, "eabi", &column, &first);
20607
20608 fputc ('\n', stream);
20609
20610 fprintf (stream, _("\
20611 -32 create o32 ABI object file%s\n"),
20612 MIPS_DEFAULT_ABI == O32_ABI ? _(" (default)") : "");
20613 fprintf (stream, _("\
20614 -n32 create n32 ABI object file%s\n"),
20615 MIPS_DEFAULT_ABI == N32_ABI ? _(" (default)") : "");
20616 fprintf (stream, _("\
20617 -64 create 64 ABI object file%s\n"),
20618 MIPS_DEFAULT_ABI == N64_ABI ? _(" (default)") : "");
20619 }
20620
20621 #ifdef TE_IRIX
20622 enum dwarf2_format
mips_dwarf2_format(asection * sec ATTRIBUTE_UNUSED)20623 mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
20624 {
20625 if (HAVE_64BIT_SYMBOLS)
20626 return dwarf2_format_64bit_irix;
20627 else
20628 return dwarf2_format_32bit;
20629 }
20630 #endif
20631
20632 int
mips_dwarf2_addr_size(void)20633 mips_dwarf2_addr_size (void)
20634 {
20635 if (HAVE_64BIT_OBJECTS)
20636 return 8;
20637 else
20638 return 4;
20639 }
20640
20641 /* Standard calling conventions leave the CFA at SP on entry. */
20642 void
mips_cfi_frame_initial_instructions(void)20643 mips_cfi_frame_initial_instructions (void)
20644 {
20645 cfi_add_CFA_def_cfa_register (SP);
20646 }
20647
20648 int
tc_mips_regname_to_dw2regnum(char * regname)20649 tc_mips_regname_to_dw2regnum (char *regname)
20650 {
20651 unsigned int regnum = -1;
20652 unsigned int reg;
20653
20654 if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®))
20655 regnum = reg;
20656
20657 return regnum;
20658 }
20659
20660 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20661 Given a symbolic attribute NAME, return the proper integer value.
20662 Returns -1 if the attribute is not known. */
20663
20664 int
mips_convert_symbolic_attribute(const char * name)20665 mips_convert_symbolic_attribute (const char *name)
20666 {
20667 static const struct
20668 {
20669 const char * name;
20670 const int tag;
20671 }
20672 attribute_table[] =
20673 {
20674 #define T(tag) {#tag, tag}
20675 T (Tag_GNU_MIPS_ABI_FP),
20676 T (Tag_GNU_MIPS_ABI_MSA),
20677 #undef T
20678 };
20679 unsigned int i;
20680
20681 if (name == NULL)
20682 return -1;
20683
20684 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
20685 if (streq (name, attribute_table[i].name))
20686 return attribute_table[i].tag;
20687
20688 return -1;
20689 }
20690
20691 void
mips_md_finish(void)20692 mips_md_finish (void)
20693 {
20694 int fpabi = Val_GNU_MIPS_ABI_FP_ANY;
20695
20696 mips_emit_delays ();
20697 if (cur_proc_ptr)
20698 as_warn (_("missing .end at end of assembly"));
20699
20700 /* Just in case no code was emitted, do the consistency check. */
20701 file_mips_check_options ();
20702
20703 /* Set a floating-point ABI if the user did not. */
20704 if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP))
20705 {
20706 /* Perform consistency checks on the floating-point ABI. */
20707 fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20708 Tag_GNU_MIPS_ABI_FP);
20709 if (fpabi != Val_GNU_MIPS_ABI_FP_ANY)
20710 check_fpabi (fpabi);
20711 }
20712 else
20713 {
20714 /* Soft-float gets precedence over single-float, the two options should
20715 not be used together so this should not matter. */
20716 if (file_mips_opts.soft_float == 1)
20717 fpabi = Val_GNU_MIPS_ABI_FP_SOFT;
20718 /* Single-float gets precedence over all double_float cases. */
20719 else if (file_mips_opts.single_float == 1)
20720 fpabi = Val_GNU_MIPS_ABI_FP_SINGLE;
20721 else
20722 {
20723 switch (file_mips_opts.fp)
20724 {
20725 case 32:
20726 if (file_mips_opts.gp == 32)
20727 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20728 break;
20729 case 0:
20730 fpabi = Val_GNU_MIPS_ABI_FP_XX;
20731 break;
20732 case 64:
20733 if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg)
20734 fpabi = Val_GNU_MIPS_ABI_FP_64A;
20735 else if (file_mips_opts.gp == 32)
20736 fpabi = Val_GNU_MIPS_ABI_FP_64;
20737 else
20738 fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE;
20739 break;
20740 }
20741 }
20742
20743 if (!bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
20744 Tag_GNU_MIPS_ABI_FP, fpabi))
20745 as_fatal (_("error adding attribute: %s"),
20746 bfd_errmsg (bfd_get_error ()));
20747 }
20748 }
20749
20750 /* Returns the relocation type required for a particular CFI encoding. */
20751
20752 bfd_reloc_code_real_type
mips_cfi_reloc_for_encoding(int encoding)20753 mips_cfi_reloc_for_encoding (int encoding)
20754 {
20755 if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel))
20756 return BFD_RELOC_32_PCREL;
20757 else return BFD_RELOC_NONE;
20758 }
20759