1 /*
2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
4 * Support: freebsdraid@avagotech.com
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer. 2. Redistributions
12 * in binary form must reproduce the above copyright notice, this list of
13 * conditions and the following disclaimer in the documentation and/or other
14 * materials provided with the distribution. 3. Neither the name of the
15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or
16 * promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing
33 * official policies,either expressed or implied, of the FreeBSD Project.
34 *
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES 1621
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
37 *
38 */
39
40 #include <sys/cdefs.h>
41 #include <dev/mrsas/mrsas.h>
42 #include <dev/mrsas/mrsas_ioctl.h>
43
44 #include <cam/cam.h>
45 #include <cam/cam_ccb.h>
46
47 #include <sys/sysctl.h>
48 #include <sys/types.h>
49 #include <sys/sysent.h>
50 #include <sys/kthread.h>
51 #include <sys/taskqueue.h>
52 #include <sys/smp.h>
53 #include <sys/endian.h>
54
55 /*
56 * Function prototypes
57 */
58 static d_open_t mrsas_open;
59 static d_close_t mrsas_close;
60 static d_read_t mrsas_read;
61 static d_write_t mrsas_write;
62 static d_ioctl_t mrsas_ioctl;
63 static d_poll_t mrsas_poll;
64
65 static void mrsas_ich_startup(void *arg);
66 static struct mrsas_mgmt_info mrsas_mgmt_info;
67 static struct mrsas_ident *mrsas_find_ident(device_t);
68 static int mrsas_setup_msix(struct mrsas_softc *sc);
69 static int mrsas_allocate_msix(struct mrsas_softc *sc);
70 static void mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode);
71 static void mrsas_flush_cache(struct mrsas_softc *sc);
72 static void mrsas_reset_reply_desc(struct mrsas_softc *sc);
73 static void mrsas_ocr_thread(void *arg);
74 static int mrsas_get_map_info(struct mrsas_softc *sc);
75 static int mrsas_get_ld_map_info(struct mrsas_softc *sc);
76 static int mrsas_sync_map_info(struct mrsas_softc *sc);
77 static int mrsas_get_pd_list(struct mrsas_softc *sc);
78 static int mrsas_get_ld_list(struct mrsas_softc *sc);
79 static int mrsas_setup_irq(struct mrsas_softc *sc);
80 static int mrsas_alloc_mem(struct mrsas_softc *sc);
81 static int mrsas_init_fw(struct mrsas_softc *sc);
82 static int mrsas_setup_raidmap(struct mrsas_softc *sc);
83 static void megasas_setup_jbod_map(struct mrsas_softc *sc);
84 static int megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend);
85 static int mrsas_clear_intr(struct mrsas_softc *sc);
86 static int mrsas_get_ctrl_info(struct mrsas_softc *sc);
87 static void mrsas_update_ext_vd_details(struct mrsas_softc *sc);
88 static int
89 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
90 struct mrsas_mfi_cmd *cmd_to_abort);
91 static void
92 mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t device_id);
93 static struct mrsas_softc *
94 mrsas_get_softc_instance(struct cdev *dev,
95 u_long cmd, caddr_t arg);
96 u_int32_t
97 mrsas_read_reg_with_retries(struct mrsas_softc *sc, int offset);
98 u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
99 u_int8_t
100 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
101 struct mrsas_mfi_cmd *mfi_cmd);
102 void mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc);
103 int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr);
104 int mrsas_init_adapter(struct mrsas_softc *sc);
105 int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc);
106 int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc);
107 int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc);
108 int mrsas_ioc_init(struct mrsas_softc *sc);
109 int mrsas_bus_scan(struct mrsas_softc *sc);
110 int mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
111 int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
112 int mrsas_reset_ctrl(struct mrsas_softc *sc, u_int8_t reset_reason);
113 int mrsas_wait_for_outstanding(struct mrsas_softc *sc, u_int8_t check_reason);
114 int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex);
115 int mrsas_reset_targets(struct mrsas_softc *sc);
116 int
117 mrsas_issue_blocked_cmd(struct mrsas_softc *sc,
118 struct mrsas_mfi_cmd *cmd);
119 int
120 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd,
121 int size);
122 void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd);
123 void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
124 void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
125 void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
126 void mrsas_disable_intr(struct mrsas_softc *sc);
127 void mrsas_enable_intr(struct mrsas_softc *sc);
128 void mrsas_free_ioc_cmd(struct mrsas_softc *sc);
129 void mrsas_free_mem(struct mrsas_softc *sc);
130 void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp);
131 void mrsas_isr(void *arg);
132 void mrsas_teardown_intr(struct mrsas_softc *sc);
133 void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
134 void mrsas_kill_hba(struct mrsas_softc *sc);
135 void mrsas_aen_handler(struct mrsas_softc *sc);
136 void
137 mrsas_write_reg(struct mrsas_softc *sc, int offset,
138 u_int32_t value);
139 void
140 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
141 u_int32_t req_desc_hi);
142 void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
143 void
144 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
145 struct mrsas_mfi_cmd *cmd, u_int8_t status);
146 struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
147
148 MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd
149 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
150
151 extern int mrsas_cam_attach(struct mrsas_softc *sc);
152 extern void mrsas_cam_detach(struct mrsas_softc *sc);
153 extern void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd);
154 extern void mrsas_free_frame(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
155 extern int mrsas_alloc_mfi_cmds(struct mrsas_softc *sc);
156 extern struct mrsas_mpt_cmd *mrsas_get_mpt_cmd(struct mrsas_softc *sc);
157 extern int mrsas_passthru(struct mrsas_softc *sc, void *arg, u_long ioctlCmd);
158 extern uint8_t MR_ValidateMapInfo(struct mrsas_softc *sc);
159 extern u_int16_t MR_GetLDTgtId(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map);
160 extern MR_LD_RAID *MR_LdRaidGet(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map);
161 extern void mrsas_xpt_freeze(struct mrsas_softc *sc);
162 extern void mrsas_xpt_release(struct mrsas_softc *sc);
163 extern MRSAS_REQUEST_DESCRIPTOR_UNION *
164 mrsas_get_request_desc(struct mrsas_softc *sc,
165 u_int16_t index);
166 extern int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim);
167 static int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc);
168 static void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc);
169 void mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd);
170
171 void mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd,
172 union ccb *ccb_ptr, u_int8_t status, u_int8_t extStatus,
173 u_int32_t data_length, u_int8_t *sense);
174 void
175 mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo,
176 u_int32_t req_desc_hi);
177
178 SYSCTL_NODE(_hw, OID_AUTO, mrsas, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
179 "MRSAS Driver Parameters");
180
181 /*
182 * PCI device struct and table
183 *
184 */
185 typedef struct mrsas_ident {
186 uint16_t vendor;
187 uint16_t device;
188 uint16_t subvendor;
189 uint16_t subdevice;
190 const char *desc;
191 } MRSAS_CTLR_ID;
192
193 MRSAS_CTLR_ID device_table[] = {
194 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "AVAGO Thunderbolt SAS Controller"},
195 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "AVAGO Invader SAS Controller"},
196 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "AVAGO Fury SAS Controller"},
197 {0x1000, MRSAS_INTRUDER, 0xffff, 0xffff, "AVAGO Intruder SAS Controller"},
198 {0x1000, MRSAS_INTRUDER_24, 0xffff, 0xffff, "AVAGO Intruder_24 SAS Controller"},
199 {0x1000, MRSAS_CUTLASS_52, 0xffff, 0xffff, "AVAGO Cutlass_52 SAS Controller"},
200 {0x1000, MRSAS_CUTLASS_53, 0xffff, 0xffff, "AVAGO Cutlass_53 SAS Controller"},
201 {0x1000, MRSAS_VENTURA, 0xffff, 0xffff, "AVAGO Ventura SAS Controller"},
202 {0x1000, MRSAS_CRUSADER, 0xffff, 0xffff, "AVAGO Crusader SAS Controller"},
203 {0x1000, MRSAS_HARPOON, 0xffff, 0xffff, "AVAGO Harpoon SAS Controller"},
204 {0x1000, MRSAS_TOMCAT, 0xffff, 0xffff, "AVAGO Tomcat SAS Controller"},
205 {0x1000, MRSAS_VENTURA_4PORT, 0xffff, 0xffff, "AVAGO Ventura_4Port SAS Controller"},
206 {0x1000, MRSAS_CRUSADER_4PORT, 0xffff, 0xffff, "AVAGO Crusader_4Port SAS Controller"},
207 {0x1000, MRSAS_AERO_10E0, 0xffff, 0xffff, "BROADCOM AERO-10E0 SAS Controller"},
208 {0x1000, MRSAS_AERO_10E1, 0xffff, 0xffff, "BROADCOM AERO-10E1 SAS Controller"},
209 {0x1000, MRSAS_AERO_10E2, 0xffff, 0xffff, "BROADCOM AERO-10E2 SAS Controller"},
210 {0x1000, MRSAS_AERO_10E3, 0xffff, 0xffff, "BROADCOM AERO-10E3 SAS Controller"},
211 {0x1000, MRSAS_AERO_10E4, 0xffff, 0xffff, "BROADCOM AERO-10E4 SAS Controller"},
212 {0x1000, MRSAS_AERO_10E5, 0xffff, 0xffff, "BROADCOM AERO-10E5 SAS Controller"},
213 {0x1000, MRSAS_AERO_10E6, 0xffff, 0xffff, "BROADCOM AERO-10E6 SAS Controller"},
214 {0x1000, MRSAS_AERO_10E7, 0xffff, 0xffff, "BROADCOM AERO-10E7 SAS Controller"},
215 {0, 0, 0, 0, NULL}
216 };
217
218 /*
219 * Character device entry points
220 *
221 */
222 static struct cdevsw mrsas_cdevsw = {
223 .d_version = D_VERSION,
224 .d_open = mrsas_open,
225 .d_close = mrsas_close,
226 .d_read = mrsas_read,
227 .d_write = mrsas_write,
228 .d_ioctl = mrsas_ioctl,
229 .d_poll = mrsas_poll,
230 .d_name = "mrsas",
231 };
232
233 MALLOC_DEFINE(M_MRSAS, "mrsasbuf", "Buffers for the MRSAS driver");
234
235 /*
236 * In the cdevsw routines, we find our softc by using the si_drv1 member of
237 * struct cdev. We set this variable to point to our softc in our attach
238 * routine when we create the /dev entry.
239 */
240 int
mrsas_open(struct cdev * dev,int oflags,int devtype,struct thread * td)241 mrsas_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
242 {
243 struct mrsas_softc *sc;
244
245 sc = dev->si_drv1;
246 return (0);
247 }
248
249 int
mrsas_close(struct cdev * dev,int fflag,int devtype,struct thread * td)250 mrsas_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
251 {
252 struct mrsas_softc *sc;
253
254 sc = dev->si_drv1;
255 return (0);
256 }
257
258 int
mrsas_read(struct cdev * dev,struct uio * uio,int ioflag)259 mrsas_read(struct cdev *dev, struct uio *uio, int ioflag)
260 {
261 struct mrsas_softc *sc;
262
263 sc = dev->si_drv1;
264 return (0);
265 }
266 int
mrsas_write(struct cdev * dev,struct uio * uio,int ioflag)267 mrsas_write(struct cdev *dev, struct uio *uio, int ioflag)
268 {
269 struct mrsas_softc *sc;
270
271 sc = dev->si_drv1;
272 return (0);
273 }
274
275 u_int32_t
mrsas_read_reg_with_retries(struct mrsas_softc * sc,int offset)276 mrsas_read_reg_with_retries(struct mrsas_softc *sc, int offset)
277 {
278 u_int32_t i = 0, ret_val;
279
280 if (sc->is_aero) {
281 do {
282 ret_val = mrsas_read_reg(sc, offset);
283 i++;
284 } while(ret_val == 0 && i < 3);
285 } else
286 ret_val = mrsas_read_reg(sc, offset);
287
288 return ret_val;
289 }
290
291 /*
292 * Register Read/Write Functions
293 *
294 */
295 void
mrsas_write_reg(struct mrsas_softc * sc,int offset,u_int32_t value)296 mrsas_write_reg(struct mrsas_softc *sc, int offset,
297 u_int32_t value)
298 {
299 bus_space_tag_t bus_tag = sc->bus_tag;
300 bus_space_handle_t bus_handle = sc->bus_handle;
301
302 bus_space_write_4(bus_tag, bus_handle, offset, value);
303 }
304
305 u_int32_t
mrsas_read_reg(struct mrsas_softc * sc,int offset)306 mrsas_read_reg(struct mrsas_softc *sc, int offset)
307 {
308 bus_space_tag_t bus_tag = sc->bus_tag;
309 bus_space_handle_t bus_handle = sc->bus_handle;
310
311 return ((u_int32_t)bus_space_read_4(bus_tag, bus_handle, offset));
312 }
313
314 /*
315 * Interrupt Disable/Enable/Clear Functions
316 *
317 */
318 void
mrsas_disable_intr(struct mrsas_softc * sc)319 mrsas_disable_intr(struct mrsas_softc *sc)
320 {
321 u_int32_t mask = 0xFFFFFFFF;
322 u_int32_t status;
323
324 sc->mask_interrupts = 1;
325 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask);
326 /* Dummy read to force pci flush */
327 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
328 }
329
330 void
mrsas_enable_intr(struct mrsas_softc * sc)331 mrsas_enable_intr(struct mrsas_softc *sc)
332 {
333 u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK;
334 u_int32_t status;
335
336 sc->mask_interrupts = 0;
337 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0);
338 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status));
339
340 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), ~mask);
341 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
342 }
343
344 static int
mrsas_clear_intr(struct mrsas_softc * sc)345 mrsas_clear_intr(struct mrsas_softc *sc)
346 {
347 u_int32_t status;
348
349 /* Read received interrupt */
350 status = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_intr_status));
351
352 /* Not our interrupt, so just return */
353 if (!(status & MFI_FUSION_ENABLE_INTERRUPT_MASK))
354 return (0);
355
356 /* We got a reply interrupt */
357 return (1);
358 }
359
360 /*
361 * PCI Support Functions
362 *
363 */
364 static struct mrsas_ident *
mrsas_find_ident(device_t dev)365 mrsas_find_ident(device_t dev)
366 {
367 struct mrsas_ident *pci_device;
368
369 for (pci_device = device_table; pci_device->vendor != 0; pci_device++) {
370 if ((pci_device->vendor == pci_get_vendor(dev)) &&
371 (pci_device->device == pci_get_device(dev)) &&
372 ((pci_device->subvendor == pci_get_subvendor(dev)) ||
373 (pci_device->subvendor == 0xffff)) &&
374 ((pci_device->subdevice == pci_get_subdevice(dev)) ||
375 (pci_device->subdevice == 0xffff)))
376 return (pci_device);
377 }
378 return (NULL);
379 }
380
381 static int
mrsas_probe(device_t dev)382 mrsas_probe(device_t dev)
383 {
384 static u_int8_t first_ctrl = 1;
385 struct mrsas_ident *id;
386
387 if ((id = mrsas_find_ident(dev)) != NULL) {
388 if (first_ctrl) {
389 printf("AVAGO MegaRAID SAS FreeBSD mrsas driver version: %s\n",
390 MRSAS_VERSION);
391 first_ctrl = 0;
392 }
393 device_set_desc(dev, id->desc);
394 /* between BUS_PROBE_DEFAULT and BUS_PROBE_LOW_PRIORITY */
395 return (-30);
396 }
397 return (ENXIO);
398 }
399
400 /*
401 * mrsas_setup_sysctl: setup sysctl values for mrsas
402 * input: Adapter instance soft state
403 *
404 * Setup sysctl entries for mrsas driver.
405 */
406 static void
mrsas_setup_sysctl(struct mrsas_softc * sc)407 mrsas_setup_sysctl(struct mrsas_softc *sc)
408 {
409 struct sysctl_ctx_list *sysctl_ctx = NULL;
410 struct sysctl_oid *sysctl_tree = NULL;
411 char tmpstr[80], tmpstr2[80];
412
413 /*
414 * Setup the sysctl variable so the user can change the debug level
415 * on the fly.
416 */
417 snprintf(tmpstr, sizeof(tmpstr), "MRSAS controller %d",
418 device_get_unit(sc->mrsas_dev));
419 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mrsas_dev));
420
421 sysctl_ctx = device_get_sysctl_ctx(sc->mrsas_dev);
422 if (sysctl_ctx != NULL)
423 sysctl_tree = device_get_sysctl_tree(sc->mrsas_dev);
424
425 if (sysctl_tree == NULL) {
426 sysctl_ctx_init(&sc->sysctl_ctx);
427 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
428 SYSCTL_STATIC_CHILDREN(_hw_mrsas), OID_AUTO, tmpstr2,
429 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, tmpstr);
430 if (sc->sysctl_tree == NULL)
431 return;
432 sysctl_ctx = &sc->sysctl_ctx;
433 sysctl_tree = sc->sysctl_tree;
434 }
435 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
436 OID_AUTO, "disable_ocr", CTLFLAG_RW, &sc->disableOnlineCtrlReset, 0,
437 "Disable the use of OCR");
438
439 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
440 OID_AUTO, "driver_version", CTLFLAG_RD, MRSAS_VERSION,
441 strlen(MRSAS_VERSION), "driver version");
442
443 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
444 OID_AUTO, "reset_count", CTLFLAG_RD,
445 &sc->reset_count, 0, "number of ocr from start of the day");
446
447 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
448 OID_AUTO, "fw_outstanding", CTLFLAG_RD,
449 &sc->fw_outstanding.val_rdonly, 0, "FW outstanding commands");
450
451 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
452 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD,
453 &sc->io_cmds_highwater, 0, "Max FW outstanding commands");
454
455 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
456 OID_AUTO, "mrsas_debug", CTLFLAG_RW, &sc->mrsas_debug, 0,
457 "Driver debug level");
458
459 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
460 OID_AUTO, "mrsas_io_timeout", CTLFLAG_RW, &sc->mrsas_io_timeout,
461 0, "Driver IO timeout value in mili-second.");
462
463 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
464 OID_AUTO, "mrsas_fw_fault_check_delay", CTLFLAG_RW,
465 &sc->mrsas_fw_fault_check_delay,
466 0, "FW fault check thread delay in seconds. <default is 1 sec>");
467
468 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
469 OID_AUTO, "reset_in_progress", CTLFLAG_RD,
470 &sc->reset_in_progress, 0, "ocr in progress status");
471
472 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
473 OID_AUTO, "block_sync_cache", CTLFLAG_RW,
474 &sc->block_sync_cache, 0,
475 "Block SYNC CACHE at driver. <default: 0, send it to FW>");
476 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
477 OID_AUTO, "stream detection", CTLFLAG_RW,
478 &sc->drv_stream_detection, 0,
479 "Disable/Enable Stream detection. <default: 1, Enable Stream Detection>");
480 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
481 OID_AUTO, "prp_count", CTLFLAG_RD,
482 &sc->prp_count.val_rdonly, 0, "Number of IOs for which PRPs are built");
483 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
484 OID_AUTO, "SGE holes", CTLFLAG_RD,
485 &sc->sge_holes.val_rdonly, 0, "Number of IOs with holes in SGEs");
486 }
487
488 /*
489 * mrsas_get_tunables: get tunable parameters.
490 * input: Adapter instance soft state
491 *
492 * Get tunable parameters. This will help to debug driver at boot time.
493 */
494 static void
mrsas_get_tunables(struct mrsas_softc * sc)495 mrsas_get_tunables(struct mrsas_softc *sc)
496 {
497 char tmpstr[80];
498
499 /* XXX default to some debugging for now */
500 sc->mrsas_debug =
501 (MRSAS_FAULT | MRSAS_OCR | MRSAS_INFO | MRSAS_TRACE | MRSAS_AEN);
502 sc->mrsas_io_timeout = MRSAS_IO_TIMEOUT;
503 sc->mrsas_fw_fault_check_delay = 1;
504 sc->reset_count = 0;
505 sc->reset_in_progress = 0;
506 sc->block_sync_cache = 0;
507 sc->drv_stream_detection = 1;
508
509 /*
510 * Grab the global variables.
511 */
512 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug);
513
514 /*
515 * Grab the global variables.
516 */
517 TUNABLE_INT_FETCH("hw.mrsas.lb_pending_cmds", &sc->lb_pending_cmds);
518
519 /* Grab the unit-instance variables */
520 snprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level",
521 device_get_unit(sc->mrsas_dev));
522 TUNABLE_INT_FETCH(tmpstr, &sc->mrsas_debug);
523 }
524
525 /*
526 * mrsas_alloc_evt_log_info cmd: Allocates memory to get event log information.
527 * Used to get sequence number at driver load time.
528 * input: Adapter soft state
529 *
530 * Allocates DMAable memory for the event log info internal command.
531 */
532 int
mrsas_alloc_evt_log_info_cmd(struct mrsas_softc * sc)533 mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc)
534 {
535 int el_info_size;
536
537 /* Allocate get event log info command */
538 el_info_size = sizeof(struct mrsas_evt_log_info);
539 if (bus_dma_tag_create(sc->mrsas_parent_tag,
540 1, 0,
541 BUS_SPACE_MAXADDR_32BIT,
542 BUS_SPACE_MAXADDR,
543 NULL, NULL,
544 el_info_size,
545 1,
546 el_info_size,
547 BUS_DMA_ALLOCNOW,
548 NULL, NULL,
549 &sc->el_info_tag)) {
550 device_printf(sc->mrsas_dev, "Cannot allocate event log info tag\n");
551 return (ENOMEM);
552 }
553 if (bus_dmamem_alloc(sc->el_info_tag, (void **)&sc->el_info_mem,
554 BUS_DMA_NOWAIT, &sc->el_info_dmamap)) {
555 device_printf(sc->mrsas_dev, "Cannot allocate event log info cmd mem\n");
556 return (ENOMEM);
557 }
558 if (bus_dmamap_load(sc->el_info_tag, sc->el_info_dmamap,
559 sc->el_info_mem, el_info_size, mrsas_addr_cb,
560 &sc->el_info_phys_addr, BUS_DMA_NOWAIT)) {
561 device_printf(sc->mrsas_dev, "Cannot load event log info cmd mem\n");
562 return (ENOMEM);
563 }
564 memset(sc->el_info_mem, 0, el_info_size);
565 return (0);
566 }
567
568 /*
569 * mrsas_free_evt_info_cmd: Free memory for Event log info command
570 * input: Adapter soft state
571 *
572 * Deallocates memory for the event log info internal command.
573 */
574 void
mrsas_free_evt_log_info_cmd(struct mrsas_softc * sc)575 mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc)
576 {
577 if (sc->el_info_phys_addr)
578 bus_dmamap_unload(sc->el_info_tag, sc->el_info_dmamap);
579 if (sc->el_info_mem != NULL)
580 bus_dmamem_free(sc->el_info_tag, sc->el_info_mem, sc->el_info_dmamap);
581 if (sc->el_info_tag != NULL)
582 bus_dma_tag_destroy(sc->el_info_tag);
583 }
584
585 /*
586 * mrsas_get_seq_num: Get latest event sequence number
587 * @sc: Adapter soft state
588 * @eli: Firmware event log sequence number information.
589 *
590 * Firmware maintains a log of all events in a non-volatile area.
591 * Driver get the sequence number using DCMD
592 * "MR_DCMD_CTRL_EVENT_GET_INFO" at driver load time.
593 */
594
595 static int
mrsas_get_seq_num(struct mrsas_softc * sc,struct mrsas_evt_log_info * eli)596 mrsas_get_seq_num(struct mrsas_softc *sc,
597 struct mrsas_evt_log_info *eli)
598 {
599 struct mrsas_mfi_cmd *cmd;
600 struct mrsas_dcmd_frame *dcmd;
601 u_int8_t do_ocr = 1, retcode = 0;
602
603 cmd = mrsas_get_mfi_cmd(sc);
604
605 if (!cmd) {
606 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n");
607 return -ENOMEM;
608 }
609 dcmd = &cmd->frame->dcmd;
610
611 if (mrsas_alloc_evt_log_info_cmd(sc) != SUCCESS) {
612 device_printf(sc->mrsas_dev, "Cannot allocate evt log info cmd\n");
613 mrsas_release_mfi_cmd(cmd);
614 return -ENOMEM;
615 }
616 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
617
618 dcmd->cmd = MFI_CMD_DCMD;
619 dcmd->cmd_status = 0x0;
620 dcmd->sge_count = 1;
621 dcmd->flags = htole16(MFI_FRAME_DIR_READ);
622 dcmd->timeout = 0;
623 dcmd->pad_0 = 0;
624 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_log_info));
625 dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_GET_INFO);
626 dcmd->sgl.sge32[0].phys_addr = htole32(sc->el_info_phys_addr & 0xFFFFFFFF);
627 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_log_info));
628
629 retcode = mrsas_issue_blocked_cmd(sc, cmd);
630 if (retcode == ETIMEDOUT)
631 goto dcmd_timeout;
632
633 do_ocr = 0;
634 /*
635 * Copy the data back into callers buffer
636 */
637 memcpy(eli, sc->el_info_mem, sizeof(struct mrsas_evt_log_info));
638 mrsas_free_evt_log_info_cmd(sc);
639
640 dcmd_timeout:
641 if (do_ocr)
642 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
643 else
644 mrsas_release_mfi_cmd(cmd);
645
646 return retcode;
647 }
648
649 /*
650 * mrsas_register_aen: Register for asynchronous event notification
651 * @sc: Adapter soft state
652 * @seq_num: Starting sequence number
653 * @class_locale: Class of the event
654 *
655 * This function subscribes for events beyond the @seq_num
656 * and type @class_locale.
657 *
658 */
659 static int
mrsas_register_aen(struct mrsas_softc * sc,u_int32_t seq_num,u_int32_t class_locale_word)660 mrsas_register_aen(struct mrsas_softc *sc, u_int32_t seq_num,
661 u_int32_t class_locale_word)
662 {
663 int ret_val;
664 struct mrsas_mfi_cmd *cmd;
665 struct mrsas_dcmd_frame *dcmd;
666 union mrsas_evt_class_locale curr_aen;
667 union mrsas_evt_class_locale prev_aen;
668
669 /*
670 * If there an AEN pending already (aen_cmd), check if the
671 * class_locale of that pending AEN is inclusive of the new AEN
672 * request we currently have. If it is, then we don't have to do
673 * anything. In other words, whichever events the current AEN request
674 * is subscribing to, have already been subscribed to. If the old_cmd
675 * is _not_ inclusive, then we have to abort that command, form a
676 * class_locale that is superset of both old and current and re-issue
677 * to the FW
678 */
679
680 curr_aen.word = class_locale_word;
681
682 if (sc->aen_cmd) {
683 prev_aen.word = le32toh(sc->aen_cmd->frame->dcmd.mbox.w[1]);
684
685 /*
686 * A class whose enum value is smaller is inclusive of all
687 * higher values. If a PROGRESS (= -1) was previously
688 * registered, then a new registration requests for higher
689 * classes need not be sent to FW. They are automatically
690 * included. Locale numbers don't have such hierarchy. They
691 * are bitmap values
692 */
693 if ((prev_aen.members.class <= curr_aen.members.class) &&
694 !((prev_aen.members.locale & curr_aen.members.locale) ^
695 curr_aen.members.locale)) {
696 /*
697 * Previously issued event registration includes
698 * current request. Nothing to do.
699 */
700 return 0;
701 } else {
702 curr_aen.members.locale |= prev_aen.members.locale;
703
704 if (prev_aen.members.class < curr_aen.members.class)
705 curr_aen.members.class = prev_aen.members.class;
706
707 sc->aen_cmd->abort_aen = 1;
708 ret_val = mrsas_issue_blocked_abort_cmd(sc,
709 sc->aen_cmd);
710
711 if (ret_val) {
712 printf("mrsas: Failed to abort previous AEN command\n");
713 return ret_val;
714 } else
715 sc->aen_cmd = NULL;
716 }
717 }
718 cmd = mrsas_get_mfi_cmd(sc);
719 if (!cmd)
720 return ENOMEM;
721
722 dcmd = &cmd->frame->dcmd;
723
724 memset(sc->evt_detail_mem, 0, sizeof(struct mrsas_evt_detail));
725
726 /*
727 * Prepare DCMD for aen registration
728 */
729 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
730
731 dcmd->cmd = MFI_CMD_DCMD;
732 dcmd->cmd_status = 0x0;
733 dcmd->sge_count = 1;
734 dcmd->flags = htole16(MFI_FRAME_DIR_READ);
735 dcmd->timeout = 0;
736 dcmd->pad_0 = 0;
737 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_detail));
738 dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_WAIT);
739 dcmd->mbox.w[0] = htole32(seq_num);
740 sc->last_seq_num = seq_num;
741 dcmd->mbox.w[1] = htole32(curr_aen.word);
742 dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->evt_detail_phys_addr & 0xFFFFFFFF);
743 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_detail));
744
745 if (sc->aen_cmd != NULL) {
746 mrsas_release_mfi_cmd(cmd);
747 return 0;
748 }
749 /*
750 * Store reference to the cmd used to register for AEN. When an
751 * application wants us to register for AEN, we have to abort this
752 * cmd and re-register with a new EVENT LOCALE supplied by that app
753 */
754 sc->aen_cmd = cmd;
755
756 /*
757 * Issue the aen registration frame
758 */
759 if (mrsas_issue_dcmd(sc, cmd)) {
760 device_printf(sc->mrsas_dev, "Cannot issue AEN DCMD command.\n");
761 return (1);
762 }
763 return 0;
764 }
765
766 /*
767 * mrsas_start_aen: Subscribes to AEN during driver load time
768 * @instance: Adapter soft state
769 */
770 static int
mrsas_start_aen(struct mrsas_softc * sc)771 mrsas_start_aen(struct mrsas_softc *sc)
772 {
773 struct mrsas_evt_log_info eli;
774 union mrsas_evt_class_locale class_locale;
775
776 /* Get the latest sequence number from FW */
777
778 memset(&eli, 0, sizeof(eli));
779
780 if (mrsas_get_seq_num(sc, &eli))
781 return -1;
782
783 /* Register AEN with FW for latest sequence number plus 1 */
784 class_locale.members.reserved = 0;
785 class_locale.members.locale = MR_EVT_LOCALE_ALL;
786 class_locale.members.class = MR_EVT_CLASS_DEBUG;
787
788 return mrsas_register_aen(sc, eli.newest_seq_num + 1,
789 class_locale.word);
790
791 }
792
793 /*
794 * mrsas_setup_msix: Allocate MSI-x vectors
795 * @sc: adapter soft state
796 */
797 static int
mrsas_setup_msix(struct mrsas_softc * sc)798 mrsas_setup_msix(struct mrsas_softc *sc)
799 {
800 int i;
801
802 for (i = 0; i < sc->msix_vectors; i++) {
803 sc->irq_context[i].sc = sc;
804 sc->irq_context[i].MSIxIndex = i;
805 sc->irq_id[i] = i + 1;
806 sc->mrsas_irq[i] = bus_alloc_resource_any
807 (sc->mrsas_dev, SYS_RES_IRQ, &sc->irq_id[i]
808 ,RF_ACTIVE);
809 if (sc->mrsas_irq[i] == NULL) {
810 device_printf(sc->mrsas_dev, "Can't allocate MSI-x\n");
811 goto irq_alloc_failed;
812 }
813 if (bus_setup_intr(sc->mrsas_dev,
814 sc->mrsas_irq[i],
815 INTR_MPSAFE | INTR_TYPE_CAM,
816 NULL, mrsas_isr, &sc->irq_context[i],
817 &sc->intr_handle[i])) {
818 device_printf(sc->mrsas_dev,
819 "Cannot set up MSI-x interrupt handler\n");
820 goto irq_alloc_failed;
821 }
822 }
823 return SUCCESS;
824
825 irq_alloc_failed:
826 mrsas_teardown_intr(sc);
827 return (FAIL);
828 }
829
830 /*
831 * mrsas_allocate_msix: Setup MSI-x vectors
832 * @sc: adapter soft state
833 */
834 static int
mrsas_allocate_msix(struct mrsas_softc * sc)835 mrsas_allocate_msix(struct mrsas_softc *sc)
836 {
837 if (pci_alloc_msix(sc->mrsas_dev, &sc->msix_vectors) == 0) {
838 device_printf(sc->mrsas_dev, "Using MSI-X with %d number"
839 " of vectors\n", sc->msix_vectors);
840 } else {
841 device_printf(sc->mrsas_dev, "MSI-x setup failed\n");
842 goto irq_alloc_failed;
843 }
844 return SUCCESS;
845
846 irq_alloc_failed:
847 mrsas_teardown_intr(sc);
848 return (FAIL);
849 }
850
851 /*
852 * mrsas_attach: PCI entry point
853 * input: pointer to device struct
854 *
855 * Performs setup of PCI and registers, initializes mutexes and linked lists,
856 * registers interrupts and CAM, and initializes the adapter/controller to
857 * its proper state.
858 */
859 static int
mrsas_attach(device_t dev)860 mrsas_attach(device_t dev)
861 {
862 struct mrsas_softc *sc = device_get_softc(dev);
863 uint32_t cmd, error;
864
865 memset(sc, 0, sizeof(struct mrsas_softc));
866
867 /* Look up our softc and initialize its fields. */
868 sc->mrsas_dev = dev;
869 sc->device_id = pci_get_device(dev);
870
871 switch (sc->device_id) {
872 case MRSAS_INVADER:
873 case MRSAS_FURY:
874 case MRSAS_INTRUDER:
875 case MRSAS_INTRUDER_24:
876 case MRSAS_CUTLASS_52:
877 case MRSAS_CUTLASS_53:
878 sc->mrsas_gen3_ctrl = 1;
879 break;
880 case MRSAS_VENTURA:
881 case MRSAS_CRUSADER:
882 case MRSAS_HARPOON:
883 case MRSAS_TOMCAT:
884 case MRSAS_VENTURA_4PORT:
885 case MRSAS_CRUSADER_4PORT:
886 sc->is_ventura = true;
887 break;
888 case MRSAS_AERO_10E1:
889 case MRSAS_AERO_10E5:
890 device_printf(dev, "Adapter is in configurable secure mode\n");
891 case MRSAS_AERO_10E2:
892 case MRSAS_AERO_10E6:
893 sc->is_aero = true;
894 break;
895 case MRSAS_AERO_10E0:
896 case MRSAS_AERO_10E3:
897 case MRSAS_AERO_10E4:
898 case MRSAS_AERO_10E7:
899 device_printf(dev, "Adapter is in non-secure mode\n");
900 return SUCCESS;
901 }
902
903 mrsas_get_tunables(sc);
904
905 /*
906 * Set up PCI and registers
907 */
908 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
909 /* Force the busmaster enable bit on. */
910 cmd |= PCIM_CMD_BUSMASTEREN;
911 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
912
913 /* For Ventura/Aero system registers are mapped to BAR0 */
914 if (sc->is_ventura || sc->is_aero)
915 sc->reg_res_id = PCIR_BAR(0); /* BAR0 offset */
916 else
917 sc->reg_res_id = PCIR_BAR(1); /* BAR1 offset */
918
919 if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
920 &(sc->reg_res_id), RF_ACTIVE))
921 == NULL) {
922 device_printf(dev, "Cannot allocate PCI registers\n");
923 goto attach_fail;
924 }
925 sc->bus_tag = rman_get_bustag(sc->reg_res);
926 sc->bus_handle = rman_get_bushandle(sc->reg_res);
927
928 /* Intialize mutexes */
929 mtx_init(&sc->sim_lock, "mrsas_sim_lock", NULL, MTX_DEF);
930 mtx_init(&sc->pci_lock, "mrsas_pci_lock", NULL, MTX_DEF);
931 mtx_init(&sc->io_lock, "mrsas_io_lock", NULL, MTX_DEF);
932 mtx_init(&sc->aen_lock, "mrsas_aen_lock", NULL, MTX_DEF);
933 mtx_init(&sc->ioctl_lock, "mrsas_ioctl_lock", NULL, MTX_SPIN);
934 mtx_init(&sc->mpt_cmd_pool_lock, "mrsas_mpt_cmd_pool_lock", NULL, MTX_DEF);
935 mtx_init(&sc->mfi_cmd_pool_lock, "mrsas_mfi_cmd_pool_lock", NULL, MTX_DEF);
936 mtx_init(&sc->raidmap_lock, "mrsas_raidmap_lock", NULL, MTX_DEF);
937 mtx_init(&sc->stream_lock, "mrsas_stream_lock", NULL, MTX_DEF);
938
939 /* Intialize linked list */
940 TAILQ_INIT(&sc->mrsas_mpt_cmd_list_head);
941 TAILQ_INIT(&sc->mrsas_mfi_cmd_list_head);
942
943 mrsas_atomic_set(&sc->fw_outstanding, 0);
944 mrsas_atomic_set(&sc->target_reset_outstanding, 0);
945 mrsas_atomic_set(&sc->prp_count, 0);
946 mrsas_atomic_set(&sc->sge_holes, 0);
947
948 sc->io_cmds_highwater = 0;
949
950 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
951 sc->UnevenSpanSupport = 0;
952
953 sc->msix_enable = 0;
954
955 /* Initialize Firmware */
956 if (mrsas_init_fw(sc) != SUCCESS) {
957 goto attach_fail_fw;
958 }
959 /* Register mrsas to CAM layer */
960 if ((mrsas_cam_attach(sc) != SUCCESS)) {
961 goto attach_fail_cam;
962 }
963 /* Register IRQs */
964 if (mrsas_setup_irq(sc) != SUCCESS) {
965 goto attach_fail_irq;
966 }
967 error = mrsas_kproc_create(mrsas_ocr_thread, sc,
968 &sc->ocr_thread, 0, 0, "mrsas_ocr%d",
969 device_get_unit(sc->mrsas_dev));
970 if (error) {
971 device_printf(sc->mrsas_dev, "Error %d starting OCR thread\n", error);
972 goto attach_fail_ocr_thread;
973 }
974 /*
975 * After FW initialization and OCR thread creation
976 * we will defer the cdev creation, AEN setup on ICH callback
977 */
978 sc->mrsas_ich.ich_func = mrsas_ich_startup;
979 sc->mrsas_ich.ich_arg = sc;
980 if (config_intrhook_establish(&sc->mrsas_ich) != 0) {
981 device_printf(sc->mrsas_dev, "Config hook is already established\n");
982 }
983 mrsas_setup_sysctl(sc);
984 return SUCCESS;
985
986 attach_fail_ocr_thread:
987 if (sc->ocr_thread_active)
988 wakeup(&sc->ocr_chan);
989 attach_fail_irq:
990 mrsas_teardown_intr(sc);
991 attach_fail_cam:
992 mrsas_cam_detach(sc);
993 attach_fail_fw:
994 /* if MSIX vector is allocated and FW Init FAILED then release MSIX */
995 if (sc->msix_enable == 1)
996 pci_release_msi(sc->mrsas_dev);
997 mrsas_free_mem(sc);
998 mtx_destroy(&sc->sim_lock);
999 mtx_destroy(&sc->aen_lock);
1000 mtx_destroy(&sc->pci_lock);
1001 mtx_destroy(&sc->io_lock);
1002 mtx_destroy(&sc->ioctl_lock);
1003 mtx_destroy(&sc->mpt_cmd_pool_lock);
1004 mtx_destroy(&sc->mfi_cmd_pool_lock);
1005 mtx_destroy(&sc->raidmap_lock);
1006 mtx_destroy(&sc->stream_lock);
1007 attach_fail:
1008 if (sc->reg_res) {
1009 bus_release_resource(sc->mrsas_dev, SYS_RES_MEMORY,
1010 sc->reg_res_id, sc->reg_res);
1011 }
1012 return (ENXIO);
1013 }
1014
1015 /*
1016 * Interrupt config hook
1017 */
1018 static void
mrsas_ich_startup(void * arg)1019 mrsas_ich_startup(void *arg)
1020 {
1021 int i = 0;
1022 struct mrsas_softc *sc = (struct mrsas_softc *)arg;
1023
1024 /*
1025 * Intialize a counting Semaphore to take care no. of concurrent IOCTLs
1026 */
1027 sema_init(&sc->ioctl_count_sema, MRSAS_MAX_IOCTL_CMDS,
1028 IOCTL_SEMA_DESCRIPTION);
1029
1030 /* Create a /dev entry for mrsas controller. */
1031 sc->mrsas_cdev = make_dev(&mrsas_cdevsw, device_get_unit(sc->mrsas_dev), UID_ROOT,
1032 GID_OPERATOR, (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP), "mrsas%u",
1033 device_get_unit(sc->mrsas_dev));
1034
1035 if (device_get_unit(sc->mrsas_dev) == 0) {
1036 make_dev_alias_p(MAKEDEV_CHECKNAME,
1037 &sc->mrsas_linux_emulator_cdev, sc->mrsas_cdev,
1038 "megaraid_sas_ioctl_node");
1039 }
1040 if (sc->mrsas_cdev)
1041 sc->mrsas_cdev->si_drv1 = sc;
1042
1043 /*
1044 * Add this controller to mrsas_mgmt_info structure so that it can be
1045 * exported to management applications
1046 */
1047 if (device_get_unit(sc->mrsas_dev) == 0)
1048 memset(&mrsas_mgmt_info, 0, sizeof(mrsas_mgmt_info));
1049
1050 mrsas_mgmt_info.count++;
1051 mrsas_mgmt_info.sc_ptr[mrsas_mgmt_info.max_index] = sc;
1052 mrsas_mgmt_info.max_index++;
1053
1054 /* Enable Interrupts */
1055 mrsas_enable_intr(sc);
1056
1057 /* Call DCMD get_pd_info for all system PDs */
1058 for (i = 0; i < MRSAS_MAX_PD; i++) {
1059 if ((sc->target_list[i].target_id != 0xffff) &&
1060 sc->pd_info_mem)
1061 mrsas_get_pd_info(sc, sc->target_list[i].target_id);
1062 }
1063
1064 /* Initiate AEN (Asynchronous Event Notification) */
1065 if (mrsas_start_aen(sc)) {
1066 device_printf(sc->mrsas_dev, "Error: AEN registration FAILED !!! "
1067 "Further events from the controller will not be communicated.\n"
1068 "Either there is some problem in the controller"
1069 "or the controller does not support AEN.\n"
1070 "Please contact to the SUPPORT TEAM if the problem persists\n");
1071 }
1072 if (sc->mrsas_ich.ich_arg != NULL) {
1073 device_printf(sc->mrsas_dev, "Disestablish mrsas intr hook\n");
1074 config_intrhook_disestablish(&sc->mrsas_ich);
1075 sc->mrsas_ich.ich_arg = NULL;
1076 }
1077 }
1078
1079 /*
1080 * mrsas_detach: De-allocates and teardown resources
1081 * input: pointer to device struct
1082 *
1083 * This function is the entry point for device disconnect and detach.
1084 * It performs memory de-allocations, shutdown of the controller and various
1085 * teardown and destroy resource functions.
1086 */
1087 static int
mrsas_detach(device_t dev)1088 mrsas_detach(device_t dev)
1089 {
1090 struct mrsas_softc *sc;
1091 int i = 0;
1092
1093 sc = device_get_softc(dev);
1094 sc->remove_in_progress = 1;
1095
1096 /* Destroy the character device so no other IOCTL will be handled */
1097 if ((device_get_unit(dev) == 0) && sc->mrsas_linux_emulator_cdev)
1098 destroy_dev(sc->mrsas_linux_emulator_cdev);
1099 destroy_dev(sc->mrsas_cdev);
1100
1101 /*
1102 * Take the instance off the instance array. Note that we will not
1103 * decrement the max_index. We let this array be sparse array
1104 */
1105 for (i = 0; i < mrsas_mgmt_info.max_index; i++) {
1106 if (mrsas_mgmt_info.sc_ptr[i] == sc) {
1107 mrsas_mgmt_info.count--;
1108 mrsas_mgmt_info.sc_ptr[i] = NULL;
1109 break;
1110 }
1111 }
1112
1113 if (sc->ocr_thread_active)
1114 wakeup(&sc->ocr_chan);
1115 while (sc->reset_in_progress) {
1116 i++;
1117 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) {
1118 mrsas_dprint(sc, MRSAS_INFO,
1119 "[%2d]waiting for OCR to be finished from %s\n", i, __func__);
1120 }
1121 pause("mr_shutdown", hz);
1122 }
1123 i = 0;
1124 while (sc->ocr_thread_active) {
1125 i++;
1126 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) {
1127 mrsas_dprint(sc, MRSAS_INFO,
1128 "[%2d]waiting for "
1129 "mrsas_ocr thread to quit ocr %d\n", i,
1130 sc->ocr_thread_active);
1131 }
1132 pause("mr_shutdown", hz);
1133 }
1134 mrsas_flush_cache(sc);
1135 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN);
1136 mrsas_disable_intr(sc);
1137
1138 if ((sc->is_ventura || sc->is_aero) && sc->streamDetectByLD) {
1139 for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i)
1140 free(sc->streamDetectByLD[i], M_MRSAS);
1141 free(sc->streamDetectByLD, M_MRSAS);
1142 sc->streamDetectByLD = NULL;
1143 }
1144
1145 mrsas_cam_detach(sc);
1146 mrsas_teardown_intr(sc);
1147 mrsas_free_mem(sc);
1148 mtx_destroy(&sc->sim_lock);
1149 mtx_destroy(&sc->aen_lock);
1150 mtx_destroy(&sc->pci_lock);
1151 mtx_destroy(&sc->io_lock);
1152 mtx_destroy(&sc->ioctl_lock);
1153 mtx_destroy(&sc->mpt_cmd_pool_lock);
1154 mtx_destroy(&sc->mfi_cmd_pool_lock);
1155 mtx_destroy(&sc->raidmap_lock);
1156 mtx_destroy(&sc->stream_lock);
1157
1158 /* Wait for all the semaphores to be released */
1159 while (sema_value(&sc->ioctl_count_sema) != MRSAS_MAX_IOCTL_CMDS)
1160 pause("mr_shutdown", hz);
1161
1162 /* Destroy the counting semaphore created for Ioctl */
1163 sema_destroy(&sc->ioctl_count_sema);
1164
1165 if (sc->reg_res) {
1166 bus_release_resource(sc->mrsas_dev,
1167 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res);
1168 }
1169 if (sc->sysctl_tree != NULL)
1170 sysctl_ctx_free(&sc->sysctl_ctx);
1171
1172 return (0);
1173 }
1174
1175 static int
mrsas_shutdown(device_t dev)1176 mrsas_shutdown(device_t dev)
1177 {
1178 struct mrsas_softc *sc;
1179 int i;
1180
1181 sc = device_get_softc(dev);
1182 sc->remove_in_progress = 1;
1183 if (!KERNEL_PANICKED()) {
1184 if (sc->ocr_thread_active)
1185 wakeup(&sc->ocr_chan);
1186 i = 0;
1187 while (sc->reset_in_progress && i < 15) {
1188 i++;
1189 if ((i % MRSAS_RESET_NOTICE_INTERVAL) == 0) {
1190 mrsas_dprint(sc, MRSAS_INFO,
1191 "[%2d]waiting for OCR to be finished "
1192 "from %s\n", i, __func__);
1193 }
1194 pause("mr_shutdown", hz);
1195 }
1196 if (sc->reset_in_progress) {
1197 mrsas_dprint(sc, MRSAS_INFO,
1198 "gave up waiting for OCR to be finished\n");
1199 return (0);
1200 }
1201 }
1202
1203 mrsas_flush_cache(sc);
1204 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN);
1205 mrsas_disable_intr(sc);
1206 return (0);
1207 }
1208
1209 /*
1210 * mrsas_free_mem: Frees allocated memory
1211 * input: Adapter instance soft state
1212 *
1213 * This function is called from mrsas_detach() to free previously allocated
1214 * memory.
1215 */
1216 void
mrsas_free_mem(struct mrsas_softc * sc)1217 mrsas_free_mem(struct mrsas_softc *sc)
1218 {
1219 int i;
1220 u_int32_t max_fw_cmds;
1221 struct mrsas_mfi_cmd *mfi_cmd;
1222 struct mrsas_mpt_cmd *mpt_cmd;
1223
1224 /*
1225 * Free RAID map memory
1226 */
1227 for (i = 0; i < 2; i++) {
1228 if (sc->raidmap_phys_addr[i])
1229 bus_dmamap_unload(sc->raidmap_tag[i], sc->raidmap_dmamap[i]);
1230 if (sc->raidmap_mem[i] != NULL)
1231 bus_dmamem_free(sc->raidmap_tag[i], sc->raidmap_mem[i], sc->raidmap_dmamap[i]);
1232 if (sc->raidmap_tag[i] != NULL)
1233 bus_dma_tag_destroy(sc->raidmap_tag[i]);
1234
1235 if (sc->ld_drv_map[i] != NULL)
1236 free(sc->ld_drv_map[i], M_MRSAS);
1237 }
1238 for (i = 0; i < 2; i++) {
1239 if (sc->jbodmap_phys_addr[i])
1240 bus_dmamap_unload(sc->jbodmap_tag[i], sc->jbodmap_dmamap[i]);
1241 if (sc->jbodmap_mem[i] != NULL)
1242 bus_dmamem_free(sc->jbodmap_tag[i], sc->jbodmap_mem[i], sc->jbodmap_dmamap[i]);
1243 if (sc->jbodmap_tag[i] != NULL)
1244 bus_dma_tag_destroy(sc->jbodmap_tag[i]);
1245 }
1246 /*
1247 * Free version buffer memory
1248 */
1249 if (sc->verbuf_phys_addr)
1250 bus_dmamap_unload(sc->verbuf_tag, sc->verbuf_dmamap);
1251 if (sc->verbuf_mem != NULL)
1252 bus_dmamem_free(sc->verbuf_tag, sc->verbuf_mem, sc->verbuf_dmamap);
1253 if (sc->verbuf_tag != NULL)
1254 bus_dma_tag_destroy(sc->verbuf_tag);
1255
1256 /*
1257 * Free sense buffer memory
1258 */
1259 if (sc->sense_phys_addr)
1260 bus_dmamap_unload(sc->sense_tag, sc->sense_dmamap);
1261 if (sc->sense_mem != NULL)
1262 bus_dmamem_free(sc->sense_tag, sc->sense_mem, sc->sense_dmamap);
1263 if (sc->sense_tag != NULL)
1264 bus_dma_tag_destroy(sc->sense_tag);
1265
1266 /*
1267 * Free chain frame memory
1268 */
1269 if (sc->chain_frame_phys_addr)
1270 bus_dmamap_unload(sc->chain_frame_tag, sc->chain_frame_dmamap);
1271 if (sc->chain_frame_mem != NULL)
1272 bus_dmamem_free(sc->chain_frame_tag, sc->chain_frame_mem, sc->chain_frame_dmamap);
1273 if (sc->chain_frame_tag != NULL)
1274 bus_dma_tag_destroy(sc->chain_frame_tag);
1275
1276 /*
1277 * Free IO Request memory
1278 */
1279 if (sc->io_request_phys_addr)
1280 bus_dmamap_unload(sc->io_request_tag, sc->io_request_dmamap);
1281 if (sc->io_request_mem != NULL)
1282 bus_dmamem_free(sc->io_request_tag, sc->io_request_mem, sc->io_request_dmamap);
1283 if (sc->io_request_tag != NULL)
1284 bus_dma_tag_destroy(sc->io_request_tag);
1285
1286 /*
1287 * Free Reply Descriptor memory
1288 */
1289 if (sc->reply_desc_phys_addr)
1290 bus_dmamap_unload(sc->reply_desc_tag, sc->reply_desc_dmamap);
1291 if (sc->reply_desc_mem != NULL)
1292 bus_dmamem_free(sc->reply_desc_tag, sc->reply_desc_mem, sc->reply_desc_dmamap);
1293 if (sc->reply_desc_tag != NULL)
1294 bus_dma_tag_destroy(sc->reply_desc_tag);
1295
1296 /*
1297 * Free event detail memory
1298 */
1299 if (sc->evt_detail_phys_addr)
1300 bus_dmamap_unload(sc->evt_detail_tag, sc->evt_detail_dmamap);
1301 if (sc->evt_detail_mem != NULL)
1302 bus_dmamem_free(sc->evt_detail_tag, sc->evt_detail_mem, sc->evt_detail_dmamap);
1303 if (sc->evt_detail_tag != NULL)
1304 bus_dma_tag_destroy(sc->evt_detail_tag);
1305
1306 /*
1307 * Free PD info memory
1308 */
1309 if (sc->pd_info_phys_addr)
1310 bus_dmamap_unload(sc->pd_info_tag, sc->pd_info_dmamap);
1311 if (sc->pd_info_mem != NULL)
1312 bus_dmamem_free(sc->pd_info_tag, sc->pd_info_mem, sc->pd_info_dmamap);
1313 if (sc->pd_info_tag != NULL)
1314 bus_dma_tag_destroy(sc->pd_info_tag);
1315
1316 /*
1317 * Free MFI frames
1318 */
1319 if (sc->mfi_cmd_list) {
1320 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) {
1321 mfi_cmd = sc->mfi_cmd_list[i];
1322 mrsas_free_frame(sc, mfi_cmd);
1323 }
1324 }
1325 if (sc->mficmd_frame_tag != NULL)
1326 bus_dma_tag_destroy(sc->mficmd_frame_tag);
1327
1328 /*
1329 * Free MPT internal command list
1330 */
1331 max_fw_cmds = sc->max_fw_cmds;
1332 if (sc->mpt_cmd_list) {
1333 for (i = 0; i < max_fw_cmds; i++) {
1334 mpt_cmd = sc->mpt_cmd_list[i];
1335 bus_dmamap_destroy(sc->data_tag, mpt_cmd->data_dmamap);
1336 free(sc->mpt_cmd_list[i], M_MRSAS);
1337 }
1338 free(sc->mpt_cmd_list, M_MRSAS);
1339 sc->mpt_cmd_list = NULL;
1340 }
1341 /*
1342 * Free MFI internal command list
1343 */
1344
1345 if (sc->mfi_cmd_list) {
1346 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) {
1347 free(sc->mfi_cmd_list[i], M_MRSAS);
1348 }
1349 free(sc->mfi_cmd_list, M_MRSAS);
1350 sc->mfi_cmd_list = NULL;
1351 }
1352 /*
1353 * Free request descriptor memory
1354 */
1355 free(sc->req_desc, M_MRSAS);
1356 sc->req_desc = NULL;
1357
1358 /*
1359 * Destroy parent tag
1360 */
1361 if (sc->mrsas_parent_tag != NULL)
1362 bus_dma_tag_destroy(sc->mrsas_parent_tag);
1363
1364 /*
1365 * Free ctrl_info memory
1366 */
1367 if (sc->ctrl_info != NULL)
1368 free(sc->ctrl_info, M_MRSAS);
1369 }
1370
1371 /*
1372 * mrsas_teardown_intr: Teardown interrupt
1373 * input: Adapter instance soft state
1374 *
1375 * This function is called from mrsas_detach() to teardown and release bus
1376 * interrupt resourse.
1377 */
1378 void
mrsas_teardown_intr(struct mrsas_softc * sc)1379 mrsas_teardown_intr(struct mrsas_softc *sc)
1380 {
1381 int i;
1382
1383 if (!sc->msix_enable) {
1384 if (sc->intr_handle[0])
1385 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq[0], sc->intr_handle[0]);
1386 if (sc->mrsas_irq[0] != NULL)
1387 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ,
1388 sc->irq_id[0], sc->mrsas_irq[0]);
1389 sc->intr_handle[0] = NULL;
1390 } else {
1391 for (i = 0; i < sc->msix_vectors; i++) {
1392 if (sc->intr_handle[i])
1393 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq[i],
1394 sc->intr_handle[i]);
1395
1396 if (sc->mrsas_irq[i] != NULL)
1397 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ,
1398 sc->irq_id[i], sc->mrsas_irq[i]);
1399
1400 sc->intr_handle[i] = NULL;
1401 }
1402 pci_release_msi(sc->mrsas_dev);
1403 }
1404
1405 }
1406
1407 /*
1408 * mrsas_suspend: Suspend entry point
1409 * input: Device struct pointer
1410 *
1411 * This function is the entry point for system suspend from the OS.
1412 */
1413 static int
mrsas_suspend(device_t dev)1414 mrsas_suspend(device_t dev)
1415 {
1416 /* This will be filled when the driver will have hibernation support */
1417 return (0);
1418 }
1419
1420 /*
1421 * mrsas_resume: Resume entry point
1422 * input: Device struct pointer
1423 *
1424 * This function is the entry point for system resume from the OS.
1425 */
1426 static int
mrsas_resume(device_t dev)1427 mrsas_resume(device_t dev)
1428 {
1429 /* This will be filled when the driver will have hibernation support */
1430 return (0);
1431 }
1432
1433 /**
1434 * mrsas_get_softc_instance: Find softc instance based on cmd type
1435 *
1436 * This function will return softc instance based on cmd type.
1437 * In some case, application fire ioctl on required management instance and
1438 * do not provide host_no. Use cdev->si_drv1 to get softc instance for those
1439 * case, else get the softc instance from host_no provided by application in
1440 * user data.
1441 */
1442
1443 static struct mrsas_softc *
mrsas_get_softc_instance(struct cdev * dev,u_long cmd,caddr_t arg)1444 mrsas_get_softc_instance(struct cdev *dev, u_long cmd, caddr_t arg)
1445 {
1446 struct mrsas_softc *sc = NULL;
1447 struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
1448
1449 if (cmd == MRSAS_IOC_GET_PCI_INFO) {
1450 sc = dev->si_drv1;
1451 } else {
1452 /*
1453 * get the Host number & the softc from data sent by the
1454 * Application
1455 */
1456 sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
1457 if (sc == NULL)
1458 printf("There is no Controller number %d\n",
1459 user_ioc->host_no);
1460 else if (user_ioc->host_no >= mrsas_mgmt_info.max_index)
1461 mrsas_dprint(sc, MRSAS_FAULT,
1462 "Invalid Controller number %d\n", user_ioc->host_no);
1463 }
1464
1465 return sc;
1466 }
1467
1468 /*
1469 * mrsas_ioctl: IOCtl commands entry point.
1470 *
1471 * This function is the entry point for IOCtls from the OS. It calls the
1472 * appropriate function for processing depending on the command received.
1473 */
1474 static int
mrsas_ioctl(struct cdev * dev,u_long cmd,caddr_t arg,int flag,struct thread * td)1475 mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag,
1476 struct thread *td)
1477 {
1478 struct mrsas_softc *sc;
1479 int ret = 0, i = 0;
1480 MRSAS_DRV_PCI_INFORMATION *pciDrvInfo;
1481
1482 sc = mrsas_get_softc_instance(dev, cmd, arg);
1483 if (!sc)
1484 return ENOENT;
1485
1486 if (sc->remove_in_progress ||
1487 (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)) {
1488 mrsas_dprint(sc, MRSAS_INFO,
1489 "Either driver remove or shutdown called or "
1490 "HW is in unrecoverable critical error state.\n");
1491 return ENOENT;
1492 }
1493 mtx_lock_spin(&sc->ioctl_lock);
1494 if (!sc->reset_in_progress) {
1495 mtx_unlock_spin(&sc->ioctl_lock);
1496 goto do_ioctl;
1497 }
1498 mtx_unlock_spin(&sc->ioctl_lock);
1499 while (sc->reset_in_progress) {
1500 i++;
1501 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) {
1502 mrsas_dprint(sc, MRSAS_INFO,
1503 "[%2d]waiting for OCR to be finished from %s\n", i, __func__);
1504 }
1505 pause("mr_ioctl", hz);
1506 }
1507
1508 do_ioctl:
1509 switch (cmd) {
1510 case MRSAS_IOC_FIRMWARE_PASS_THROUGH64:
1511 #ifdef COMPAT_FREEBSD32
1512 case MRSAS_IOC_FIRMWARE_PASS_THROUGH32:
1513 #endif
1514 /*
1515 * Decrement the Ioctl counting Semaphore before getting an
1516 * mfi command
1517 */
1518 sema_wait(&sc->ioctl_count_sema);
1519
1520 ret = mrsas_passthru(sc, (void *)arg, cmd);
1521
1522 /* Increment the Ioctl counting semaphore value */
1523 sema_post(&sc->ioctl_count_sema);
1524
1525 break;
1526 case MRSAS_IOC_SCAN_BUS:
1527 ret = mrsas_bus_scan(sc);
1528 break;
1529
1530 case MRSAS_IOC_GET_PCI_INFO:
1531 pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *) arg;
1532 memset(pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION));
1533 pciDrvInfo->busNumber = pci_get_bus(sc->mrsas_dev);
1534 pciDrvInfo->deviceNumber = pci_get_slot(sc->mrsas_dev);
1535 pciDrvInfo->functionNumber = pci_get_function(sc->mrsas_dev);
1536 pciDrvInfo->domainID = pci_get_domain(sc->mrsas_dev);
1537 mrsas_dprint(sc, MRSAS_INFO, "pci bus no: %d,"
1538 "pci device no: %d, pci function no: %d,"
1539 "pci domain ID: %d\n",
1540 pciDrvInfo->busNumber, pciDrvInfo->deviceNumber,
1541 pciDrvInfo->functionNumber, pciDrvInfo->domainID);
1542 ret = 0;
1543 break;
1544
1545 default:
1546 mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd);
1547 ret = ENOENT;
1548 }
1549
1550 return (ret);
1551 }
1552
1553 /*
1554 * mrsas_poll: poll entry point for mrsas driver fd
1555 *
1556 * This function is the entry point for poll from the OS. It waits for some AEN
1557 * events to be triggered from the controller and notifies back.
1558 */
1559 static int
mrsas_poll(struct cdev * dev,int poll_events,struct thread * td)1560 mrsas_poll(struct cdev *dev, int poll_events, struct thread *td)
1561 {
1562 struct mrsas_softc *sc;
1563 int revents = 0;
1564
1565 sc = dev->si_drv1;
1566
1567 if (poll_events & (POLLIN | POLLRDNORM)) {
1568 if (sc->mrsas_aen_triggered) {
1569 revents |= poll_events & (POLLIN | POLLRDNORM);
1570 }
1571 }
1572 if (revents == 0) {
1573 if (poll_events & (POLLIN | POLLRDNORM)) {
1574 mtx_lock(&sc->aen_lock);
1575 sc->mrsas_poll_waiting = 1;
1576 selrecord(td, &sc->mrsas_select);
1577 mtx_unlock(&sc->aen_lock);
1578 }
1579 }
1580 return revents;
1581 }
1582
1583 /*
1584 * mrsas_setup_irq: Set up interrupt
1585 * input: Adapter instance soft state
1586 *
1587 * This function sets up interrupts as a bus resource, with flags indicating
1588 * resource permitting contemporaneous sharing and for resource to activate
1589 * atomically.
1590 */
1591 static int
mrsas_setup_irq(struct mrsas_softc * sc)1592 mrsas_setup_irq(struct mrsas_softc *sc)
1593 {
1594 if (sc->msix_enable && (mrsas_setup_msix(sc) == SUCCESS))
1595 device_printf(sc->mrsas_dev, "MSI-x interrupts setup success\n");
1596
1597 else {
1598 device_printf(sc->mrsas_dev, "Fall back to legacy interrupt\n");
1599 sc->irq_context[0].sc = sc;
1600 sc->irq_context[0].MSIxIndex = 0;
1601 sc->irq_id[0] = 0;
1602 sc->mrsas_irq[0] = bus_alloc_resource_any(sc->mrsas_dev,
1603 SYS_RES_IRQ, &sc->irq_id[0], RF_SHAREABLE | RF_ACTIVE);
1604 if (sc->mrsas_irq[0] == NULL) {
1605 device_printf(sc->mrsas_dev, "Cannot allocate legcay"
1606 "interrupt\n");
1607 return (FAIL);
1608 }
1609 if (bus_setup_intr(sc->mrsas_dev, sc->mrsas_irq[0],
1610 INTR_MPSAFE | INTR_TYPE_CAM, NULL, mrsas_isr,
1611 &sc->irq_context[0], &sc->intr_handle[0])) {
1612 device_printf(sc->mrsas_dev, "Cannot set up legacy"
1613 "interrupt\n");
1614 return (FAIL);
1615 }
1616 }
1617 return (0);
1618 }
1619
1620 /*
1621 * mrsas_isr: ISR entry point
1622 * input: argument pointer
1623 *
1624 * This function is the interrupt service routine entry point. There are two
1625 * types of interrupts, state change interrupt and response interrupt. If an
1626 * interrupt is not ours, we just return.
1627 */
1628 void
mrsas_isr(void * arg)1629 mrsas_isr(void *arg)
1630 {
1631 struct mrsas_irq_context *irq_context = (struct mrsas_irq_context *)arg;
1632 struct mrsas_softc *sc = irq_context->sc;
1633 int status = 0;
1634
1635 if (sc->mask_interrupts)
1636 return;
1637
1638 if (!sc->msix_vectors) {
1639 status = mrsas_clear_intr(sc);
1640 if (!status)
1641 return;
1642 }
1643 /* If we are resetting, bail */
1644 if (mrsas_test_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags)) {
1645 printf(" Entered into ISR when OCR is going active. \n");
1646 mrsas_clear_intr(sc);
1647 return;
1648 }
1649 /* Process for reply request and clear response interrupt */
1650 if (mrsas_complete_cmd(sc, irq_context->MSIxIndex) != SUCCESS)
1651 mrsas_clear_intr(sc);
1652
1653 return;
1654 }
1655
1656 /*
1657 * mrsas_complete_cmd: Process reply request
1658 * input: Adapter instance soft state
1659 *
1660 * This function is called from mrsas_isr() to process reply request and clear
1661 * response interrupt. Processing of the reply request entails walking
1662 * through the reply descriptor array for the command request pended from
1663 * Firmware. We look at the Function field to determine the command type and
1664 * perform the appropriate action. Before we return, we clear the response
1665 * interrupt.
1666 */
1667 int
mrsas_complete_cmd(struct mrsas_softc * sc,u_int32_t MSIxIndex)1668 mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex)
1669 {
1670 Mpi2ReplyDescriptorsUnion_t *desc;
1671 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc;
1672 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req;
1673 struct mrsas_mpt_cmd *cmd_mpt, *r1_cmd = NULL;
1674 struct mrsas_mfi_cmd *cmd_mfi;
1675 u_int8_t reply_descript_type, *sense;
1676 u_int16_t smid, num_completed;
1677 u_int8_t status, extStatus;
1678 union desc_value desc_val;
1679 PLD_LOAD_BALANCE_INFO lbinfo;
1680 u_int32_t device_id, data_length;
1681 int threshold_reply_count = 0;
1682 #if TM_DEBUG
1683 MR_TASK_MANAGE_REQUEST *mr_tm_req;
1684 MPI2_SCSI_TASK_MANAGE_REQUEST *mpi_tm_req;
1685 #endif
1686
1687 /* If we have a hardware error, not need to continue */
1688 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)
1689 return (DONE);
1690
1691 desc = sc->reply_desc_mem;
1692 desc += ((MSIxIndex * sc->reply_alloc_sz) / sizeof(MPI2_REPLY_DESCRIPTORS_UNION))
1693 + sc->last_reply_idx[MSIxIndex];
1694
1695 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *) desc;
1696
1697 desc_val.word = desc->Words;
1698 num_completed = 0;
1699
1700 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1701
1702 /* Find our reply descriptor for the command and process */
1703 while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) {
1704 smid = le16toh(reply_desc->SMID);
1705 cmd_mpt = sc->mpt_cmd_list[smid - 1];
1706 scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request;
1707
1708 status = scsi_io_req->RaidContext.raid_context.status;
1709 extStatus = scsi_io_req->RaidContext.raid_context.exStatus;
1710 sense = cmd_mpt->sense;
1711 data_length = scsi_io_req->DataLength;
1712
1713 switch (scsi_io_req->Function) {
1714 case MPI2_FUNCTION_SCSI_TASK_MGMT:
1715 #if TM_DEBUG
1716 mr_tm_req = (MR_TASK_MANAGE_REQUEST *) cmd_mpt->io_request;
1717 mpi_tm_req = (MPI2_SCSI_TASK_MANAGE_REQUEST *)
1718 &mr_tm_req->TmRequest;
1719 device_printf(sc->mrsas_dev, "TM completion type 0x%X, "
1720 "TaskMID: 0x%X", mpi_tm_req->TaskType, mpi_tm_req->TaskMID);
1721 #endif
1722 wakeup_one((void *)&sc->ocr_chan);
1723 break;
1724 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */
1725 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id;
1726 lbinfo = &sc->load_balance_info[device_id];
1727 /* R1 load balancing for READ */
1728 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) {
1729 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]);
1730 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG;
1731 }
1732 /* Fall thru and complete IO */
1733 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST:
1734 if (cmd_mpt->r1_alt_dev_handle == MR_DEVHANDLE_INVALID) {
1735 mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status,
1736 extStatus, le32toh(data_length), sense);
1737 mrsas_cmd_done(sc, cmd_mpt);
1738 mrsas_atomic_dec(&sc->fw_outstanding);
1739 } else {
1740 /*
1741 * If the peer Raid 1/10 fast path failed,
1742 * mark IO as failed to the scsi layer.
1743 * Overwrite the current status by the failed status
1744 * and make sure that if any command fails,
1745 * driver returns fail status to CAM.
1746 */
1747 cmd_mpt->cmd_completed = 1;
1748 r1_cmd = cmd_mpt->peer_cmd;
1749 if (r1_cmd->cmd_completed) {
1750 if (r1_cmd->io_request->RaidContext.raid_context.status != MFI_STAT_OK) {
1751 status = r1_cmd->io_request->RaidContext.raid_context.status;
1752 extStatus = r1_cmd->io_request->RaidContext.raid_context.exStatus;
1753 data_length = r1_cmd->io_request->DataLength;
1754 sense = r1_cmd->sense;
1755 }
1756 mtx_lock(&sc->sim_lock);
1757 r1_cmd->ccb_ptr = NULL;
1758 if (r1_cmd->callout_owner) {
1759 callout_stop(&r1_cmd->cm_callout);
1760 r1_cmd->callout_owner = false;
1761 }
1762 mtx_unlock(&sc->sim_lock);
1763 mrsas_release_mpt_cmd(r1_cmd);
1764 mrsas_atomic_dec(&sc->fw_outstanding);
1765 mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status,
1766 extStatus, le32toh(data_length), sense);
1767 mrsas_cmd_done(sc, cmd_mpt);
1768 mrsas_atomic_dec(&sc->fw_outstanding);
1769 }
1770 }
1771 break;
1772 case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */
1773 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
1774 /*
1775 * Make sure NOT TO release the mfi command from the called
1776 * function's context if it is fired with issue_polled call.
1777 * And also make sure that the issue_polled call should only be
1778 * used if INTERRUPT IS DISABLED.
1779 */
1780 if (cmd_mfi->frame->hdr.flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE))
1781 mrsas_release_mfi_cmd(cmd_mfi);
1782 else
1783 mrsas_complete_mptmfi_passthru(sc, cmd_mfi, status);
1784 break;
1785 }
1786
1787 sc->last_reply_idx[MSIxIndex]++;
1788 if (sc->last_reply_idx[MSIxIndex] >= sc->reply_q_depth)
1789 sc->last_reply_idx[MSIxIndex] = 0;
1790
1791 desc->Words = ~((uint64_t)0x00); /* set it back to all
1792 * 0xFFFFFFFFs */
1793 num_completed++;
1794 threshold_reply_count++;
1795
1796 /* Get the next reply descriptor */
1797 if (!sc->last_reply_idx[MSIxIndex]) {
1798 desc = sc->reply_desc_mem;
1799 desc += ((MSIxIndex * sc->reply_alloc_sz) / sizeof(MPI2_REPLY_DESCRIPTORS_UNION));
1800 } else
1801 desc++;
1802
1803 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *) desc;
1804 desc_val.word = desc->Words;
1805
1806 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1807
1808 if (reply_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1809 break;
1810
1811 /*
1812 * Write to reply post index after completing threshold reply
1813 * count and still there are more replies in reply queue
1814 * pending to be completed.
1815 */
1816 if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) {
1817 if (sc->msix_enable) {
1818 if (sc->msix_combined)
1819 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8],
1820 ((MSIxIndex & 0x7) << 24) |
1821 sc->last_reply_idx[MSIxIndex]);
1822 else
1823 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) |
1824 sc->last_reply_idx[MSIxIndex]);
1825 } else
1826 mrsas_write_reg(sc, offsetof(mrsas_reg_set,
1827 reply_post_host_index), sc->last_reply_idx[0]);
1828
1829 threshold_reply_count = 0;
1830 }
1831 }
1832
1833 /* No match, just return */
1834 if (num_completed == 0)
1835 return (DONE);
1836
1837 /* Clear response interrupt */
1838 if (sc->msix_enable) {
1839 if (sc->msix_combined) {
1840 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8],
1841 ((MSIxIndex & 0x7) << 24) |
1842 sc->last_reply_idx[MSIxIndex]);
1843 } else
1844 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) |
1845 sc->last_reply_idx[MSIxIndex]);
1846 } else
1847 mrsas_write_reg(sc, offsetof(mrsas_reg_set,
1848 reply_post_host_index), sc->last_reply_idx[0]);
1849
1850 return (0);
1851 }
1852
1853 /*
1854 * mrsas_map_mpt_cmd_status: Allocate DMAable memory.
1855 * input: Adapter instance soft state
1856 *
1857 * This function is called from mrsas_complete_cmd(), for LD IO and FastPath IO.
1858 * It checks the command status and maps the appropriate CAM status for the
1859 * CCB.
1860 */
1861 void
mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd * cmd,union ccb * ccb_ptr,u_int8_t status,u_int8_t extStatus,u_int32_t data_length,u_int8_t * sense)1862 mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, union ccb *ccb_ptr, u_int8_t status,
1863 u_int8_t extStatus, u_int32_t data_length, u_int8_t *sense)
1864 {
1865 struct mrsas_softc *sc = cmd->sc;
1866 u_int8_t *sense_data;
1867
1868 switch (status) {
1869 case MFI_STAT_OK:
1870 ccb_ptr->ccb_h.status = CAM_REQ_CMP;
1871 break;
1872 case MFI_STAT_SCSI_IO_FAILED:
1873 case MFI_STAT_SCSI_DONE_WITH_ERROR:
1874 ccb_ptr->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1875 sense_data = (u_int8_t *)&ccb_ptr->csio.sense_data;
1876 if (sense_data) {
1877 /* For now just copy 18 bytes back */
1878 memcpy(sense_data, sense, 18);
1879 ccb_ptr->csio.sense_len = 18;
1880 ccb_ptr->ccb_h.status |= CAM_AUTOSNS_VALID;
1881 }
1882 break;
1883 case MFI_STAT_LD_OFFLINE:
1884 case MFI_STAT_DEVICE_NOT_FOUND:
1885 if (ccb_ptr->ccb_h.target_lun)
1886 ccb_ptr->ccb_h.status |= CAM_LUN_INVALID;
1887 else
1888 ccb_ptr->ccb_h.status |= CAM_DEV_NOT_THERE;
1889 break;
1890 case MFI_STAT_CONFIG_SEQ_MISMATCH:
1891 ccb_ptr->ccb_h.status |= CAM_REQUEUE_REQ;
1892 break;
1893 default:
1894 device_printf(sc->mrsas_dev, "FW cmd complete status %x\n", status);
1895 ccb_ptr->ccb_h.status = CAM_REQ_CMP_ERR;
1896 ccb_ptr->csio.scsi_status = status;
1897 }
1898 return;
1899 }
1900
1901 /*
1902 * mrsas_alloc_mem: Allocate DMAable memory
1903 * input: Adapter instance soft state
1904 *
1905 * This function creates the parent DMA tag and allocates DMAable memory. DMA
1906 * tag describes constraints of DMA mapping. Memory allocated is mapped into
1907 * Kernel virtual address. Callback argument is physical memory address.
1908 */
1909 static int
mrsas_alloc_mem(struct mrsas_softc * sc)1910 mrsas_alloc_mem(struct mrsas_softc *sc)
1911 {
1912 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size,
1913 evt_detail_size, count, pd_info_size;
1914
1915 /*
1916 * Allocate parent DMA tag
1917 */
1918 if (bus_dma_tag_create(
1919 bus_get_dma_tag(sc->mrsas_dev), /* parent */
1920 1, /* alignment */
1921 0, /* boundary */
1922 BUS_SPACE_MAXADDR, /* lowaddr */
1923 BUS_SPACE_MAXADDR, /* highaddr */
1924 NULL, NULL, /* filter, filterarg */
1925 BUS_SPACE_MAXSIZE, /* maxsize */
1926 BUS_SPACE_UNRESTRICTED, /* nsegments */
1927 BUS_SPACE_MAXSIZE, /* maxsegsize */
1928 0, /* flags */
1929 NULL, NULL, /* lockfunc, lockarg */
1930 &sc->mrsas_parent_tag /* tag */
1931 )) {
1932 device_printf(sc->mrsas_dev, "Cannot allocate parent DMA tag\n");
1933 return (ENOMEM);
1934 }
1935 /*
1936 * Allocate for version buffer
1937 */
1938 verbuf_size = MRSAS_MAX_NAME_LENGTH * (sizeof(bus_addr_t));
1939 if (bus_dma_tag_create(sc->mrsas_parent_tag,
1940 1, 0,
1941 BUS_SPACE_MAXADDR_32BIT,
1942 BUS_SPACE_MAXADDR,
1943 NULL, NULL,
1944 verbuf_size,
1945 1,
1946 verbuf_size,
1947 BUS_DMA_ALLOCNOW,
1948 NULL, NULL,
1949 &sc->verbuf_tag)) {
1950 device_printf(sc->mrsas_dev, "Cannot allocate verbuf DMA tag\n");
1951 return (ENOMEM);
1952 }
1953 if (bus_dmamem_alloc(sc->verbuf_tag, (void **)&sc->verbuf_mem,
1954 BUS_DMA_NOWAIT, &sc->verbuf_dmamap)) {
1955 device_printf(sc->mrsas_dev, "Cannot allocate verbuf memory\n");
1956 return (ENOMEM);
1957 }
1958 bzero(sc->verbuf_mem, verbuf_size);
1959 if (bus_dmamap_load(sc->verbuf_tag, sc->verbuf_dmamap, sc->verbuf_mem,
1960 verbuf_size, mrsas_addr_cb, &sc->verbuf_phys_addr,
1961 BUS_DMA_NOWAIT)) {
1962 device_printf(sc->mrsas_dev, "Cannot load verbuf DMA map\n");
1963 return (ENOMEM);
1964 }
1965 /*
1966 * Allocate IO Request Frames
1967 */
1968 io_req_size = sc->io_frames_alloc_sz;
1969 if (bus_dma_tag_create(sc->mrsas_parent_tag,
1970 16, 0,
1971 BUS_SPACE_MAXADDR_32BIT,
1972 BUS_SPACE_MAXADDR,
1973 NULL, NULL,
1974 io_req_size,
1975 1,
1976 io_req_size,
1977 BUS_DMA_ALLOCNOW,
1978 NULL, NULL,
1979 &sc->io_request_tag)) {
1980 device_printf(sc->mrsas_dev, "Cannot create IO request tag\n");
1981 return (ENOMEM);
1982 }
1983 if (bus_dmamem_alloc(sc->io_request_tag, (void **)&sc->io_request_mem,
1984 BUS_DMA_NOWAIT, &sc->io_request_dmamap)) {
1985 device_printf(sc->mrsas_dev, "Cannot alloc IO request memory\n");
1986 return (ENOMEM);
1987 }
1988 bzero(sc->io_request_mem, io_req_size);
1989 if (bus_dmamap_load(sc->io_request_tag, sc->io_request_dmamap,
1990 sc->io_request_mem, io_req_size, mrsas_addr_cb,
1991 &sc->io_request_phys_addr, BUS_DMA_NOWAIT)) {
1992 device_printf(sc->mrsas_dev, "Cannot load IO request memory\n");
1993 return (ENOMEM);
1994 }
1995 /*
1996 * Allocate Chain Frames
1997 */
1998 chain_frame_size = sc->chain_frames_alloc_sz;
1999 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2000 4, 0,
2001 BUS_SPACE_MAXADDR_32BIT,
2002 BUS_SPACE_MAXADDR,
2003 NULL, NULL,
2004 chain_frame_size,
2005 1,
2006 chain_frame_size,
2007 BUS_DMA_ALLOCNOW,
2008 NULL, NULL,
2009 &sc->chain_frame_tag)) {
2010 device_printf(sc->mrsas_dev, "Cannot create chain frame tag\n");
2011 return (ENOMEM);
2012 }
2013 if (bus_dmamem_alloc(sc->chain_frame_tag, (void **)&sc->chain_frame_mem,
2014 BUS_DMA_NOWAIT, &sc->chain_frame_dmamap)) {
2015 device_printf(sc->mrsas_dev, "Cannot alloc chain frame memory\n");
2016 return (ENOMEM);
2017 }
2018 bzero(sc->chain_frame_mem, chain_frame_size);
2019 if (bus_dmamap_load(sc->chain_frame_tag, sc->chain_frame_dmamap,
2020 sc->chain_frame_mem, chain_frame_size, mrsas_addr_cb,
2021 &sc->chain_frame_phys_addr, BUS_DMA_NOWAIT)) {
2022 device_printf(sc->mrsas_dev, "Cannot load chain frame memory\n");
2023 return (ENOMEM);
2024 }
2025 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
2026 /*
2027 * Allocate Reply Descriptor Array
2028 */
2029 reply_desc_size = sc->reply_alloc_sz * count;
2030 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2031 16, 0,
2032 BUS_SPACE_MAXADDR_32BIT,
2033 BUS_SPACE_MAXADDR,
2034 NULL, NULL,
2035 reply_desc_size,
2036 1,
2037 reply_desc_size,
2038 BUS_DMA_ALLOCNOW,
2039 NULL, NULL,
2040 &sc->reply_desc_tag)) {
2041 device_printf(sc->mrsas_dev, "Cannot create reply descriptor tag\n");
2042 return (ENOMEM);
2043 }
2044 if (bus_dmamem_alloc(sc->reply_desc_tag, (void **)&sc->reply_desc_mem,
2045 BUS_DMA_NOWAIT, &sc->reply_desc_dmamap)) {
2046 device_printf(sc->mrsas_dev, "Cannot alloc reply descriptor memory\n");
2047 return (ENOMEM);
2048 }
2049 if (bus_dmamap_load(sc->reply_desc_tag, sc->reply_desc_dmamap,
2050 sc->reply_desc_mem, reply_desc_size, mrsas_addr_cb,
2051 &sc->reply_desc_phys_addr, BUS_DMA_NOWAIT)) {
2052 device_printf(sc->mrsas_dev, "Cannot load reply descriptor memory\n");
2053 return (ENOMEM);
2054 }
2055 /*
2056 * Allocate Sense Buffer Array. Keep in lower 4GB
2057 */
2058 sense_size = sc->max_fw_cmds * MRSAS_SENSE_LEN;
2059 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2060 64, 0,
2061 BUS_SPACE_MAXADDR_32BIT,
2062 BUS_SPACE_MAXADDR,
2063 NULL, NULL,
2064 sense_size,
2065 1,
2066 sense_size,
2067 BUS_DMA_ALLOCNOW,
2068 NULL, NULL,
2069 &sc->sense_tag)) {
2070 device_printf(sc->mrsas_dev, "Cannot allocate sense buf tag\n");
2071 return (ENOMEM);
2072 }
2073 if (bus_dmamem_alloc(sc->sense_tag, (void **)&sc->sense_mem,
2074 BUS_DMA_NOWAIT, &sc->sense_dmamap)) {
2075 device_printf(sc->mrsas_dev, "Cannot allocate sense buf memory\n");
2076 return (ENOMEM);
2077 }
2078 if (bus_dmamap_load(sc->sense_tag, sc->sense_dmamap,
2079 sc->sense_mem, sense_size, mrsas_addr_cb, &sc->sense_phys_addr,
2080 BUS_DMA_NOWAIT)) {
2081 device_printf(sc->mrsas_dev, "Cannot load sense buf memory\n");
2082 return (ENOMEM);
2083 }
2084
2085 /*
2086 * Allocate for Event detail structure
2087 */
2088 evt_detail_size = sizeof(struct mrsas_evt_detail);
2089 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2090 1, 0,
2091 BUS_SPACE_MAXADDR_32BIT,
2092 BUS_SPACE_MAXADDR,
2093 NULL, NULL,
2094 evt_detail_size,
2095 1,
2096 evt_detail_size,
2097 BUS_DMA_ALLOCNOW,
2098 NULL, NULL,
2099 &sc->evt_detail_tag)) {
2100 device_printf(sc->mrsas_dev, "Cannot create Event detail tag\n");
2101 return (ENOMEM);
2102 }
2103 if (bus_dmamem_alloc(sc->evt_detail_tag, (void **)&sc->evt_detail_mem,
2104 BUS_DMA_NOWAIT, &sc->evt_detail_dmamap)) {
2105 device_printf(sc->mrsas_dev, "Cannot alloc Event detail buffer memory\n");
2106 return (ENOMEM);
2107 }
2108 bzero(sc->evt_detail_mem, evt_detail_size);
2109 if (bus_dmamap_load(sc->evt_detail_tag, sc->evt_detail_dmamap,
2110 sc->evt_detail_mem, evt_detail_size, mrsas_addr_cb,
2111 &sc->evt_detail_phys_addr, BUS_DMA_NOWAIT)) {
2112 device_printf(sc->mrsas_dev, "Cannot load Event detail buffer memory\n");
2113 return (ENOMEM);
2114 }
2115
2116 /*
2117 * Allocate for PD INFO structure
2118 */
2119 pd_info_size = sizeof(struct mrsas_pd_info);
2120 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2121 1, 0,
2122 BUS_SPACE_MAXADDR_32BIT,
2123 BUS_SPACE_MAXADDR,
2124 NULL, NULL,
2125 pd_info_size,
2126 1,
2127 pd_info_size,
2128 BUS_DMA_ALLOCNOW,
2129 NULL, NULL,
2130 &sc->pd_info_tag)) {
2131 device_printf(sc->mrsas_dev, "Cannot create PD INFO tag\n");
2132 return (ENOMEM);
2133 }
2134 if (bus_dmamem_alloc(sc->pd_info_tag, (void **)&sc->pd_info_mem,
2135 BUS_DMA_NOWAIT, &sc->pd_info_dmamap)) {
2136 device_printf(sc->mrsas_dev, "Cannot alloc PD INFO buffer memory\n");
2137 return (ENOMEM);
2138 }
2139 bzero(sc->pd_info_mem, pd_info_size);
2140 if (bus_dmamap_load(sc->pd_info_tag, sc->pd_info_dmamap,
2141 sc->pd_info_mem, pd_info_size, mrsas_addr_cb,
2142 &sc->pd_info_phys_addr, BUS_DMA_NOWAIT)) {
2143 device_printf(sc->mrsas_dev, "Cannot load PD INFO buffer memory\n");
2144 return (ENOMEM);
2145 }
2146
2147 /*
2148 * Create a dma tag for data buffers; size will be the maximum
2149 * possible I/O size (280kB).
2150 */
2151 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2152 1,
2153 0,
2154 BUS_SPACE_MAXADDR,
2155 BUS_SPACE_MAXADDR,
2156 NULL, NULL,
2157 maxphys,
2158 sc->max_num_sge, /* nsegments */
2159 maxphys,
2160 BUS_DMA_ALLOCNOW,
2161 busdma_lock_mutex,
2162 &sc->io_lock,
2163 &sc->data_tag)) {
2164 device_printf(sc->mrsas_dev, "Cannot create data dma tag\n");
2165 return (ENOMEM);
2166 }
2167 return (0);
2168 }
2169
2170 /*
2171 * mrsas_addr_cb: Callback function of bus_dmamap_load()
2172 * input: callback argument, machine dependent type
2173 * that describes DMA segments, number of segments, error code
2174 *
2175 * This function is for the driver to receive mapping information resultant of
2176 * the bus_dmamap_load(). The information is actually not being used, but the
2177 * address is saved anyway.
2178 */
2179 void
mrsas_addr_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)2180 mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2181 {
2182 bus_addr_t *addr;
2183
2184 addr = arg;
2185 *addr = segs[0].ds_addr;
2186 }
2187
2188 /*
2189 * mrsas_setup_raidmap: Set up RAID map.
2190 * input: Adapter instance soft state
2191 *
2192 * Allocate DMA memory for the RAID maps and perform setup.
2193 */
2194 static int
mrsas_setup_raidmap(struct mrsas_softc * sc)2195 mrsas_setup_raidmap(struct mrsas_softc *sc)
2196 {
2197 int i;
2198
2199 for (i = 0; i < 2; i++) {
2200 sc->ld_drv_map[i] =
2201 (void *)malloc(sc->drv_map_sz, M_MRSAS, M_NOWAIT);
2202 /* Do Error handling */
2203 if (!sc->ld_drv_map[i]) {
2204 device_printf(sc->mrsas_dev, "Could not allocate memory for local map");
2205
2206 if (i == 1)
2207 free(sc->ld_drv_map[0], M_MRSAS);
2208 /* ABORT driver initialization */
2209 goto ABORT;
2210 }
2211 }
2212
2213 for (int i = 0; i < 2; i++) {
2214 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2215 4, 0,
2216 BUS_SPACE_MAXADDR_32BIT,
2217 BUS_SPACE_MAXADDR,
2218 NULL, NULL,
2219 sc->max_map_sz,
2220 1,
2221 sc->max_map_sz,
2222 BUS_DMA_ALLOCNOW,
2223 NULL, NULL,
2224 &sc->raidmap_tag[i])) {
2225 device_printf(sc->mrsas_dev,
2226 "Cannot allocate raid map tag.\n");
2227 return (ENOMEM);
2228 }
2229 if (bus_dmamem_alloc(sc->raidmap_tag[i],
2230 (void **)&sc->raidmap_mem[i],
2231 BUS_DMA_NOWAIT, &sc->raidmap_dmamap[i])) {
2232 device_printf(sc->mrsas_dev,
2233 "Cannot allocate raidmap memory.\n");
2234 return (ENOMEM);
2235 }
2236 bzero(sc->raidmap_mem[i], sc->max_map_sz);
2237
2238 if (bus_dmamap_load(sc->raidmap_tag[i], sc->raidmap_dmamap[i],
2239 sc->raidmap_mem[i], sc->max_map_sz,
2240 mrsas_addr_cb, &sc->raidmap_phys_addr[i],
2241 BUS_DMA_NOWAIT)) {
2242 device_printf(sc->mrsas_dev, "Cannot load raidmap memory.\n");
2243 return (ENOMEM);
2244 }
2245 if (!sc->raidmap_mem[i]) {
2246 device_printf(sc->mrsas_dev,
2247 "Cannot allocate memory for raid map.\n");
2248 return (ENOMEM);
2249 }
2250 }
2251
2252 if (!mrsas_get_map_info(sc))
2253 mrsas_sync_map_info(sc);
2254
2255 return (0);
2256
2257 ABORT:
2258 return (1);
2259 }
2260
2261 /**
2262 * megasas_setup_jbod_map - setup jbod map for FP seq_number.
2263 * @sc: Adapter soft state
2264 *
2265 * Return 0 on success.
2266 */
2267 void
megasas_setup_jbod_map(struct mrsas_softc * sc)2268 megasas_setup_jbod_map(struct mrsas_softc *sc)
2269 {
2270 int i;
2271 uint32_t pd_seq_map_sz;
2272
2273 pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) +
2274 (sizeof(struct MR_PD_CFG_SEQ) * (MAX_PHYSICAL_DEVICES - 1));
2275
2276 if (!sc->ctrl_info->adapterOperations3.useSeqNumJbodFP) {
2277 sc->use_seqnum_jbod_fp = 0;
2278 return;
2279 }
2280 if (sc->jbodmap_mem[0])
2281 goto skip_alloc;
2282
2283 for (i = 0; i < 2; i++) {
2284 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2285 4, 0,
2286 BUS_SPACE_MAXADDR_32BIT,
2287 BUS_SPACE_MAXADDR,
2288 NULL, NULL,
2289 pd_seq_map_sz,
2290 1,
2291 pd_seq_map_sz,
2292 BUS_DMA_ALLOCNOW,
2293 NULL, NULL,
2294 &sc->jbodmap_tag[i])) {
2295 device_printf(sc->mrsas_dev,
2296 "Cannot allocate jbod map tag.\n");
2297 return;
2298 }
2299 if (bus_dmamem_alloc(sc->jbodmap_tag[i],
2300 (void **)&sc->jbodmap_mem[i],
2301 BUS_DMA_NOWAIT, &sc->jbodmap_dmamap[i])) {
2302 device_printf(sc->mrsas_dev,
2303 "Cannot allocate jbod map memory.\n");
2304 return;
2305 }
2306 bzero(sc->jbodmap_mem[i], pd_seq_map_sz);
2307
2308 if (bus_dmamap_load(sc->jbodmap_tag[i], sc->jbodmap_dmamap[i],
2309 sc->jbodmap_mem[i], pd_seq_map_sz,
2310 mrsas_addr_cb, &sc->jbodmap_phys_addr[i],
2311 BUS_DMA_NOWAIT)) {
2312 device_printf(sc->mrsas_dev, "Cannot load jbod map memory.\n");
2313 return;
2314 }
2315 if (!sc->jbodmap_mem[i]) {
2316 device_printf(sc->mrsas_dev,
2317 "Cannot allocate memory for jbod map.\n");
2318 sc->use_seqnum_jbod_fp = 0;
2319 return;
2320 }
2321 }
2322
2323 skip_alloc:
2324 if (!megasas_sync_pd_seq_num(sc, false) &&
2325 !megasas_sync_pd_seq_num(sc, true))
2326 sc->use_seqnum_jbod_fp = 1;
2327 else
2328 sc->use_seqnum_jbod_fp = 0;
2329
2330 device_printf(sc->mrsas_dev, "Jbod map is supported\n");
2331 }
2332
2333 /*
2334 * mrsas_init_fw: Initialize Firmware
2335 * input: Adapter soft state
2336 *
2337 * Calls transition_to_ready() to make sure Firmware is in operational state and
2338 * calls mrsas_init_adapter() to send IOC_INIT command to Firmware. It
2339 * issues internal commands to get the controller info after the IOC_INIT
2340 * command response is received by Firmware. Note: code relating to
2341 * get_pdlist, get_ld_list and max_sectors are currently not being used, it
2342 * is left here as placeholder.
2343 */
2344 static int
mrsas_init_fw(struct mrsas_softc * sc)2345 mrsas_init_fw(struct mrsas_softc *sc)
2346 {
2347
2348 int ret, loop, ocr = 0;
2349 u_int32_t max_sectors_1;
2350 u_int32_t max_sectors_2;
2351 u_int32_t tmp_sectors;
2352 u_int32_t scratch_pad_2, scratch_pad_3, scratch_pad_4;
2353 int msix_enable = 0;
2354 int fw_msix_count = 0;
2355 int i, j;
2356
2357 /* Make sure Firmware is ready */
2358 ret = mrsas_transition_to_ready(sc, ocr);
2359 if (ret != SUCCESS) {
2360 return (ret);
2361 }
2362 if (sc->is_ventura || sc->is_aero) {
2363 scratch_pad_3 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad_3));
2364 #if VD_EXT_DEBUG
2365 device_printf(sc->mrsas_dev, "scratch_pad_3 0x%x\n", scratch_pad_3);
2366 #endif
2367 sc->maxRaidMapSize = ((scratch_pad_3 >>
2368 MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT) &
2369 MR_MAX_RAID_MAP_SIZE_MASK);
2370 }
2371 /* MSI-x index 0- reply post host index register */
2372 sc->msix_reg_offset[0] = MPI2_REPLY_POST_HOST_INDEX_OFFSET;
2373 /* Check if MSI-X is supported while in ready state */
2374 msix_enable = (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)) & 0x4000000) >> 0x1a;
2375
2376 if (msix_enable) {
2377 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
2378 outbound_scratch_pad_2));
2379
2380 /* Check max MSI-X vectors */
2381 if (sc->device_id == MRSAS_TBOLT) {
2382 sc->msix_vectors = (scratch_pad_2
2383 & MR_MAX_REPLY_QUEUES_OFFSET) + 1;
2384 fw_msix_count = sc->msix_vectors;
2385 } else {
2386 /* Invader/Fury supports 96 MSI-X vectors */
2387 sc->msix_vectors = ((scratch_pad_2
2388 & MR_MAX_REPLY_QUEUES_EXT_OFFSET)
2389 >> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1;
2390 fw_msix_count = sc->msix_vectors;
2391
2392 if ((sc->mrsas_gen3_ctrl && (sc->msix_vectors > 8)) ||
2393 ((sc->is_ventura || sc->is_aero) && (sc->msix_vectors > 16)))
2394 sc->msix_combined = true;
2395 /*
2396 * Save 1-15 reply post index
2397 * address to local memory Index 0
2398 * is already saved from reg offset
2399 * MPI2_REPLY_POST_HOST_INDEX_OFFSET
2400 */
2401 for (loop = 1; loop < MR_MAX_MSIX_REG_ARRAY;
2402 loop++) {
2403 sc->msix_reg_offset[loop] =
2404 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2405 (loop * 0x10);
2406 }
2407 }
2408
2409 /* Don't bother allocating more MSI-X vectors than cpus */
2410 sc->msix_vectors = min(sc->msix_vectors,
2411 mp_ncpus);
2412
2413 /* Allocate MSI-x vectors */
2414 if (mrsas_allocate_msix(sc) == SUCCESS)
2415 sc->msix_enable = 1;
2416 else
2417 sc->msix_enable = 0;
2418
2419 device_printf(sc->mrsas_dev, "FW supports <%d> MSIX vector,"
2420 "Online CPU %d Current MSIX <%d>\n",
2421 fw_msix_count, mp_ncpus, sc->msix_vectors);
2422 }
2423 /*
2424 * MSI-X host index 0 is common for all adapter.
2425 * It is used for all MPT based Adapters.
2426 */
2427 if (sc->msix_combined) {
2428 sc->msix_reg_offset[0] =
2429 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET;
2430 }
2431 if (mrsas_init_adapter(sc) != SUCCESS) {
2432 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n");
2433 return (1);
2434 }
2435
2436 if (sc->is_ventura || sc->is_aero) {
2437 scratch_pad_4 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
2438 outbound_scratch_pad_4));
2439 if ((scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK) >= MR_DEFAULT_NVME_PAGE_SHIFT)
2440 sc->nvme_page_size = 1 << (scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK);
2441
2442 device_printf(sc->mrsas_dev, "NVME page size\t: (%d)\n", sc->nvme_page_size);
2443 }
2444
2445 /* Allocate internal commands for pass-thru */
2446 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) {
2447 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
2448 return (1);
2449 }
2450 sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
2451 if (!sc->ctrl_info) {
2452 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");
2453 return (1);
2454 }
2455 /*
2456 * Get the controller info from FW, so that the MAX VD support
2457 * availability can be decided.
2458 */
2459 if (mrsas_get_ctrl_info(sc)) {
2460 device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n");
2461 return (1);
2462 }
2463 sc->secure_jbod_support =
2464 (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
2465
2466 if (sc->secure_jbod_support)
2467 device_printf(sc->mrsas_dev, "FW supports SED \n");
2468
2469 if (sc->use_seqnum_jbod_fp)
2470 device_printf(sc->mrsas_dev, "FW supports JBOD Map \n");
2471
2472 if (sc->support_morethan256jbod)
2473 device_printf(sc->mrsas_dev, "FW supports JBOD Map Ext \n");
2474
2475 if (mrsas_setup_raidmap(sc) != SUCCESS) {
2476 device_printf(sc->mrsas_dev, "Error: RAID map setup FAILED !!! "
2477 "There seems to be some problem in the controller\n"
2478 "Please contact to the SUPPORT TEAM if the problem persists\n");
2479 }
2480 megasas_setup_jbod_map(sc);
2481
2482 memset(sc->target_list, 0,
2483 MRSAS_MAX_TM_TARGETS * sizeof(struct mrsas_target));
2484 for (i = 0; i < MRSAS_MAX_TM_TARGETS; i++)
2485 sc->target_list[i].target_id = 0xffff;
2486
2487 /* For pass-thru, get PD/LD list and controller info */
2488 memset(sc->pd_list, 0,
2489 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
2490 if (mrsas_get_pd_list(sc) != SUCCESS) {
2491 device_printf(sc->mrsas_dev, "Get PD list failed.\n");
2492 return (1);
2493 }
2494 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD_IDS);
2495 if (mrsas_get_ld_list(sc) != SUCCESS) {
2496 device_printf(sc->mrsas_dev, "Get LD lsit failed.\n");
2497 return (1);
2498 }
2499
2500 if ((sc->is_ventura || sc->is_aero) && sc->drv_stream_detection) {
2501 sc->streamDetectByLD = malloc(sizeof(PTR_LD_STREAM_DETECT) *
2502 MAX_LOGICAL_DRIVES_EXT, M_MRSAS, M_NOWAIT);
2503 if (!sc->streamDetectByLD) {
2504 device_printf(sc->mrsas_dev,
2505 "unable to allocate stream detection for pool of LDs\n");
2506 return (1);
2507 }
2508 for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i) {
2509 sc->streamDetectByLD[i] = malloc(sizeof(LD_STREAM_DETECT), M_MRSAS, M_NOWAIT);
2510 if (!sc->streamDetectByLD[i]) {
2511 device_printf(sc->mrsas_dev, "unable to allocate stream detect by LD\n");
2512 for (j = 0; j < i; ++j)
2513 free(sc->streamDetectByLD[j], M_MRSAS);
2514 free(sc->streamDetectByLD, M_MRSAS);
2515 sc->streamDetectByLD = NULL;
2516 return (1);
2517 }
2518 memset(sc->streamDetectByLD[i], 0, sizeof(LD_STREAM_DETECT));
2519 sc->streamDetectByLD[i]->mruBitMap = MR_STREAM_BITMAP;
2520 }
2521 }
2522
2523 /*
2524 * Compute the max allowed sectors per IO: The controller info has
2525 * two limits on max sectors. Driver should use the minimum of these
2526 * two.
2527 *
2528 * 1 << stripe_sz_ops.min = max sectors per strip
2529 *
2530 * Note that older firmwares ( < FW ver 30) didn't report information to
2531 * calculate max_sectors_1. So the number ended up as zero always.
2532 */
2533 tmp_sectors = 0;
2534 max_sectors_1 = (1 << sc->ctrl_info->stripe_sz_ops.min) *
2535 sc->ctrl_info->max_strips_per_io;
2536 max_sectors_2 = sc->ctrl_info->max_request_size;
2537 tmp_sectors = min(max_sectors_1, max_sectors_2);
2538 sc->max_sectors_per_req = (sc->max_num_sge - 1) * MRSAS_PAGE_SIZE / 512;
2539
2540 if (tmp_sectors && (sc->max_sectors_per_req > tmp_sectors))
2541 sc->max_sectors_per_req = tmp_sectors;
2542
2543 sc->disableOnlineCtrlReset =
2544 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
2545 sc->UnevenSpanSupport =
2546 sc->ctrl_info->adapterOperations2.supportUnevenSpans;
2547 if (sc->UnevenSpanSupport) {
2548 device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n",
2549 sc->UnevenSpanSupport);
2550
2551 if (MR_ValidateMapInfo(sc))
2552 sc->fast_path_io = 1;
2553 else
2554 sc->fast_path_io = 0;
2555 }
2556
2557 device_printf(sc->mrsas_dev, "max_fw_cmds: %u max_scsi_cmds: %u\n",
2558 sc->max_fw_cmds, sc->max_scsi_cmds);
2559 return (0);
2560 }
2561
2562 /*
2563 * mrsas_init_adapter: Initializes the adapter/controller
2564 * input: Adapter soft state
2565 *
2566 * Prepares for the issuing of the IOC Init cmd to FW for initializing the
2567 * ROC/controller. The FW register is read to determined the number of
2568 * commands that is supported. All memory allocations for IO is based on
2569 * max_cmd. Appropriate calculations are performed in this function.
2570 */
2571 int
mrsas_init_adapter(struct mrsas_softc * sc)2572 mrsas_init_adapter(struct mrsas_softc *sc)
2573 {
2574 uint32_t status;
2575 u_int32_t scratch_pad_2;
2576 int ret;
2577 int i = 0;
2578
2579 /* Read FW status register */
2580 status = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad));
2581
2582 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK;
2583
2584 /* Decrement the max supported by 1, to correlate with FW */
2585 sc->max_fw_cmds = sc->max_fw_cmds - 1;
2586 sc->max_scsi_cmds = sc->max_fw_cmds - MRSAS_MAX_MFI_CMDS;
2587
2588 /* Determine allocation size of command frames */
2589 sc->reply_q_depth = ((sc->max_fw_cmds + 1 + 15) / 16 * 16) * 2;
2590 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * sc->max_fw_cmds;
2591 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
2592 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE +
2593 (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (sc->max_fw_cmds + 1));
2594 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
2595 outbound_scratch_pad_2));
2596
2597 mrsas_dprint(sc, MRSAS_TRACE, "%s: sc->reply_q_depth 0x%x,"
2598 "sc->request_alloc_sz 0x%x, sc->reply_alloc_sz 0x%x,"
2599 "sc->io_frames_alloc_sz 0x%x\n", __func__,
2600 sc->reply_q_depth, sc->request_alloc_sz,
2601 sc->reply_alloc_sz, sc->io_frames_alloc_sz);
2602
2603 /*
2604 * If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
2605 * Firmware support extended IO chain frame which is 4 time more
2606 * than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) =
2607 * 1K 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K
2608 */
2609 if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK)
2610 sc->max_chain_frame_sz =
2611 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
2612 * MEGASAS_1MB_IO;
2613 else
2614 sc->max_chain_frame_sz =
2615 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
2616 * MEGASAS_256K_IO;
2617
2618 sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * sc->max_fw_cmds;
2619 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2620 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16;
2621
2622 sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION);
2623 sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2;
2624
2625 mrsas_dprint(sc, MRSAS_INFO,
2626 "max sge: 0x%x, max chain frame size: 0x%x, "
2627 "max fw cmd: 0x%x sc->chain_frames_alloc_sz: 0x%x\n",
2628 sc->max_num_sge,
2629 sc->max_chain_frame_sz, sc->max_fw_cmds,
2630 sc->chain_frames_alloc_sz);
2631
2632 /* Used for pass thru MFI frame (DCMD) */
2633 sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16;
2634
2635 sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2636 sizeof(MPI2_SGE_IO_UNION)) / 16;
2637
2638 int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
2639
2640 for (i = 0; i < count; i++)
2641 sc->last_reply_idx[i] = 0;
2642
2643 ret = mrsas_alloc_mem(sc);
2644 if (ret != SUCCESS)
2645 return (ret);
2646
2647 ret = mrsas_alloc_mpt_cmds(sc);
2648 if (ret != SUCCESS)
2649 return (ret);
2650
2651 ret = mrsas_ioc_init(sc);
2652 if (ret != SUCCESS)
2653 return (ret);
2654
2655 return (0);
2656 }
2657
2658 /*
2659 * mrsas_alloc_ioc_cmd: Allocates memory for IOC Init command
2660 * input: Adapter soft state
2661 *
2662 * Allocates for the IOC Init cmd to FW to initialize the ROC/controller.
2663 */
2664 int
mrsas_alloc_ioc_cmd(struct mrsas_softc * sc)2665 mrsas_alloc_ioc_cmd(struct mrsas_softc *sc)
2666 {
2667 int ioc_init_size;
2668
2669 /* Allocate IOC INIT command */
2670 ioc_init_size = 1024 + sizeof(MPI2_IOC_INIT_REQUEST);
2671 if (bus_dma_tag_create(sc->mrsas_parent_tag,
2672 1, 0,
2673 BUS_SPACE_MAXADDR_32BIT,
2674 BUS_SPACE_MAXADDR,
2675 NULL, NULL,
2676 ioc_init_size,
2677 1,
2678 ioc_init_size,
2679 BUS_DMA_ALLOCNOW,
2680 NULL, NULL,
2681 &sc->ioc_init_tag)) {
2682 device_printf(sc->mrsas_dev, "Cannot allocate ioc init tag\n");
2683 return (ENOMEM);
2684 }
2685 if (bus_dmamem_alloc(sc->ioc_init_tag, (void **)&sc->ioc_init_mem,
2686 BUS_DMA_NOWAIT, &sc->ioc_init_dmamap)) {
2687 device_printf(sc->mrsas_dev, "Cannot allocate ioc init cmd mem\n");
2688 return (ENOMEM);
2689 }
2690 bzero(sc->ioc_init_mem, ioc_init_size);
2691 if (bus_dmamap_load(sc->ioc_init_tag, sc->ioc_init_dmamap,
2692 sc->ioc_init_mem, ioc_init_size, mrsas_addr_cb,
2693 &sc->ioc_init_phys_mem, BUS_DMA_NOWAIT)) {
2694 device_printf(sc->mrsas_dev, "Cannot load ioc init cmd mem\n");
2695 return (ENOMEM);
2696 }
2697 return (0);
2698 }
2699
2700 /*
2701 * mrsas_free_ioc_cmd: Allocates memory for IOC Init command
2702 * input: Adapter soft state
2703 *
2704 * Deallocates memory of the IOC Init cmd.
2705 */
2706 void
mrsas_free_ioc_cmd(struct mrsas_softc * sc)2707 mrsas_free_ioc_cmd(struct mrsas_softc *sc)
2708 {
2709 if (sc->ioc_init_phys_mem)
2710 bus_dmamap_unload(sc->ioc_init_tag, sc->ioc_init_dmamap);
2711 if (sc->ioc_init_mem != NULL)
2712 bus_dmamem_free(sc->ioc_init_tag, sc->ioc_init_mem, sc->ioc_init_dmamap);
2713 if (sc->ioc_init_tag != NULL)
2714 bus_dma_tag_destroy(sc->ioc_init_tag);
2715 }
2716
2717 /*
2718 * mrsas_ioc_init: Sends IOC Init command to FW
2719 * input: Adapter soft state
2720 *
2721 * Issues the IOC Init cmd to FW to initialize the ROC/controller.
2722 */
2723 int
mrsas_ioc_init(struct mrsas_softc * sc)2724 mrsas_ioc_init(struct mrsas_softc *sc)
2725 {
2726 struct mrsas_init_frame *init_frame;
2727 pMpi2IOCInitRequest_t IOCInitMsg;
2728 MRSAS_REQUEST_DESCRIPTOR_UNION req_desc;
2729 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME;
2730 bus_addr_t phys_addr;
2731 int i, retcode = 0;
2732 u_int32_t scratch_pad_2;
2733
2734 /* Allocate memory for the IOC INIT command */
2735 if (mrsas_alloc_ioc_cmd(sc)) {
2736 device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n");
2737 return (1);
2738 }
2739
2740 if (!sc->block_sync_cache) {
2741 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
2742 outbound_scratch_pad_2));
2743 sc->fw_sync_cache_support = (scratch_pad_2 &
2744 MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0;
2745 }
2746
2747 IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024);
2748 IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT;
2749 IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER;
2750 IOCInitMsg->MsgVersion = htole16(MPI2_VERSION);
2751 IOCInitMsg->HeaderVersion = htole16(MPI2_HEADER_VERSION);
2752 IOCInitMsg->SystemRequestFrameSize = htole16(MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4);
2753 IOCInitMsg->ReplyDescriptorPostQueueDepth = htole16(sc->reply_q_depth);
2754 IOCInitMsg->ReplyDescriptorPostQueueAddress = htole64(sc->reply_desc_phys_addr);
2755 IOCInitMsg->SystemRequestFrameBaseAddress = htole64(sc->io_request_phys_addr);
2756 IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0);
2757 IOCInitMsg->HostPageSize = MR_DEFAULT_NVME_PAGE_SHIFT;
2758
2759 init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem;
2760 init_frame->cmd = MFI_CMD_INIT;
2761 init_frame->cmd_status = 0xFF;
2762 init_frame->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE);
2763
2764 /* driver support Extended MSIX */
2765 if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) {
2766 init_frame->driver_operations.
2767 mfi_capabilities.support_additional_msix = 1;
2768 }
2769 if (sc->verbuf_mem) {
2770 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n",
2771 MRSAS_VERSION);
2772 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr;
2773 init_frame->driver_ver_hi = 0;
2774 }
2775 init_frame->driver_operations.mfi_capabilities.support_ndrive_r1_lb = 1;
2776 init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1;
2777 init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1;
2778 if (sc->max_chain_frame_sz > MEGASAS_CHAIN_FRAME_SZ_MIN)
2779 init_frame->driver_operations.mfi_capabilities.support_ext_io_size = 1;
2780
2781 init_frame->driver_operations.reg = htole32(init_frame->driver_operations.reg);
2782
2783 phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024;
2784 init_frame->queue_info_new_phys_addr_lo = htole32(phys_addr);
2785 init_frame->data_xfer_len = htole32(sizeof(Mpi2IOCInitRequest_t));
2786
2787 req_desc.addr.Words = htole64((bus_addr_t)sc->ioc_init_phys_mem);
2788 req_desc.MFAIo.RequestFlags =
2789 (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
2790
2791 mrsas_disable_intr(sc);
2792 mrsas_dprint(sc, MRSAS_OCR, "Issuing IOC INIT command to FW.\n");
2793 mrsas_write_64bit_req_desc(sc, req_desc.addr.u.low, req_desc.addr.u.high);
2794
2795 /*
2796 * Poll response timer to wait for Firmware response. While this
2797 * timer with the DELAY call could block CPU, the time interval for
2798 * this is only 1 millisecond.
2799 */
2800 if (init_frame->cmd_status == 0xFF) {
2801 for (i = 0; i < (max_wait * 1000); i++) {
2802 if (init_frame->cmd_status == 0xFF)
2803 DELAY(1000);
2804 else
2805 break;
2806 }
2807 }
2808 if (init_frame->cmd_status == 0)
2809 mrsas_dprint(sc, MRSAS_OCR,
2810 "IOC INIT response received from FW.\n");
2811 else {
2812 if (init_frame->cmd_status == 0xFF)
2813 device_printf(sc->mrsas_dev, "IOC Init timed out after %d seconds.\n", max_wait);
2814 else
2815 device_printf(sc->mrsas_dev, "IOC Init failed, status = 0x%x\n", init_frame->cmd_status);
2816 retcode = 1;
2817 }
2818
2819 if (sc->is_aero) {
2820 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
2821 outbound_scratch_pad_2));
2822 sc->atomic_desc_support = (scratch_pad_2 &
2823 MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET) ? 1 : 0;
2824 device_printf(sc->mrsas_dev, "FW supports atomic descriptor: %s\n",
2825 sc->atomic_desc_support ? "Yes" : "No");
2826 }
2827
2828 mrsas_free_ioc_cmd(sc);
2829 return (retcode);
2830 }
2831
2832 /*
2833 * mrsas_alloc_mpt_cmds: Allocates the command packets
2834 * input: Adapter instance soft state
2835 *
2836 * This function allocates the internal commands for IOs. Each command that is
2837 * issued to FW is wrapped in a local data structure called mrsas_mpt_cmd. An
2838 * array is allocated with mrsas_mpt_cmd context. The free commands are
2839 * maintained in a linked list (cmd pool). SMID value range is from 1 to
2840 * max_fw_cmds.
2841 */
2842 int
mrsas_alloc_mpt_cmds(struct mrsas_softc * sc)2843 mrsas_alloc_mpt_cmds(struct mrsas_softc *sc)
2844 {
2845 int i, j;
2846 u_int32_t max_fw_cmds, count;
2847 struct mrsas_mpt_cmd *cmd;
2848 pMpi2ReplyDescriptorsUnion_t reply_desc;
2849 u_int32_t offset, chain_offset, sense_offset;
2850 bus_addr_t io_req_base_phys, chain_frame_base_phys, sense_base_phys;
2851 u_int8_t *io_req_base, *chain_frame_base, *sense_base;
2852
2853 max_fw_cmds = sc->max_fw_cmds;
2854
2855 sc->req_desc = malloc(sc->request_alloc_sz, M_MRSAS, M_NOWAIT);
2856 if (!sc->req_desc) {
2857 device_printf(sc->mrsas_dev, "Out of memory, cannot alloc req desc\n");
2858 return (ENOMEM);
2859 }
2860 memset(sc->req_desc, 0, sc->request_alloc_sz);
2861
2862 /*
2863 * sc->mpt_cmd_list is an array of struct mrsas_mpt_cmd pointers.
2864 * Allocate the dynamic array first and then allocate individual
2865 * commands.
2866 */
2867 sc->mpt_cmd_list = malloc(sizeof(struct mrsas_mpt_cmd *) * max_fw_cmds,
2868 M_MRSAS, M_NOWAIT);
2869 if (!sc->mpt_cmd_list) {
2870 device_printf(sc->mrsas_dev, "Cannot alloc memory for mpt_cmd_list.\n");
2871 return (ENOMEM);
2872 }
2873 memset(sc->mpt_cmd_list, 0, sizeof(struct mrsas_mpt_cmd *) * max_fw_cmds);
2874 for (i = 0; i < max_fw_cmds; i++) {
2875 sc->mpt_cmd_list[i] = malloc(sizeof(struct mrsas_mpt_cmd),
2876 M_MRSAS, M_NOWAIT);
2877 if (!sc->mpt_cmd_list[i]) {
2878 for (j = 0; j < i; j++)
2879 free(sc->mpt_cmd_list[j], M_MRSAS);
2880 free(sc->mpt_cmd_list, M_MRSAS);
2881 sc->mpt_cmd_list = NULL;
2882 return (ENOMEM);
2883 }
2884 }
2885
2886 io_req_base = (u_int8_t *)sc->io_request_mem + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
2887 io_req_base_phys = (bus_addr_t)sc->io_request_phys_addr + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
2888 chain_frame_base = (u_int8_t *)sc->chain_frame_mem;
2889 chain_frame_base_phys = (bus_addr_t)sc->chain_frame_phys_addr;
2890 sense_base = (u_int8_t *)sc->sense_mem;
2891 sense_base_phys = (bus_addr_t)sc->sense_phys_addr;
2892 for (i = 0; i < max_fw_cmds; i++) {
2893 cmd = sc->mpt_cmd_list[i];
2894 offset = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * i;
2895 chain_offset = sc->max_chain_frame_sz * i;
2896 sense_offset = MRSAS_SENSE_LEN * i;
2897 memset(cmd, 0, sizeof(struct mrsas_mpt_cmd));
2898 cmd->index = i + 1;
2899 cmd->ccb_ptr = NULL;
2900 cmd->r1_alt_dev_handle = MR_DEVHANDLE_INVALID;
2901 callout_init_mtx(&cmd->cm_callout, &sc->sim_lock, 0);
2902 cmd->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX;
2903 cmd->sc = sc;
2904 cmd->io_request = (MRSAS_RAID_SCSI_IO_REQUEST *) (io_req_base + offset);
2905 memset(cmd->io_request, 0, sizeof(MRSAS_RAID_SCSI_IO_REQUEST));
2906 cmd->io_request_phys_addr = io_req_base_phys + offset;
2907 cmd->chain_frame = (MPI2_SGE_IO_UNION *) (chain_frame_base + chain_offset);
2908 cmd->chain_frame_phys_addr = chain_frame_base_phys + chain_offset;
2909 cmd->sense = sense_base + sense_offset;
2910 cmd->sense_phys_addr = sense_base_phys + sense_offset;
2911 if (bus_dmamap_create(sc->data_tag, 0, &cmd->data_dmamap)) {
2912 return (FAIL);
2913 }
2914 TAILQ_INSERT_TAIL(&(sc->mrsas_mpt_cmd_list_head), cmd, next);
2915 }
2916
2917 /* Initialize reply descriptor array to 0xFFFFFFFF */
2918 reply_desc = sc->reply_desc_mem;
2919 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
2920 for (i = 0; i < sc->reply_q_depth * count; i++, reply_desc++) {
2921 reply_desc->Words = MRSAS_ULONG_MAX;
2922 }
2923 return (0);
2924 }
2925
2926 /*
2927 * mrsas_write_64bit_req_dsc: Writes 64 bit request descriptor to FW
2928 * input: Adapter softstate
2929 * request descriptor address low
2930 * request descriptor address high
2931 */
2932 void
mrsas_write_64bit_req_desc(struct mrsas_softc * sc,u_int32_t req_desc_lo,u_int32_t req_desc_hi)2933 mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo,
2934 u_int32_t req_desc_hi)
2935 {
2936 mtx_lock(&sc->pci_lock);
2937 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port),
2938 le32toh(req_desc_lo));
2939 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port),
2940 le32toh(req_desc_hi));
2941 mtx_unlock(&sc->pci_lock);
2942 }
2943
2944 /*
2945 * mrsas_fire_cmd: Sends command to FW
2946 * input: Adapter softstate
2947 * request descriptor address low
2948 * request descriptor address high
2949 *
2950 * This functions fires the command to Firmware by writing to the
2951 * inbound_low_queue_port and inbound_high_queue_port.
2952 */
2953 void
mrsas_fire_cmd(struct mrsas_softc * sc,u_int32_t req_desc_lo,u_int32_t req_desc_hi)2954 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
2955 u_int32_t req_desc_hi)
2956 {
2957 if (sc->atomic_desc_support)
2958 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_single_queue_port),
2959 le32toh(req_desc_lo));
2960 else
2961 mrsas_write_64bit_req_desc(sc, req_desc_lo, req_desc_hi);
2962 }
2963
2964 /*
2965 * mrsas_transition_to_ready: Move FW to Ready state input:
2966 * Adapter instance soft state
2967 *
2968 * During the initialization, FW passes can potentially be in any one of several
2969 * possible states. If the FW in operational, waiting-for-handshake states,
2970 * driver must take steps to bring it to ready state. Otherwise, it has to
2971 * wait for the ready state.
2972 */
2973 int
mrsas_transition_to_ready(struct mrsas_softc * sc,int ocr)2974 mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr)
2975 {
2976 int i;
2977 u_int8_t max_wait;
2978 u_int32_t val, fw_state;
2979 u_int32_t cur_state;
2980 u_int32_t abs_state, curr_abs_state;
2981
2982 val = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad));
2983 fw_state = val & MFI_STATE_MASK;
2984 max_wait = MRSAS_RESET_WAIT_TIME;
2985
2986 if (fw_state != MFI_STATE_READY)
2987 device_printf(sc->mrsas_dev, "Waiting for FW to come to ready state\n");
2988
2989 while (fw_state != MFI_STATE_READY) {
2990 abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad));
2991 switch (fw_state) {
2992 case MFI_STATE_FAULT:
2993 device_printf(sc->mrsas_dev, "FW is in FAULT state!!\n");
2994 if (ocr) {
2995 cur_state = MFI_STATE_FAULT;
2996 break;
2997 } else
2998 return -ENODEV;
2999 case MFI_STATE_WAIT_HANDSHAKE:
3000 /* Set the CLR bit in inbound doorbell */
3001 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell),
3002 MFI_INIT_CLEAR_HANDSHAKE | MFI_INIT_HOTPLUG);
3003 cur_state = MFI_STATE_WAIT_HANDSHAKE;
3004 break;
3005 case MFI_STATE_BOOT_MESSAGE_PENDING:
3006 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell),
3007 MFI_INIT_HOTPLUG);
3008 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING;
3009 break;
3010 case MFI_STATE_OPERATIONAL:
3011 /*
3012 * Bring it to READY state; assuming max wait 10
3013 * secs
3014 */
3015 mrsas_disable_intr(sc);
3016 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), MFI_RESET_FLAGS);
3017 for (i = 0; i < max_wait * 1000; i++) {
3018 if (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, doorbell)) & 1)
3019 DELAY(1000);
3020 else
3021 break;
3022 }
3023 cur_state = MFI_STATE_OPERATIONAL;
3024 break;
3025 case MFI_STATE_UNDEFINED:
3026 /*
3027 * This state should not last for more than 2
3028 * seconds
3029 */
3030 cur_state = MFI_STATE_UNDEFINED;
3031 break;
3032 case MFI_STATE_BB_INIT:
3033 cur_state = MFI_STATE_BB_INIT;
3034 break;
3035 case MFI_STATE_FW_INIT:
3036 cur_state = MFI_STATE_FW_INIT;
3037 break;
3038 case MFI_STATE_FW_INIT_2:
3039 cur_state = MFI_STATE_FW_INIT_2;
3040 break;
3041 case MFI_STATE_DEVICE_SCAN:
3042 cur_state = MFI_STATE_DEVICE_SCAN;
3043 break;
3044 case MFI_STATE_FLUSH_CACHE:
3045 cur_state = MFI_STATE_FLUSH_CACHE;
3046 break;
3047 default:
3048 device_printf(sc->mrsas_dev, "Unknown state 0x%x\n", fw_state);
3049 return -ENODEV;
3050 }
3051
3052 /*
3053 * The cur_state should not last for more than max_wait secs
3054 */
3055 for (i = 0; i < (max_wait * 1000); i++) {
3056 fw_state = (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3057 outbound_scratch_pad)) & MFI_STATE_MASK);
3058 curr_abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3059 outbound_scratch_pad));
3060 if (abs_state == curr_abs_state)
3061 DELAY(1000);
3062 else
3063 break;
3064 }
3065
3066 /*
3067 * Return error if fw_state hasn't changed after max_wait
3068 */
3069 if (curr_abs_state == abs_state) {
3070 device_printf(sc->mrsas_dev, "FW state [%d] hasn't changed "
3071 "in %d secs\n", fw_state, max_wait);
3072 return -ENODEV;
3073 }
3074 }
3075 mrsas_dprint(sc, MRSAS_OCR, "FW now in Ready state\n");
3076 return 0;
3077 }
3078
3079 /*
3080 * mrsas_get_mfi_cmd: Get a cmd from free command pool
3081 * input: Adapter soft state
3082 *
3083 * This function removes an MFI command from the command list.
3084 */
3085 struct mrsas_mfi_cmd *
mrsas_get_mfi_cmd(struct mrsas_softc * sc)3086 mrsas_get_mfi_cmd(struct mrsas_softc *sc)
3087 {
3088 struct mrsas_mfi_cmd *cmd = NULL;
3089
3090 mtx_lock(&sc->mfi_cmd_pool_lock);
3091 if (!TAILQ_EMPTY(&sc->mrsas_mfi_cmd_list_head)) {
3092 cmd = TAILQ_FIRST(&sc->mrsas_mfi_cmd_list_head);
3093 TAILQ_REMOVE(&sc->mrsas_mfi_cmd_list_head, cmd, next);
3094 }
3095 mtx_unlock(&sc->mfi_cmd_pool_lock);
3096
3097 return cmd;
3098 }
3099
3100 /*
3101 * mrsas_ocr_thread: Thread to handle OCR/Kill Adapter.
3102 * input: Adapter Context.
3103 *
3104 * This function will check FW status register and flag do_timeout_reset flag.
3105 * It will do OCR/Kill adapter if FW is in fault state or IO timed out has
3106 * trigger reset.
3107 */
3108 static void
mrsas_ocr_thread(void * arg)3109 mrsas_ocr_thread(void *arg)
3110 {
3111 struct mrsas_softc *sc;
3112 u_int32_t fw_status, fw_state;
3113 u_int8_t tm_target_reset_failed = 0;
3114
3115 sc = (struct mrsas_softc *)arg;
3116
3117 mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__);
3118 sc->ocr_thread_active = 1;
3119 mtx_lock(&sc->sim_lock);
3120 for (;;) {
3121 /* Sleep for 1 second and check the queue status */
3122 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO,
3123 "mrsas_ocr", sc->mrsas_fw_fault_check_delay * hz);
3124 if (sc->remove_in_progress ||
3125 sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) {
3126 mrsas_dprint(sc, MRSAS_OCR,
3127 "Exit due to %s from %s\n",
3128 sc->remove_in_progress ? "Shutdown" :
3129 "Hardware critical error", __func__);
3130 break;
3131 }
3132 fw_status = mrsas_read_reg_with_retries(sc,
3133 offsetof(mrsas_reg_set, outbound_scratch_pad));
3134 fw_state = fw_status & MFI_STATE_MASK;
3135 if (fw_state == MFI_STATE_FAULT || sc->do_timedout_reset ||
3136 mrsas_atomic_read(&sc->target_reset_outstanding)) {
3137 /* First, freeze further IOs to come to the SIM */
3138 mrsas_xpt_freeze(sc);
3139
3140 /* If this is an IO timeout then go for target reset */
3141 if (mrsas_atomic_read(&sc->target_reset_outstanding)) {
3142 device_printf(sc->mrsas_dev, "Initiating Target RESET "
3143 "because of SCSI IO timeout!\n");
3144
3145 /* Let the remaining IOs to complete */
3146 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO,
3147 "mrsas_reset_targets", 5 * hz);
3148
3149 /* Try to reset the target device */
3150 if (mrsas_reset_targets(sc) == FAIL)
3151 tm_target_reset_failed = 1;
3152 }
3153
3154 /* If this is a DCMD timeout or FW fault,
3155 * then go for controller reset
3156 */
3157 if (fw_state == MFI_STATE_FAULT || tm_target_reset_failed ||
3158 (sc->do_timedout_reset == MFI_DCMD_TIMEOUT_OCR)) {
3159 if (tm_target_reset_failed)
3160 device_printf(sc->mrsas_dev, "Initiaiting OCR because of "
3161 "TM FAILURE!\n");
3162 else
3163 device_printf(sc->mrsas_dev, "Initiaiting OCR "
3164 "because of %s!\n", sc->do_timedout_reset ?
3165 "DCMD IO Timeout" : "FW fault");
3166
3167 mtx_lock_spin(&sc->ioctl_lock);
3168 sc->reset_in_progress = 1;
3169 mtx_unlock_spin(&sc->ioctl_lock);
3170 sc->reset_count++;
3171
3172 /*
3173 * Wait for the AEN task to be completed if it is running.
3174 */
3175 mtx_unlock(&sc->sim_lock);
3176 taskqueue_drain(sc->ev_tq, &sc->ev_task);
3177 mtx_lock(&sc->sim_lock);
3178
3179 taskqueue_block(sc->ev_tq);
3180 /* Try to reset the controller */
3181 mrsas_reset_ctrl(sc, sc->do_timedout_reset);
3182
3183 sc->do_timedout_reset = 0;
3184 sc->reset_in_progress = 0;
3185 tm_target_reset_failed = 0;
3186 mrsas_atomic_set(&sc->target_reset_outstanding, 0);
3187 memset(sc->target_reset_pool, 0,
3188 sizeof(sc->target_reset_pool));
3189 taskqueue_unblock(sc->ev_tq);
3190 }
3191
3192 /* Now allow IOs to come to the SIM */
3193 mrsas_xpt_release(sc);
3194 }
3195 }
3196 mtx_unlock(&sc->sim_lock);
3197 sc->ocr_thread_active = 0;
3198 mrsas_kproc_exit(0);
3199 }
3200
3201 /*
3202 * mrsas_reset_reply_desc: Reset Reply descriptor as part of OCR.
3203 * input: Adapter Context.
3204 *
3205 * This function will clear reply descriptor so that post OCR driver and FW will
3206 * lost old history.
3207 */
3208 void
mrsas_reset_reply_desc(struct mrsas_softc * sc)3209 mrsas_reset_reply_desc(struct mrsas_softc *sc)
3210 {
3211 int i, count;
3212 pMpi2ReplyDescriptorsUnion_t reply_desc;
3213
3214 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
3215 for (i = 0; i < count; i++)
3216 sc->last_reply_idx[i] = 0;
3217
3218 reply_desc = sc->reply_desc_mem;
3219 for (i = 0; i < sc->reply_q_depth; i++, reply_desc++) {
3220 reply_desc->Words = MRSAS_ULONG_MAX;
3221 }
3222 }
3223
3224 /*
3225 * mrsas_reset_ctrl: Core function to OCR/Kill adapter.
3226 * input: Adapter Context.
3227 *
3228 * This function will run from thread context so that it can sleep. 1. Do not
3229 * handle OCR if FW is in HW critical error. 2. Wait for outstanding command
3230 * to complete for 180 seconds. 3. If #2 does not find any outstanding
3231 * command Controller is in working state, so skip OCR. Otherwise, do
3232 * OCR/kill Adapter based on flag disableOnlineCtrlReset. 4. Start of the
3233 * OCR, return all SCSI command back to CAM layer which has ccb_ptr. 5. Post
3234 * OCR, Re-fire Management command and move Controller to Operation state.
3235 */
3236 int
mrsas_reset_ctrl(struct mrsas_softc * sc,u_int8_t reset_reason)3237 mrsas_reset_ctrl(struct mrsas_softc *sc, u_int8_t reset_reason)
3238 {
3239 int retval = SUCCESS, i, j, retry = 0;
3240 u_int32_t host_diag, abs_state, status_reg, reset_adapter;
3241 union ccb *ccb;
3242 struct mrsas_mfi_cmd *mfi_cmd;
3243 struct mrsas_mpt_cmd *mpt_cmd;
3244 union mrsas_evt_class_locale class_locale;
3245 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc;
3246
3247 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) {
3248 device_printf(sc->mrsas_dev,
3249 "mrsas: Hardware critical error, returning FAIL.\n");
3250 return FAIL;
3251 }
3252 mrsas_set_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
3253 sc->adprecovery = MRSAS_ADPRESET_SM_INFAULT;
3254 mrsas_disable_intr(sc);
3255 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, "mrsas_ocr",
3256 sc->mrsas_fw_fault_check_delay * hz);
3257
3258 /* First try waiting for commands to complete */
3259 if (mrsas_wait_for_outstanding(sc, reset_reason)) {
3260 mrsas_dprint(sc, MRSAS_OCR,
3261 "resetting adapter from %s.\n",
3262 __func__);
3263 /* Now return commands back to the CAM layer */
3264 mtx_unlock(&sc->sim_lock);
3265 for (i = 0; i < sc->max_fw_cmds; i++) {
3266 mpt_cmd = sc->mpt_cmd_list[i];
3267
3268 if (mpt_cmd->peer_cmd) {
3269 mrsas_dprint(sc, MRSAS_OCR,
3270 "R1 FP command [%d] - (mpt_cmd) %p, (peer_cmd) %p\n",
3271 i, mpt_cmd, mpt_cmd->peer_cmd);
3272 }
3273
3274 if (mpt_cmd->ccb_ptr) {
3275 if (mpt_cmd->callout_owner) {
3276 ccb = (union ccb *)(mpt_cmd->ccb_ptr);
3277 ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
3278 mrsas_cmd_done(sc, mpt_cmd);
3279 } else {
3280 mpt_cmd->ccb_ptr = NULL;
3281 mrsas_release_mpt_cmd(mpt_cmd);
3282 }
3283 }
3284 }
3285
3286 mrsas_atomic_set(&sc->fw_outstanding, 0);
3287
3288 mtx_lock(&sc->sim_lock);
3289
3290 status_reg = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3291 outbound_scratch_pad));
3292 abs_state = status_reg & MFI_STATE_MASK;
3293 reset_adapter = status_reg & MFI_RESET_ADAPTER;
3294 if (sc->disableOnlineCtrlReset ||
3295 (abs_state == MFI_STATE_FAULT && !reset_adapter)) {
3296 /* Reset not supported, kill adapter */
3297 mrsas_dprint(sc, MRSAS_OCR, "Reset not supported, killing adapter.\n");
3298 mrsas_kill_hba(sc);
3299 retval = FAIL;
3300 goto out;
3301 }
3302 /* Now try to reset the chip */
3303 for (i = 0; i < MRSAS_FUSION_MAX_RESET_TRIES; i++) {
3304 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3305 MPI2_WRSEQ_FLUSH_KEY_VALUE);
3306 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3307 MPI2_WRSEQ_1ST_KEY_VALUE);
3308 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3309 MPI2_WRSEQ_2ND_KEY_VALUE);
3310 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3311 MPI2_WRSEQ_3RD_KEY_VALUE);
3312 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3313 MPI2_WRSEQ_4TH_KEY_VALUE);
3314 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3315 MPI2_WRSEQ_5TH_KEY_VALUE);
3316 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
3317 MPI2_WRSEQ_6TH_KEY_VALUE);
3318
3319 /* Check that the diag write enable (DRWE) bit is on */
3320 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3321 fusion_host_diag));
3322 retry = 0;
3323 while (!(host_diag & HOST_DIAG_WRITE_ENABLE)) {
3324 DELAY(100 * 1000);
3325 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3326 fusion_host_diag));
3327 if (retry++ == 100) {
3328 mrsas_dprint(sc, MRSAS_OCR,
3329 "Host diag unlock failed!\n");
3330 break;
3331 }
3332 }
3333 if (!(host_diag & HOST_DIAG_WRITE_ENABLE))
3334 continue;
3335
3336 /* Send chip reset command */
3337 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_host_diag),
3338 host_diag | HOST_DIAG_RESET_ADAPTER);
3339 DELAY(3000 * 1000);
3340
3341 /* Make sure reset adapter bit is cleared */
3342 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3343 fusion_host_diag));
3344 retry = 0;
3345 while (host_diag & HOST_DIAG_RESET_ADAPTER) {
3346 DELAY(100 * 1000);
3347 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3348 fusion_host_diag));
3349 if (retry++ == 1000) {
3350 mrsas_dprint(sc, MRSAS_OCR,
3351 "Diag reset adapter never cleared!\n");
3352 break;
3353 }
3354 }
3355 if (host_diag & HOST_DIAG_RESET_ADAPTER)
3356 continue;
3357
3358 abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3359 outbound_scratch_pad)) & MFI_STATE_MASK;
3360 retry = 0;
3361
3362 while ((abs_state <= MFI_STATE_FW_INIT) && (retry++ < 1000)) {
3363 DELAY(100 * 1000);
3364 abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3365 outbound_scratch_pad)) & MFI_STATE_MASK;
3366 }
3367 if (abs_state <= MFI_STATE_FW_INIT) {
3368 mrsas_dprint(sc, MRSAS_OCR, "firmware state < MFI_STATE_FW_INIT,"
3369 " state = 0x%x\n", abs_state);
3370 continue;
3371 }
3372 /* Wait for FW to become ready */
3373 if (mrsas_transition_to_ready(sc, 1)) {
3374 mrsas_dprint(sc, MRSAS_OCR,
3375 "mrsas: Failed to transition controller to ready.\n");
3376 continue;
3377 }
3378 mrsas_reset_reply_desc(sc);
3379 if (mrsas_ioc_init(sc)) {
3380 mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n");
3381 continue;
3382 }
3383 for (j = 0; j < sc->max_fw_cmds; j++) {
3384 mpt_cmd = sc->mpt_cmd_list[j];
3385 if (mpt_cmd->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
3386 mfi_cmd = sc->mfi_cmd_list[mpt_cmd->sync_cmd_idx];
3387 /* If not an IOCTL then release the command else re-fire */
3388 if (!mfi_cmd->sync_cmd) {
3389 mrsas_release_mfi_cmd(mfi_cmd);
3390 } else {
3391 req_desc = mrsas_get_request_desc(sc,
3392 mfi_cmd->cmd_id.context.smid - 1);
3393 mrsas_dprint(sc, MRSAS_OCR,
3394 "Re-fire command DCMD opcode 0x%x index %d\n ",
3395 mfi_cmd->frame->dcmd.opcode, j);
3396 if (!req_desc)
3397 device_printf(sc->mrsas_dev,
3398 "Cannot build MPT cmd.\n");
3399 else
3400 mrsas_fire_cmd(sc, req_desc->addr.u.low,
3401 req_desc->addr.u.high);
3402 }
3403 }
3404 }
3405
3406 /* Reset load balance info */
3407 memset(sc->load_balance_info, 0,
3408 sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES_EXT);
3409
3410 if (mrsas_get_ctrl_info(sc)) {
3411 mrsas_kill_hba(sc);
3412 retval = FAIL;
3413 goto out;
3414 }
3415 if (!mrsas_get_map_info(sc))
3416 mrsas_sync_map_info(sc);
3417
3418 megasas_setup_jbod_map(sc);
3419
3420 if ((sc->is_ventura || sc->is_aero) && sc->streamDetectByLD) {
3421 for (j = 0; j < MAX_LOGICAL_DRIVES_EXT; ++j) {
3422 memset(sc->streamDetectByLD[i], 0, sizeof(LD_STREAM_DETECT));
3423 sc->streamDetectByLD[i]->mruBitMap = MR_STREAM_BITMAP;
3424 }
3425 }
3426
3427 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
3428 mrsas_enable_intr(sc);
3429 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
3430
3431 /* Register AEN with FW for last sequence number */
3432 class_locale.members.reserved = 0;
3433 class_locale.members.locale = MR_EVT_LOCALE_ALL;
3434 class_locale.members.class = MR_EVT_CLASS_DEBUG;
3435
3436 mtx_unlock(&sc->sim_lock);
3437 if (mrsas_register_aen(sc, sc->last_seq_num,
3438 class_locale.word)) {
3439 device_printf(sc->mrsas_dev,
3440 "ERROR: AEN registration FAILED from OCR !!! "
3441 "Further events from the controller cannot be notified."
3442 "Either there is some problem in the controller"
3443 "or the controller does not support AEN.\n"
3444 "Please contact to the SUPPORT TEAM if the problem persists\n");
3445 }
3446 mtx_lock(&sc->sim_lock);
3447
3448 /* Adapter reset completed successfully */
3449 device_printf(sc->mrsas_dev, "Reset successful\n");
3450 retval = SUCCESS;
3451 goto out;
3452 }
3453 /* Reset failed, kill the adapter */
3454 device_printf(sc->mrsas_dev, "Reset failed, killing adapter.\n");
3455 mrsas_kill_hba(sc);
3456 retval = FAIL;
3457 } else {
3458 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
3459 mrsas_enable_intr(sc);
3460 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
3461 }
3462 out:
3463 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
3464 mrsas_dprint(sc, MRSAS_OCR,
3465 "Reset Exit with %d.\n", retval);
3466 return retval;
3467 }
3468
3469 /*
3470 * mrsas_kill_hba: Kill HBA when OCR is not supported
3471 * input: Adapter Context.
3472 *
3473 * This function will kill HBA when OCR is not supported.
3474 */
3475 void
mrsas_kill_hba(struct mrsas_softc * sc)3476 mrsas_kill_hba(struct mrsas_softc *sc)
3477 {
3478 sc->adprecovery = MRSAS_HW_CRITICAL_ERROR;
3479 DELAY(1000 * 1000);
3480 mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__);
3481 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell),
3482 MFI_STOP_ADP);
3483 /* Flush */
3484 mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell));
3485 mrsas_complete_outstanding_ioctls(sc);
3486 }
3487
3488 /**
3489 * mrsas_complete_outstanding_ioctls Complete pending IOCTLS after kill_hba
3490 * input: Controller softc
3491 *
3492 * Returns void
3493 */
3494 void
mrsas_complete_outstanding_ioctls(struct mrsas_softc * sc)3495 mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc)
3496 {
3497 int i;
3498 struct mrsas_mpt_cmd *cmd_mpt;
3499 struct mrsas_mfi_cmd *cmd_mfi;
3500 u_int32_t count, MSIxIndex;
3501
3502 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
3503 for (i = 0; i < sc->max_fw_cmds; i++) {
3504 cmd_mpt = sc->mpt_cmd_list[i];
3505
3506 if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
3507 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
3508 if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) {
3509 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
3510 mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
3511 cmd_mpt->io_request->RaidContext.raid_context.status);
3512 }
3513 }
3514 }
3515 }
3516
3517 /*
3518 * mrsas_wait_for_outstanding: Wait for outstanding commands
3519 * input: Adapter Context.
3520 *
3521 * This function will wait for 180 seconds for outstanding commands to be
3522 * completed.
3523 */
3524 int
mrsas_wait_for_outstanding(struct mrsas_softc * sc,u_int8_t check_reason)3525 mrsas_wait_for_outstanding(struct mrsas_softc *sc, u_int8_t check_reason)
3526 {
3527 int i, outstanding, retval = 0;
3528 u_int32_t fw_state, count, MSIxIndex;
3529
3530 for (i = 0; i < MRSAS_RESET_WAIT_TIME; i++) {
3531 if (sc->remove_in_progress) {
3532 mrsas_dprint(sc, MRSAS_OCR,
3533 "Driver remove or shutdown called.\n");
3534 retval = 1;
3535 goto out;
3536 }
3537 /* Check if firmware is in fault state */
3538 fw_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
3539 outbound_scratch_pad)) & MFI_STATE_MASK;
3540 if (fw_state == MFI_STATE_FAULT) {
3541 mrsas_dprint(sc, MRSAS_OCR,
3542 "Found FW in FAULT state, will reset adapter.\n");
3543 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
3544 mtx_unlock(&sc->sim_lock);
3545 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
3546 mrsas_complete_cmd(sc, MSIxIndex);
3547 mtx_lock(&sc->sim_lock);
3548 retval = 1;
3549 goto out;
3550 }
3551 if (check_reason == MFI_DCMD_TIMEOUT_OCR) {
3552 mrsas_dprint(sc, MRSAS_OCR,
3553 "DCMD IO TIMEOUT detected, will reset adapter.\n");
3554 retval = 1;
3555 goto out;
3556 }
3557 outstanding = mrsas_atomic_read(&sc->fw_outstanding);
3558 if (!outstanding)
3559 goto out;
3560
3561 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) {
3562 mrsas_dprint(sc, MRSAS_OCR, "[%2d]waiting for %d "
3563 "commands to complete\n", i, outstanding);
3564 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
3565 mtx_unlock(&sc->sim_lock);
3566 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
3567 mrsas_complete_cmd(sc, MSIxIndex);
3568 mtx_lock(&sc->sim_lock);
3569 }
3570 DELAY(1000 * 1000);
3571 }
3572
3573 if (mrsas_atomic_read(&sc->fw_outstanding)) {
3574 mrsas_dprint(sc, MRSAS_OCR,
3575 " pending commands remain after waiting,"
3576 " will reset adapter.\n");
3577 retval = 1;
3578 }
3579 out:
3580 return retval;
3581 }
3582
3583 /*
3584 * mrsas_release_mfi_cmd: Return a cmd to free command pool
3585 * input: Command packet for return to free cmd pool
3586 *
3587 * This function returns the MFI & MPT command to the command list.
3588 */
3589 void
mrsas_release_mfi_cmd(struct mrsas_mfi_cmd * cmd_mfi)3590 mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd_mfi)
3591 {
3592 struct mrsas_softc *sc = cmd_mfi->sc;
3593 struct mrsas_mpt_cmd *cmd_mpt;
3594
3595 mtx_lock(&sc->mfi_cmd_pool_lock);
3596 /*
3597 * Release the mpt command (if at all it is allocated
3598 * associated with the mfi command
3599 */
3600 if (cmd_mfi->cmd_id.context.smid) {
3601 mtx_lock(&sc->mpt_cmd_pool_lock);
3602 /* Get the mpt cmd from mfi cmd frame's smid value */
3603 cmd_mpt = sc->mpt_cmd_list[cmd_mfi->cmd_id.context.smid-1];
3604 cmd_mpt->flags = 0;
3605 cmd_mpt->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX;
3606 TAILQ_INSERT_HEAD(&(sc->mrsas_mpt_cmd_list_head), cmd_mpt, next);
3607 mtx_unlock(&sc->mpt_cmd_pool_lock);
3608 }
3609 /* Release the mfi command */
3610 cmd_mfi->ccb_ptr = NULL;
3611 cmd_mfi->cmd_id.frame_count = 0;
3612 TAILQ_INSERT_HEAD(&(sc->mrsas_mfi_cmd_list_head), cmd_mfi, next);
3613 mtx_unlock(&sc->mfi_cmd_pool_lock);
3614
3615 return;
3616 }
3617
3618 /*
3619 * mrsas_get_controller_info: Returns FW's controller structure
3620 * input: Adapter soft state
3621 * Controller information structure
3622 *
3623 * Issues an internal command (DCMD) to get the FW's controller structure. This
3624 * information is mainly used to find out the maximum IO transfer per command
3625 * supported by the FW.
3626 */
3627 static int
mrsas_get_ctrl_info(struct mrsas_softc * sc)3628 mrsas_get_ctrl_info(struct mrsas_softc *sc)
3629 {
3630 int retcode = 0;
3631 u_int8_t do_ocr = 1;
3632 struct mrsas_mfi_cmd *cmd;
3633 struct mrsas_dcmd_frame *dcmd;
3634
3635 cmd = mrsas_get_mfi_cmd(sc);
3636
3637 if (!cmd) {
3638 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n");
3639 return -ENOMEM;
3640 }
3641 dcmd = &cmd->frame->dcmd;
3642
3643 if (mrsas_alloc_ctlr_info_cmd(sc) != SUCCESS) {
3644 device_printf(sc->mrsas_dev, "Cannot allocate get ctlr info cmd\n");
3645 mrsas_release_mfi_cmd(cmd);
3646 return -ENOMEM;
3647 }
3648 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
3649
3650 dcmd->cmd = MFI_CMD_DCMD;
3651 dcmd->cmd_status = 0xFF;
3652 dcmd->sge_count = 1;
3653 dcmd->flags = MFI_FRAME_DIR_READ;
3654 dcmd->timeout = 0;
3655 dcmd->pad_0 = 0;
3656 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_ctrl_info));
3657 dcmd->opcode = htole32(MR_DCMD_CTRL_GET_INFO);
3658 dcmd->sgl.sge32[0].phys_addr = htole32(sc->ctlr_info_phys_addr & 0xFFFFFFFF);
3659 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_ctrl_info));
3660
3661 if (!sc->mask_interrupts)
3662 retcode = mrsas_issue_blocked_cmd(sc, cmd);
3663 else
3664 retcode = mrsas_issue_polled(sc, cmd);
3665
3666 if (retcode == ETIMEDOUT)
3667 goto dcmd_timeout;
3668 else {
3669 memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
3670 le32_to_cpus(&sc->ctrl_info->properties.OnOffProperties);
3671 le32_to_cpus(&sc->ctrl_info->adapterOperations2);
3672 le32_to_cpus(&sc->ctrl_info->adapterOperations3);
3673 le16_to_cpus(&sc->ctrl_info->adapterOperations4);
3674 }
3675
3676 do_ocr = 0;
3677 mrsas_update_ext_vd_details(sc);
3678
3679 sc->use_seqnum_jbod_fp =
3680 sc->ctrl_info->adapterOperations3.useSeqNumJbodFP;
3681 sc->support_morethan256jbod =
3682 sc->ctrl_info->adapterOperations4.supportPdMapTargetId;
3683
3684 sc->disableOnlineCtrlReset =
3685 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
3686
3687 dcmd_timeout:
3688 mrsas_free_ctlr_info_cmd(sc);
3689
3690 if (do_ocr)
3691 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
3692
3693 if (!sc->mask_interrupts)
3694 mrsas_release_mfi_cmd(cmd);
3695
3696 return (retcode);
3697 }
3698
3699 /*
3700 * mrsas_update_ext_vd_details : Update details w.r.t Extended VD
3701 * input:
3702 * sc - Controller's softc
3703 */
3704 static void
mrsas_update_ext_vd_details(struct mrsas_softc * sc)3705 mrsas_update_ext_vd_details(struct mrsas_softc *sc)
3706 {
3707 u_int32_t ventura_map_sz = 0;
3708 sc->max256vdSupport =
3709 sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
3710
3711 /* Below is additional check to address future FW enhancement */
3712 if (sc->ctrl_info->max_lds > 64)
3713 sc->max256vdSupport = 1;
3714
3715 sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS
3716 * MRSAS_MAX_DEV_PER_CHANNEL;
3717 sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS
3718 * MRSAS_MAX_DEV_PER_CHANNEL;
3719 if (sc->max256vdSupport) {
3720 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
3721 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3722 } else {
3723 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
3724 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3725 }
3726
3727 if (sc->maxRaidMapSize) {
3728 ventura_map_sz = sc->maxRaidMapSize *
3729 MR_MIN_MAP_SIZE;
3730 sc->current_map_sz = ventura_map_sz;
3731 sc->max_map_sz = ventura_map_sz;
3732 } else {
3733 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
3734 (sizeof(MR_LD_SPAN_MAP) * (sc->fw_supported_vd_count - 1));
3735 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
3736 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
3737 if (sc->max256vdSupport)
3738 sc->current_map_sz = sc->new_map_sz;
3739 else
3740 sc->current_map_sz = sc->old_map_sz;
3741 }
3742
3743 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP_ALL);
3744 #if VD_EXT_DEBUG
3745 device_printf(sc->mrsas_dev, "sc->maxRaidMapSize 0x%x \n",
3746 sc->maxRaidMapSize);
3747 device_printf(sc->mrsas_dev,
3748 "new_map_sz = 0x%x, old_map_sz = 0x%x, "
3749 "ventura_map_sz = 0x%x, current_map_sz = 0x%x "
3750 "fusion->drv_map_sz =0x%x, size of driver raid map 0x%lx \n",
3751 sc->new_map_sz, sc->old_map_sz, ventura_map_sz,
3752 sc->current_map_sz, sc->drv_map_sz, sizeof(MR_DRV_RAID_MAP_ALL));
3753 #endif
3754 }
3755
3756 /*
3757 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command
3758 * input: Adapter soft state
3759 *
3760 * Allocates DMAable memory for the controller info internal command.
3761 */
3762 int
mrsas_alloc_ctlr_info_cmd(struct mrsas_softc * sc)3763 mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc)
3764 {
3765 int ctlr_info_size;
3766
3767 /* Allocate get controller info command */
3768 ctlr_info_size = sizeof(struct mrsas_ctrl_info);
3769 if (bus_dma_tag_create(sc->mrsas_parent_tag,
3770 1, 0,
3771 BUS_SPACE_MAXADDR_32BIT,
3772 BUS_SPACE_MAXADDR,
3773 NULL, NULL,
3774 ctlr_info_size,
3775 1,
3776 ctlr_info_size,
3777 BUS_DMA_ALLOCNOW,
3778 NULL, NULL,
3779 &sc->ctlr_info_tag)) {
3780 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info tag\n");
3781 return (ENOMEM);
3782 }
3783 if (bus_dmamem_alloc(sc->ctlr_info_tag, (void **)&sc->ctlr_info_mem,
3784 BUS_DMA_NOWAIT, &sc->ctlr_info_dmamap)) {
3785 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info cmd mem\n");
3786 return (ENOMEM);
3787 }
3788 if (bus_dmamap_load(sc->ctlr_info_tag, sc->ctlr_info_dmamap,
3789 sc->ctlr_info_mem, ctlr_info_size, mrsas_addr_cb,
3790 &sc->ctlr_info_phys_addr, BUS_DMA_NOWAIT)) {
3791 device_printf(sc->mrsas_dev, "Cannot load ctlr info cmd mem\n");
3792 return (ENOMEM);
3793 }
3794 memset(sc->ctlr_info_mem, 0, ctlr_info_size);
3795 return (0);
3796 }
3797
3798 /*
3799 * mrsas_free_ctlr_info_cmd: Free memory for controller info command
3800 * input: Adapter soft state
3801 *
3802 * Deallocates memory of the get controller info cmd.
3803 */
3804 void
mrsas_free_ctlr_info_cmd(struct mrsas_softc * sc)3805 mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc)
3806 {
3807 if (sc->ctlr_info_phys_addr)
3808 bus_dmamap_unload(sc->ctlr_info_tag, sc->ctlr_info_dmamap);
3809 if (sc->ctlr_info_mem != NULL)
3810 bus_dmamem_free(sc->ctlr_info_tag, sc->ctlr_info_mem, sc->ctlr_info_dmamap);
3811 if (sc->ctlr_info_tag != NULL)
3812 bus_dma_tag_destroy(sc->ctlr_info_tag);
3813 }
3814
3815 /*
3816 * mrsas_issue_polled: Issues a polling command
3817 * inputs: Adapter soft state
3818 * Command packet to be issued
3819 *
3820 * This function is for posting of internal commands to Firmware. MFI requires
3821 * the cmd_status to be set to 0xFF before posting. The maximun wait time of
3822 * the poll response timer is 180 seconds.
3823 */
3824 int
mrsas_issue_polled(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)3825 mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
3826 {
3827 struct mrsas_header *frame_hdr = &cmd->frame->hdr;
3828 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME;
3829 int i, retcode = SUCCESS;
3830
3831 frame_hdr->cmd_status = 0xFF;
3832 frame_hdr->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE);
3833
3834 /* Issue the frame using inbound queue port */
3835 if (mrsas_issue_dcmd(sc, cmd)) {
3836 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n");
3837 return (1);
3838 }
3839 /*
3840 * Poll response timer to wait for Firmware response. While this
3841 * timer with the DELAY call could block CPU, the time interval for
3842 * this is only 1 millisecond.
3843 */
3844 if (frame_hdr->cmd_status == 0xFF) {
3845 for (i = 0; i < (max_wait * 1000); i++) {
3846 if (frame_hdr->cmd_status == 0xFF)
3847 DELAY(1000);
3848 else
3849 break;
3850 }
3851 }
3852 if (frame_hdr->cmd_status == 0xFF) {
3853 device_printf(sc->mrsas_dev, "DCMD timed out after %d "
3854 "seconds from %s\n", max_wait, __func__);
3855 device_printf(sc->mrsas_dev, "DCMD opcode 0x%X\n",
3856 cmd->frame->dcmd.opcode);
3857 retcode = ETIMEDOUT;
3858 }
3859 return (retcode);
3860 }
3861
3862 /*
3863 * mrsas_issue_dcmd: Issues a MFI Pass thru cmd
3864 * input: Adapter soft state mfi cmd pointer
3865 *
3866 * This function is called by mrsas_issued_blocked_cmd() and
3867 * mrsas_issued_polled(), to build the MPT command and then fire the command
3868 * to Firmware.
3869 */
3870 int
mrsas_issue_dcmd(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)3871 mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
3872 {
3873 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc;
3874
3875 req_desc = mrsas_build_mpt_cmd(sc, cmd);
3876 if (!req_desc) {
3877 device_printf(sc->mrsas_dev, "Cannot build MPT cmd.\n");
3878 return (1);
3879 }
3880 mrsas_fire_cmd(sc, req_desc->addr.u.low, req_desc->addr.u.high);
3881
3882 return (0);
3883 }
3884
3885 /*
3886 * mrsas_build_mpt_cmd: Calls helper function to build Passthru cmd
3887 * input: Adapter soft state mfi cmd to build
3888 *
3889 * This function is called by mrsas_issue_cmd() to build the MPT-MFI passthru
3890 * command and prepares the MPT command to send to Firmware.
3891 */
3892 MRSAS_REQUEST_DESCRIPTOR_UNION *
mrsas_build_mpt_cmd(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)3893 mrsas_build_mpt_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
3894 {
3895 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc;
3896 u_int16_t index;
3897
3898 if (mrsas_build_mptmfi_passthru(sc, cmd)) {
3899 device_printf(sc->mrsas_dev, "Cannot build MPT-MFI passthru cmd.\n");
3900 return NULL;
3901 }
3902 index = cmd->cmd_id.context.smid;
3903
3904 req_desc = mrsas_get_request_desc(sc, index - 1);
3905 if (!req_desc)
3906 return NULL;
3907
3908 req_desc->addr.Words = 0;
3909 req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
3910
3911 req_desc->SCSIIO.SMID = htole16(index);
3912
3913 return (req_desc);
3914 }
3915
3916 /*
3917 * mrsas_build_mptmfi_passthru: Builds a MPT MFI Passthru command
3918 * input: Adapter soft state mfi cmd pointer
3919 *
3920 * The MPT command and the io_request are setup as a passthru command. The SGE
3921 * chain address is set to frame_phys_addr of the MFI command.
3922 */
3923 u_int8_t
mrsas_build_mptmfi_passthru(struct mrsas_softc * sc,struct mrsas_mfi_cmd * mfi_cmd)3924 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *mfi_cmd)
3925 {
3926 MPI25_IEEE_SGE_CHAIN64 *mpi25_ieee_chain;
3927 PTR_MRSAS_RAID_SCSI_IO_REQUEST io_req;
3928 struct mrsas_mpt_cmd *mpt_cmd;
3929 struct mrsas_header *frame_hdr = &mfi_cmd->frame->hdr;
3930
3931 mpt_cmd = mrsas_get_mpt_cmd(sc);
3932 if (!mpt_cmd)
3933 return (1);
3934
3935 /* Save the smid. To be used for returning the cmd */
3936 mfi_cmd->cmd_id.context.smid = mpt_cmd->index;
3937
3938 mpt_cmd->sync_cmd_idx = mfi_cmd->index;
3939
3940 /*
3941 * For cmds where the flag is set, store the flag and check on
3942 * completion. For cmds with this flag, don't call
3943 * mrsas_complete_cmd.
3944 */
3945
3946 if (frame_hdr->flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE))
3947 mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
3948
3949 io_req = mpt_cmd->io_request;
3950
3951 if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) {
3952 pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL;
3953
3954 sgl_ptr_end += sc->max_sge_in_main_msg - 1;
3955 sgl_ptr_end->Flags = 0;
3956 }
3957 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain;
3958
3959 io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST;
3960 io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4;
3961 io_req->ChainOffset = sc->chain_offset_mfi_pthru;
3962
3963 mpi25_ieee_chain->Address = htole64(mfi_cmd->frame_phys_addr);
3964
3965 mpi25_ieee_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT |
3966 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR;
3967
3968 mpi25_ieee_chain->Length = htole32(sc->max_chain_frame_sz);
3969
3970 return (0);
3971 }
3972
3973 /*
3974 * mrsas_issue_blocked_cmd: Synchronous wrapper around regular FW cmds
3975 * input: Adapter soft state Command to be issued
3976 *
3977 * This function waits on an event for the command to be returned from the ISR.
3978 * Max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME secs. Used for issuing
3979 * internal and ioctl commands.
3980 */
3981 int
mrsas_issue_blocked_cmd(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)3982 mrsas_issue_blocked_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
3983 {
3984 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME;
3985 unsigned long total_time = 0;
3986 int retcode = SUCCESS;
3987
3988 /* Initialize cmd_status */
3989 cmd->cmd_status = 0xFF;
3990
3991 /* Build MPT-MFI command for issue to FW */
3992 if (mrsas_issue_dcmd(sc, cmd)) {
3993 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n");
3994 return (1);
3995 }
3996 sc->chan = (void *)&cmd;
3997
3998 while (1) {
3999 if (cmd->cmd_status == 0xFF) {
4000 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz);
4001 } else
4002 break;
4003
4004 if (!cmd->sync_cmd) { /* cmd->sync will be set for an IOCTL
4005 * command */
4006 total_time++;
4007 if (total_time >= max_wait) {
4008 device_printf(sc->mrsas_dev,
4009 "Internal command timed out after %d seconds.\n", max_wait);
4010 retcode = 1;
4011 break;
4012 }
4013 }
4014 }
4015 sc->chan = NULL;
4016
4017 if (cmd->cmd_status == 0xFF) {
4018 device_printf(sc->mrsas_dev, "DCMD timed out after %d "
4019 "seconds from %s\n", max_wait, __func__);
4020 device_printf(sc->mrsas_dev, "DCMD opcode 0x%X\n",
4021 cmd->frame->dcmd.opcode);
4022 retcode = ETIMEDOUT;
4023 }
4024 return (retcode);
4025 }
4026
4027 /*
4028 * mrsas_complete_mptmfi_passthru: Completes a command
4029 * input: @sc: Adapter soft state
4030 * @cmd: Command to be completed
4031 * @status: cmd completion status
4032 *
4033 * This function is called from mrsas_complete_cmd() after an interrupt is
4034 * received from Firmware, and io_request->Function is
4035 * MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST.
4036 */
4037 void
mrsas_complete_mptmfi_passthru(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd,u_int8_t status)4038 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd,
4039 u_int8_t status)
4040 {
4041 struct mrsas_header *hdr = &cmd->frame->hdr;
4042 u_int8_t cmd_status = cmd->frame->hdr.cmd_status;
4043
4044 /* Reset the retry counter for future re-tries */
4045 cmd->retry_for_fw_reset = 0;
4046
4047 if (cmd->ccb_ptr)
4048 cmd->ccb_ptr = NULL;
4049
4050 switch (hdr->cmd) {
4051 case MFI_CMD_INVALID:
4052 device_printf(sc->mrsas_dev, "MFI_CMD_INVALID command.\n");
4053 break;
4054 case MFI_CMD_PD_SCSI_IO:
4055 case MFI_CMD_LD_SCSI_IO:
4056 /*
4057 * MFI_CMD_PD_SCSI_IO and MFI_CMD_LD_SCSI_IO could have been
4058 * issued either through an IO path or an IOCTL path. If it
4059 * was via IOCTL, we will send it to internal completion.
4060 */
4061 if (cmd->sync_cmd) {
4062 cmd->sync_cmd = 0;
4063 mrsas_wakeup(sc, cmd);
4064 break;
4065 }
4066 case MFI_CMD_SMP:
4067 case MFI_CMD_STP:
4068 case MFI_CMD_DCMD:
4069 /* Check for LD map update */
4070 if ((cmd->frame->dcmd.opcode == MR_DCMD_LD_MAP_GET_INFO) &&
4071 (cmd->frame->dcmd.mbox.b[1] == 1)) {
4072 sc->fast_path_io = 0;
4073 mtx_lock(&sc->raidmap_lock);
4074 sc->map_update_cmd = NULL;
4075 if (cmd_status != 0) {
4076 if (cmd_status != MFI_STAT_NOT_FOUND)
4077 device_printf(sc->mrsas_dev, "map sync failed, status=%x\n", cmd_status);
4078 else {
4079 mrsas_release_mfi_cmd(cmd);
4080 mtx_unlock(&sc->raidmap_lock);
4081 break;
4082 }
4083 } else
4084 sc->map_id++;
4085 mrsas_release_mfi_cmd(cmd);
4086 if (MR_ValidateMapInfo(sc))
4087 sc->fast_path_io = 0;
4088 else
4089 sc->fast_path_io = 1;
4090 mrsas_sync_map_info(sc);
4091 mtx_unlock(&sc->raidmap_lock);
4092 break;
4093 }
4094 if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET_INFO ||
4095 cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET) {
4096 sc->mrsas_aen_triggered = 0;
4097 }
4098 /* FW has an updated PD sequence */
4099 if ((cmd->frame->dcmd.opcode ==
4100 MR_DCMD_SYSTEM_PD_MAP_GET_INFO) &&
4101 (cmd->frame->dcmd.mbox.b[0] == 1)) {
4102 mtx_lock(&sc->raidmap_lock);
4103 sc->jbod_seq_cmd = NULL;
4104 mrsas_release_mfi_cmd(cmd);
4105
4106 if (cmd_status == MFI_STAT_OK) {
4107 sc->pd_seq_map_id++;
4108 /* Re-register a pd sync seq num cmd */
4109 if (megasas_sync_pd_seq_num(sc, true))
4110 sc->use_seqnum_jbod_fp = 0;
4111 } else {
4112 sc->use_seqnum_jbod_fp = 0;
4113 device_printf(sc->mrsas_dev,
4114 "Jbod map sync failed, status=%x\n", cmd_status);
4115 }
4116 mtx_unlock(&sc->raidmap_lock);
4117 break;
4118 }
4119 /* See if got an event notification */
4120 if (le32toh(cmd->frame->dcmd.opcode) == MR_DCMD_CTRL_EVENT_WAIT)
4121 mrsas_complete_aen(sc, cmd);
4122 else
4123 mrsas_wakeup(sc, cmd);
4124 break;
4125 case MFI_CMD_ABORT:
4126 /* Command issued to abort another cmd return */
4127 mrsas_complete_abort(sc, cmd);
4128 break;
4129 default:
4130 device_printf(sc->mrsas_dev, "Unknown command completed! [0x%X]\n", hdr->cmd);
4131 break;
4132 }
4133 }
4134
4135 /*
4136 * mrsas_wakeup: Completes an internal command
4137 * input: Adapter soft state
4138 * Command to be completed
4139 *
4140 * In mrsas_issue_blocked_cmd(), after a command is issued to Firmware, a wait
4141 * timer is started. This function is called from
4142 * mrsas_complete_mptmfi_passthru() as it completes the command, to wake up
4143 * from the command wait.
4144 */
4145 void
mrsas_wakeup(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)4146 mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
4147 {
4148 cmd->cmd_status = cmd->frame->io.cmd_status;
4149
4150 if (cmd->cmd_status == 0xFF)
4151 cmd->cmd_status = 0;
4152
4153 sc->chan = (void *)&cmd;
4154 wakeup_one((void *)&sc->chan);
4155 return;
4156 }
4157
4158 /*
4159 * mrsas_shutdown_ctlr: Instructs FW to shutdown the controller input:
4160 * Adapter soft state Shutdown/Hibernate
4161 *
4162 * This function issues a DCMD internal command to Firmware to initiate shutdown
4163 * of the controller.
4164 */
4165 static void
mrsas_shutdown_ctlr(struct mrsas_softc * sc,u_int32_t opcode)4166 mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode)
4167 {
4168 struct mrsas_mfi_cmd *cmd;
4169 struct mrsas_dcmd_frame *dcmd;
4170
4171 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)
4172 return;
4173
4174 cmd = mrsas_get_mfi_cmd(sc);
4175 if (!cmd) {
4176 device_printf(sc->mrsas_dev, "Cannot allocate for shutdown cmd.\n");
4177 return;
4178 }
4179 if (sc->aen_cmd)
4180 mrsas_issue_blocked_abort_cmd(sc, sc->aen_cmd);
4181 if (sc->map_update_cmd)
4182 mrsas_issue_blocked_abort_cmd(sc, sc->map_update_cmd);
4183 if (sc->jbod_seq_cmd)
4184 mrsas_issue_blocked_abort_cmd(sc, sc->jbod_seq_cmd);
4185
4186 dcmd = &cmd->frame->dcmd;
4187 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4188
4189 dcmd->cmd = MFI_CMD_DCMD;
4190 dcmd->cmd_status = 0x0;
4191 dcmd->sge_count = 0;
4192 dcmd->flags = MFI_FRAME_DIR_NONE;
4193 dcmd->timeout = 0;
4194 dcmd->pad_0 = 0;
4195 dcmd->data_xfer_len = 0;
4196 dcmd->opcode = opcode;
4197
4198 device_printf(sc->mrsas_dev, "Preparing to shut down controller.\n");
4199
4200 mrsas_issue_blocked_cmd(sc, cmd);
4201 mrsas_release_mfi_cmd(cmd);
4202
4203 return;
4204 }
4205
4206 /*
4207 * mrsas_flush_cache: Requests FW to flush all its caches input:
4208 * Adapter soft state
4209 *
4210 * This function is issues a DCMD internal command to Firmware to initiate
4211 * flushing of all caches.
4212 */
4213 static void
mrsas_flush_cache(struct mrsas_softc * sc)4214 mrsas_flush_cache(struct mrsas_softc *sc)
4215 {
4216 struct mrsas_mfi_cmd *cmd;
4217 struct mrsas_dcmd_frame *dcmd;
4218
4219 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)
4220 return;
4221
4222 cmd = mrsas_get_mfi_cmd(sc);
4223 if (!cmd) {
4224 device_printf(sc->mrsas_dev, "Cannot allocate for flush cache cmd.\n");
4225 return;
4226 }
4227 dcmd = &cmd->frame->dcmd;
4228 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4229
4230 dcmd->cmd = MFI_CMD_DCMD;
4231 dcmd->cmd_status = 0x0;
4232 dcmd->sge_count = 0;
4233 dcmd->flags = MFI_FRAME_DIR_NONE;
4234 dcmd->timeout = 0;
4235 dcmd->pad_0 = 0;
4236 dcmd->data_xfer_len = 0;
4237 dcmd->opcode = MR_DCMD_CTRL_CACHE_FLUSH;
4238 dcmd->mbox.b[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE;
4239
4240 mrsas_issue_blocked_cmd(sc, cmd);
4241 mrsas_release_mfi_cmd(cmd);
4242
4243 return;
4244 }
4245
4246 int
megasas_sync_pd_seq_num(struct mrsas_softc * sc,boolean_t pend)4247 megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend)
4248 {
4249 int retcode = 0;
4250 u_int8_t do_ocr = 1;
4251 struct mrsas_mfi_cmd *cmd;
4252 struct mrsas_dcmd_frame *dcmd;
4253 uint32_t pd_seq_map_sz;
4254 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_sync;
4255 bus_addr_t pd_seq_h;
4256
4257 pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) +
4258 (sizeof(struct MR_PD_CFG_SEQ) *
4259 (MAX_PHYSICAL_DEVICES - 1));
4260
4261 cmd = mrsas_get_mfi_cmd(sc);
4262 if (!cmd) {
4263 device_printf(sc->mrsas_dev,
4264 "Cannot alloc for ld map info cmd.\n");
4265 return 1;
4266 }
4267 dcmd = &cmd->frame->dcmd;
4268
4269 pd_sync = (void *)sc->jbodmap_mem[(sc->pd_seq_map_id & 1)];
4270 pd_seq_h = sc->jbodmap_phys_addr[(sc->pd_seq_map_id & 1)];
4271 if (!pd_sync) {
4272 device_printf(sc->mrsas_dev,
4273 "Failed to alloc mem for jbod map info.\n");
4274 mrsas_release_mfi_cmd(cmd);
4275 return (ENOMEM);
4276 }
4277 memset(pd_sync, 0, pd_seq_map_sz);
4278 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4279 dcmd->cmd = MFI_CMD_DCMD;
4280 dcmd->cmd_status = 0xFF;
4281 dcmd->sge_count = 1;
4282 dcmd->timeout = 0;
4283 dcmd->pad_0 = 0;
4284 dcmd->data_xfer_len = htole32(pd_seq_map_sz);
4285 dcmd->opcode = htole32(MR_DCMD_SYSTEM_PD_MAP_GET_INFO);
4286 dcmd->sgl.sge32[0].phys_addr = htole32(pd_seq_h & 0xFFFFFFFF);
4287 dcmd->sgl.sge32[0].length = htole32(pd_seq_map_sz);
4288
4289 if (pend) {
4290 dcmd->mbox.b[0] = MRSAS_DCMD_MBOX_PEND_FLAG;
4291 dcmd->flags = htole16(MFI_FRAME_DIR_WRITE);
4292 sc->jbod_seq_cmd = cmd;
4293 if (mrsas_issue_dcmd(sc, cmd)) {
4294 device_printf(sc->mrsas_dev,
4295 "Fail to send sync map info command.\n");
4296 return 1;
4297 } else
4298 return 0;
4299 } else
4300 dcmd->flags = htole16(MFI_FRAME_DIR_READ);
4301
4302 retcode = mrsas_issue_polled(sc, cmd);
4303 if (retcode == ETIMEDOUT)
4304 goto dcmd_timeout;
4305
4306 if (le32toh(pd_sync->count) > MAX_PHYSICAL_DEVICES) {
4307 device_printf(sc->mrsas_dev,
4308 "driver supports max %d JBOD, but FW reports %d\n",
4309 MAX_PHYSICAL_DEVICES, pd_sync->count);
4310 retcode = -EINVAL;
4311 }
4312 if (!retcode)
4313 sc->pd_seq_map_id++;
4314 do_ocr = 0;
4315
4316 dcmd_timeout:
4317 if (do_ocr)
4318 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
4319
4320 return (retcode);
4321 }
4322
4323 /*
4324 * mrsas_get_map_info: Load and validate RAID map input:
4325 * Adapter instance soft state
4326 *
4327 * This function calls mrsas_get_ld_map_info() and MR_ValidateMapInfo() to load
4328 * and validate RAID map. It returns 0 if successful, 1 other- wise.
4329 */
4330 static int
mrsas_get_map_info(struct mrsas_softc * sc)4331 mrsas_get_map_info(struct mrsas_softc *sc)
4332 {
4333 uint8_t retcode = 0;
4334
4335 sc->fast_path_io = 0;
4336 if (!mrsas_get_ld_map_info(sc)) {
4337 retcode = MR_ValidateMapInfo(sc);
4338 if (retcode == 0) {
4339 sc->fast_path_io = 1;
4340 return 0;
4341 }
4342 }
4343 return 1;
4344 }
4345
4346 /*
4347 * mrsas_get_ld_map_info: Get FW's ld_map structure input:
4348 * Adapter instance soft state
4349 *
4350 * Issues an internal command (DCMD) to get the FW's controller PD list
4351 * structure.
4352 */
4353 static int
mrsas_get_ld_map_info(struct mrsas_softc * sc)4354 mrsas_get_ld_map_info(struct mrsas_softc *sc)
4355 {
4356 int retcode = 0;
4357 struct mrsas_mfi_cmd *cmd;
4358 struct mrsas_dcmd_frame *dcmd;
4359 void *map;
4360 bus_addr_t map_phys_addr = 0;
4361
4362 cmd = mrsas_get_mfi_cmd(sc);
4363 if (!cmd) {
4364 device_printf(sc->mrsas_dev,
4365 "Cannot alloc for ld map info cmd.\n");
4366 return 1;
4367 }
4368 dcmd = &cmd->frame->dcmd;
4369
4370 map = (void *)sc->raidmap_mem[(sc->map_id & 1)];
4371 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id & 1)];
4372 if (!map) {
4373 device_printf(sc->mrsas_dev,
4374 "Failed to alloc mem for ld map info.\n");
4375 mrsas_release_mfi_cmd(cmd);
4376 return (ENOMEM);
4377 }
4378 memset(map, 0, sizeof(sc->max_map_sz));
4379 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4380
4381 dcmd->cmd = MFI_CMD_DCMD;
4382 dcmd->cmd_status = 0xFF;
4383 dcmd->sge_count = 1;
4384 dcmd->flags = htole16(MFI_FRAME_DIR_READ);
4385 dcmd->timeout = 0;
4386 dcmd->pad_0 = 0;
4387 dcmd->data_xfer_len = htole32(sc->current_map_sz);
4388 dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO);
4389 dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF);
4390 dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz);
4391
4392 retcode = mrsas_issue_polled(sc, cmd);
4393 if (retcode == ETIMEDOUT)
4394 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
4395
4396 return (retcode);
4397 }
4398
4399 /*
4400 * mrsas_sync_map_info: Get FW's ld_map structure input:
4401 * Adapter instance soft state
4402 *
4403 * Issues an internal command (DCMD) to get the FW's controller PD list
4404 * structure.
4405 */
4406 static int
mrsas_sync_map_info(struct mrsas_softc * sc)4407 mrsas_sync_map_info(struct mrsas_softc *sc)
4408 {
4409 int retcode = 0, i;
4410 struct mrsas_mfi_cmd *cmd;
4411 struct mrsas_dcmd_frame *dcmd;
4412 uint32_t size_sync_info, num_lds;
4413 MR_LD_TARGET_SYNC *target_map = NULL;
4414 MR_DRV_RAID_MAP_ALL *map;
4415 MR_LD_RAID *raid;
4416 MR_LD_TARGET_SYNC *ld_sync;
4417 bus_addr_t map_phys_addr = 0;
4418
4419 cmd = mrsas_get_mfi_cmd(sc);
4420 if (!cmd) {
4421 device_printf(sc->mrsas_dev, "Cannot alloc for sync map info cmd\n");
4422 return ENOMEM;
4423 }
4424 map = sc->ld_drv_map[sc->map_id & 1];
4425 num_lds = map->raidMap.ldCount;
4426
4427 dcmd = &cmd->frame->dcmd;
4428 size_sync_info = sizeof(MR_LD_TARGET_SYNC) * num_lds;
4429 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4430
4431 target_map = (MR_LD_TARGET_SYNC *) sc->raidmap_mem[(sc->map_id - 1) & 1];
4432 memset(target_map, 0, sc->max_map_sz);
4433
4434 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id - 1) & 1];
4435
4436 ld_sync = (MR_LD_TARGET_SYNC *) target_map;
4437
4438 for (i = 0; i < num_lds; i++, ld_sync++) {
4439 raid = MR_LdRaidGet(i, map);
4440 ld_sync->targetId = MR_GetLDTgtId(i, map);
4441 ld_sync->seqNum = raid->seqNum;
4442 }
4443
4444 dcmd->cmd = MFI_CMD_DCMD;
4445 dcmd->cmd_status = 0xFF;
4446 dcmd->sge_count = 1;
4447 dcmd->flags = htole16(MFI_FRAME_DIR_WRITE);
4448 dcmd->timeout = 0;
4449 dcmd->pad_0 = 0;
4450 dcmd->data_xfer_len = htole32(sc->current_map_sz);
4451 dcmd->mbox.b[0] = num_lds;
4452 dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG;
4453 dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO);
4454 dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF);
4455 dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz);
4456
4457 sc->map_update_cmd = cmd;
4458 if (mrsas_issue_dcmd(sc, cmd)) {
4459 device_printf(sc->mrsas_dev,
4460 "Fail to send sync map info command.\n");
4461 return (1);
4462 }
4463 return (retcode);
4464 }
4465
4466 /* Input: dcmd.opcode - MR_DCMD_PD_GET_INFO
4467 * dcmd.mbox.s[0] - deviceId for this physical drive
4468 * dcmd.sge IN - ptr to returned MR_PD_INFO structure
4469 * Desc: Firmware return the physical drive info structure
4470 *
4471 */
4472 static void
mrsas_get_pd_info(struct mrsas_softc * sc,u_int16_t device_id)4473 mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t device_id)
4474 {
4475 int retcode;
4476 u_int8_t do_ocr = 1;
4477 struct mrsas_mfi_cmd *cmd;
4478 struct mrsas_dcmd_frame *dcmd;
4479
4480 cmd = mrsas_get_mfi_cmd(sc);
4481
4482 if (!cmd) {
4483 device_printf(sc->mrsas_dev,
4484 "Cannot alloc for get PD info cmd\n");
4485 return;
4486 }
4487 dcmd = &cmd->frame->dcmd;
4488
4489 memset(sc->pd_info_mem, 0, sizeof(struct mrsas_pd_info));
4490 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4491
4492 dcmd->mbox.s[0] = htole16(device_id);
4493 dcmd->cmd = MFI_CMD_DCMD;
4494 dcmd->cmd_status = 0xFF;
4495 dcmd->sge_count = 1;
4496 dcmd->flags = MFI_FRAME_DIR_READ;
4497 dcmd->timeout = 0;
4498 dcmd->pad_0 = 0;
4499 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_pd_info));
4500 dcmd->opcode = htole32(MR_DCMD_PD_GET_INFO);
4501 dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->pd_info_phys_addr & 0xFFFFFFFF);
4502 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_pd_info));
4503
4504 if (!sc->mask_interrupts)
4505 retcode = mrsas_issue_blocked_cmd(sc, cmd);
4506 else
4507 retcode = mrsas_issue_polled(sc, cmd);
4508
4509 if (retcode == ETIMEDOUT)
4510 goto dcmd_timeout;
4511
4512 sc->target_list[device_id].interface_type =
4513 le16toh(sc->pd_info_mem->state.ddf.pdType.intf);
4514
4515 do_ocr = 0;
4516
4517 dcmd_timeout:
4518
4519 if (do_ocr)
4520 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
4521
4522 if (!sc->mask_interrupts)
4523 mrsas_release_mfi_cmd(cmd);
4524 }
4525
4526 /*
4527 * mrsas_add_target: Add target ID of system PD/VD to driver's data structure.
4528 * sc: Adapter's soft state
4529 * target_id: Unique target id per controller(managed by driver)
4530 * for system PDs- target ID ranges from 0 to (MRSAS_MAX_PD - 1)
4531 * for VDs- target ID ranges from MRSAS_MAX_PD to MRSAS_MAX_TM_TARGETS
4532 * return: void
4533 * Descripton: This function will be called whenever system PD or VD is created.
4534 */
mrsas_add_target(struct mrsas_softc * sc,u_int16_t target_id)4535 static void mrsas_add_target(struct mrsas_softc *sc,
4536 u_int16_t target_id)
4537 {
4538 sc->target_list[target_id].target_id = target_id;
4539
4540 device_printf(sc->mrsas_dev,
4541 "%s created target ID: 0x%x\n",
4542 (target_id < MRSAS_MAX_PD ? "System PD" : "VD"),
4543 (target_id < MRSAS_MAX_PD ? target_id : (target_id - MRSAS_MAX_PD)));
4544 /*
4545 * If interrupts are enabled, then only fire DCMD to get pd_info
4546 * for system PDs
4547 */
4548 if (!sc->mask_interrupts && sc->pd_info_mem &&
4549 (target_id < MRSAS_MAX_PD))
4550 mrsas_get_pd_info(sc, target_id);
4551
4552 }
4553
4554 /*
4555 * mrsas_remove_target: Remove target ID of system PD/VD from driver's data structure.
4556 * sc: Adapter's soft state
4557 * target_id: Unique target id per controller(managed by driver)
4558 * for system PDs- target ID ranges from 0 to (MRSAS_MAX_PD - 1)
4559 * for VDs- target ID ranges from MRSAS_MAX_PD to MRSAS_MAX_TM_TARGETS
4560 * return: void
4561 * Descripton: This function will be called whenever system PD or VD is deleted
4562 */
mrsas_remove_target(struct mrsas_softc * sc,u_int16_t target_id)4563 static void mrsas_remove_target(struct mrsas_softc *sc,
4564 u_int16_t target_id)
4565 {
4566 sc->target_list[target_id].target_id = 0xffff;
4567 device_printf(sc->mrsas_dev,
4568 "%s deleted target ID: 0x%x\n",
4569 (target_id < MRSAS_MAX_PD ? "System PD" : "VD"),
4570 (target_id < MRSAS_MAX_PD ? target_id : (target_id - MRSAS_MAX_PD)));
4571 }
4572
4573 /*
4574 * mrsas_get_pd_list: Returns FW's PD list structure input:
4575 * Adapter soft state
4576 *
4577 * Issues an internal command (DCMD) to get the FW's controller PD list
4578 * structure. This information is mainly used to find out about system
4579 * supported by Firmware.
4580 */
4581 static int
mrsas_get_pd_list(struct mrsas_softc * sc)4582 mrsas_get_pd_list(struct mrsas_softc *sc)
4583 {
4584 int retcode = 0, pd_index = 0, pd_count = 0, pd_list_size;
4585 u_int8_t do_ocr = 1;
4586 struct mrsas_mfi_cmd *cmd;
4587 struct mrsas_dcmd_frame *dcmd;
4588 struct MR_PD_LIST *pd_list_mem;
4589 struct MR_PD_ADDRESS *pd_addr;
4590 bus_addr_t pd_list_phys_addr = 0;
4591 struct mrsas_tmp_dcmd *tcmd;
4592 u_int16_t dev_id;
4593
4594 cmd = mrsas_get_mfi_cmd(sc);
4595 if (!cmd) {
4596 device_printf(sc->mrsas_dev,
4597 "Cannot alloc for get PD list cmd\n");
4598 return 1;
4599 }
4600 dcmd = &cmd->frame->dcmd;
4601
4602 tcmd = malloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT);
4603 pd_list_size = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST);
4604 if (mrsas_alloc_tmp_dcmd(sc, tcmd, pd_list_size) != SUCCESS) {
4605 device_printf(sc->mrsas_dev,
4606 "Cannot alloc dmamap for get PD list cmd\n");
4607 mrsas_release_mfi_cmd(cmd);
4608 mrsas_free_tmp_dcmd(tcmd);
4609 free(tcmd, M_MRSAS);
4610 return (ENOMEM);
4611 } else {
4612 pd_list_mem = tcmd->tmp_dcmd_mem;
4613 pd_list_phys_addr = tcmd->tmp_dcmd_phys_addr;
4614 }
4615 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4616
4617 dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST;
4618 dcmd->mbox.b[1] = 0;
4619 dcmd->cmd = MFI_CMD_DCMD;
4620 dcmd->cmd_status = 0xFF;
4621 dcmd->sge_count = 1;
4622 dcmd->flags = htole16(MFI_FRAME_DIR_READ);
4623 dcmd->timeout = 0;
4624 dcmd->pad_0 = 0;
4625 dcmd->data_xfer_len = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST));
4626 dcmd->opcode = htole32(MR_DCMD_PD_LIST_QUERY);
4627 dcmd->sgl.sge32[0].phys_addr = htole32(pd_list_phys_addr & 0xFFFFFFFF);
4628 dcmd->sgl.sge32[0].length = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST));
4629
4630 if (!sc->mask_interrupts)
4631 retcode = mrsas_issue_blocked_cmd(sc, cmd);
4632 else
4633 retcode = mrsas_issue_polled(sc, cmd);
4634
4635 if (retcode == ETIMEDOUT)
4636 goto dcmd_timeout;
4637
4638 /* Get the instance PD list */
4639 pd_count = MRSAS_MAX_PD;
4640 pd_addr = pd_list_mem->addr;
4641 if (le32toh(pd_list_mem->count) < pd_count) {
4642 memset(sc->local_pd_list, 0,
4643 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
4644 for (pd_index = 0; pd_index < le32toh(pd_list_mem->count); pd_index++) {
4645 dev_id = le16toh(pd_addr->deviceId);
4646 sc->local_pd_list[dev_id].tid = dev_id;
4647 sc->local_pd_list[dev_id].driveType =
4648 le16toh(pd_addr->scsiDevType);
4649 sc->local_pd_list[dev_id].driveState =
4650 MR_PD_STATE_SYSTEM;
4651 if (sc->target_list[dev_id].target_id == 0xffff)
4652 mrsas_add_target(sc, dev_id);
4653 pd_addr++;
4654 }
4655 for (pd_index = 0; pd_index < MRSAS_MAX_PD; pd_index++) {
4656 if ((sc->local_pd_list[pd_index].driveState !=
4657 MR_PD_STATE_SYSTEM) &&
4658 (sc->target_list[pd_index].target_id !=
4659 0xffff)) {
4660 mrsas_remove_target(sc, pd_index);
4661 }
4662 }
4663 /*
4664 * Use mutext/spinlock if pd_list component size increase more than
4665 * 32 bit.
4666 */
4667 memcpy(sc->pd_list, sc->local_pd_list, sizeof(sc->local_pd_list));
4668 do_ocr = 0;
4669 }
4670 dcmd_timeout:
4671 mrsas_free_tmp_dcmd(tcmd);
4672 free(tcmd, M_MRSAS);
4673
4674 if (do_ocr)
4675 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
4676
4677 if (!sc->mask_interrupts)
4678 mrsas_release_mfi_cmd(cmd);
4679
4680 return (retcode);
4681 }
4682
4683 /*
4684 * mrsas_get_ld_list: Returns FW's LD list structure input:
4685 * Adapter soft state
4686 *
4687 * Issues an internal command (DCMD) to get the FW's controller PD list
4688 * structure. This information is mainly used to find out about supported by
4689 * the FW.
4690 */
4691 static int
mrsas_get_ld_list(struct mrsas_softc * sc)4692 mrsas_get_ld_list(struct mrsas_softc *sc)
4693 {
4694 int ld_list_size, retcode = 0, ld_index = 0, ids = 0, drv_tgt_id;
4695 u_int8_t do_ocr = 1;
4696 struct mrsas_mfi_cmd *cmd;
4697 struct mrsas_dcmd_frame *dcmd;
4698 struct MR_LD_LIST *ld_list_mem;
4699 bus_addr_t ld_list_phys_addr = 0;
4700 struct mrsas_tmp_dcmd *tcmd;
4701
4702 cmd = mrsas_get_mfi_cmd(sc);
4703 if (!cmd) {
4704 device_printf(sc->mrsas_dev,
4705 "Cannot alloc for get LD list cmd\n");
4706 return 1;
4707 }
4708 dcmd = &cmd->frame->dcmd;
4709
4710 tcmd = malloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT);
4711 ld_list_size = sizeof(struct MR_LD_LIST);
4712 if (mrsas_alloc_tmp_dcmd(sc, tcmd, ld_list_size) != SUCCESS) {
4713 device_printf(sc->mrsas_dev,
4714 "Cannot alloc dmamap for get LD list cmd\n");
4715 mrsas_release_mfi_cmd(cmd);
4716 mrsas_free_tmp_dcmd(tcmd);
4717 free(tcmd, M_MRSAS);
4718 return (ENOMEM);
4719 } else {
4720 ld_list_mem = tcmd->tmp_dcmd_mem;
4721 ld_list_phys_addr = tcmd->tmp_dcmd_phys_addr;
4722 }
4723 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
4724
4725 if (sc->max256vdSupport)
4726 dcmd->mbox.b[0] = 1;
4727
4728 dcmd->cmd = MFI_CMD_DCMD;
4729 dcmd->cmd_status = 0xFF;
4730 dcmd->sge_count = 1;
4731 dcmd->flags = MFI_FRAME_DIR_READ;
4732 dcmd->timeout = 0;
4733 dcmd->data_xfer_len = htole32(sizeof(struct MR_LD_LIST));
4734 dcmd->opcode = htole32(MR_DCMD_LD_GET_LIST);
4735 dcmd->sgl.sge32[0].phys_addr = htole32(ld_list_phys_addr);
4736 dcmd->sgl.sge32[0].length = htole32(sizeof(struct MR_LD_LIST));
4737 dcmd->pad_0 = 0;
4738
4739 if (!sc->mask_interrupts)
4740 retcode = mrsas_issue_blocked_cmd(sc, cmd);
4741 else
4742 retcode = mrsas_issue_polled(sc, cmd);
4743
4744 if (retcode == ETIMEDOUT)
4745 goto dcmd_timeout;
4746
4747 #if VD_EXT_DEBUG
4748 printf("Number of LDs %d\n", ld_list_mem->ldCount);
4749 #endif
4750
4751 /* Get the instance LD list */
4752 if (le32toh(ld_list_mem->ldCount) <= sc->fw_supported_vd_count) {
4753 sc->CurLdCount = le32toh(ld_list_mem->ldCount);
4754 memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT);
4755 for (ld_index = 0; ld_index < le32toh(ld_list_mem->ldCount); ld_index++) {
4756 ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
4757 drv_tgt_id = ids + MRSAS_MAX_PD;
4758 if (ld_list_mem->ldList[ld_index].state != 0) {
4759 sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
4760 if (sc->target_list[drv_tgt_id].target_id ==
4761 0xffff)
4762 mrsas_add_target(sc, drv_tgt_id);
4763 } else {
4764 if (sc->target_list[drv_tgt_id].target_id !=
4765 0xffff)
4766 mrsas_remove_target(sc,
4767 drv_tgt_id);
4768 }
4769 }
4770
4771 do_ocr = 0;
4772 }
4773 dcmd_timeout:
4774 mrsas_free_tmp_dcmd(tcmd);
4775 free(tcmd, M_MRSAS);
4776
4777 if (do_ocr)
4778 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR;
4779 if (!sc->mask_interrupts)
4780 mrsas_release_mfi_cmd(cmd);
4781
4782 return (retcode);
4783 }
4784
4785 /*
4786 * mrsas_alloc_tmp_dcmd: Allocates memory for temporary command input:
4787 * Adapter soft state Temp command Size of allocation
4788 *
4789 * Allocates DMAable memory for a temporary internal command. The allocated
4790 * memory is initialized to all zeros upon successful loading of the dma
4791 * mapped memory.
4792 */
4793 int
mrsas_alloc_tmp_dcmd(struct mrsas_softc * sc,struct mrsas_tmp_dcmd * tcmd,int size)4794 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc,
4795 struct mrsas_tmp_dcmd *tcmd, int size)
4796 {
4797 if (bus_dma_tag_create(sc->mrsas_parent_tag,
4798 1, 0,
4799 BUS_SPACE_MAXADDR_32BIT,
4800 BUS_SPACE_MAXADDR,
4801 NULL, NULL,
4802 size,
4803 1,
4804 size,
4805 BUS_DMA_ALLOCNOW,
4806 NULL, NULL,
4807 &tcmd->tmp_dcmd_tag)) {
4808 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd tag\n");
4809 return (ENOMEM);
4810 }
4811 if (bus_dmamem_alloc(tcmd->tmp_dcmd_tag, (void **)&tcmd->tmp_dcmd_mem,
4812 BUS_DMA_NOWAIT, &tcmd->tmp_dcmd_dmamap)) {
4813 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd mem\n");
4814 return (ENOMEM);
4815 }
4816 if (bus_dmamap_load(tcmd->tmp_dcmd_tag, tcmd->tmp_dcmd_dmamap,
4817 tcmd->tmp_dcmd_mem, size, mrsas_addr_cb,
4818 &tcmd->tmp_dcmd_phys_addr, BUS_DMA_NOWAIT)) {
4819 device_printf(sc->mrsas_dev, "Cannot load tmp dcmd mem\n");
4820 return (ENOMEM);
4821 }
4822 memset(tcmd->tmp_dcmd_mem, 0, size);
4823 return (0);
4824 }
4825
4826 /*
4827 * mrsas_free_tmp_dcmd: Free memory for temporary command input:
4828 * temporary dcmd pointer
4829 *
4830 * Deallocates memory of the temporary command for use in the construction of
4831 * the internal DCMD.
4832 */
4833 void
mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd * tmp)4834 mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp)
4835 {
4836 if (tmp->tmp_dcmd_phys_addr)
4837 bus_dmamap_unload(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_dmamap);
4838 if (tmp->tmp_dcmd_mem != NULL)
4839 bus_dmamem_free(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_mem, tmp->tmp_dcmd_dmamap);
4840 if (tmp->tmp_dcmd_tag != NULL)
4841 bus_dma_tag_destroy(tmp->tmp_dcmd_tag);
4842 }
4843
4844 /*
4845 * mrsas_issue_blocked_abort_cmd: Aborts previously issued cmd input:
4846 * Adapter soft state Previously issued cmd to be aborted
4847 *
4848 * This function is used to abort previously issued commands, such as AEN and
4849 * RAID map sync map commands. The abort command is sent as a DCMD internal
4850 * command and subsequently the driver will wait for a return status. The
4851 * max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME seconds.
4852 */
4853 static int
mrsas_issue_blocked_abort_cmd(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd_to_abort)4854 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
4855 struct mrsas_mfi_cmd *cmd_to_abort)
4856 {
4857 struct mrsas_mfi_cmd *cmd;
4858 struct mrsas_abort_frame *abort_fr;
4859 u_int8_t retcode = 0;
4860 unsigned long total_time = 0;
4861 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME;
4862
4863 cmd = mrsas_get_mfi_cmd(sc);
4864 if (!cmd) {
4865 device_printf(sc->mrsas_dev, "Cannot alloc for abort cmd\n");
4866 return (1);
4867 }
4868 abort_fr = &cmd->frame->abort;
4869
4870 /* Prepare and issue the abort frame */
4871 abort_fr->cmd = MFI_CMD_ABORT;
4872 abort_fr->cmd_status = 0xFF;
4873 abort_fr->flags = 0;
4874 abort_fr->abort_context = cmd_to_abort->index;
4875 abort_fr->abort_mfi_phys_addr_lo = cmd_to_abort->frame_phys_addr;
4876 abort_fr->abort_mfi_phys_addr_hi = 0;
4877
4878 cmd->sync_cmd = 1;
4879 cmd->cmd_status = 0xFF;
4880
4881 if (mrsas_issue_dcmd(sc, cmd)) {
4882 device_printf(sc->mrsas_dev, "Fail to send abort command.\n");
4883 return (1);
4884 }
4885 /* Wait for this cmd to complete */
4886 sc->chan = (void *)&cmd;
4887 while (1) {
4888 if (cmd->cmd_status == 0xFF) {
4889 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz);
4890 } else
4891 break;
4892 total_time++;
4893 if (total_time >= max_wait) {
4894 device_printf(sc->mrsas_dev, "Abort cmd timed out after %d sec.\n", max_wait);
4895 retcode = 1;
4896 break;
4897 }
4898 }
4899
4900 cmd->sync_cmd = 0;
4901 mrsas_release_mfi_cmd(cmd);
4902 return (retcode);
4903 }
4904
4905 /*
4906 * mrsas_complete_abort: Completes aborting a command input:
4907 * Adapter soft state Cmd that was issued to abort another cmd
4908 *
4909 * The mrsas_issue_blocked_abort_cmd() function waits for the command status to
4910 * change after sending the command. This function is called from
4911 * mrsas_complete_mptmfi_passthru() to wake up the sleep thread associated.
4912 */
4913 void
mrsas_complete_abort(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)4914 mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
4915 {
4916 if (cmd->sync_cmd) {
4917 cmd->sync_cmd = 0;
4918 cmd->cmd_status = 0;
4919 sc->chan = (void *)&cmd;
4920 wakeup_one((void *)&sc->chan);
4921 }
4922 return;
4923 }
4924
4925 /*
4926 * mrsas_aen_handler: AEN processing callback function from thread context
4927 * input: Adapter soft state
4928 *
4929 * Asynchronous event handler
4930 */
4931 void
mrsas_aen_handler(struct mrsas_softc * sc)4932 mrsas_aen_handler(struct mrsas_softc *sc)
4933 {
4934 union mrsas_evt_class_locale class_locale;
4935 int doscan = 0;
4936 u_int32_t seq_num;
4937 int error, fail_aen = 0;
4938
4939 if (sc == NULL) {
4940 printf("invalid instance!\n");
4941 return;
4942 }
4943 if (sc->remove_in_progress || sc->reset_in_progress) {
4944 device_printf(sc->mrsas_dev, "Returning from %s, line no %d\n",
4945 __func__, __LINE__);
4946 return;
4947 }
4948 if (sc->evt_detail_mem) {
4949 switch (sc->evt_detail_mem->code) {
4950 case MR_EVT_PD_INSERTED:
4951 fail_aen = mrsas_get_pd_list(sc);
4952 if (!fail_aen)
4953 mrsas_bus_scan_sim(sc, sc->sim_1);
4954 else
4955 goto skip_register_aen;
4956 break;
4957 case MR_EVT_PD_REMOVED:
4958 fail_aen = mrsas_get_pd_list(sc);
4959 if (!fail_aen)
4960 mrsas_bus_scan_sim(sc, sc->sim_1);
4961 else
4962 goto skip_register_aen;
4963 break;
4964 case MR_EVT_LD_OFFLINE:
4965 case MR_EVT_CFG_CLEARED:
4966 case MR_EVT_LD_DELETED:
4967 mrsas_bus_scan_sim(sc, sc->sim_0);
4968 break;
4969 case MR_EVT_LD_CREATED:
4970 fail_aen = mrsas_get_ld_list(sc);
4971 if (!fail_aen)
4972 mrsas_bus_scan_sim(sc, sc->sim_0);
4973 else
4974 goto skip_register_aen;
4975 break;
4976 case MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED:
4977 case MR_EVT_FOREIGN_CFG_IMPORTED:
4978 case MR_EVT_LD_STATE_CHANGE:
4979 doscan = 1;
4980 break;
4981 case MR_EVT_CTRL_PROP_CHANGED:
4982 fail_aen = mrsas_get_ctrl_info(sc);
4983 if (fail_aen)
4984 goto skip_register_aen;
4985 break;
4986 default:
4987 break;
4988 }
4989 } else {
4990 device_printf(sc->mrsas_dev, "invalid evt_detail\n");
4991 return;
4992 }
4993 if (doscan) {
4994 fail_aen = mrsas_get_pd_list(sc);
4995 if (!fail_aen) {
4996 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 1\n");
4997 mrsas_bus_scan_sim(sc, sc->sim_1);
4998 } else
4999 goto skip_register_aen;
5000
5001 fail_aen = mrsas_get_ld_list(sc);
5002 if (!fail_aen) {
5003 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 0\n");
5004 mrsas_bus_scan_sim(sc, sc->sim_0);
5005 } else
5006 goto skip_register_aen;
5007 }
5008 seq_num = sc->evt_detail_mem->seq_num + 1;
5009
5010 /* Register AEN with FW for latest sequence number plus 1 */
5011 class_locale.members.reserved = 0;
5012 class_locale.members.locale = MR_EVT_LOCALE_ALL;
5013 class_locale.members.class = MR_EVT_CLASS_DEBUG;
5014
5015 if (sc->aen_cmd != NULL)
5016 return;
5017
5018 mtx_lock(&sc->aen_lock);
5019 error = mrsas_register_aen(sc, seq_num,
5020 class_locale.word);
5021 mtx_unlock(&sc->aen_lock);
5022
5023 if (error)
5024 device_printf(sc->mrsas_dev, "register aen failed error %x\n", error);
5025
5026 skip_register_aen:
5027 return;
5028
5029 }
5030
5031 /*
5032 * mrsas_complete_aen: Completes AEN command
5033 * input: Adapter soft state
5034 * Cmd that was issued to abort another cmd
5035 *
5036 * This function will be called from ISR and will continue event processing from
5037 * thread context by enqueuing task in ev_tq (callback function
5038 * "mrsas_aen_handler").
5039 */
5040 void
mrsas_complete_aen(struct mrsas_softc * sc,struct mrsas_mfi_cmd * cmd)5041 mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
5042 {
5043 /*
5044 * Don't signal app if it is just an aborted previously registered
5045 * aen
5046 */
5047 if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) {
5048 sc->mrsas_aen_triggered = 1;
5049 mtx_lock(&sc->aen_lock);
5050 if (sc->mrsas_poll_waiting) {
5051 sc->mrsas_poll_waiting = 0;
5052 selwakeup(&sc->mrsas_select);
5053 }
5054 mtx_unlock(&sc->aen_lock);
5055 } else
5056 cmd->abort_aen = 0;
5057
5058 sc->aen_cmd = NULL;
5059 mrsas_release_mfi_cmd(cmd);
5060
5061 taskqueue_enqueue(sc->ev_tq, &sc->ev_task);
5062
5063 return;
5064 }
5065
5066 static device_method_t mrsas_methods[] = {
5067 DEVMETHOD(device_probe, mrsas_probe),
5068 DEVMETHOD(device_attach, mrsas_attach),
5069 DEVMETHOD(device_detach, mrsas_detach),
5070 DEVMETHOD(device_shutdown, mrsas_shutdown),
5071 DEVMETHOD(device_suspend, mrsas_suspend),
5072 DEVMETHOD(device_resume, mrsas_resume),
5073 DEVMETHOD(bus_print_child, bus_generic_print_child),
5074 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
5075 {0, 0}
5076 };
5077
5078 static driver_t mrsas_driver = {
5079 "mrsas",
5080 mrsas_methods,
5081 sizeof(struct mrsas_softc)
5082 };
5083
5084 static devclass_t mrsas_devclass;
5085
5086 DRIVER_MODULE(mrsas, pci, mrsas_driver, mrsas_devclass, 0, 0);
5087 MODULE_DEPEND(mrsas, cam, 1, 1, 1);
5088