1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/acpi.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32
33 #include <drm/drm_device.h>
34
35 #include "atom.h"
36 #include "radeon.h"
37 #include "radeon_reg.h"
38
39 #if defined(__amd64__) || defined(__i386__)
40 #include <dev/isa/isareg.h>
41 #include <dev/isa/isavar.h>
42 #endif
43
44 #if defined (__loongson__)
45 #include <machine/autoconf.h>
46 #endif
47
48 /*
49 * BIOS.
50 */
51
52 /* If you boot an IGP board with a discrete card as the primary,
53 * the IGP rom is not accessible via the rom bar as the IGP rom is
54 * part of the system bios. On boot, the system bios puts a
55 * copy of the igp rom at the start of vram if a discrete card is
56 * present.
57 */
58 #ifdef __linux__
igp_read_bios_from_vram(struct radeon_device * rdev)59 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
60 {
61 uint8_t __iomem *bios;
62 resource_size_t vram_base;
63 resource_size_t size = 256 * 1024; /* ??? */
64
65 if (!(rdev->flags & RADEON_IS_IGP))
66 if (!radeon_card_posted(rdev))
67 return false;
68
69 rdev->bios = NULL;
70 vram_base = pci_resource_start(rdev->pdev, 0);
71 bios = ioremap(vram_base, size);
72 if (!bios) {
73 return false;
74 }
75
76 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
77 iounmap(bios);
78 return false;
79 }
80 rdev->bios = kmalloc(size, GFP_KERNEL);
81 if (rdev->bios == NULL) {
82 iounmap(bios);
83 return false;
84 }
85 memcpy_fromio(rdev->bios, bios, size);
86 iounmap(bios);
87 return true;
88 }
89 #else
igp_read_bios_from_vram(struct radeon_device * rdev)90 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
91 {
92 bus_size_t size = 256 * 1024; /* ??? */
93 bus_space_handle_t bsh;
94 bus_space_tag_t bst = rdev->memt;
95
96 if (!(rdev->flags & RADEON_IS_IGP))
97 if (!radeon_card_posted(rdev))
98 return false;
99
100 rdev->bios = NULL;
101
102 if (bus_space_map(bst, rdev->fb_aper_offset, size, 0, &bsh) != 0)
103 return false;
104
105 rdev->bios = kmalloc(size, GFP_KERNEL);
106 bus_space_read_region_1(rdev->memt, bsh, 0, rdev->bios, size);
107 bus_space_unmap(bst, bsh, size);
108
109 if (size == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
110 kfree(rdev->bios);
111 rdev->bios = NULL;
112 return false;
113 }
114
115 return true;
116 }
117 #endif
118
119 #ifdef __linux__
radeon_read_bios(struct radeon_device * rdev)120 static bool radeon_read_bios(struct radeon_device *rdev)
121 {
122 uint8_t __iomem *bios, val1, val2;
123 size_t size;
124
125 rdev->bios = NULL;
126 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
127 bios = pci_map_rom(rdev->pdev, &size);
128 if (!bios) {
129 return false;
130 }
131
132 val1 = readb(&bios[0]);
133 val2 = readb(&bios[1]);
134
135 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
136 pci_unmap_rom(rdev->pdev, bios);
137 return false;
138 }
139 rdev->bios = kzalloc(size, GFP_KERNEL);
140 if (rdev->bios == NULL) {
141 pci_unmap_rom(rdev->pdev, bios);
142 return false;
143 }
144 memcpy_fromio(rdev->bios, bios, size);
145 pci_unmap_rom(rdev->pdev, bios);
146 return true;
147 }
148 #else
radeon_read_bios(struct radeon_device * rdev)149 static bool radeon_read_bios(struct radeon_device *rdev)
150 {
151 bus_size_t size;
152 pcireg_t address, mask;
153 bus_space_handle_t romh;
154 int rc;
155
156 rdev->bios = NULL;
157 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
158
159 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);
160 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
161 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);
162 address |= PCI_ROM_ENABLE;
163 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address);
164
165 size = PCI_ROM_SIZE(mask);
166 if (size == 0)
167 return false;
168 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 0, &romh);
169 if (rc != 0) {
170 printf(": can't map PCI ROM (%d)\n", rc);
171 return false;
172 }
173
174 rdev->bios = kmalloc(size, GFP_KERNEL);
175 bus_space_read_region_1(rdev->memt, romh, 0, rdev->bios, size);
176 bus_space_unmap(rdev->memt, romh, size);
177
178 if (size == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
179 kfree(rdev->bios);
180 rdev->bios = NULL;
181 return false;
182 }
183 return true;
184 }
185
186 #endif
187
188 #ifdef __linux__
radeon_read_platform_bios(struct radeon_device * rdev)189 static bool radeon_read_platform_bios(struct radeon_device *rdev)
190 {
191 phys_addr_t rom = rdev->pdev->rom;
192 size_t romlen = rdev->pdev->romlen;
193 void __iomem *bios;
194
195 rdev->bios = NULL;
196
197 if (!rom || romlen == 0)
198 return false;
199
200 rdev->bios = kzalloc(romlen, GFP_KERNEL);
201 if (!rdev->bios)
202 return false;
203
204 bios = ioremap(rom, romlen);
205 if (!bios)
206 goto free_bios;
207
208 memcpy_fromio(rdev->bios, bios, romlen);
209 iounmap(bios);
210
211 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
212 goto free_bios;
213
214 return true;
215 free_bios:
216 kfree(rdev->bios);
217 return false;
218 }
219 #else
radeon_read_platform_bios(struct radeon_device * rdev)220 static bool radeon_read_platform_bios(struct radeon_device *rdev)
221 {
222 #if defined(__amd64__) || defined(__i386__) || defined(__loongson__)
223 uint8_t __iomem *bios;
224 bus_size_t size = 256 * 1024; /* ??? */
225 uint8_t *found = NULL;
226 int i;
227
228 if (!(rdev->flags & RADEON_IS_IGP))
229 if (!radeon_card_posted(rdev))
230 return false;
231
232 rdev->bios = NULL;
233
234 #if defined(__loongson__)
235 if (loongson_videobios == NULL)
236 return false;
237 bios = loongson_videobios;
238 #else
239 bios = (u8 *)ISA_HOLE_VADDR(0xc0000);
240 #endif
241
242 for (i = 0; i + 2 < size; i++) {
243 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) {
244 found = bios + i;
245 break;
246 }
247
248 }
249 if (found == NULL) {
250 DRM_ERROR("bios size zero or checksum mismatch\n");
251 return false;
252 }
253
254 rdev->bios = kmalloc(size, GFP_KERNEL);
255 if (rdev->bios == NULL)
256 return false;
257
258 memcpy(rdev->bios, found, size);
259
260 return true;
261 #endif
262 return false;
263 }
264 #endif
265
266 #ifdef CONFIG_ACPI
267 /* ATRM is used to get the BIOS on the discrete cards in
268 * dual-gpu systems.
269 */
270 /* retrieve the ROM in 4k blocks */
271 #define ATRM_BIOS_PAGE 4096
272 /**
273 * radeon_atrm_call - fetch a chunk of the vbios
274 *
275 * @atrm_handle: acpi ATRM handle
276 * @bios: vbios image pointer
277 * @offset: offset of vbios image data to fetch
278 * @len: length of vbios image data to fetch
279 *
280 * Executes ATRM to fetch a chunk of the discrete
281 * vbios image on PX systems (all asics).
282 * Returns the length of the buffer fetched.
283 */
radeon_atrm_call(acpi_handle atrm_handle,uint8_t * bios,int offset,int len)284 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
285 int offset, int len)
286 {
287 acpi_status status;
288 union acpi_object atrm_arg_elements[2], *obj;
289 struct acpi_object_list atrm_arg;
290 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
291
292 atrm_arg.count = 2;
293 atrm_arg.pointer = &atrm_arg_elements[0];
294
295 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
296 atrm_arg_elements[0].integer.value = offset;
297
298 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
299 atrm_arg_elements[1].integer.value = len;
300
301 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
302 if (ACPI_FAILURE(status)) {
303 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
304 return -ENODEV;
305 }
306
307 obj = (union acpi_object *)buffer.pointer;
308 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
309 len = obj->buffer.length;
310 kfree(buffer.pointer);
311 return len;
312 }
313
radeon_atrm_get_bios(struct radeon_device * rdev)314 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
315 {
316 int ret;
317 int size = 256 * 1024;
318 int i;
319 struct pci_dev *pdev = NULL;
320 acpi_handle dhandle, atrm_handle;
321 acpi_status status;
322 bool found = false;
323
324 /* ATRM is for the discrete card only */
325 if (rdev->flags & RADEON_IS_IGP)
326 return false;
327
328 #ifdef notyet
329 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) {
330 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) &&
331 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8))
332 continue;
333
334 dhandle = ACPI_HANDLE(&pdev->dev);
335 if (!dhandle)
336 continue;
337
338 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
339 if (ACPI_SUCCESS(status)) {
340 found = true;
341 break;
342 }
343 }
344 #else
345 {
346 pdev = rdev->pdev;
347 dhandle = ACPI_HANDLE(&pdev->dev);
348
349 if (dhandle) {
350 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
351 if (ACPI_SUCCESS(status)) {
352 found = true;
353 }
354 }
355 }
356 #endif
357
358 if (!found)
359 return false;
360 pci_dev_put(pdev);
361
362 rdev->bios = kmalloc(size, GFP_KERNEL);
363 if (!rdev->bios) {
364 DRM_ERROR("Unable to allocate bios\n");
365 return false;
366 }
367
368 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
369 ret = radeon_atrm_call(atrm_handle,
370 rdev->bios,
371 (i * ATRM_BIOS_PAGE),
372 ATRM_BIOS_PAGE);
373 if (ret < ATRM_BIOS_PAGE)
374 break;
375 }
376
377 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
378 kfree(rdev->bios);
379 return false;
380 }
381 return true;
382 }
383 #else
radeon_atrm_get_bios(struct radeon_device * rdev)384 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
385 {
386 return false;
387 }
388 #endif
389
ni_read_disabled_bios(struct radeon_device * rdev)390 static bool ni_read_disabled_bios(struct radeon_device *rdev)
391 {
392 u32 bus_cntl;
393 u32 d1vga_control;
394 u32 d2vga_control;
395 u32 vga_render_control;
396 u32 rom_cntl;
397 bool r;
398
399 bus_cntl = RREG32(R600_BUS_CNTL);
400 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
401 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
402 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
403 rom_cntl = RREG32(R600_ROM_CNTL);
404
405 /* enable the rom */
406 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
407 if (!ASIC_IS_NODCE(rdev)) {
408 /* Disable VGA mode */
409 WREG32(AVIVO_D1VGA_CONTROL,
410 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
411 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
412 WREG32(AVIVO_D2VGA_CONTROL,
413 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
414 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
415 WREG32(AVIVO_VGA_RENDER_CONTROL,
416 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
417 }
418 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
419
420 r = radeon_read_bios(rdev);
421
422 /* restore regs */
423 WREG32(R600_BUS_CNTL, bus_cntl);
424 if (!ASIC_IS_NODCE(rdev)) {
425 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
426 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
427 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
428 }
429 WREG32(R600_ROM_CNTL, rom_cntl);
430 return r;
431 }
432
r700_read_disabled_bios(struct radeon_device * rdev)433 static bool r700_read_disabled_bios(struct radeon_device *rdev)
434 {
435 uint32_t viph_control;
436 uint32_t bus_cntl;
437 uint32_t d1vga_control;
438 uint32_t d2vga_control;
439 uint32_t vga_render_control;
440 uint32_t rom_cntl;
441 uint32_t cg_spll_func_cntl = 0;
442 uint32_t cg_spll_status;
443 bool r;
444
445 viph_control = RREG32(RADEON_VIPH_CONTROL);
446 bus_cntl = RREG32(R600_BUS_CNTL);
447 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
448 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
449 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
450 rom_cntl = RREG32(R600_ROM_CNTL);
451
452 /* disable VIP */
453 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
454 /* enable the rom */
455 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
456 /* Disable VGA mode */
457 WREG32(AVIVO_D1VGA_CONTROL,
458 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
459 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
460 WREG32(AVIVO_D2VGA_CONTROL,
461 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
462 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
463 WREG32(AVIVO_VGA_RENDER_CONTROL,
464 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
465
466 if (rdev->family == CHIP_RV730) {
467 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
468
469 /* enable bypass mode */
470 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
471 R600_SPLL_BYPASS_EN));
472
473 /* wait for SPLL_CHG_STATUS to change to 1 */
474 cg_spll_status = 0;
475 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
476 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
477
478 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
479 } else
480 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
481
482 r = radeon_read_bios(rdev);
483
484 /* restore regs */
485 if (rdev->family == CHIP_RV730) {
486 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
487
488 /* wait for SPLL_CHG_STATUS to change to 1 */
489 cg_spll_status = 0;
490 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
491 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
492 }
493 WREG32(RADEON_VIPH_CONTROL, viph_control);
494 WREG32(R600_BUS_CNTL, bus_cntl);
495 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
496 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
497 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
498 WREG32(R600_ROM_CNTL, rom_cntl);
499 return r;
500 }
501
r600_read_disabled_bios(struct radeon_device * rdev)502 static bool r600_read_disabled_bios(struct radeon_device *rdev)
503 {
504 uint32_t viph_control;
505 uint32_t bus_cntl;
506 uint32_t d1vga_control;
507 uint32_t d2vga_control;
508 uint32_t vga_render_control;
509 uint32_t rom_cntl;
510 uint32_t general_pwrmgt;
511 uint32_t low_vid_lower_gpio_cntl;
512 uint32_t medium_vid_lower_gpio_cntl;
513 uint32_t high_vid_lower_gpio_cntl;
514 uint32_t ctxsw_vid_lower_gpio_cntl;
515 uint32_t lower_gpio_enable;
516 bool r;
517
518 /*
519 * Some machines with RV610 running amd64 pass initial checks but later
520 * fail atombios specific checks. Return early here so the bios will be
521 * read from 0xc0000 in radeon_read_platform_bios() instead.
522 * RV610 0x1002:0x94C3 0x1028:0x0402 0x00
523 * RV610 0x1002:0x94C1 0x1028:0x0D02 0x00
524 */
525 if (rdev->family == CHIP_RV610)
526 return false;
527
528 viph_control = RREG32(RADEON_VIPH_CONTROL);
529 bus_cntl = RREG32(R600_BUS_CNTL);
530 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
531 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
532 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
533 rom_cntl = RREG32(R600_ROM_CNTL);
534 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
535 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
536 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
537 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
538 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
539 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
540
541 /* disable VIP */
542 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
543 /* enable the rom */
544 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
545 /* Disable VGA mode */
546 WREG32(AVIVO_D1VGA_CONTROL,
547 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
548 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
549 WREG32(AVIVO_D2VGA_CONTROL,
550 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
551 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
552 WREG32(AVIVO_VGA_RENDER_CONTROL,
553 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
554
555 WREG32(R600_ROM_CNTL,
556 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
557 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
558 R600_SCK_OVERWRITE));
559
560 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
561 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
562 (low_vid_lower_gpio_cntl & ~0x400));
563 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
564 (medium_vid_lower_gpio_cntl & ~0x400));
565 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
566 (high_vid_lower_gpio_cntl & ~0x400));
567 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
568 (ctxsw_vid_lower_gpio_cntl & ~0x400));
569 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
570
571 r = radeon_read_bios(rdev);
572
573 /* restore regs */
574 WREG32(RADEON_VIPH_CONTROL, viph_control);
575 WREG32(R600_BUS_CNTL, bus_cntl);
576 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
577 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
578 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
579 WREG32(R600_ROM_CNTL, rom_cntl);
580 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
581 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
582 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
583 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
584 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
585 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
586 return r;
587 }
588
avivo_read_disabled_bios(struct radeon_device * rdev)589 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
590 {
591 uint32_t seprom_cntl1;
592 uint32_t viph_control;
593 uint32_t bus_cntl;
594 uint32_t d1vga_control;
595 uint32_t d2vga_control;
596 uint32_t vga_render_control;
597 uint32_t gpiopad_a;
598 uint32_t gpiopad_en;
599 uint32_t gpiopad_mask;
600 bool r;
601
602 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
603 viph_control = RREG32(RADEON_VIPH_CONTROL);
604 bus_cntl = RREG32(RV370_BUS_CNTL);
605 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
606 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
607 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
608 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
609 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
610 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
611
612 WREG32(RADEON_SEPROM_CNTL1,
613 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
614 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
615 WREG32(RADEON_GPIOPAD_A, 0);
616 WREG32(RADEON_GPIOPAD_EN, 0);
617 WREG32(RADEON_GPIOPAD_MASK, 0);
618
619 /* disable VIP */
620 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
621
622 /* enable the rom */
623 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
624
625 /* Disable VGA mode */
626 WREG32(AVIVO_D1VGA_CONTROL,
627 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
628 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
629 WREG32(AVIVO_D2VGA_CONTROL,
630 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
631 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
632 WREG32(AVIVO_VGA_RENDER_CONTROL,
633 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
634
635 r = radeon_read_bios(rdev);
636
637 /* restore regs */
638 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
639 WREG32(RADEON_VIPH_CONTROL, viph_control);
640 WREG32(RV370_BUS_CNTL, bus_cntl);
641 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
642 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
643 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
644 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
645 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
646 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
647 return r;
648 }
649
legacy_read_disabled_bios(struct radeon_device * rdev)650 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
651 {
652 uint32_t seprom_cntl1;
653 uint32_t viph_control;
654 uint32_t bus_cntl;
655 uint32_t crtc_gen_cntl;
656 uint32_t crtc2_gen_cntl;
657 uint32_t crtc_ext_cntl;
658 uint32_t fp2_gen_cntl;
659 bool r;
660
661 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
662 viph_control = RREG32(RADEON_VIPH_CONTROL);
663 if (rdev->flags & RADEON_IS_PCIE)
664 bus_cntl = RREG32(RV370_BUS_CNTL);
665 else
666 bus_cntl = RREG32(RADEON_BUS_CNTL);
667 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
668 crtc2_gen_cntl = 0;
669 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
670 fp2_gen_cntl = 0;
671
672 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
673 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
674 }
675
676 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
677 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
678 }
679
680 WREG32(RADEON_SEPROM_CNTL1,
681 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
682 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
683
684 /* disable VIP */
685 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
686
687 /* enable the rom */
688 if (rdev->flags & RADEON_IS_PCIE)
689 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
690 else
691 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
692
693 /* Turn off mem requests and CRTC for both controllers */
694 WREG32(RADEON_CRTC_GEN_CNTL,
695 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
696 (RADEON_CRTC_DISP_REQ_EN_B |
697 RADEON_CRTC_EXT_DISP_EN)));
698 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
699 WREG32(RADEON_CRTC2_GEN_CNTL,
700 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
701 RADEON_CRTC2_DISP_REQ_EN_B));
702 }
703 /* Turn off CRTC */
704 WREG32(RADEON_CRTC_EXT_CNTL,
705 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
706 (RADEON_CRTC_SYNC_TRISTAT |
707 RADEON_CRTC_DISPLAY_DIS)));
708
709 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
710 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
711 }
712
713 r = radeon_read_bios(rdev);
714
715 /* restore regs */
716 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
717 WREG32(RADEON_VIPH_CONTROL, viph_control);
718 if (rdev->flags & RADEON_IS_PCIE)
719 WREG32(RV370_BUS_CNTL, bus_cntl);
720 else
721 WREG32(RADEON_BUS_CNTL, bus_cntl);
722 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
723 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
724 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
725 }
726 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
727 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
728 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
729 }
730 return r;
731 }
732
radeon_read_disabled_bios(struct radeon_device * rdev)733 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
734 {
735 if (rdev->flags & RADEON_IS_IGP)
736 return igp_read_bios_from_vram(rdev);
737 else if (rdev->family >= CHIP_BARTS)
738 return ni_read_disabled_bios(rdev);
739 else if (rdev->family >= CHIP_RV770)
740 return r700_read_disabled_bios(rdev);
741 else if (rdev->family >= CHIP_R600)
742 return r600_read_disabled_bios(rdev);
743 else if (rdev->family >= CHIP_RS600)
744 return avivo_read_disabled_bios(rdev);
745 else
746 return legacy_read_disabled_bios(rdev);
747 }
748
749 #ifdef CONFIG_ACPI
radeon_acpi_vfct_bios(struct radeon_device * rdev)750 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
751 {
752 struct acpi_table_header *hdr;
753 acpi_size tbl_size;
754 UEFI_ACPI_VFCT *vfct;
755 unsigned offset;
756 bool r = false;
757
758 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
759 return false;
760 tbl_size = hdr->length;
761 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
762 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
763 goto out;
764 }
765
766 vfct = (UEFI_ACPI_VFCT *)hdr;
767 offset = vfct->VBIOSImageOffset;
768
769 while (offset < tbl_size) {
770 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
771 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
772
773 offset += sizeof(VFCT_IMAGE_HEADER);
774 if (offset > tbl_size) {
775 DRM_ERROR("ACPI VFCT image header truncated\n");
776 goto out;
777 }
778
779 offset += vhdr->ImageLength;
780 if (offset > tbl_size) {
781 DRM_ERROR("ACPI VFCT image truncated\n");
782 goto out;
783 }
784
785 if (vhdr->ImageLength &&
786 vhdr->PCIBus == rdev->pdev->bus->number &&
787 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
788 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
789 vhdr->VendorID == rdev->pdev->vendor &&
790 vhdr->DeviceID == rdev->pdev->device) {
791 rdev->bios = kmemdup(&vbios->VbiosContent,
792 vhdr->ImageLength,
793 GFP_KERNEL);
794 if (rdev->bios)
795 r = true;
796
797 goto out;
798 }
799 }
800
801 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
802
803 out:
804 acpi_put_table(hdr);
805 return r;
806 }
807 #else
radeon_acpi_vfct_bios(struct radeon_device * rdev)808 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
809 {
810 return false;
811 }
812 #endif
813
radeon_get_bios(struct radeon_device * rdev)814 bool radeon_get_bios(struct radeon_device *rdev)
815 {
816 bool r;
817 uint16_t tmp;
818
819 r = radeon_atrm_get_bios(rdev);
820 if (!r)
821 r = radeon_acpi_vfct_bios(rdev);
822 if (!r)
823 r = igp_read_bios_from_vram(rdev);
824 if (!r)
825 r = radeon_read_bios(rdev);
826 if (!r)
827 r = radeon_read_disabled_bios(rdev);
828 if (!r)
829 r = radeon_read_platform_bios(rdev);
830 if (!r || rdev->bios == NULL) {
831 DRM_ERROR("Unable to locate a BIOS ROM\n");
832 rdev->bios = NULL;
833 return false;
834 }
835 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
836 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
837 goto free_bios;
838 }
839
840 tmp = RBIOS16(0x18);
841 if (RBIOS8(tmp + 0x14) != 0x0) {
842 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
843 goto free_bios;
844 }
845
846 rdev->bios_header_start = RBIOS16(0x48);
847 if (!rdev->bios_header_start) {
848 goto free_bios;
849 }
850 tmp = rdev->bios_header_start + 4;
851 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
852 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
853 rdev->is_atom_bios = true;
854 } else {
855 rdev->is_atom_bios = false;
856 }
857
858 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
859 return true;
860 free_bios:
861 kfree(rdev->bios);
862 rdev->bios = NULL;
863 return false;
864 }
865