1;; Arm M-profile Vector Extension Machine Description 2;; Copyright (C) 2019-2022 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but 12;; WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14;; General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_insn "*mve_mov<mode>" 21 [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Ux,w") 22 (match_operand:MVE_types 1 "general_operand" "w,r,w,Dn,UxUi,r,Dm,w,Ul"))] 23 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" 24{ 25 if (which_alternative == 3 || which_alternative == 6) 26 { 27 int width, is_valid; 28 static char templ[40]; 29 30 is_valid = simd_immediate_valid_for_move (operands[1], <MODE>mode, 31 &operands[1], &width); 32 33 gcc_assert (is_valid != 0); 34 35 if (width == 0) 36 return "vmov.f32\t%q0, %1 @ <mode>"; 37 else 38 sprintf (templ, "vmov.i%d\t%%q0, %%x1 @ <mode>", width); 39 return templ; 40 } 41 42 if (which_alternative == 4 || which_alternative == 7) 43 { 44 if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode || <MODE>mode == TImode) 45 { 46 if (which_alternative == 7) 47 output_asm_insn ("vstrw.32\t%q1, %E0", operands); 48 else 49 output_asm_insn ("vldrw.u32\t%q0, %E1",operands); 50 } 51 else 52 { 53 if (which_alternative == 7) 54 output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0", operands); 55 else 56 output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1", operands); 57 } 58 return ""; 59 } 60 switch (which_alternative) 61 { 62 case 0: 63 return "vmov\t%q0, %q1"; 64 case 1: 65 return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1"; 66 case 2: 67 return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1"; 68 case 5: 69 return output_move_quad (operands); 70 case 8: 71 return output_move_neon (operands); 72 default: 73 gcc_unreachable (); 74 return ""; 75 } 76} 77 [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_move,mve_store,mve_load") 78 (set_attr "length" "4,8,8,4,8,8,4,4,4") 79 (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*") 80 (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")]) 81 82(define_insn "*mve_vdup<mode>" 83 [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w") 84 (vec_duplicate:MVE_vecs 85 (match_operand:<V_elem> 1 "s_register_operand" "r")))] 86 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" 87 "vdup.<V_sz_elem>\t%q0, %1" 88 [(set_attr "length" "4") 89 (set_attr "type" "mve_move")]) 90 91;; 92;; [vst4q]) 93;; 94(define_insn "mve_vst4q<mode>" 95 [(set (match_operand:XI 0 "mve_struct_operand" "=Ug") 96 (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") 97 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 98 VST4Q)) 99 ] 100 "TARGET_HAVE_MVE" 101{ 102 rtx ops[6]; 103 int regno = REGNO (operands[1]); 104 ops[0] = gen_rtx_REG (TImode, regno); 105 ops[1] = gen_rtx_REG (TImode, regno+4); 106 ops[2] = gen_rtx_REG (TImode, regno+8); 107 ops[3] = gen_rtx_REG (TImode, regno+12); 108 rtx reg = operands[0]; 109 while (reg && !REG_P (reg)) 110 reg = XEXP (reg, 0); 111 gcc_assert (REG_P (reg)); 112 ops[4] = reg; 113 ops[5] = operands[0]; 114 /* Here in first three instructions data is stored to ops[4]'s location but 115 in the fourth instruction data is stored to operands[0], this is to 116 support the writeback. */ 117 output_asm_insn ("vst40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" 118 "vst41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" 119 "vst42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" 120 "vst43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); 121 return ""; 122} 123 [(set_attr "length" "16")]) 124 125;; 126;; [vrndq_m_f]) 127;; 128(define_insn "mve_vrndq_m_f<mode>" 129 [ 130 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 131 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 132 (match_operand:MVE_0 2 "s_register_operand" "w") 133 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 134 VRNDQ_M_F)) 135 ] 136 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 137 "vpst\;vrintzt.f%#<V_sz_elem>\t%q0, %q2" 138 [(set_attr "type" "mve_move") 139 (set_attr "length""8")]) 140 141;; 142;; [vrndxq_f]) 143;; 144(define_insn "mve_vrndxq_f<mode>" 145 [ 146 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 147 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 148 VRNDXQ_F)) 149 ] 150 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 151 "vrintx.f%#<V_sz_elem> %q0, %q1" 152 [(set_attr "type" "mve_move") 153]) 154 155;; 156;; [vrndq_f]) 157;; 158(define_insn "mve_vrndq_f<mode>" 159 [ 160 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 161 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 162 VRNDQ_F)) 163 ] 164 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 165 "vrintz.f%#<V_sz_elem> %q0, %q1" 166 [(set_attr "type" "mve_move") 167]) 168 169;; 170;; [vrndpq_f]) 171;; 172(define_insn "mve_vrndpq_f<mode>" 173 [ 174 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 175 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 176 VRNDPQ_F)) 177 ] 178 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 179 "vrintp.f%#<V_sz_elem> %q0, %q1" 180 [(set_attr "type" "mve_move") 181]) 182 183;; 184;; [vrndnq_f]) 185;; 186(define_insn "mve_vrndnq_f<mode>" 187 [ 188 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 189 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 190 VRNDNQ_F)) 191 ] 192 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 193 "vrintn.f%#<V_sz_elem> %q0, %q1" 194 [(set_attr "type" "mve_move") 195]) 196 197;; 198;; [vrndmq_f]) 199;; 200(define_insn "mve_vrndmq_f<mode>" 201 [ 202 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 203 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 204 VRNDMQ_F)) 205 ] 206 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 207 "vrintm.f%#<V_sz_elem> %q0, %q1" 208 [(set_attr "type" "mve_move") 209]) 210 211;; 212;; [vrndaq_f]) 213;; 214(define_insn "mve_vrndaq_f<mode>" 215 [ 216 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 217 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 218 VRNDAQ_F)) 219 ] 220 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 221 "vrinta.f%#<V_sz_elem> %q0, %q1" 222 [(set_attr "type" "mve_move") 223]) 224 225;; 226;; [vrev64q_f]) 227;; 228(define_insn "mve_vrev64q_f<mode>" 229 [ 230 (set (match_operand:MVE_0 0 "s_register_operand" "=&w") 231 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] 232 VREV64Q_F)) 233 ] 234 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 235 "vrev64.%#<V_sz_elem>\t%q0, %q1" 236 [(set_attr "type" "mve_move") 237]) 238 239;; 240;; [vnegq_f]) 241;; 242(define_insn "mve_vnegq_f<mode>" 243 [ 244 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 245 (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) 246 ] 247 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 248 "vneg.f%#<V_sz_elem>\t%q0, %q1" 249 [(set_attr "type" "mve_move") 250]) 251 252;; 253;; [vdupq_n_f]) 254;; 255(define_insn "mve_vdupq_n_f<mode>" 256 [ 257 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 258 (unspec:MVE_0 [(match_operand:<V_elem> 1 "s_register_operand" "r")] 259 VDUPQ_N_F)) 260 ] 261 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 262 "vdup.%#<V_sz_elem>\t%q0, %1" 263 [(set_attr "type" "mve_move") 264]) 265 266;; 267;; [vabsq_f]) 268;; 269(define_insn "mve_vabsq_f<mode>" 270 [ 271 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 272 (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) 273 ] 274 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 275 "vabs.f%#<V_sz_elem>\t%q0, %q1" 276 [(set_attr "type" "mve_move") 277]) 278 279;; 280;; [vrev32q_f]) 281;; 282(define_insn "mve_vrev32q_fv8hf" 283 [ 284 (set (match_operand:V8HF 0 "s_register_operand" "=w") 285 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] 286 VREV32Q_F)) 287 ] 288 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 289 "vrev32.16\t%q0, %q1" 290 [(set_attr "type" "mve_move") 291]) 292;; 293;; [vcvttq_f32_f16]) 294;; 295(define_insn "mve_vcvttq_f32_f16v4sf" 296 [ 297 (set (match_operand:V4SF 0 "s_register_operand" "=w") 298 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] 299 VCVTTQ_F32_F16)) 300 ] 301 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 302 "vcvtt.f32.f16\t%q0, %q1" 303 [(set_attr "type" "mve_move") 304]) 305 306;; 307;; [vcvtbq_f32_f16]) 308;; 309(define_insn "mve_vcvtbq_f32_f16v4sf" 310 [ 311 (set (match_operand:V4SF 0 "s_register_operand" "=w") 312 (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] 313 VCVTBQ_F32_F16)) 314 ] 315 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 316 "vcvtb.f32.f16\t%q0, %q1" 317 [(set_attr "type" "mve_move") 318]) 319 320;; 321;; [vcvtq_to_f_s, vcvtq_to_f_u]) 322;; 323(define_insn "mve_vcvtq_to_f_<supf><mode>" 324 [ 325 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 326 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] 327 VCVTQ_TO_F)) 328 ] 329 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 330 "vcvt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q1" 331 [(set_attr "type" "mve_move") 332]) 333 334;; 335;; [vrev64q_u, vrev64q_s]) 336;; 337(define_insn "mve_vrev64q_<supf><mode>" 338 [ 339 (set (match_operand:MVE_2 0 "s_register_operand" "=&w") 340 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] 341 VREV64Q)) 342 ] 343 "TARGET_HAVE_MVE" 344 "vrev64.%#<V_sz_elem>\t%q0, %q1" 345 [(set_attr "type" "mve_move") 346]) 347 348;; 349;; [vcvtq_from_f_s, vcvtq_from_f_u]) 350;; 351(define_insn "mve_vcvtq_from_f_<supf><mode>" 352 [ 353 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 354 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] 355 VCVTQ_FROM_F)) 356 ] 357 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 358 "vcvt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" 359 [(set_attr "type" "mve_move") 360]) 361;; [vqnegq_s]) 362;; 363(define_insn "mve_vqnegq_s<mode>" 364 [ 365 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 366 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] 367 VQNEGQ_S)) 368 ] 369 "TARGET_HAVE_MVE" 370 "vqneg.s%#<V_sz_elem>\t%q0, %q1" 371 [(set_attr "type" "mve_move") 372]) 373 374;; 375;; [vqabsq_s]) 376;; 377(define_insn "mve_vqabsq_s<mode>" 378 [ 379 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 380 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] 381 VQABSQ_S)) 382 ] 383 "TARGET_HAVE_MVE" 384 "vqabs.s%#<V_sz_elem>\t%q0, %q1" 385 [(set_attr "type" "mve_move") 386]) 387 388;; 389;; [vnegq_s]) 390;; 391(define_insn "mve_vnegq_s<mode>" 392 [ 393 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 394 (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) 395 ] 396 "TARGET_HAVE_MVE" 397 "vneg.s%#<V_sz_elem>\t%q0, %q1" 398 [(set_attr "type" "mve_move") 399]) 400 401;; 402;; [vmvnq_u, vmvnq_s]) 403;; 404(define_insn "mve_vmvnq_u<mode>" 405 [ 406 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 407 (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) 408 ] 409 "TARGET_HAVE_MVE" 410 "vmvn\t%q0, %q1" 411 [(set_attr "type" "mve_move") 412]) 413(define_expand "mve_vmvnq_s<mode>" 414 [ 415 (set (match_operand:MVE_2 0 "s_register_operand") 416 (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) 417 ] 418 "TARGET_HAVE_MVE" 419) 420 421;; 422;; [vdupq_n_u, vdupq_n_s]) 423;; 424(define_insn "mve_vdupq_n_<supf><mode>" 425 [ 426 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 427 (unspec:MVE_2 [(match_operand:<V_elem> 1 "s_register_operand" "r")] 428 VDUPQ_N)) 429 ] 430 "TARGET_HAVE_MVE" 431 "vdup.%#<V_sz_elem>\t%q0, %1" 432 [(set_attr "type" "mve_move") 433]) 434 435;; 436;; [vclzq_u, vclzq_s]) 437;; 438(define_insn "@mve_vclzq_s<mode>" 439 [ 440 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 441 (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) 442 ] 443 "TARGET_HAVE_MVE" 444 "vclz.i%#<V_sz_elem>\t%q0, %q1" 445 [(set_attr "type" "mve_move") 446]) 447(define_expand "mve_vclzq_u<mode>" 448 [ 449 (set (match_operand:MVE_2 0 "s_register_operand") 450 (clz:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) 451 ] 452 "TARGET_HAVE_MVE" 453) 454 455;; 456;; [vclsq_s]) 457;; 458(define_insn "mve_vclsq_s<mode>" 459 [ 460 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 461 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] 462 VCLSQ_S)) 463 ] 464 "TARGET_HAVE_MVE" 465 "vcls.s%#<V_sz_elem>\t%q0, %q1" 466 [(set_attr "type" "mve_move") 467]) 468 469;; 470;; [vaddvq_s, vaddvq_u]) 471;; 472(define_insn "@mve_vaddvq_<supf><mode>" 473 [ 474 (set (match_operand:SI 0 "s_register_operand" "=Te") 475 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] 476 VADDVQ)) 477 ] 478 "TARGET_HAVE_MVE" 479 "vaddv.<supf>%#<V_sz_elem>\t%0, %q1" 480 [(set_attr "type" "mve_move") 481]) 482 483;; 484;; [vabsq_s]) 485;; 486(define_insn "mve_vabsq_s<mode>" 487 [ 488 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 489 (abs:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) 490 ] 491 "TARGET_HAVE_MVE" 492 "vabs.s%#<V_sz_elem>\t%q0, %q1" 493 [(set_attr "type" "mve_move") 494]) 495 496;; 497;; [vrev32q_u, vrev32q_s]) 498;; 499(define_insn "mve_vrev32q_<supf><mode>" 500 [ 501 (set (match_operand:MVE_3 0 "s_register_operand" "=w") 502 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] 503 VREV32Q)) 504 ] 505 "TARGET_HAVE_MVE" 506 "vrev32.%#<V_sz_elem>\t%q0, %q1" 507 [(set_attr "type" "mve_move") 508]) 509 510;; 511;; [vmovltq_u, vmovltq_s]) 512;; 513(define_insn "mve_vmovltq_<supf><mode>" 514 [ 515 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 516 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] 517 VMOVLTQ)) 518 ] 519 "TARGET_HAVE_MVE" 520 "vmovlt.<supf>%#<V_sz_elem>\t%q0, %q1" 521 [(set_attr "type" "mve_move") 522]) 523 524;; 525;; [vmovlbq_s, vmovlbq_u]) 526;; 527(define_insn "mve_vmovlbq_<supf><mode>" 528 [ 529 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 530 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w")] 531 VMOVLBQ)) 532 ] 533 "TARGET_HAVE_MVE" 534 "vmovlb.<supf>%#<V_sz_elem>\t%q0, %q1" 535 [(set_attr "type" "mve_move") 536]) 537 538;; 539;; [vcvtpq_s, vcvtpq_u]) 540;; 541(define_insn "mve_vcvtpq_<supf><mode>" 542 [ 543 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 544 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] 545 VCVTPQ)) 546 ] 547 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 548 "vcvtp.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" 549 [(set_attr "type" "mve_move") 550]) 551 552;; 553;; [vcvtnq_s, vcvtnq_u]) 554;; 555(define_insn "mve_vcvtnq_<supf><mode>" 556 [ 557 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 558 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] 559 VCVTNQ)) 560 ] 561 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 562 "vcvtn.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" 563 [(set_attr "type" "mve_move") 564]) 565 566;; 567;; [vcvtmq_s, vcvtmq_u]) 568;; 569(define_insn "mve_vcvtmq_<supf><mode>" 570 [ 571 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 572 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] 573 VCVTMQ)) 574 ] 575 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 576 "vcvtm.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" 577 [(set_attr "type" "mve_move") 578]) 579 580;; 581;; [vcvtaq_u, vcvtaq_s]) 582;; 583(define_insn "mve_vcvtaq_<supf><mode>" 584 [ 585 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 586 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w")] 587 VCVTAQ)) 588 ] 589 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 590 "vcvta.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q1" 591 [(set_attr "type" "mve_move") 592]) 593 594;; 595;; [vmvnq_n_u, vmvnq_n_s]) 596;; 597(define_insn "mve_vmvnq_n_<supf><mode>" 598 [ 599 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 600 (unspec:MVE_5 [(match_operand:<V_elem> 1 "immediate_operand" "i")] 601 VMVNQ_N)) 602 ] 603 "TARGET_HAVE_MVE" 604 "vmvn.i%#<V_sz_elem>\t%q0, %1" 605 [(set_attr "type" "mve_move") 606]) 607 608;; 609;; [vrev16q_u, vrev16q_s]) 610;; 611(define_insn "mve_vrev16q_<supf>v16qi" 612 [ 613 (set (match_operand:V16QI 0 "s_register_operand" "=w") 614 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")] 615 VREV16Q)) 616 ] 617 "TARGET_HAVE_MVE" 618 "vrev16.8\t%q0, %q1" 619 [(set_attr "type" "mve_move") 620]) 621 622;; 623;; [vaddlvq_s vaddlvq_u]) 624;; 625(define_insn "mve_vaddlvq_<supf>v4si" 626 [ 627 (set (match_operand:DI 0 "s_register_operand" "=r") 628 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")] 629 VADDLVQ)) 630 ] 631 "TARGET_HAVE_MVE" 632 "vaddlv.<supf>32\t%Q0, %R0, %q1" 633 [(set_attr "type" "mve_move") 634]) 635 636;; 637;; [vctp8q vctp16q vctp32q vctp64q]) 638;; 639(define_insn "mve_vctp<mode1>qhi" 640 [ 641 (set (match_operand:HI 0 "vpr_register_operand" "=Up") 642 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")] 643 VCTPQ)) 644 ] 645 "TARGET_HAVE_MVE" 646 "vctp.<mode1>\t%1" 647 [(set_attr "type" "mve_move") 648]) 649 650;; 651;; [vpnot]) 652;; 653(define_insn "mve_vpnothi" 654 [ 655 (set (match_operand:HI 0 "vpr_register_operand" "=Up") 656 (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")] 657 VPNOT)) 658 ] 659 "TARGET_HAVE_MVE" 660 "vpnot" 661 [(set_attr "type" "mve_move") 662]) 663 664;; 665;; [vsubq_n_f]) 666;; 667(define_insn "mve_vsubq_n_f<mode>" 668 [ 669 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 670 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 671 (match_operand:<V_elem> 2 "s_register_operand" "r")] 672 VSUBQ_N_F)) 673 ] 674 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 675 "vsub.f<V_sz_elem>\t%q0, %q1, %2" 676 [(set_attr "type" "mve_move") 677]) 678 679;; 680;; [vbrsrq_n_f]) 681;; 682(define_insn "mve_vbrsrq_n_f<mode>" 683 [ 684 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 685 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 686 (match_operand:SI 2 "s_register_operand" "r")] 687 VBRSRQ_N_F)) 688 ] 689 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 690 "vbrsr.<V_sz_elem>\t%q0, %q1, %2" 691 [(set_attr "type" "mve_move") 692]) 693 694;; 695;; [vcvtq_n_to_f_s, vcvtq_n_to_f_u]) 696;; 697(define_insn "mve_vcvtq_n_to_f_<supf><mode>" 698 [ 699 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 700 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") 701 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] 702 VCVTQ_N_TO_F)) 703 ] 704 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 705 "vcvt.f<V_sz_elem>.<supf><V_sz_elem>\t%q0, %q1, %2" 706 [(set_attr "type" "mve_move") 707]) 708 709;; [vcreateq_f]) 710;; 711(define_insn "mve_vcreateq_f<mode>" 712 [ 713 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 714 (unspec:MVE_0 [(match_operand:DI 1 "s_register_operand" "r") 715 (match_operand:DI 2 "s_register_operand" "r")] 716 VCREATEQ_F)) 717 ] 718 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 719 "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" 720 [(set_attr "type" "mve_move") 721 (set_attr "length""8")]) 722 723;; 724;; [vcreateq_u, vcreateq_s]) 725;; 726(define_insn "mve_vcreateq_<supf><mode>" 727 [ 728 (set (match_operand:MVE_1 0 "s_register_operand" "=w") 729 (unspec:MVE_1 [(match_operand:DI 1 "s_register_operand" "r") 730 (match_operand:DI 2 "s_register_operand" "r")] 731 VCREATEQ)) 732 ] 733 "TARGET_HAVE_MVE" 734 "vmov %q0[2], %q0[0], %Q1, %Q2\;vmov %q0[3], %q0[1], %R1, %R2" 735 [(set_attr "type" "mve_move") 736 (set_attr "length""8")]) 737 738;; 739;; [vshrq_n_s, vshrq_n_u]) 740;; 741;; Version that takes an immediate as operand 2. 742(define_insn "mve_vshrq_n_<supf><mode>" 743 [ 744 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 745 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 746 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] 747 VSHRQ_N)) 748 ] 749 "TARGET_HAVE_MVE" 750 "vshr.<supf><V_sz_elem>\t%q0, %q1, %2" 751 [(set_attr "type" "mve_move") 752]) 753 754;; Versions that take constant vectors as operand 2 (with all elements 755;; equal). 756(define_insn "mve_vshrq_n_s<mode>_imm" 757 [ 758 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 759 (ashiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 760 (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i"))) 761 ] 762 "TARGET_HAVE_MVE" 763 { 764 return neon_output_shift_immediate ("vshr", 's', &operands[2], 765 <MODE>mode, 766 VALID_NEON_QREG_MODE (<MODE>mode), 767 true); 768 } 769 [(set_attr "type" "mve_move") 770]) 771(define_insn "mve_vshrq_n_u<mode>_imm" 772 [ 773 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 774 (lshiftrt:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 775 (match_operand:MVE_2 2 "imm_for_neon_rshift_operand" "i"))) 776 ] 777 "TARGET_HAVE_MVE" 778 { 779 return neon_output_shift_immediate ("vshr", 'u', &operands[2], 780 <MODE>mode, 781 VALID_NEON_QREG_MODE (<MODE>mode), 782 true); 783 } 784 [(set_attr "type" "mve_move") 785]) 786 787;; 788;; [vcvtq_n_from_f_s, vcvtq_n_from_f_u]) 789;; 790(define_insn "mve_vcvtq_n_from_f_<supf><mode>" 791 [ 792 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 793 (unspec:MVE_5 [(match_operand:<MVE_CNVT> 1 "s_register_operand" "w") 794 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] 795 VCVTQ_N_FROM_F)) 796 ] 797 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 798 "vcvt.<supf><V_sz_elem>.f<V_sz_elem>\t%q0, %q1, %2" 799 [(set_attr "type" "mve_move") 800]) 801 802;; 803;; [vaddlvq_p_s]) 804;; 805(define_insn "mve_vaddlvq_p_<supf>v4si" 806 [ 807 (set (match_operand:DI 0 "s_register_operand" "=r") 808 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 809 (match_operand:V4BI 2 "vpr_register_operand" "Up")] 810 VADDLVQ_P)) 811 ] 812 "TARGET_HAVE_MVE" 813 "vpst\;vaddlvt.<supf>32\t%Q0, %R0, %q1" 814 [(set_attr "type" "mve_move") 815 (set_attr "length""8")]) 816 817;; 818;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_]) 819;; 820(define_insn "@mve_vcmp<mve_cmp_op>q_<mode>" 821 [ 822 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 823 (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w") 824 (match_operand:MVE_2 2 "s_register_operand" "w"))) 825 ] 826 "TARGET_HAVE_MVE" 827 "vcmp.<mve_cmp_type>%#<V_sz_elem>\t<mve_cmp_op>, %q1, %q2" 828 [(set_attr "type" "mve_move") 829]) 830 831;; 832;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_]) 833;; 834(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>" 835 [ 836 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 837 (MVE_COMPARISONS:<MVE_VPRED> 838 (match_operand:MVE_2 1 "s_register_operand" "w") 839 (vec_duplicate:MVE_2 (match_operand:<V_elem> 2 "s_register_operand" "r")))) 840 ] 841 "TARGET_HAVE_MVE" 842 "vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2" 843 [(set_attr "type" "mve_move") 844]) 845 846;; 847;; [vshlq_s, vshlq_u]) 848;; See vec-common.md 849 850;; 851;; [vabdq_s, vabdq_u]) 852;; 853(define_insn "mve_vabdq_<supf><mode>" 854 [ 855 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 856 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 857 (match_operand:MVE_2 2 "s_register_operand" "w")] 858 VABDQ)) 859 ] 860 "TARGET_HAVE_MVE" 861 "vabd.<supf>%#<V_sz_elem> %q0, %q1, %q2" 862 [(set_attr "type" "mve_move") 863]) 864 865;; 866;; [vaddq_n_s, vaddq_n_u]) 867;; 868(define_insn "mve_vaddq_n_<supf><mode>" 869 [ 870 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 871 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 872 (match_operand:<V_elem> 2 "s_register_operand" "r")] 873 VADDQ_N)) 874 ] 875 "TARGET_HAVE_MVE" 876 "vadd.i%#<V_sz_elem>\t%q0, %q1, %2" 877 [(set_attr "type" "mve_move") 878]) 879 880;; 881;; [vaddvaq_s, vaddvaq_u]) 882;; 883(define_insn "mve_vaddvaq_<supf><mode>" 884 [ 885 (set (match_operand:SI 0 "s_register_operand" "=Te") 886 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 887 (match_operand:MVE_2 2 "s_register_operand" "w")] 888 VADDVAQ)) 889 ] 890 "TARGET_HAVE_MVE" 891 "vaddva.<supf>%#<V_sz_elem>\t%0, %q2" 892 [(set_attr "type" "mve_move") 893]) 894 895;; 896;; [vaddvq_p_u, vaddvq_p_s]) 897;; 898(define_insn "mve_vaddvq_p_<supf><mode>" 899 [ 900 (set (match_operand:SI 0 "s_register_operand" "=Te") 901 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 902 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] 903 VADDVQ_P)) 904 ] 905 "TARGET_HAVE_MVE" 906 "vpst\;vaddvt.<supf>%#<V_sz_elem> %0, %q1" 907 [(set_attr "type" "mve_move") 908 (set_attr "length""8")]) 909 910;; 911;; [vandq_u, vandq_s]) 912;; 913;; signed and unsigned versions are the same: define the unsigned 914;; insn, and use an expander for the signed one as we still reference 915;; both names from arm_mve.h. 916;; We use the same code as in neon.md (TODO: avoid this duplication). 917(define_insn "mve_vandq_u<mode>" 918 [ 919 (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") 920 (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") 921 (match_operand:MVE_2 2 "neon_inv_logic_op2" "w,DL"))) 922 ] 923 "TARGET_HAVE_MVE" 924 "@ 925 vand\t%q0, %q1, %q2 926 * return neon_output_logic_immediate (\"vand\", &operands[2], <MODE>mode, 1, VALID_NEON_QREG_MODE (<MODE>mode));" 927 [(set_attr "type" "mve_move") 928]) 929(define_expand "mve_vandq_s<mode>" 930 [ 931 (set (match_operand:MVE_2 0 "s_register_operand") 932 (and:MVE_2 (match_operand:MVE_2 1 "s_register_operand") 933 (match_operand:MVE_2 2 "neon_inv_logic_op2"))) 934 ] 935 "TARGET_HAVE_MVE" 936) 937 938;; 939;; [vbicq_s, vbicq_u]) 940;; 941(define_insn "mve_vbicq_u<mode>" 942 [ 943 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 944 (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w")) 945 (match_operand:MVE_2 1 "s_register_operand" "w"))) 946 ] 947 "TARGET_HAVE_MVE" 948 "vbic\t%q0, %q1, %q2" 949 [(set_attr "type" "mve_move") 950]) 951 952(define_expand "mve_vbicq_s<mode>" 953 [ 954 (set (match_operand:MVE_2 0 "s_register_operand") 955 (and:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand")) 956 (match_operand:MVE_2 1 "s_register_operand"))) 957 ] 958 "TARGET_HAVE_MVE" 959) 960 961;; 962;; [vbrsrq_n_u, vbrsrq_n_s]) 963;; 964(define_insn "mve_vbrsrq_n_<supf><mode>" 965 [ 966 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 967 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 968 (match_operand:SI 2 "s_register_operand" "r")] 969 VBRSRQ_N)) 970 ] 971 "TARGET_HAVE_MVE" 972 "vbrsr.%#<V_sz_elem>\t%q0, %q1, %2" 973 [(set_attr "type" "mve_move") 974]) 975 976;; 977;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270]) 978;; 979(define_insn "mve_vcaddq<mve_rot><mode>" 980 [ 981 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 982 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 983 (match_operand:MVE_2 2 "s_register_operand" "w")] 984 VCADD)) 985 ] 986 "TARGET_HAVE_MVE" 987 "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #<rot>" 988 [(set_attr "type" "mve_move") 989]) 990 991;; Auto vectorizer pattern for int vcadd 992(define_expand "cadd<rot><mode>3" 993 [(set (match_operand:MVE_2 0 "register_operand") 994 (unspec:MVE_2 [(match_operand:MVE_2 1 "register_operand") 995 (match_operand:MVE_2 2 "register_operand")] 996 VCADD))] 997 "TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN" 998) 999 1000;; 1001;; [veorq_u, veorq_s]) 1002;; 1003(define_insn "mve_veorq_u<mode>" 1004 [ 1005 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1006 (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1007 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1008 ] 1009 "TARGET_HAVE_MVE" 1010 "veor\t%q0, %q1, %q2" 1011 [(set_attr "type" "mve_move") 1012]) 1013(define_expand "mve_veorq_s<mode>" 1014 [ 1015 (set (match_operand:MVE_2 0 "s_register_operand") 1016 (xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand") 1017 (match_operand:MVE_2 2 "s_register_operand"))) 1018 ] 1019 "TARGET_HAVE_MVE" 1020) 1021 1022;; 1023;; [vhaddq_n_u, vhaddq_n_s]) 1024;; 1025(define_insn "mve_vhaddq_n_<supf><mode>" 1026 [ 1027 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1028 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1029 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1030 VHADDQ_N)) 1031 ] 1032 "TARGET_HAVE_MVE" 1033 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1034 [(set_attr "type" "mve_move") 1035]) 1036 1037;; 1038;; [vhaddq_s, vhaddq_u]) 1039;; 1040(define_insn "@mve_vhaddq_<supf><mode>" 1041 [ 1042 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1043 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1044 (match_operand:MVE_2 2 "s_register_operand" "w")] 1045 VHADDQ)) 1046 ] 1047 "TARGET_HAVE_MVE" 1048 "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1049 [(set_attr "type" "mve_move") 1050]) 1051 1052;; 1053;; [vhcaddq_rot270_s]) 1054;; 1055(define_insn "mve_vhcaddq_rot270_s<mode>" 1056 [ 1057 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 1058 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1059 (match_operand:MVE_2 2 "s_register_operand" "w")] 1060 VHCADDQ_ROT270_S)) 1061 ] 1062 "TARGET_HAVE_MVE" 1063 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270" 1064 [(set_attr "type" "mve_move") 1065]) 1066 1067;; 1068;; [vhcaddq_rot90_s]) 1069;; 1070(define_insn "mve_vhcaddq_rot90_s<mode>" 1071 [ 1072 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 1073 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1074 (match_operand:MVE_2 2 "s_register_operand" "w")] 1075 VHCADDQ_ROT90_S)) 1076 ] 1077 "TARGET_HAVE_MVE" 1078 "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90" 1079 [(set_attr "type" "mve_move") 1080]) 1081 1082;; 1083;; [vhsubq_n_u, vhsubq_n_s]) 1084;; 1085(define_insn "mve_vhsubq_n_<supf><mode>" 1086 [ 1087 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1088 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1089 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1090 VHSUBQ_N)) 1091 ] 1092 "TARGET_HAVE_MVE" 1093 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1094 [(set_attr "type" "mve_move") 1095]) 1096 1097;; 1098;; [vhsubq_s, vhsubq_u]) 1099;; 1100(define_insn "mve_vhsubq_<supf><mode>" 1101 [ 1102 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1103 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1104 (match_operand:MVE_2 2 "s_register_operand" "w")] 1105 VHSUBQ)) 1106 ] 1107 "TARGET_HAVE_MVE" 1108 "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1109 [(set_attr "type" "mve_move") 1110]) 1111 1112;; 1113;; [vmaxaq_s]) 1114;; 1115(define_insn "mve_vmaxaq_s<mode>" 1116 [ 1117 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1118 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 1119 (match_operand:MVE_2 2 "s_register_operand" "w")] 1120 VMAXAQ_S)) 1121 ] 1122 "TARGET_HAVE_MVE" 1123 "vmaxa.s%#<V_sz_elem> %q0, %q2" 1124 [(set_attr "type" "mve_move") 1125]) 1126 1127;; 1128;; [vmaxavq_s]) 1129;; 1130(define_insn "mve_vmaxavq_s<mode>" 1131 [ 1132 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 1133 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 1134 (match_operand:MVE_2 2 "s_register_operand" "w")] 1135 VMAXAVQ_S)) 1136 ] 1137 "TARGET_HAVE_MVE" 1138 "vmaxav.s%#<V_sz_elem>\t%0, %q2" 1139 [(set_attr "type" "mve_move") 1140]) 1141 1142;; 1143;; [vmaxq_u, vmaxq_s]) 1144;; 1145(define_insn "mve_vmaxq_s<mode>" 1146 [ 1147 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1148 (smax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1149 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1150 ] 1151 "TARGET_HAVE_MVE" 1152 "vmax.%#<V_s_elem>\t%q0, %q1, %q2" 1153 [(set_attr "type" "mve_move") 1154]) 1155 1156(define_insn "mve_vmaxq_u<mode>" 1157 [ 1158 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1159 (umax:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1160 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1161 ] 1162 "TARGET_HAVE_MVE" 1163 "vmax.%#<V_u_elem>\t%q0, %q1, %q2" 1164 [(set_attr "type" "mve_move") 1165]) 1166 1167;; 1168;; [vmaxvq_u, vmaxvq_s]) 1169;; 1170(define_insn "mve_vmaxvq_<supf><mode>" 1171 [ 1172 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 1173 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 1174 (match_operand:MVE_2 2 "s_register_operand" "w")] 1175 VMAXVQ)) 1176 ] 1177 "TARGET_HAVE_MVE" 1178 "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2" 1179 [(set_attr "type" "mve_move") 1180]) 1181 1182;; 1183;; [vminaq_s]) 1184;; 1185(define_insn "mve_vminaq_s<mode>" 1186 [ 1187 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1188 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 1189 (match_operand:MVE_2 2 "s_register_operand" "w")] 1190 VMINAQ_S)) 1191 ] 1192 "TARGET_HAVE_MVE" 1193 "vmina.s%#<V_sz_elem>\t%q0, %q2" 1194 [(set_attr "type" "mve_move") 1195]) 1196 1197;; 1198;; [vminavq_s]) 1199;; 1200(define_insn "mve_vminavq_s<mode>" 1201 [ 1202 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 1203 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 1204 (match_operand:MVE_2 2 "s_register_operand" "w")] 1205 VMINAVQ_S)) 1206 ] 1207 "TARGET_HAVE_MVE" 1208 "vminav.s%#<V_sz_elem>\t%0, %q2" 1209 [(set_attr "type" "mve_move") 1210]) 1211 1212;; 1213;; [vminq_s, vminq_u]) 1214;; 1215(define_insn "mve_vminq_s<mode>" 1216 [ 1217 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1218 (smin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1219 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1220 ] 1221 "TARGET_HAVE_MVE" 1222 "vmin.%#<V_s_elem>\t%q0, %q1, %q2" 1223 [(set_attr "type" "mve_move") 1224]) 1225 1226(define_insn "mve_vminq_u<mode>" 1227 [ 1228 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1229 (umin:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1230 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1231 ] 1232 "TARGET_HAVE_MVE" 1233 "vmin.%#<V_u_elem>\t%q0, %q1, %q2" 1234 [(set_attr "type" "mve_move") 1235]) 1236 1237;; 1238;; [vminvq_u, vminvq_s]) 1239;; 1240(define_insn "mve_vminvq_<supf><mode>" 1241 [ 1242 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 1243 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 1244 (match_operand:MVE_2 2 "s_register_operand" "w")] 1245 VMINVQ)) 1246 ] 1247 "TARGET_HAVE_MVE" 1248 "vminv.<supf>%#<V_sz_elem>\t%0, %q2" 1249 [(set_attr "type" "mve_move") 1250]) 1251 1252;; 1253;; [vmladavq_u, vmladavq_s]) 1254;; 1255(define_insn "mve_vmladavq_<supf><mode>" 1256 [ 1257 (set (match_operand:SI 0 "s_register_operand" "=Te") 1258 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 1259 (match_operand:MVE_2 2 "s_register_operand" "w")] 1260 VMLADAVQ)) 1261 ] 1262 "TARGET_HAVE_MVE" 1263 "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2" 1264 [(set_attr "type" "mve_move") 1265]) 1266 1267;; 1268;; [vmladavxq_s]) 1269;; 1270(define_insn "mve_vmladavxq_s<mode>" 1271 [ 1272 (set (match_operand:SI 0 "s_register_operand" "=Te") 1273 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 1274 (match_operand:MVE_2 2 "s_register_operand" "w")] 1275 VMLADAVXQ_S)) 1276 ] 1277 "TARGET_HAVE_MVE" 1278 "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2" 1279 [(set_attr "type" "mve_move") 1280]) 1281 1282;; 1283;; [vmlsdavq_s]) 1284;; 1285(define_insn "mve_vmlsdavq_s<mode>" 1286 [ 1287 (set (match_operand:SI 0 "s_register_operand" "=Te") 1288 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 1289 (match_operand:MVE_2 2 "s_register_operand" "w")] 1290 VMLSDAVQ_S)) 1291 ] 1292 "TARGET_HAVE_MVE" 1293 "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2" 1294 [(set_attr "type" "mve_move") 1295]) 1296 1297;; 1298;; [vmlsdavxq_s]) 1299;; 1300(define_insn "mve_vmlsdavxq_s<mode>" 1301 [ 1302 (set (match_operand:SI 0 "s_register_operand" "=Te") 1303 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 1304 (match_operand:MVE_2 2 "s_register_operand" "w")] 1305 VMLSDAVXQ_S)) 1306 ] 1307 "TARGET_HAVE_MVE" 1308 "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2" 1309 [(set_attr "type" "mve_move") 1310]) 1311 1312;; 1313;; [vmulhq_s, vmulhq_u]) 1314;; 1315(define_insn "mve_vmulhq_<supf><mode>" 1316 [ 1317 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1318 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1319 (match_operand:MVE_2 2 "s_register_operand" "w")] 1320 VMULHQ)) 1321 ] 1322 "TARGET_HAVE_MVE" 1323 "vmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1324 [(set_attr "type" "mve_move") 1325]) 1326 1327;; 1328;; [vmullbq_int_u, vmullbq_int_s]) 1329;; 1330(define_insn "mve_vmullbq_int_<supf><mode>" 1331 [ 1332 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 1333 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") 1334 (match_operand:MVE_2 2 "s_register_operand" "w")] 1335 VMULLBQ_INT)) 1336 ] 1337 "TARGET_HAVE_MVE" 1338 "vmullb.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1339 [(set_attr "type" "mve_move") 1340]) 1341 1342;; 1343;; [vmulltq_int_u, vmulltq_int_s]) 1344;; 1345(define_insn "mve_vmulltq_int_<supf><mode>" 1346 [ 1347 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 1348 (unspec:<V_double_width> [(match_operand:MVE_2 1 "s_register_operand" "w") 1349 (match_operand:MVE_2 2 "s_register_operand" "w")] 1350 VMULLTQ_INT)) 1351 ] 1352 "TARGET_HAVE_MVE" 1353 "vmullt.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1354 [(set_attr "type" "mve_move") 1355]) 1356 1357;; 1358;; [vmulq_n_u, vmulq_n_s]) 1359;; 1360(define_insn "mve_vmulq_n_<supf><mode>" 1361 [ 1362 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1363 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1364 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1365 VMULQ_N)) 1366 ] 1367 "TARGET_HAVE_MVE" 1368 "vmul.i%#<V_sz_elem>\t%q0, %q1, %2" 1369 [(set_attr "type" "mve_move") 1370]) 1371 1372;; 1373;; [vmulq_u, vmulq_s]) 1374;; 1375(define_insn "mve_vmulq_<supf><mode>" 1376 [ 1377 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1378 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1379 (match_operand:MVE_2 2 "s_register_operand" "w")] 1380 VMULQ)) 1381 ] 1382 "TARGET_HAVE_MVE" 1383 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2" 1384 [(set_attr "type" "mve_move") 1385]) 1386 1387(define_insn "mve_vmulq<mode>" 1388 [ 1389 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1390 (mult:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1391 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1392 ] 1393 "TARGET_HAVE_MVE" 1394 "vmul.i%#<V_sz_elem>\t%q0, %q1, %q2" 1395 [(set_attr "type" "mve_move") 1396]) 1397 1398;; 1399;; [vornq_u, vornq_s]) 1400;; 1401(define_insn "mve_vornq_s<mode>" 1402 [ 1403 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1404 (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand" "w")) 1405 (match_operand:MVE_2 1 "s_register_operand" "w"))) 1406 ] 1407 "TARGET_HAVE_MVE" 1408 "vorn\t%q0, %q1, %q2" 1409 [(set_attr "type" "mve_move") 1410]) 1411 1412(define_expand "mve_vornq_u<mode>" 1413 [ 1414 (set (match_operand:MVE_2 0 "s_register_operand") 1415 (ior:MVE_2 (not:MVE_2 (match_operand:MVE_2 2 "s_register_operand")) 1416 (match_operand:MVE_2 1 "s_register_operand"))) 1417 ] 1418 "TARGET_HAVE_MVE" 1419) 1420 1421;; 1422;; [vorrq_s, vorrq_u]) 1423;; 1424;; signed and unsigned versions are the same: define the unsigned 1425;; insn, and use an expander for the signed one as we still reference 1426;; both names from arm_mve.h. 1427;; We use the same code as in neon.md (TODO: avoid this duplication). 1428(define_insn "mve_vorrq_s<mode>" 1429 [ 1430 (set (match_operand:MVE_2 0 "s_register_operand" "=w,w") 1431 (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w,0") 1432 (match_operand:MVE_2 2 "neon_logic_op2" "w,Dl"))) 1433 ] 1434 "TARGET_HAVE_MVE" 1435 "@ 1436 vorr\t%q0, %q1, %q2 1437 * return neon_output_logic_immediate (\"vorr\", &operands[2], <MODE>mode, 0, VALID_NEON_QREG_MODE (<MODE>mode));" 1438 [(set_attr "type" "mve_move") 1439]) 1440(define_expand "mve_vorrq_u<mode>" 1441 [ 1442 (set (match_operand:MVE_2 0 "s_register_operand") 1443 (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand") 1444 (match_operand:MVE_2 2 "neon_logic_op2"))) 1445 ] 1446 "TARGET_HAVE_MVE" 1447) 1448 1449;; 1450;; [vqaddq_n_s, vqaddq_n_u]) 1451;; 1452(define_insn "mve_vqaddq_n_<supf><mode>" 1453 [ 1454 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1455 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1456 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1457 VQADDQ_N)) 1458 ] 1459 "TARGET_HAVE_MVE" 1460 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1461 [(set_attr "type" "mve_move") 1462]) 1463 1464;; 1465;; [vqaddq_u, vqaddq_s]) 1466;; 1467(define_insn "mve_vqaddq_<supf><mode>" 1468 [ 1469 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1470 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1471 (match_operand:MVE_2 2 "s_register_operand" "w")] 1472 VQADDQ)) 1473 ] 1474 "TARGET_HAVE_MVE" 1475 "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1476 [(set_attr "type" "mve_move") 1477]) 1478 1479;; 1480;; [vqdmulhq_n_s]) 1481;; 1482(define_insn "mve_vqdmulhq_n_s<mode>" 1483 [ 1484 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1485 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1486 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1487 VQDMULHQ_N_S)) 1488 ] 1489 "TARGET_HAVE_MVE" 1490 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2" 1491 [(set_attr "type" "mve_move") 1492]) 1493 1494;; 1495;; [vqdmulhq_s]) 1496;; 1497(define_insn "mve_vqdmulhq_s<mode>" 1498 [ 1499 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1500 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1501 (match_operand:MVE_2 2 "s_register_operand" "w")] 1502 VQDMULHQ_S)) 1503 ] 1504 "TARGET_HAVE_MVE" 1505 "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2" 1506 [(set_attr "type" "mve_move") 1507]) 1508 1509;; 1510;; [vqrdmulhq_n_s]) 1511;; 1512(define_insn "mve_vqrdmulhq_n_s<mode>" 1513 [ 1514 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1515 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1516 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1517 VQRDMULHQ_N_S)) 1518 ] 1519 "TARGET_HAVE_MVE" 1520 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2" 1521 [(set_attr "type" "mve_move") 1522]) 1523 1524;; 1525;; [vqrdmulhq_s]) 1526;; 1527(define_insn "mve_vqrdmulhq_s<mode>" 1528 [ 1529 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1530 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1531 (match_operand:MVE_2 2 "s_register_operand" "w")] 1532 VQRDMULHQ_S)) 1533 ] 1534 "TARGET_HAVE_MVE" 1535 "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %q2" 1536 [(set_attr "type" "mve_move") 1537]) 1538 1539;; 1540;; [vqrshlq_n_s, vqrshlq_n_u]) 1541;; 1542(define_insn "mve_vqrshlq_n_<supf><mode>" 1543 [ 1544 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1545 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 1546 (match_operand:SI 2 "s_register_operand" "r")] 1547 VQRSHLQ_N)) 1548 ] 1549 "TARGET_HAVE_MVE" 1550 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2" 1551 [(set_attr "type" "mve_move") 1552]) 1553 1554;; 1555;; [vqrshlq_s, vqrshlq_u]) 1556;; 1557(define_insn "mve_vqrshlq_<supf><mode>" 1558 [ 1559 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1560 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1561 (match_operand:MVE_2 2 "s_register_operand" "w")] 1562 VQRSHLQ)) 1563 ] 1564 "TARGET_HAVE_MVE" 1565 "vqrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1566 [(set_attr "type" "mve_move") 1567]) 1568 1569;; 1570;; [vqshlq_n_s, vqshlq_n_u]) 1571;; 1572(define_insn "mve_vqshlq_n_<supf><mode>" 1573 [ 1574 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1575 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1576 (match_operand:SI 2 "immediate_operand" "i")] 1577 VQSHLQ_N)) 1578 ] 1579 "TARGET_HAVE_MVE" 1580 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1581 [(set_attr "type" "mve_move") 1582]) 1583 1584;; 1585;; [vqshlq_r_u, vqshlq_r_s]) 1586;; 1587(define_insn "mve_vqshlq_r_<supf><mode>" 1588 [ 1589 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1590 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 1591 (match_operand:SI 2 "s_register_operand" "r")] 1592 VQSHLQ_R)) 1593 ] 1594 "TARGET_HAVE_MVE" 1595 "vqshl.<supf>%#<V_sz_elem>\t%q0, %2" 1596 [(set_attr "type" "mve_move") 1597]) 1598 1599;; 1600;; [vqshlq_s, vqshlq_u]) 1601;; 1602(define_insn "mve_vqshlq_<supf><mode>" 1603 [ 1604 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1605 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1606 (match_operand:MVE_2 2 "s_register_operand" "w")] 1607 VQSHLQ)) 1608 ] 1609 "TARGET_HAVE_MVE" 1610 "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1611 [(set_attr "type" "mve_move") 1612]) 1613 1614;; 1615;; [vqshluq_n_s]) 1616;; 1617(define_insn "mve_vqshluq_n_s<mode>" 1618 [ 1619 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1620 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1621 (match_operand:SI 2 "<MVE_pred>" "<MVE_constraint>")] 1622 VQSHLUQ_N_S)) 1623 ] 1624 "TARGET_HAVE_MVE" 1625 "vqshlu.s%#<V_sz_elem>\t%q0, %q1, %2" 1626 [(set_attr "type" "mve_move") 1627]) 1628 1629;; 1630;; [vqsubq_n_s, vqsubq_n_u]) 1631;; 1632(define_insn "mve_vqsubq_n_<supf><mode>" 1633 [ 1634 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1635 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1636 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1637 VQSUBQ_N)) 1638 ] 1639 "TARGET_HAVE_MVE" 1640 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1641 [(set_attr "type" "mve_move") 1642]) 1643 1644;; 1645;; [vqsubq_u, vqsubq_s]) 1646;; 1647(define_insn "mve_vqsubq_<supf><mode>" 1648 [ 1649 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1650 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1651 (match_operand:MVE_2 2 "s_register_operand" "w")] 1652 VQSUBQ)) 1653 ] 1654 "TARGET_HAVE_MVE" 1655 "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1656 [(set_attr "type" "mve_move") 1657]) 1658 1659;; 1660;; [vrhaddq_s, vrhaddq_u]) 1661;; 1662(define_insn "@mve_vrhaddq_<supf><mode>" 1663 [ 1664 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1665 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1666 (match_operand:MVE_2 2 "s_register_operand" "w")] 1667 VRHADDQ)) 1668 ] 1669 "TARGET_HAVE_MVE" 1670 "vrhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1671 [(set_attr "type" "mve_move") 1672]) 1673 1674;; 1675;; [vrmulhq_s, vrmulhq_u]) 1676;; 1677(define_insn "mve_vrmulhq_<supf><mode>" 1678 [ 1679 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1680 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1681 (match_operand:MVE_2 2 "s_register_operand" "w")] 1682 VRMULHQ)) 1683 ] 1684 "TARGET_HAVE_MVE" 1685 "vrmulh.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1686 [(set_attr "type" "mve_move") 1687]) 1688 1689;; 1690;; [vrshlq_n_u, vrshlq_n_s]) 1691;; 1692(define_insn "mve_vrshlq_n_<supf><mode>" 1693 [ 1694 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1695 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 1696 (match_operand:SI 2 "s_register_operand" "r")] 1697 VRSHLQ_N)) 1698 ] 1699 "TARGET_HAVE_MVE" 1700 "vrshl.<supf>%#<V_sz_elem>\t%q0, %2" 1701 [(set_attr "type" "mve_move") 1702]) 1703 1704;; 1705;; [vrshlq_s, vrshlq_u]) 1706;; 1707(define_insn "mve_vrshlq_<supf><mode>" 1708 [ 1709 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1710 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1711 (match_operand:MVE_2 2 "s_register_operand" "w")] 1712 VRSHLQ)) 1713 ] 1714 "TARGET_HAVE_MVE" 1715 "vrshl.<supf>%#<V_sz_elem>\t%q0, %q1, %q2" 1716 [(set_attr "type" "mve_move") 1717]) 1718 1719;; 1720;; [vrshrq_n_s, vrshrq_n_u]) 1721;; 1722(define_insn "mve_vrshrq_n_<supf><mode>" 1723 [ 1724 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1725 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1726 (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")] 1727 VRSHRQ_N)) 1728 ] 1729 "TARGET_HAVE_MVE" 1730 "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1731 [(set_attr "type" "mve_move") 1732]) 1733 1734;; 1735;; [vshlq_n_u, vshlq_n_s]) 1736;; 1737(define_insn "mve_vshlq_n_<supf><mode>" 1738 [ 1739 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1740 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1741 (match_operand:SI 2 "immediate_operand" "i")] 1742 VSHLQ_N)) 1743 ] 1744 "TARGET_HAVE_MVE" 1745 "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 1746 [(set_attr "type" "mve_move") 1747]) 1748 1749;; 1750;; [vshlq_r_s, vshlq_r_u]) 1751;; 1752(define_insn "mve_vshlq_r_<supf><mode>" 1753 [ 1754 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1755 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 1756 (match_operand:SI 2 "s_register_operand" "r")] 1757 VSHLQ_R)) 1758 ] 1759 "TARGET_HAVE_MVE" 1760 "vshl.<supf>%#<V_sz_elem>\t%q0, %2" 1761 [(set_attr "type" "mve_move") 1762]) 1763 1764;; 1765;; [vsubq_n_s, vsubq_n_u]) 1766;; 1767(define_insn "mve_vsubq_n_<supf><mode>" 1768 [ 1769 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1770 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1771 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1772 VSUBQ_N)) 1773 ] 1774 "TARGET_HAVE_MVE" 1775 "vsub.i%#<V_sz_elem>\t%q0, %q1, %2" 1776 [(set_attr "type" "mve_move") 1777]) 1778 1779;; 1780;; [vsubq_s, vsubq_u]) 1781;; 1782(define_insn "mve_vsubq_<supf><mode>" 1783 [ 1784 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1785 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") 1786 (match_operand:MVE_2 2 "s_register_operand" "w")] 1787 VSUBQ)) 1788 ] 1789 "TARGET_HAVE_MVE" 1790 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2" 1791 [(set_attr "type" "mve_move") 1792]) 1793 1794(define_insn "mve_vsubq<mode>" 1795 [ 1796 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 1797 (minus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 1798 (match_operand:MVE_2 2 "s_register_operand" "w"))) 1799 ] 1800 "TARGET_HAVE_MVE" 1801 "vsub.i%#<V_sz_elem>\t%q0, %q1, %q2" 1802 [(set_attr "type" "mve_move") 1803]) 1804 1805;; 1806;; [vabdq_f]) 1807;; 1808(define_insn "mve_vabdq_f<mode>" 1809 [ 1810 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 1811 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 1812 (match_operand:MVE_0 2 "s_register_operand" "w")] 1813 VABDQ_F)) 1814 ] 1815 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1816 "vabd.f%#<V_sz_elem> %q0, %q1, %q2" 1817 [(set_attr "type" "mve_move") 1818]) 1819 1820;; 1821;; [vaddlvaq_s vaddlvaq_u]) 1822;; 1823(define_insn "mve_vaddlvaq_<supf>v4si" 1824 [ 1825 (set (match_operand:DI 0 "s_register_operand" "=r") 1826 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 1827 (match_operand:V4SI 2 "s_register_operand" "w")] 1828 VADDLVAQ)) 1829 ] 1830 "TARGET_HAVE_MVE" 1831 "vaddlva.<supf>32\t%Q0, %R0, %q2" 1832 [(set_attr "type" "mve_move") 1833]) 1834 1835;; 1836;; [vaddq_n_f]) 1837;; 1838(define_insn "mve_vaddq_n_f<mode>" 1839 [ 1840 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 1841 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 1842 (match_operand:<V_elem> 2 "s_register_operand" "r")] 1843 VADDQ_N_F)) 1844 ] 1845 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1846 "vadd.f%#<V_sz_elem>\t%q0, %q1, %2" 1847 [(set_attr "type" "mve_move") 1848]) 1849 1850;; 1851;; [vandq_f]) 1852;; 1853(define_insn "mve_vandq_f<mode>" 1854 [ 1855 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 1856 (and:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 1857 (match_operand:MVE_0 2 "s_register_operand" "w"))) 1858 ] 1859 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1860 "vand\t%q0, %q1, %q2" 1861 [(set_attr "type" "mve_move") 1862]) 1863 1864;; 1865;; [vbicq_f]) 1866;; 1867(define_insn "mve_vbicq_f<mode>" 1868 [ 1869 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 1870 (and:MVE_0 (not:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")) 1871 (match_operand:MVE_0 2 "s_register_operand" "w"))) 1872 ] 1873 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1874 "vbic\t%q0, %q1, %q2" 1875 [(set_attr "type" "mve_move") 1876]) 1877 1878;; 1879;; [vbicq_n_s, vbicq_n_u]) 1880;; 1881(define_insn "mve_vbicq_n_<supf><mode>" 1882 [ 1883 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 1884 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 1885 (match_operand:SI 2 "immediate_operand" "i")] 1886 VBICQ_N)) 1887 ] 1888 "TARGET_HAVE_MVE" 1889 "vbic.i%#<V_sz_elem>\t%q0, %2" 1890 [(set_attr "type" "mve_move") 1891]) 1892 1893;; 1894;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270]) 1895;; 1896(define_insn "mve_vcaddq<mve_rot><mode>" 1897 [ 1898 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 1899 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 1900 (match_operand:MVE_0 2 "s_register_operand" "w")] 1901 VCADD)) 1902 ] 1903 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1904 "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>" 1905 [(set_attr "type" "mve_move") 1906]) 1907 1908;; 1909;; [vcmpeqq_f, vcmpgeq_f, vcmpgtq_f, vcmpleq_f, vcmpltq_f, vcmpneq_f]) 1910;; 1911(define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>" 1912 [ 1913 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 1914 (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w") 1915 (match_operand:MVE_0 2 "s_register_operand" "w"))) 1916 ] 1917 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1918 "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %q2" 1919 [(set_attr "type" "mve_move") 1920]) 1921 1922;; 1923;; [vcmpeqq_n_f, vcmpgeq_n_f, vcmpgtq_n_f, vcmpleq_n_f, vcmpltq_n_f, vcmpneq_n_f]) 1924;; 1925(define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>" 1926 [ 1927 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 1928 (MVE_FP_COMPARISONS:<MVE_VPRED> 1929 (match_operand:MVE_0 1 "s_register_operand" "w") 1930 (vec_duplicate:MVE_0 (match_operand:<V_elem> 2 "s_register_operand" "r")))) 1931 ] 1932 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1933 "vcmp.f%#<V_sz_elem> <mve_cmp_op>, %q1, %2" 1934 [(set_attr "type" "mve_move") 1935]) 1936 1937;; 1938;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270]) 1939;; 1940(define_insn "mve_vcmulq<mve_rot><mode>" 1941 [ 1942 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 1943 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 1944 (match_operand:MVE_0 2 "s_register_operand" "w")] 1945 VCMUL)) 1946 ] 1947 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1948 "vcmul.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>" 1949 [(set_attr "type" "mve_move") 1950]) 1951 1952;; 1953;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m]) 1954;; 1955(define_insn "mve_vctp<mode1>q_mhi" 1956 [ 1957 (set (match_operand:HI 0 "vpr_register_operand" "=Up") 1958 (unspec:HI [(match_operand:SI 1 "s_register_operand" "r") 1959 (match_operand:HI 2 "vpr_register_operand" "Up")] 1960 VCTPQ_M)) 1961 ] 1962 "TARGET_HAVE_MVE" 1963 "vpst\;vctpt.<mode1>\t%1" 1964 [(set_attr "type" "mve_move") 1965 (set_attr "length""8")]) 1966 1967;; 1968;; [vcvtbq_f16_f32]) 1969;; 1970(define_insn "mve_vcvtbq_f16_f32v8hf" 1971 [ 1972 (set (match_operand:V8HF 0 "s_register_operand" "=w") 1973 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") 1974 (match_operand:V4SF 2 "s_register_operand" "w")] 1975 VCVTBQ_F16_F32)) 1976 ] 1977 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1978 "vcvtb.f16.f32\t%q0, %q2" 1979 [(set_attr "type" "mve_move") 1980]) 1981 1982;; 1983;; [vcvttq_f16_f32]) 1984;; 1985(define_insn "mve_vcvttq_f16_f32v8hf" 1986 [ 1987 (set (match_operand:V8HF 0 "s_register_operand" "=w") 1988 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") 1989 (match_operand:V4SF 2 "s_register_operand" "w")] 1990 VCVTTQ_F16_F32)) 1991 ] 1992 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 1993 "vcvtt.f16.f32\t%q0, %q2" 1994 [(set_attr "type" "mve_move") 1995]) 1996 1997;; 1998;; [veorq_f]) 1999;; 2000(define_insn "mve_veorq_f<mode>" 2001 [ 2002 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2003 (xor:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 2004 (match_operand:MVE_0 2 "s_register_operand" "w"))) 2005 ] 2006 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2007 "veor\t%q0, %q1, %q2" 2008 [(set_attr "type" "mve_move") 2009]) 2010 2011;; 2012;; [vmaxnmaq_f]) 2013;; 2014(define_insn "mve_vmaxnmaq_f<mode>" 2015 [ 2016 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2017 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 2018 (match_operand:MVE_0 2 "s_register_operand" "w")] 2019 VMAXNMAQ_F)) 2020 ] 2021 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2022 "vmaxnma.f%#<V_sz_elem> %q0, %q2" 2023 [(set_attr "type" "mve_move") 2024]) 2025 2026;; 2027;; [vmaxnmavq_f]) 2028;; 2029(define_insn "mve_vmaxnmavq_f<mode>" 2030 [ 2031 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 2032 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 2033 (match_operand:MVE_0 2 "s_register_operand" "w")] 2034 VMAXNMAVQ_F)) 2035 ] 2036 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2037 "vmaxnmav.f%#<V_sz_elem> %0, %q2" 2038 [(set_attr "type" "mve_move") 2039]) 2040 2041;; 2042;; [vmaxnmq_f]) 2043;; 2044(define_insn "mve_vmaxnmq_f<mode>" 2045 [ 2046 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2047 (smax:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 2048 (match_operand:MVE_0 2 "s_register_operand" "w"))) 2049 ] 2050 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2051 "vmaxnm.f%#<V_sz_elem> %q0, %q1, %q2" 2052 [(set_attr "type" "mve_move") 2053]) 2054 2055;; 2056;; [vmaxnmvq_f]) 2057;; 2058(define_insn "mve_vmaxnmvq_f<mode>" 2059 [ 2060 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 2061 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 2062 (match_operand:MVE_0 2 "s_register_operand" "w")] 2063 VMAXNMVQ_F)) 2064 ] 2065 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2066 "vmaxnmv.f%#<V_sz_elem> %0, %q2" 2067 [(set_attr "type" "mve_move") 2068]) 2069 2070;; 2071;; [vminnmaq_f]) 2072;; 2073(define_insn "mve_vminnmaq_f<mode>" 2074 [ 2075 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2076 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 2077 (match_operand:MVE_0 2 "s_register_operand" "w")] 2078 VMINNMAQ_F)) 2079 ] 2080 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2081 "vminnma.f%#<V_sz_elem> %q0, %q2" 2082 [(set_attr "type" "mve_move") 2083]) 2084 2085;; 2086;; [vminnmavq_f]) 2087;; 2088(define_insn "mve_vminnmavq_f<mode>" 2089 [ 2090 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 2091 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 2092 (match_operand:MVE_0 2 "s_register_operand" "w")] 2093 VMINNMAVQ_F)) 2094 ] 2095 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2096 "vminnmav.f%#<V_sz_elem> %0, %q2" 2097 [(set_attr "type" "mve_move") 2098]) 2099 2100;; 2101;; [vminnmq_f]) 2102;; 2103(define_insn "mve_vminnmq_f<mode>" 2104 [ 2105 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2106 (smin:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 2107 (match_operand:MVE_0 2 "s_register_operand" "w"))) 2108 ] 2109 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2110 "vminnm.f%#<V_sz_elem> %q0, %q1, %q2" 2111 [(set_attr "type" "mve_move") 2112]) 2113 2114;; 2115;; [vminnmvq_f]) 2116;; 2117(define_insn "mve_vminnmvq_f<mode>" 2118 [ 2119 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 2120 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 2121 (match_operand:MVE_0 2 "s_register_operand" "w")] 2122 VMINNMVQ_F)) 2123 ] 2124 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2125 "vminnmv.f%#<V_sz_elem> %0, %q2" 2126 [(set_attr "type" "mve_move") 2127]) 2128 2129;; 2130;; [vmlaldavq_u, vmlaldavq_s]) 2131;; 2132(define_insn "mve_vmlaldavq_<supf><mode>" 2133 [ 2134 (set (match_operand:DI 0 "s_register_operand" "=r") 2135 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 2136 (match_operand:MVE_5 2 "s_register_operand" "w")] 2137 VMLALDAVQ)) 2138 ] 2139 "TARGET_HAVE_MVE" 2140 "vmlaldav.<supf>%#<V_sz_elem> %Q0, %R0, %q1, %q2" 2141 [(set_attr "type" "mve_move") 2142]) 2143 2144;; 2145;; [vmlaldavxq_s]) 2146;; 2147(define_insn "mve_vmlaldavxq_s<mode>" 2148 [ 2149 (set (match_operand:DI 0 "s_register_operand" "=r") 2150 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 2151 (match_operand:MVE_5 2 "s_register_operand" "w")] 2152 VMLALDAVXQ_S)) 2153 ] 2154 "TARGET_HAVE_MVE" 2155 "vmlaldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 2156 [(set_attr "type" "mve_move") 2157]) 2158 2159;; 2160;; [vmlsldavq_s]) 2161;; 2162(define_insn "mve_vmlsldavq_s<mode>" 2163 [ 2164 (set (match_operand:DI 0 "s_register_operand" "=r") 2165 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 2166 (match_operand:MVE_5 2 "s_register_operand" "w")] 2167 VMLSLDAVQ_S)) 2168 ] 2169 "TARGET_HAVE_MVE" 2170 "vmlsldav.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 2171 [(set_attr "type" "mve_move") 2172]) 2173 2174;; 2175;; [vmlsldavxq_s]) 2176;; 2177(define_insn "mve_vmlsldavxq_s<mode>" 2178 [ 2179 (set (match_operand:DI 0 "s_register_operand" "=r") 2180 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 2181 (match_operand:MVE_5 2 "s_register_operand" "w")] 2182 VMLSLDAVXQ_S)) 2183 ] 2184 "TARGET_HAVE_MVE" 2185 "vmlsldavx.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 2186 [(set_attr "type" "mve_move") 2187]) 2188 2189;; 2190;; [vmovnbq_u, vmovnbq_s]) 2191;; 2192(define_insn "mve_vmovnbq_<supf><mode>" 2193 [ 2194 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2195 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2196 (match_operand:MVE_5 2 "s_register_operand" "w")] 2197 VMOVNBQ)) 2198 ] 2199 "TARGET_HAVE_MVE" 2200 "vmovnb.i%#<V_sz_elem> %q0, %q2" 2201 [(set_attr "type" "mve_move") 2202]) 2203 2204;; 2205;; [vmovntq_s, vmovntq_u]) 2206;; 2207(define_insn "mve_vmovntq_<supf><mode>" 2208 [ 2209 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2210 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2211 (match_operand:MVE_5 2 "s_register_operand" "w")] 2212 VMOVNTQ)) 2213 ] 2214 "TARGET_HAVE_MVE" 2215 "vmovnt.i%#<V_sz_elem> %q0, %q2" 2216 [(set_attr "type" "mve_move") 2217]) 2218 2219;; 2220;; [vmulq_f]) 2221;; 2222(define_insn "mve_vmulq_f<mode>" 2223 [ 2224 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2225 (mult:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 2226 (match_operand:MVE_0 2 "s_register_operand" "w"))) 2227 ] 2228 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2229 "vmul.f%#<V_sz_elem> %q0, %q1, %q2" 2230 [(set_attr "type" "mve_move") 2231]) 2232 2233;; 2234;; [vmulq_n_f]) 2235;; 2236(define_insn "mve_vmulq_n_f<mode>" 2237 [ 2238 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2239 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 2240 (match_operand:<V_elem> 2 "s_register_operand" "r")] 2241 VMULQ_N_F)) 2242 ] 2243 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2244 "vmul.f%#<V_sz_elem> %q0, %q1, %2" 2245 [(set_attr "type" "mve_move") 2246]) 2247 2248;; 2249;; [vornq_f]) 2250;; 2251(define_insn "mve_vornq_f<mode>" 2252 [ 2253 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2254 (ior:MVE_0 (not:MVE_0 (match_operand:MVE_0 2 "s_register_operand" "w")) 2255 (match_operand:MVE_0 1 "s_register_operand" "w"))) 2256 ] 2257 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2258 "vorn\t%q0, %q1, %q2" 2259 [(set_attr "type" "mve_move") 2260]) 2261 2262;; 2263;; [vorrq_f]) 2264;; 2265(define_insn "mve_vorrq_f<mode>" 2266 [ 2267 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2268 (ior:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 2269 (match_operand:MVE_0 2 "s_register_operand" "w"))) 2270 ] 2271 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2272 "vorr\t%q0, %q1, %q2" 2273 [(set_attr "type" "mve_move") 2274]) 2275 2276;; 2277;; [vorrq_n_u, vorrq_n_s]) 2278;; 2279(define_insn "mve_vorrq_n_<supf><mode>" 2280 [ 2281 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 2282 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 2283 (match_operand:SI 2 "immediate_operand" "i")] 2284 VORRQ_N)) 2285 ] 2286 "TARGET_HAVE_MVE" 2287 "vorr.i%#<V_sz_elem> %q0, %2" 2288 [(set_attr "type" "mve_move") 2289]) 2290 2291;; 2292;; [vqdmullbq_n_s]) 2293;; 2294(define_insn "mve_vqdmullbq_n_s<mode>" 2295 [ 2296 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 2297 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") 2298 (match_operand:<V_elem> 2 "s_register_operand" "r")] 2299 VQDMULLBQ_N_S)) 2300 ] 2301 "TARGET_HAVE_MVE" 2302 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %2" 2303 [(set_attr "type" "mve_move") 2304]) 2305 2306;; 2307;; [vqdmullbq_s]) 2308;; 2309(define_insn "mve_vqdmullbq_s<mode>" 2310 [ 2311 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 2312 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") 2313 (match_operand:MVE_5 2 "s_register_operand" "w")] 2314 VQDMULLBQ_S)) 2315 ] 2316 "TARGET_HAVE_MVE" 2317 "vqdmullb.s%#<V_sz_elem> %q0, %q1, %q2" 2318 [(set_attr "type" "mve_move") 2319]) 2320 2321;; 2322;; [vqdmulltq_n_s]) 2323;; 2324(define_insn "mve_vqdmulltq_n_s<mode>" 2325 [ 2326 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 2327 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") 2328 (match_operand:<V_elem> 2 "s_register_operand" "r")] 2329 VQDMULLTQ_N_S)) 2330 ] 2331 "TARGET_HAVE_MVE" 2332 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %2" 2333 [(set_attr "type" "mve_move") 2334]) 2335 2336;; 2337;; [vqdmulltq_s]) 2338;; 2339(define_insn "mve_vqdmulltq_s<mode>" 2340 [ 2341 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 2342 (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w") 2343 (match_operand:MVE_5 2 "s_register_operand" "w")] 2344 VQDMULLTQ_S)) 2345 ] 2346 "TARGET_HAVE_MVE" 2347 "vqdmullt.s%#<V_sz_elem> %q0, %q1, %q2" 2348 [(set_attr "type" "mve_move") 2349]) 2350 2351;; 2352;; [vqmovnbq_u, vqmovnbq_s]) 2353;; 2354(define_insn "mve_vqmovnbq_<supf><mode>" 2355 [ 2356 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2357 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2358 (match_operand:MVE_5 2 "s_register_operand" "w")] 2359 VQMOVNBQ)) 2360 ] 2361 "TARGET_HAVE_MVE" 2362 "vqmovnb.<supf>%#<V_sz_elem> %q0, %q2" 2363 [(set_attr "type" "mve_move") 2364]) 2365 2366;; 2367;; [vqmovntq_u, vqmovntq_s]) 2368;; 2369(define_insn "mve_vqmovntq_<supf><mode>" 2370 [ 2371 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2372 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2373 (match_operand:MVE_5 2 "s_register_operand" "w")] 2374 VQMOVNTQ)) 2375 ] 2376 "TARGET_HAVE_MVE" 2377 "vqmovnt.<supf>%#<V_sz_elem> %q0, %q2" 2378 [(set_attr "type" "mve_move") 2379]) 2380 2381;; 2382;; [vqmovunbq_s]) 2383;; 2384(define_insn "mve_vqmovunbq_s<mode>" 2385 [ 2386 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2387 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2388 (match_operand:MVE_5 2 "s_register_operand" "w")] 2389 VQMOVUNBQ_S)) 2390 ] 2391 "TARGET_HAVE_MVE" 2392 "vqmovunb.s%#<V_sz_elem> %q0, %q2" 2393 [(set_attr "type" "mve_move") 2394]) 2395 2396;; 2397;; [vqmovuntq_s]) 2398;; 2399(define_insn "mve_vqmovuntq_s<mode>" 2400 [ 2401 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2402 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2403 (match_operand:MVE_5 2 "s_register_operand" "w")] 2404 VQMOVUNTQ_S)) 2405 ] 2406 "TARGET_HAVE_MVE" 2407 "vqmovunt.s%#<V_sz_elem> %q0, %q2" 2408 [(set_attr "type" "mve_move") 2409]) 2410 2411;; 2412;; [vrmlaldavhxq_s]) 2413;; 2414(define_insn "mve_vrmlaldavhxq_sv4si" 2415 [ 2416 (set (match_operand:DI 0 "s_register_operand" "=r") 2417 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 2418 (match_operand:V4SI 2 "s_register_operand" "w")] 2419 VRMLALDAVHXQ_S)) 2420 ] 2421 "TARGET_HAVE_MVE" 2422 "vrmlaldavhx.s32\t%Q0, %R0, %q1, %q2" 2423 [(set_attr "type" "mve_move") 2424]) 2425 2426;; 2427;; [vrmlsldavhq_s]) 2428;; 2429(define_insn "mve_vrmlsldavhq_sv4si" 2430 [ 2431 (set (match_operand:DI 0 "s_register_operand" "=r") 2432 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 2433 (match_operand:V4SI 2 "s_register_operand" "w")] 2434 VRMLSLDAVHQ_S)) 2435 ] 2436 "TARGET_HAVE_MVE" 2437 "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2" 2438 [(set_attr "type" "mve_move") 2439]) 2440 2441;; 2442;; [vrmlsldavhxq_s]) 2443;; 2444(define_insn "mve_vrmlsldavhxq_sv4si" 2445 [ 2446 (set (match_operand:DI 0 "s_register_operand" "=r") 2447 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 2448 (match_operand:V4SI 2 "s_register_operand" "w")] 2449 VRMLSLDAVHXQ_S)) 2450 ] 2451 "TARGET_HAVE_MVE" 2452 "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2" 2453 [(set_attr "type" "mve_move") 2454]) 2455 2456;; 2457;; [vshllbq_n_s, vshllbq_n_u]) 2458;; 2459(define_insn "mve_vshllbq_n_<supf><mode>" 2460 [ 2461 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 2462 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") 2463 (match_operand:SI 2 "immediate_operand" "i")] 2464 VSHLLBQ_N)) 2465 ] 2466 "TARGET_HAVE_MVE" 2467 "vshllb.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 2468 [(set_attr "type" "mve_move") 2469]) 2470 2471;; 2472;; [vshlltq_n_u, vshlltq_n_s]) 2473;; 2474(define_insn "mve_vshlltq_n_<supf><mode>" 2475 [ 2476 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 2477 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") 2478 (match_operand:SI 2 "immediate_operand" "i")] 2479 VSHLLTQ_N)) 2480 ] 2481 "TARGET_HAVE_MVE" 2482 "vshllt.<supf>%#<V_sz_elem>\t%q0, %q1, %2" 2483 [(set_attr "type" "mve_move") 2484]) 2485 2486;; 2487;; [vsubq_f]) 2488;; 2489(define_insn "mve_vsubq_f<mode>" 2490 [ 2491 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2492 (minus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 2493 (match_operand:MVE_0 2 "s_register_operand" "w"))) 2494 ] 2495 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2496 "vsub.f%#<V_sz_elem>\t%q0, %q1, %q2" 2497 [(set_attr "type" "mve_move") 2498]) 2499 2500;; 2501;; [vmulltq_poly_p]) 2502;; 2503(define_insn "mve_vmulltq_poly_p<mode>" 2504 [ 2505 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 2506 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") 2507 (match_operand:MVE_3 2 "s_register_operand" "w")] 2508 VMULLTQ_POLY_P)) 2509 ] 2510 "TARGET_HAVE_MVE" 2511 "vmullt.p%#<V_sz_elem>\t%q0, %q1, %q2" 2512 [(set_attr "type" "mve_move") 2513]) 2514 2515;; 2516;; [vmullbq_poly_p]) 2517;; 2518(define_insn "mve_vmullbq_poly_p<mode>" 2519 [ 2520 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 2521 (unspec:<V_double_width> [(match_operand:MVE_3 1 "s_register_operand" "w") 2522 (match_operand:MVE_3 2 "s_register_operand" "w")] 2523 VMULLBQ_POLY_P)) 2524 ] 2525 "TARGET_HAVE_MVE" 2526 "vmullb.p%#<V_sz_elem>\t%q0, %q1, %q2" 2527 [(set_attr "type" "mve_move") 2528]) 2529 2530;; 2531;; [vrmlaldavhq_u vrmlaldavhq_s]) 2532;; 2533(define_insn "mve_vrmlaldavhq_<supf>v4si" 2534 [ 2535 (set (match_operand:DI 0 "s_register_operand" "=r") 2536 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 2537 (match_operand:V4SI 2 "s_register_operand" "w")] 2538 VRMLALDAVHQ)) 2539 ] 2540 "TARGET_HAVE_MVE" 2541 "vrmlaldavh.<supf>32\t%Q0, %R0, %q1, %q2" 2542 [(set_attr "type" "mve_move") 2543]) 2544 2545;; 2546;; [vbicq_m_n_s, vbicq_m_n_u]) 2547;; 2548(define_insn "mve_vbicq_m_n_<supf><mode>" 2549 [ 2550 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 2551 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 2552 (match_operand:SI 2 "immediate_operand" "i") 2553 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2554 VBICQ_M_N)) 2555 ] 2556 "TARGET_HAVE_MVE" 2557 "vpst\;vbict.i%#<V_sz_elem>\t%q0, %2" 2558 [(set_attr "type" "mve_move") 2559 (set_attr "length""8")]) 2560;; 2561;; [vcmpeqq_m_f]) 2562;; 2563(define_insn "mve_vcmpeqq_m_f<mode>" 2564 [ 2565 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2566 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 2567 (match_operand:MVE_0 2 "s_register_operand" "w") 2568 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2569 VCMPEQQ_M_F)) 2570 ] 2571 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2572 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %q2" 2573 [(set_attr "type" "mve_move") 2574 (set_attr "length""8")]) 2575;; 2576;; [vcvtaq_m_u, vcvtaq_m_s]) 2577;; 2578(define_insn "mve_vcvtaq_m_<supf><mode>" 2579 [ 2580 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 2581 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 2582 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 2583 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2584 VCVTAQ_M)) 2585 ] 2586 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2587 "vpst\;vcvtat.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" 2588 [(set_attr "type" "mve_move") 2589 (set_attr "length""8")]) 2590;; 2591;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) 2592;; 2593(define_insn "mve_vcvtq_m_to_f_<supf><mode>" 2594 [ 2595 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 2596 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 2597 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 2598 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2599 VCVTQ_M_TO_F)) 2600 ] 2601 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 2602 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2" 2603 [(set_attr "type" "mve_move") 2604 (set_attr "length""8")]) 2605;; 2606;; [vqrshrnbq_n_u, vqrshrnbq_n_s]) 2607;; 2608(define_insn "mve_vqrshrnbq_n_<supf><mode>" 2609 [ 2610 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2611 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2612 (match_operand:MVE_5 2 "s_register_operand" "w") 2613 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 2614 VQRSHRNBQ_N)) 2615 ] 2616 "TARGET_HAVE_MVE" 2617 "vqrshrnb.<supf>%#<V_sz_elem> %q0, %q2, %3" 2618 [(set_attr "type" "mve_move") 2619]) 2620;; 2621;; [vqrshrunbq_n_s]) 2622;; 2623(define_insn "mve_vqrshrunbq_n_s<mode>" 2624 [ 2625 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 2626 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 2627 (match_operand:MVE_5 2 "s_register_operand" "w") 2628 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 2629 VQRSHRUNBQ_N_S)) 2630 ] 2631 "TARGET_HAVE_MVE" 2632 "vqrshrunb.s%#<V_sz_elem>\t%q0, %q2, %3" 2633 [(set_attr "type" "mve_move") 2634]) 2635;; 2636;; [vrmlaldavhaq_s vrmlaldavhaq_u]) 2637;; 2638(define_insn "mve_vrmlaldavhaq_<supf>v4si" 2639 [ 2640 (set (match_operand:DI 0 "s_register_operand" "=r") 2641 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 2642 (match_operand:V4SI 2 "s_register_operand" "w") 2643 (match_operand:V4SI 3 "s_register_operand" "w")] 2644 VRMLALDAVHAQ)) 2645 ] 2646 "TARGET_HAVE_MVE" 2647 "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3" 2648 [(set_attr "type" "mve_move") 2649]) 2650 2651;; 2652;; [vabavq_s, vabavq_u]) 2653;; 2654(define_insn "mve_vabavq_<supf><mode>" 2655 [ 2656 (set (match_operand:SI 0 "s_register_operand" "=r") 2657 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 2658 (match_operand:MVE_2 2 "s_register_operand" "w") 2659 (match_operand:MVE_2 3 "s_register_operand" "w")] 2660 VABAVQ)) 2661 ] 2662 "TARGET_HAVE_MVE" 2663 "vabav.<supf>%#<V_sz_elem>\t%0, %q2, %q3" 2664 [(set_attr "type" "mve_move") 2665]) 2666 2667;; 2668;; [vshlcq_u vshlcq_s] 2669;; 2670(define_expand "mve_vshlcq_vec_<supf><mode>" 2671 [(match_operand:MVE_2 0 "s_register_operand") 2672 (match_operand:MVE_2 1 "s_register_operand") 2673 (match_operand:SI 2 "s_register_operand") 2674 (match_operand:SI 3 "mve_imm_32") 2675 (unspec:MVE_2 [(const_int 0)] VSHLCQ)] 2676 "TARGET_HAVE_MVE" 2677{ 2678 rtx ignore_wb = gen_reg_rtx (SImode); 2679 emit_insn(gen_mve_vshlcq_<supf><mode>(operands[0], ignore_wb, operands[1], 2680 operands[2], operands[3])); 2681 DONE; 2682}) 2683 2684(define_expand "mve_vshlcq_carry_<supf><mode>" 2685 [(match_operand:SI 0 "s_register_operand") 2686 (match_operand:MVE_2 1 "s_register_operand") 2687 (match_operand:SI 2 "s_register_operand") 2688 (match_operand:SI 3 "mve_imm_32") 2689 (unspec:MVE_2 [(const_int 0)] VSHLCQ)] 2690 "TARGET_HAVE_MVE" 2691{ 2692 rtx ignore_vec = gen_reg_rtx (<MODE>mode); 2693 emit_insn(gen_mve_vshlcq_<supf><mode>(ignore_vec, operands[0], operands[1], 2694 operands[2], operands[3])); 2695 DONE; 2696}) 2697 2698(define_insn "mve_vshlcq_<supf><mode>" 2699 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 2700 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") 2701 (match_operand:SI 3 "s_register_operand" "1") 2702 (match_operand:SI 4 "mve_imm_32" "Rf")] 2703 VSHLCQ)) 2704 (set (match_operand:SI 1 "s_register_operand" "=r") 2705 (unspec:SI [(match_dup 2) 2706 (match_dup 3) 2707 (match_dup 4)] 2708 VSHLCQ))] 2709 "TARGET_HAVE_MVE" 2710 "vshlc\t%q0, %1, %4") 2711 2712;; 2713;; [vabsq_m_s]) 2714;; 2715(define_insn "mve_vabsq_m_s<mode>" 2716 [ 2717 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 2718 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 2719 (match_operand:MVE_2 2 "s_register_operand" "w") 2720 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2721 VABSQ_M_S)) 2722 ] 2723 "TARGET_HAVE_MVE" 2724 "vpst\;vabst.s%#<V_sz_elem> %q0, %q2" 2725 [(set_attr "type" "mve_move") 2726 (set_attr "length""8")]) 2727 2728;; 2729;; [vaddvaq_p_u, vaddvaq_p_s]) 2730;; 2731(define_insn "mve_vaddvaq_p_<supf><mode>" 2732 [ 2733 (set (match_operand:SI 0 "s_register_operand" "=Te") 2734 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 2735 (match_operand:MVE_2 2 "s_register_operand" "w") 2736 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2737 VADDVAQ_P)) 2738 ] 2739 "TARGET_HAVE_MVE" 2740 "vpst\;vaddvat.<supf>%#<V_sz_elem> %0, %q2" 2741 [(set_attr "type" "mve_move") 2742 (set_attr "length""8")]) 2743 2744;; 2745;; [vclsq_m_s]) 2746;; 2747(define_insn "mve_vclsq_m_s<mode>" 2748 [ 2749 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 2750 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 2751 (match_operand:MVE_2 2 "s_register_operand" "w") 2752 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2753 VCLSQ_M_S)) 2754 ] 2755 "TARGET_HAVE_MVE" 2756 "vpst\;vclst.s%#<V_sz_elem> %q0, %q2" 2757 [(set_attr "type" "mve_move") 2758 (set_attr "length""8")]) 2759 2760;; 2761;; [vclzq_m_s, vclzq_m_u]) 2762;; 2763(define_insn "mve_vclzq_m_<supf><mode>" 2764 [ 2765 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 2766 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 2767 (match_operand:MVE_2 2 "s_register_operand" "w") 2768 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2769 VCLZQ_M)) 2770 ] 2771 "TARGET_HAVE_MVE" 2772 "vpst\;vclzt.i%#<V_sz_elem> %q0, %q2" 2773 [(set_attr "type" "mve_move") 2774 (set_attr "length""8")]) 2775 2776;; 2777;; [vcmpcsq_m_n_u]) 2778;; 2779(define_insn "mve_vcmpcsq_m_n_u<mode>" 2780 [ 2781 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2782 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2783 (match_operand:<V_elem> 2 "s_register_operand" "r") 2784 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2785 VCMPCSQ_M_N_U)) 2786 ] 2787 "TARGET_HAVE_MVE" 2788 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %2" 2789 [(set_attr "type" "mve_move") 2790 (set_attr "length""8")]) 2791 2792;; 2793;; [vcmpcsq_m_u]) 2794;; 2795(define_insn "mve_vcmpcsq_m_u<mode>" 2796 [ 2797 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2798 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2799 (match_operand:MVE_2 2 "s_register_operand" "w") 2800 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2801 VCMPCSQ_M_U)) 2802 ] 2803 "TARGET_HAVE_MVE" 2804 "vpst\;vcmpt.u%#<V_sz_elem> cs, %q1, %q2" 2805 [(set_attr "type" "mve_move") 2806 (set_attr "length""8")]) 2807 2808;; 2809;; [vcmpeqq_m_n_u, vcmpeqq_m_n_s]) 2810;; 2811(define_insn "mve_vcmpeqq_m_n_<supf><mode>" 2812 [ 2813 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2814 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2815 (match_operand:<V_elem> 2 "s_register_operand" "r") 2816 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2817 VCMPEQQ_M_N)) 2818 ] 2819 "TARGET_HAVE_MVE" 2820 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %2" 2821 [(set_attr "type" "mve_move") 2822 (set_attr "length""8")]) 2823 2824;; 2825;; [vcmpeqq_m_u, vcmpeqq_m_s]) 2826;; 2827(define_insn "mve_vcmpeqq_m_<supf><mode>" 2828 [ 2829 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2830 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2831 (match_operand:MVE_2 2 "s_register_operand" "w") 2832 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2833 VCMPEQQ_M)) 2834 ] 2835 "TARGET_HAVE_MVE" 2836 "vpst\;vcmpt.i%#<V_sz_elem> eq, %q1, %q2" 2837 [(set_attr "type" "mve_move") 2838 (set_attr "length""8")]) 2839 2840;; 2841;; [vcmpgeq_m_n_s]) 2842;; 2843(define_insn "mve_vcmpgeq_m_n_s<mode>" 2844 [ 2845 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2846 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2847 (match_operand:<V_elem> 2 "s_register_operand" "r") 2848 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2849 VCMPGEQ_M_N_S)) 2850 ] 2851 "TARGET_HAVE_MVE" 2852 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %2" 2853 [(set_attr "type" "mve_move") 2854 (set_attr "length""8")]) 2855 2856;; 2857;; [vcmpgeq_m_s]) 2858;; 2859(define_insn "mve_vcmpgeq_m_s<mode>" 2860 [ 2861 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2862 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2863 (match_operand:MVE_2 2 "s_register_operand" "w") 2864 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2865 VCMPGEQ_M_S)) 2866 ] 2867 "TARGET_HAVE_MVE" 2868 "vpst\;vcmpt.s%#<V_sz_elem> ge, %q1, %q2" 2869 [(set_attr "type" "mve_move") 2870 (set_attr "length""8")]) 2871 2872;; 2873;; [vcmpgtq_m_n_s]) 2874;; 2875(define_insn "mve_vcmpgtq_m_n_s<mode>" 2876 [ 2877 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2878 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2879 (match_operand:<V_elem> 2 "s_register_operand" "r") 2880 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2881 VCMPGTQ_M_N_S)) 2882 ] 2883 "TARGET_HAVE_MVE" 2884 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %2" 2885 [(set_attr "type" "mve_move") 2886 (set_attr "length""8")]) 2887 2888;; 2889;; [vcmpgtq_m_s]) 2890;; 2891(define_insn "mve_vcmpgtq_m_s<mode>" 2892 [ 2893 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2894 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2895 (match_operand:MVE_2 2 "s_register_operand" "w") 2896 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2897 VCMPGTQ_M_S)) 2898 ] 2899 "TARGET_HAVE_MVE" 2900 "vpst\;vcmpt.s%#<V_sz_elem> gt, %q1, %q2" 2901 [(set_attr "type" "mve_move") 2902 (set_attr "length""8")]) 2903 2904;; 2905;; [vcmphiq_m_n_u]) 2906;; 2907(define_insn "mve_vcmphiq_m_n_u<mode>" 2908 [ 2909 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2910 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2911 (match_operand:<V_elem> 2 "s_register_operand" "r") 2912 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2913 VCMPHIQ_M_N_U)) 2914 ] 2915 "TARGET_HAVE_MVE" 2916 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %2" 2917 [(set_attr "type" "mve_move") 2918 (set_attr "length""8")]) 2919 2920;; 2921;; [vcmphiq_m_u]) 2922;; 2923(define_insn "mve_vcmphiq_m_u<mode>" 2924 [ 2925 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2926 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2927 (match_operand:MVE_2 2 "s_register_operand" "w") 2928 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2929 VCMPHIQ_M_U)) 2930 ] 2931 "TARGET_HAVE_MVE" 2932 "vpst\;vcmpt.u%#<V_sz_elem> hi, %q1, %q2" 2933 [(set_attr "type" "mve_move") 2934 (set_attr "length""8")]) 2935 2936;; 2937;; [vcmpleq_m_n_s]) 2938;; 2939(define_insn "mve_vcmpleq_m_n_s<mode>" 2940 [ 2941 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2942 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2943 (match_operand:<V_elem> 2 "s_register_operand" "r") 2944 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2945 VCMPLEQ_M_N_S)) 2946 ] 2947 "TARGET_HAVE_MVE" 2948 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %2" 2949 [(set_attr "type" "mve_move") 2950 (set_attr "length""8")]) 2951 2952;; 2953;; [vcmpleq_m_s]) 2954;; 2955(define_insn "mve_vcmpleq_m_s<mode>" 2956 [ 2957 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2958 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2959 (match_operand:MVE_2 2 "s_register_operand" "w") 2960 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2961 VCMPLEQ_M_S)) 2962 ] 2963 "TARGET_HAVE_MVE" 2964 "vpst\;vcmpt.s%#<V_sz_elem> le, %q1, %q2" 2965 [(set_attr "type" "mve_move") 2966 (set_attr "length""8")]) 2967 2968;; 2969;; [vcmpltq_m_n_s]) 2970;; 2971(define_insn "mve_vcmpltq_m_n_s<mode>" 2972 [ 2973 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2974 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2975 (match_operand:<V_elem> 2 "s_register_operand" "r") 2976 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2977 VCMPLTQ_M_N_S)) 2978 ] 2979 "TARGET_HAVE_MVE" 2980 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %2" 2981 [(set_attr "type" "mve_move") 2982 (set_attr "length""8")]) 2983 2984;; 2985;; [vcmpltq_m_s]) 2986;; 2987(define_insn "mve_vcmpltq_m_s<mode>" 2988 [ 2989 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 2990 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 2991 (match_operand:MVE_2 2 "s_register_operand" "w") 2992 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 2993 VCMPLTQ_M_S)) 2994 ] 2995 "TARGET_HAVE_MVE" 2996 "vpst\;vcmpt.s%#<V_sz_elem> lt, %q1, %q2" 2997 [(set_attr "type" "mve_move") 2998 (set_attr "length""8")]) 2999 3000;; 3001;; [vcmpneq_m_n_u, vcmpneq_m_n_s]) 3002;; 3003(define_insn "mve_vcmpneq_m_n_<supf><mode>" 3004 [ 3005 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3006 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 3007 (match_operand:<V_elem> 2 "s_register_operand" "r") 3008 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3009 VCMPNEQ_M_N)) 3010 ] 3011 "TARGET_HAVE_MVE" 3012 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %2" 3013 [(set_attr "type" "mve_move") 3014 (set_attr "length""8")]) 3015 3016;; 3017;; [vcmpneq_m_s, vcmpneq_m_u]) 3018;; 3019(define_insn "mve_vcmpneq_m_<supf><mode>" 3020 [ 3021 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3022 (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w") 3023 (match_operand:MVE_2 2 "s_register_operand" "w") 3024 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3025 VCMPNEQ_M)) 3026 ] 3027 "TARGET_HAVE_MVE" 3028 "vpst\;vcmpt.i%#<V_sz_elem> ne, %q1, %q2" 3029 [(set_attr "type" "mve_move") 3030 (set_attr "length""8")]) 3031 3032;; 3033;; [vdupq_m_n_s, vdupq_m_n_u]) 3034;; 3035(define_insn "mve_vdupq_m_n_<supf><mode>" 3036 [ 3037 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3038 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3039 (match_operand:<V_elem> 2 "s_register_operand" "r") 3040 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3041 VDUPQ_M_N)) 3042 ] 3043 "TARGET_HAVE_MVE" 3044 "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2" 3045 [(set_attr "type" "mve_move") 3046 (set_attr "length""8")]) 3047 3048;; 3049;; [vmaxaq_m_s]) 3050;; 3051(define_insn "mve_vmaxaq_m_s<mode>" 3052 [ 3053 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3054 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3055 (match_operand:MVE_2 2 "s_register_operand" "w") 3056 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3057 VMAXAQ_M_S)) 3058 ] 3059 "TARGET_HAVE_MVE" 3060 "vpst\;vmaxat.s%#<V_sz_elem> %q0, %q2" 3061 [(set_attr "type" "mve_move") 3062 (set_attr "length""8")]) 3063 3064;; 3065;; [vmaxavq_p_s]) 3066;; 3067(define_insn "mve_vmaxavq_p_s<mode>" 3068 [ 3069 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 3070 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 3071 (match_operand:MVE_2 2 "s_register_operand" "w") 3072 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3073 VMAXAVQ_P_S)) 3074 ] 3075 "TARGET_HAVE_MVE" 3076 "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2" 3077 [(set_attr "type" "mve_move") 3078 (set_attr "length""8")]) 3079 3080;; 3081;; [vmaxvq_p_u, vmaxvq_p_s]) 3082;; 3083(define_insn "mve_vmaxvq_p_<supf><mode>" 3084 [ 3085 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 3086 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 3087 (match_operand:MVE_2 2 "s_register_operand" "w") 3088 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3089 VMAXVQ_P)) 3090 ] 3091 "TARGET_HAVE_MVE" 3092 "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2" 3093 [(set_attr "type" "mve_move") 3094 (set_attr "length""8")]) 3095 3096;; 3097;; [vminaq_m_s]) 3098;; 3099(define_insn "mve_vminaq_m_s<mode>" 3100 [ 3101 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3102 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3103 (match_operand:MVE_2 2 "s_register_operand" "w") 3104 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3105 VMINAQ_M_S)) 3106 ] 3107 "TARGET_HAVE_MVE" 3108 "vpst\;vminat.s%#<V_sz_elem> %q0, %q2" 3109 [(set_attr "type" "mve_move") 3110 (set_attr "length""8")]) 3111 3112;; 3113;; [vminavq_p_s]) 3114;; 3115(define_insn "mve_vminavq_p_s<mode>" 3116 [ 3117 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 3118 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 3119 (match_operand:MVE_2 2 "s_register_operand" "w") 3120 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3121 VMINAVQ_P_S)) 3122 ] 3123 "TARGET_HAVE_MVE" 3124 "vpst\;vminavt.s%#<V_sz_elem> %0, %q2" 3125 [(set_attr "type" "mve_move") 3126 (set_attr "length""8")]) 3127 3128;; 3129;; [vminvq_p_s, vminvq_p_u]) 3130;; 3131(define_insn "mve_vminvq_p_<supf><mode>" 3132 [ 3133 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 3134 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 3135 (match_operand:MVE_2 2 "s_register_operand" "w") 3136 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3137 VMINVQ_P)) 3138 ] 3139 "TARGET_HAVE_MVE" 3140 "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2" 3141 [(set_attr "type" "mve_move") 3142 (set_attr "length""8")]) 3143 3144;; 3145;; [vmladavaq_u, vmladavaq_s]) 3146;; 3147(define_insn "mve_vmladavaq_<supf><mode>" 3148 [ 3149 (set (match_operand:SI 0 "s_register_operand" "=Te") 3150 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 3151 (match_operand:MVE_2 2 "s_register_operand" "w") 3152 (match_operand:MVE_2 3 "s_register_operand" "w")] 3153 VMLADAVAQ)) 3154 ] 3155 "TARGET_HAVE_MVE" 3156 "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3" 3157 [(set_attr "type" "mve_move") 3158]) 3159 3160;; 3161;; [vmladavq_p_u, vmladavq_p_s]) 3162;; 3163(define_insn "mve_vmladavq_p_<supf><mode>" 3164 [ 3165 (set (match_operand:SI 0 "s_register_operand" "=Te") 3166 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 3167 (match_operand:MVE_2 2 "s_register_operand" "w") 3168 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3169 VMLADAVQ_P)) 3170 ] 3171 "TARGET_HAVE_MVE" 3172 "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2" 3173 [(set_attr "type" "mve_move") 3174 (set_attr "length""8")]) 3175 3176;; 3177;; [vmladavxq_p_s]) 3178;; 3179(define_insn "mve_vmladavxq_p_s<mode>" 3180 [ 3181 (set (match_operand:SI 0 "s_register_operand" "=Te") 3182 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 3183 (match_operand:MVE_2 2 "s_register_operand" "w") 3184 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3185 VMLADAVXQ_P_S)) 3186 ] 3187 "TARGET_HAVE_MVE" 3188 "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2" 3189 [(set_attr "type" "mve_move") 3190 (set_attr "length""8")]) 3191 3192;; 3193;; [vmlaq_n_u, vmlaq_n_s]) 3194;; 3195(define_insn "mve_vmlaq_n_<supf><mode>" 3196 [ 3197 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3198 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3199 (match_operand:MVE_2 2 "s_register_operand" "w") 3200 (match_operand:<V_elem> 3 "s_register_operand" "r")] 3201 VMLAQ_N)) 3202 ] 3203 "TARGET_HAVE_MVE" 3204 "vmla.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 3205 [(set_attr "type" "mve_move") 3206]) 3207 3208;; 3209;; [vmlasq_n_u, vmlasq_n_s]) 3210;; 3211(define_insn "mve_vmlasq_n_<supf><mode>" 3212 [ 3213 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3214 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3215 (match_operand:MVE_2 2 "s_register_operand" "w") 3216 (match_operand:<V_elem> 3 "s_register_operand" "r")] 3217 VMLASQ_N)) 3218 ] 3219 "TARGET_HAVE_MVE" 3220 "vmlas.<supf>%#<V_sz_elem> %q0, %q2, %3" 3221 [(set_attr "type" "mve_move") 3222]) 3223 3224;; 3225;; [vmlsdavq_p_s]) 3226;; 3227(define_insn "mve_vmlsdavq_p_s<mode>" 3228 [ 3229 (set (match_operand:SI 0 "s_register_operand" "=Te") 3230 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 3231 (match_operand:MVE_2 2 "s_register_operand" "w") 3232 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3233 VMLSDAVQ_P_S)) 3234 ] 3235 "TARGET_HAVE_MVE" 3236 "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2" 3237 [(set_attr "type" "mve_move") 3238 (set_attr "length""8")]) 3239 3240;; 3241;; [vmlsdavxq_p_s]) 3242;; 3243(define_insn "mve_vmlsdavxq_p_s<mode>" 3244 [ 3245 (set (match_operand:SI 0 "s_register_operand" "=Te") 3246 (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w") 3247 (match_operand:MVE_2 2 "s_register_operand" "w") 3248 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3249 VMLSDAVXQ_P_S)) 3250 ] 3251 "TARGET_HAVE_MVE" 3252 "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2" 3253 [(set_attr "type" "mve_move") 3254 (set_attr "length""8")]) 3255 3256;; 3257;; [vmvnq_m_s, vmvnq_m_u]) 3258;; 3259(define_insn "mve_vmvnq_m_<supf><mode>" 3260 [ 3261 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3262 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3263 (match_operand:MVE_2 2 "s_register_operand" "w") 3264 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3265 VMVNQ_M)) 3266 ] 3267 "TARGET_HAVE_MVE" 3268 "vpst\;vmvnt\t%q0, %q2" 3269 [(set_attr "type" "mve_move") 3270 (set_attr "length""8")]) 3271 3272;; 3273;; [vnegq_m_s]) 3274;; 3275(define_insn "mve_vnegq_m_s<mode>" 3276 [ 3277 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3278 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3279 (match_operand:MVE_2 2 "s_register_operand" "w") 3280 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3281 VNEGQ_M_S)) 3282 ] 3283 "TARGET_HAVE_MVE" 3284 "vpst\;vnegt.s%#<V_sz_elem>\t%q0, %q2" 3285 [(set_attr "type" "mve_move") 3286 (set_attr "length""8")]) 3287 3288;; 3289;; [vpselq_u, vpselq_s]) 3290;; 3291(define_insn "@mve_vpselq_<supf><mode>" 3292 [ 3293 (set (match_operand:MVE_1 0 "s_register_operand" "=w") 3294 (unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w") 3295 (match_operand:MVE_1 2 "s_register_operand" "w") 3296 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3297 VPSELQ)) 3298 ] 3299 "TARGET_HAVE_MVE" 3300 "vpsel\t%q0, %q1, %q2" 3301 [(set_attr "type" "mve_move") 3302]) 3303 3304;; 3305;; [vqabsq_m_s]) 3306;; 3307(define_insn "mve_vqabsq_m_s<mode>" 3308 [ 3309 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3310 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3311 (match_operand:MVE_2 2 "s_register_operand" "w") 3312 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3313 VQABSQ_M_S)) 3314 ] 3315 "TARGET_HAVE_MVE" 3316 "vpst\;vqabst.s%#<V_sz_elem>\t%q0, %q2" 3317 [(set_attr "type" "mve_move") 3318 (set_attr "length""8")]) 3319 3320;; 3321;; [vqdmlahq_n_s]) 3322;; 3323(define_insn "mve_vqdmlahq_n_<supf><mode>" 3324 [ 3325 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3326 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3327 (match_operand:MVE_2 2 "s_register_operand" "w") 3328 (match_operand:<V_elem> 3 "s_register_operand" "r")] 3329 VQDMLAHQ_N)) 3330 ] 3331 "TARGET_HAVE_MVE" 3332 "vqdmlah.s%#<V_sz_elem>\t%q0, %q2, %3" 3333 [(set_attr "type" "mve_move") 3334]) 3335 3336;; 3337;; [vqdmlashq_n_s]) 3338;; 3339(define_insn "mve_vqdmlashq_n_<supf><mode>" 3340 [ 3341 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3342 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3343 (match_operand:MVE_2 2 "s_register_operand" "w") 3344 (match_operand:<V_elem> 3 "s_register_operand" "r")] 3345 VQDMLASHQ_N)) 3346 ] 3347 "TARGET_HAVE_MVE" 3348 "vqdmlash.s%#<V_sz_elem>\t%q0, %q2, %3" 3349 [(set_attr "type" "mve_move") 3350]) 3351 3352;; 3353;; [vqnegq_m_s]) 3354;; 3355(define_insn "mve_vqnegq_m_s<mode>" 3356 [ 3357 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3358 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3359 (match_operand:MVE_2 2 "s_register_operand" "w") 3360 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3361 VQNEGQ_M_S)) 3362 ] 3363 "TARGET_HAVE_MVE" 3364 "vpst\;vqnegt.s%#<V_sz_elem> %q0, %q2" 3365 [(set_attr "type" "mve_move") 3366 (set_attr "length""8")]) 3367 3368;; 3369;; [vqrdmladhq_s]) 3370;; 3371(define_insn "mve_vqrdmladhq_s<mode>" 3372 [ 3373 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3374 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3375 (match_operand:MVE_2 2 "s_register_operand" "w") 3376 (match_operand:MVE_2 3 "s_register_operand" "w")] 3377 VQRDMLADHQ_S)) 3378 ] 3379 "TARGET_HAVE_MVE" 3380 "vqrdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3" 3381 [(set_attr "type" "mve_move") 3382]) 3383 3384;; 3385;; [vqrdmladhxq_s]) 3386;; 3387(define_insn "mve_vqrdmladhxq_s<mode>" 3388 [ 3389 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3390 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3391 (match_operand:MVE_2 2 "s_register_operand" "w") 3392 (match_operand:MVE_2 3 "s_register_operand" "w")] 3393 VQRDMLADHXQ_S)) 3394 ] 3395 "TARGET_HAVE_MVE" 3396 "vqrdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3" 3397 [(set_attr "type" "mve_move") 3398]) 3399 3400;; 3401;; [vqrdmlahq_n_s]) 3402;; 3403(define_insn "mve_vqrdmlahq_n_<supf><mode>" 3404 [ 3405 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3406 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3407 (match_operand:MVE_2 2 "s_register_operand" "w") 3408 (match_operand:<V_elem> 3 "s_register_operand" "r")] 3409 VQRDMLAHQ_N)) 3410 ] 3411 "TARGET_HAVE_MVE" 3412 "vqrdmlah.s%#<V_sz_elem>\t%q0, %q2, %3" 3413 [(set_attr "type" "mve_move") 3414]) 3415 3416;; 3417;; [vqrdmlashq_n_s]) 3418;; 3419(define_insn "mve_vqrdmlashq_n_<supf><mode>" 3420 [ 3421 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3422 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3423 (match_operand:MVE_2 2 "s_register_operand" "w") 3424 (match_operand:<V_elem> 3 "s_register_operand" "r")] 3425 VQRDMLASHQ_N)) 3426 ] 3427 "TARGET_HAVE_MVE" 3428 "vqrdmlash.s%#<V_sz_elem>\t%q0, %q2, %3" 3429 [(set_attr "type" "mve_move") 3430]) 3431 3432;; 3433;; [vqrdmlsdhq_s]) 3434;; 3435(define_insn "mve_vqrdmlsdhq_s<mode>" 3436 [ 3437 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3438 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3439 (match_operand:MVE_2 2 "s_register_operand" "w") 3440 (match_operand:MVE_2 3 "s_register_operand" "w")] 3441 VQRDMLSDHQ_S)) 3442 ] 3443 "TARGET_HAVE_MVE" 3444 "vqrdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3" 3445 [(set_attr "type" "mve_move") 3446]) 3447 3448;; 3449;; [vqrdmlsdhxq_s]) 3450;; 3451(define_insn "mve_vqrdmlsdhxq_s<mode>" 3452 [ 3453 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3454 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3455 (match_operand:MVE_2 2 "s_register_operand" "w") 3456 (match_operand:MVE_2 3 "s_register_operand" "w")] 3457 VQRDMLSDHXQ_S)) 3458 ] 3459 "TARGET_HAVE_MVE" 3460 "vqrdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3" 3461 [(set_attr "type" "mve_move") 3462]) 3463 3464;; 3465;; [vqrshlq_m_n_s, vqrshlq_m_n_u]) 3466;; 3467(define_insn "mve_vqrshlq_m_n_<supf><mode>" 3468 [ 3469 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3470 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3471 (match_operand:SI 2 "s_register_operand" "r") 3472 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3473 VQRSHLQ_M_N)) 3474 ] 3475 "TARGET_HAVE_MVE" 3476 "vpst\;vqrshlt.<supf>%#<V_sz_elem> %q0, %2" 3477 [(set_attr "type" "mve_move") 3478 (set_attr "length""8")]) 3479 3480;; 3481;; [vqshlq_m_r_u, vqshlq_m_r_s]) 3482;; 3483(define_insn "mve_vqshlq_m_r_<supf><mode>" 3484 [ 3485 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3486 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3487 (match_operand:SI 2 "s_register_operand" "r") 3488 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3489 VQSHLQ_M_R)) 3490 ] 3491 "TARGET_HAVE_MVE" 3492 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2" 3493 [(set_attr "type" "mve_move") 3494 (set_attr "length""8")]) 3495 3496;; 3497;; [vrev64q_m_u, vrev64q_m_s]) 3498;; 3499(define_insn "mve_vrev64q_m_<supf><mode>" 3500 [ 3501 (set (match_operand:MVE_2 0 "s_register_operand" "=&w") 3502 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3503 (match_operand:MVE_2 2 "s_register_operand" "w") 3504 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3505 VREV64Q_M)) 3506 ] 3507 "TARGET_HAVE_MVE" 3508 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2" 3509 [(set_attr "type" "mve_move") 3510 (set_attr "length""8")]) 3511 3512;; 3513;; [vrshlq_m_n_s, vrshlq_m_n_u]) 3514;; 3515(define_insn "mve_vrshlq_m_n_<supf><mode>" 3516 [ 3517 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3518 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3519 (match_operand:SI 2 "s_register_operand" "r") 3520 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3521 VRSHLQ_M_N)) 3522 ] 3523 "TARGET_HAVE_MVE" 3524 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2" 3525 [(set_attr "type" "mve_move") 3526 (set_attr "length""8")]) 3527 3528;; 3529;; [vshlq_m_r_u, vshlq_m_r_s]) 3530;; 3531(define_insn "mve_vshlq_m_r_<supf><mode>" 3532 [ 3533 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3534 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3535 (match_operand:SI 2 "s_register_operand" "r") 3536 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3537 VSHLQ_M_R)) 3538 ] 3539 "TARGET_HAVE_MVE" 3540 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2" 3541 [(set_attr "type" "mve_move") 3542 (set_attr "length""8")]) 3543 3544;; 3545;; [vsliq_n_u, vsliq_n_s]) 3546;; 3547(define_insn "mve_vsliq_n_<supf><mode>" 3548 [ 3549 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3550 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3551 (match_operand:MVE_2 2 "s_register_operand" "w") 3552 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>")] 3553 VSLIQ_N)) 3554 ] 3555 "TARGET_HAVE_MVE" 3556 "vsli.%#<V_sz_elem>\t%q0, %q2, %3" 3557 [(set_attr "type" "mve_move") 3558]) 3559 3560;; 3561;; [vsriq_n_u, vsriq_n_s]) 3562;; 3563(define_insn "mve_vsriq_n_<supf><mode>" 3564 [ 3565 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3566 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3567 (match_operand:MVE_2 2 "s_register_operand" "w") 3568 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")] 3569 VSRIQ_N)) 3570 ] 3571 "TARGET_HAVE_MVE" 3572 "vsri.%#<V_sz_elem>\t%q0, %q2, %3" 3573 [(set_attr "type" "mve_move") 3574]) 3575 3576;; 3577;; [vqdmlsdhxq_s]) 3578;; 3579(define_insn "mve_vqdmlsdhxq_s<mode>" 3580 [ 3581 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3582 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3583 (match_operand:MVE_2 2 "s_register_operand" "w") 3584 (match_operand:MVE_2 3 "s_register_operand" "w")] 3585 VQDMLSDHXQ_S)) 3586 ] 3587 "TARGET_HAVE_MVE" 3588 "vqdmlsdhx.s%#<V_sz_elem>\t%q0, %q2, %q3" 3589 [(set_attr "type" "mve_move") 3590]) 3591 3592;; 3593;; [vqdmlsdhq_s]) 3594;; 3595(define_insn "mve_vqdmlsdhq_s<mode>" 3596 [ 3597 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3598 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3599 (match_operand:MVE_2 2 "s_register_operand" "w") 3600 (match_operand:MVE_2 3 "s_register_operand" "w")] 3601 VQDMLSDHQ_S)) 3602 ] 3603 "TARGET_HAVE_MVE" 3604 "vqdmlsdh.s%#<V_sz_elem>\t%q0, %q2, %q3" 3605 [(set_attr "type" "mve_move") 3606]) 3607 3608;; 3609;; [vqdmladhxq_s]) 3610;; 3611(define_insn "mve_vqdmladhxq_s<mode>" 3612 [ 3613 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3614 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3615 (match_operand:MVE_2 2 "s_register_operand" "w") 3616 (match_operand:MVE_2 3 "s_register_operand" "w")] 3617 VQDMLADHXQ_S)) 3618 ] 3619 "TARGET_HAVE_MVE" 3620 "vqdmladhx.s%#<V_sz_elem>\t%q0, %q2, %q3" 3621 [(set_attr "type" "mve_move") 3622]) 3623 3624;; 3625;; [vqdmladhq_s]) 3626;; 3627(define_insn "mve_vqdmladhq_s<mode>" 3628 [ 3629 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 3630 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 3631 (match_operand:MVE_2 2 "s_register_operand" "w") 3632 (match_operand:MVE_2 3 "s_register_operand" "w")] 3633 VQDMLADHQ_S)) 3634 ] 3635 "TARGET_HAVE_MVE" 3636 "vqdmladh.s%#<V_sz_elem>\t%q0, %q2, %q3" 3637 [(set_attr "type" "mve_move") 3638]) 3639 3640;; 3641;; [vmlsdavaxq_s]) 3642;; 3643(define_insn "mve_vmlsdavaxq_s<mode>" 3644 [ 3645 (set (match_operand:SI 0 "s_register_operand" "=Te") 3646 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 3647 (match_operand:MVE_2 2 "s_register_operand" "w") 3648 (match_operand:MVE_2 3 "s_register_operand" "w")] 3649 VMLSDAVAXQ_S)) 3650 ] 3651 "TARGET_HAVE_MVE" 3652 "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3" 3653 [(set_attr "type" "mve_move") 3654]) 3655 3656;; 3657;; [vmlsdavaq_s]) 3658;; 3659(define_insn "mve_vmlsdavaq_s<mode>" 3660 [ 3661 (set (match_operand:SI 0 "s_register_operand" "=Te") 3662 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 3663 (match_operand:MVE_2 2 "s_register_operand" "w") 3664 (match_operand:MVE_2 3 "s_register_operand" "w")] 3665 VMLSDAVAQ_S)) 3666 ] 3667 "TARGET_HAVE_MVE" 3668 "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3" 3669 [(set_attr "type" "mve_move") 3670]) 3671 3672;; 3673;; [vmladavaxq_s]) 3674;; 3675(define_insn "mve_vmladavaxq_s<mode>" 3676 [ 3677 (set (match_operand:SI 0 "s_register_operand" "=Te") 3678 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 3679 (match_operand:MVE_2 2 "s_register_operand" "w") 3680 (match_operand:MVE_2 3 "s_register_operand" "w")] 3681 VMLADAVAXQ_S)) 3682 ] 3683 "TARGET_HAVE_MVE" 3684 "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3" 3685 [(set_attr "type" "mve_move") 3686]) 3687;; 3688;; [vabsq_m_f]) 3689;; 3690(define_insn "mve_vabsq_m_f<mode>" 3691 [ 3692 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 3693 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 3694 (match_operand:MVE_0 2 "s_register_operand" "w") 3695 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3696 VABSQ_M_F)) 3697 ] 3698 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3699 "vpst\;vabst.f%#<V_sz_elem> %q0, %q2" 3700 [(set_attr "type" "mve_move") 3701 (set_attr "length""8")]) 3702 3703;; 3704;; [vaddlvaq_p_s vaddlvaq_p_u]) 3705;; 3706(define_insn "mve_vaddlvaq_p_<supf>v4si" 3707 [ 3708 (set (match_operand:DI 0 "s_register_operand" "=r") 3709 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 3710 (match_operand:V4SI 2 "s_register_operand" "w") 3711 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 3712 VADDLVAQ_P)) 3713 ] 3714 "TARGET_HAVE_MVE" 3715 "vpst\;vaddlvat.<supf>32\t%Q0, %R0, %q2" 3716 [(set_attr "type" "mve_move") 3717 (set_attr "length""8")]) 3718;; 3719;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270]) 3720;; 3721(define_insn "mve_vcmlaq<mve_rot><mode>" 3722 [ 3723 (set (match_operand:MVE_0 0 "s_register_operand" "=w,w") 3724 (plus:MVE_0 (match_operand:MVE_0 1 "reg_or_zero_operand" "Dz,0") 3725 (unspec:MVE_0 3726 [(match_operand:MVE_0 2 "s_register_operand" "w,w") 3727 (match_operand:MVE_0 3 "s_register_operand" "w,w")] 3728 VCMLA))) 3729 ] 3730 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3731 "@ 3732 vcmul.f%#<V_sz_elem> %q0, %q2, %q3, #<rot> 3733 vcmla.f%#<V_sz_elem> %q0, %q2, %q3, #<rot>" 3734 [(set_attr "type" "mve_move") 3735]) 3736 3737;; 3738;; [vcmpeqq_m_n_f]) 3739;; 3740(define_insn "mve_vcmpeqq_m_n_f<mode>" 3741 [ 3742 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3743 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3744 (match_operand:<V_elem> 2 "s_register_operand" "r") 3745 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3746 VCMPEQQ_M_N_F)) 3747 ] 3748 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3749 "vpst\;vcmpt.f%#<V_sz_elem> eq, %q1, %2" 3750 [(set_attr "type" "mve_move") 3751 (set_attr "length""8")]) 3752 3753;; 3754;; [vcmpgeq_m_f]) 3755;; 3756(define_insn "mve_vcmpgeq_m_f<mode>" 3757 [ 3758 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3759 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3760 (match_operand:MVE_0 2 "s_register_operand" "w") 3761 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3762 VCMPGEQ_M_F)) 3763 ] 3764 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3765 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %q2" 3766 [(set_attr "type" "mve_move") 3767 (set_attr "length""8")]) 3768 3769;; 3770;; [vcmpgeq_m_n_f]) 3771;; 3772(define_insn "mve_vcmpgeq_m_n_f<mode>" 3773 [ 3774 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3775 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3776 (match_operand:<V_elem> 2 "s_register_operand" "r") 3777 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3778 VCMPGEQ_M_N_F)) 3779 ] 3780 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3781 "vpst\;vcmpt.f%#<V_sz_elem> ge, %q1, %2" 3782 [(set_attr "type" "mve_move") 3783 (set_attr "length""8")]) 3784 3785;; 3786;; [vcmpgtq_m_f]) 3787;; 3788(define_insn "mve_vcmpgtq_m_f<mode>" 3789 [ 3790 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3791 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3792 (match_operand:MVE_0 2 "s_register_operand" "w") 3793 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3794 VCMPGTQ_M_F)) 3795 ] 3796 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3797 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %q2" 3798 [(set_attr "type" "mve_move") 3799 (set_attr "length""8")]) 3800 3801;; 3802;; [vcmpgtq_m_n_f]) 3803;; 3804(define_insn "mve_vcmpgtq_m_n_f<mode>" 3805 [ 3806 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3807 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3808 (match_operand:<V_elem> 2 "s_register_operand" "r") 3809 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3810 VCMPGTQ_M_N_F)) 3811 ] 3812 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3813 "vpst\;vcmpt.f%#<V_sz_elem> gt, %q1, %2" 3814 [(set_attr "type" "mve_move") 3815 (set_attr "length""8")]) 3816 3817;; 3818;; [vcmpleq_m_f]) 3819;; 3820(define_insn "mve_vcmpleq_m_f<mode>" 3821 [ 3822 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3823 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3824 (match_operand:MVE_0 2 "s_register_operand" "w") 3825 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3826 VCMPLEQ_M_F)) 3827 ] 3828 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3829 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %q2" 3830 [(set_attr "type" "mve_move") 3831 (set_attr "length""8")]) 3832 3833;; 3834;; [vcmpleq_m_n_f]) 3835;; 3836(define_insn "mve_vcmpleq_m_n_f<mode>" 3837 [ 3838 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3839 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3840 (match_operand:<V_elem> 2 "s_register_operand" "r") 3841 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3842 VCMPLEQ_M_N_F)) 3843 ] 3844 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3845 "vpst\;vcmpt.f%#<V_sz_elem> le, %q1, %2" 3846 [(set_attr "type" "mve_move") 3847 (set_attr "length""8")]) 3848 3849;; 3850;; [vcmpltq_m_f]) 3851;; 3852(define_insn "mve_vcmpltq_m_f<mode>" 3853 [ 3854 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3855 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3856 (match_operand:MVE_0 2 "s_register_operand" "w") 3857 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3858 VCMPLTQ_M_F)) 3859 ] 3860 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3861 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %q2" 3862 [(set_attr "type" "mve_move") 3863 (set_attr "length""8")]) 3864 3865;; 3866;; [vcmpltq_m_n_f]) 3867;; 3868(define_insn "mve_vcmpltq_m_n_f<mode>" 3869 [ 3870 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3871 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3872 (match_operand:<V_elem> 2 "s_register_operand" "r") 3873 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3874 VCMPLTQ_M_N_F)) 3875 ] 3876 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3877 "vpst\;vcmpt.f%#<V_sz_elem> lt, %q1, %2" 3878 [(set_attr "type" "mve_move") 3879 (set_attr "length""8")]) 3880 3881;; 3882;; [vcmpneq_m_f]) 3883;; 3884(define_insn "mve_vcmpneq_m_f<mode>" 3885 [ 3886 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3887 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3888 (match_operand:MVE_0 2 "s_register_operand" "w") 3889 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3890 VCMPNEQ_M_F)) 3891 ] 3892 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3893 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %q2" 3894 [(set_attr "type" "mve_move") 3895 (set_attr "length""8")]) 3896 3897;; 3898;; [vcmpneq_m_n_f]) 3899;; 3900(define_insn "mve_vcmpneq_m_n_f<mode>" 3901 [ 3902 (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up") 3903 (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w") 3904 (match_operand:<V_elem> 2 "s_register_operand" "r") 3905 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3906 VCMPNEQ_M_N_F)) 3907 ] 3908 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3909 "vpst\;vcmpt.f%#<V_sz_elem> ne, %q1, %2" 3910 [(set_attr "type" "mve_move") 3911 (set_attr "length""8")]) 3912 3913;; 3914;; [vcvtbq_m_f16_f32]) 3915;; 3916(define_insn "mve_vcvtbq_m_f16_f32v8hf" 3917 [ 3918 (set (match_operand:V8HF 0 "s_register_operand" "=w") 3919 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") 3920 (match_operand:V4SF 2 "s_register_operand" "w") 3921 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3922 VCVTBQ_M_F16_F32)) 3923 ] 3924 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3925 "vpst\;vcvtbt.f16.f32\t%q0, %q2" 3926 [(set_attr "type" "mve_move") 3927 (set_attr "length""8")]) 3928 3929;; 3930;; [vcvtbq_m_f32_f16]) 3931;; 3932(define_insn "mve_vcvtbq_m_f32_f16v4sf" 3933 [ 3934 (set (match_operand:V4SF 0 "s_register_operand" "=w") 3935 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") 3936 (match_operand:V8HF 2 "s_register_operand" "w") 3937 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3938 VCVTBQ_M_F32_F16)) 3939 ] 3940 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3941 "vpst\;vcvtbt.f32.f16\t%q0, %q2" 3942 [(set_attr "type" "mve_move") 3943 (set_attr "length""8")]) 3944 3945;; 3946;; [vcvttq_m_f16_f32]) 3947;; 3948(define_insn "mve_vcvttq_m_f16_f32v8hf" 3949 [ 3950 (set (match_operand:V8HF 0 "s_register_operand" "=w") 3951 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") 3952 (match_operand:V4SF 2 "s_register_operand" "w") 3953 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3954 VCVTTQ_M_F16_F32)) 3955 ] 3956 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3957 "vpst\;vcvttt.f16.f32\t%q0, %q2" 3958 [(set_attr "type" "mve_move") 3959 (set_attr "length""8")]) 3960 3961;; 3962;; [vcvttq_m_f32_f16]) 3963;; 3964(define_insn "mve_vcvttq_m_f32_f16v4sf" 3965 [ 3966 (set (match_operand:V4SF 0 "s_register_operand" "=w") 3967 (unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0") 3968 (match_operand:V8HF 2 "s_register_operand" "w") 3969 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3970 VCVTTQ_M_F32_F16)) 3971 ] 3972 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3973 "vpst\;vcvttt.f32.f16\t%q0, %q2" 3974 [(set_attr "type" "mve_move") 3975 (set_attr "length""8")]) 3976 3977;; 3978;; [vdupq_m_n_f]) 3979;; 3980(define_insn "mve_vdupq_m_n_f<mode>" 3981 [ 3982 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 3983 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 3984 (match_operand:<V_elem> 2 "s_register_operand" "r") 3985 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 3986 VDUPQ_M_N_F)) 3987 ] 3988 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 3989 "vpst\;vdupt.%#<V_sz_elem>\t%q0, %2" 3990 [(set_attr "type" "mve_move") 3991 (set_attr "length""8")]) 3992 3993;; 3994;; [vfmaq_f]) 3995;; 3996(define_insn "mve_vfmaq_f<mode>" 3997 [ 3998 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 3999 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4000 (match_operand:MVE_0 2 "s_register_operand" "w") 4001 (match_operand:MVE_0 3 "s_register_operand" "w")] 4002 VFMAQ_F)) 4003 ] 4004 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4005 "vfma.f%#<V_sz_elem> %q0, %q2, %q3" 4006 [(set_attr "type" "mve_move") 4007]) 4008 4009;; 4010;; [vfmaq_n_f]) 4011;; 4012(define_insn "mve_vfmaq_n_f<mode>" 4013 [ 4014 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4015 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4016 (match_operand:MVE_0 2 "s_register_operand" "w") 4017 (match_operand:<V_elem> 3 "s_register_operand" "r")] 4018 VFMAQ_N_F)) 4019 ] 4020 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4021 "vfma.f%#<V_sz_elem> %q0, %q2, %3" 4022 [(set_attr "type" "mve_move") 4023]) 4024 4025;; 4026;; [vfmasq_n_f]) 4027;; 4028(define_insn "mve_vfmasq_n_f<mode>" 4029 [ 4030 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4031 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4032 (match_operand:MVE_0 2 "s_register_operand" "w") 4033 (match_operand:<V_elem> 3 "s_register_operand" "r")] 4034 VFMASQ_N_F)) 4035 ] 4036 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4037 "vfmas.f%#<V_sz_elem> %q0, %q2, %3" 4038 [(set_attr "type" "mve_move") 4039]) 4040;; 4041;; [vfmsq_f]) 4042;; 4043(define_insn "mve_vfmsq_f<mode>" 4044 [ 4045 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4046 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4047 (match_operand:MVE_0 2 "s_register_operand" "w") 4048 (match_operand:MVE_0 3 "s_register_operand" "w")] 4049 VFMSQ_F)) 4050 ] 4051 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4052 "vfms.f%#<V_sz_elem> %q0, %q2, %q3" 4053 [(set_attr "type" "mve_move") 4054]) 4055 4056;; 4057;; [vmaxnmaq_m_f]) 4058;; 4059(define_insn "mve_vmaxnmaq_m_f<mode>" 4060 [ 4061 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4062 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4063 (match_operand:MVE_0 2 "s_register_operand" "w") 4064 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4065 VMAXNMAQ_M_F)) 4066 ] 4067 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4068 "vpst\;vmaxnmat.f%#<V_sz_elem> %q0, %q2" 4069 [(set_attr "type" "mve_move") 4070 (set_attr "length""8")]) 4071;; 4072;; [vmaxnmavq_p_f]) 4073;; 4074(define_insn "mve_vmaxnmavq_p_f<mode>" 4075 [ 4076 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 4077 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 4078 (match_operand:MVE_0 2 "s_register_operand" "w") 4079 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4080 VMAXNMAVQ_P_F)) 4081 ] 4082 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4083 "vpst\;vmaxnmavt.f%#<V_sz_elem> %0, %q2" 4084 [(set_attr "type" "mve_move") 4085 (set_attr "length""8")]) 4086 4087;; 4088;; [vmaxnmvq_p_f]) 4089;; 4090(define_insn "mve_vmaxnmvq_p_f<mode>" 4091 [ 4092 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 4093 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 4094 (match_operand:MVE_0 2 "s_register_operand" "w") 4095 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4096 VMAXNMVQ_P_F)) 4097 ] 4098 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4099 "vpst\;vmaxnmvt.f%#<V_sz_elem> %0, %q2" 4100 [(set_attr "type" "mve_move") 4101 (set_attr "length""8")]) 4102;; 4103;; [vminnmaq_m_f]) 4104;; 4105(define_insn "mve_vminnmaq_m_f<mode>" 4106 [ 4107 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4108 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4109 (match_operand:MVE_0 2 "s_register_operand" "w") 4110 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4111 VMINNMAQ_M_F)) 4112 ] 4113 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4114 "vpst\;vminnmat.f%#<V_sz_elem> %q0, %q2" 4115 [(set_attr "type" "mve_move") 4116 (set_attr "length""8")]) 4117 4118;; 4119;; [vminnmavq_p_f]) 4120;; 4121(define_insn "mve_vminnmavq_p_f<mode>" 4122 [ 4123 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 4124 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 4125 (match_operand:MVE_0 2 "s_register_operand" "w") 4126 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4127 VMINNMAVQ_P_F)) 4128 ] 4129 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4130 "vpst\;vminnmavt.f%#<V_sz_elem> %0, %q2" 4131 [(set_attr "type" "mve_move") 4132 (set_attr "length""8")]) 4133;; 4134;; [vminnmvq_p_f]) 4135;; 4136(define_insn "mve_vminnmvq_p_f<mode>" 4137 [ 4138 (set (match_operand:<V_elem> 0 "s_register_operand" "=r") 4139 (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0") 4140 (match_operand:MVE_0 2 "s_register_operand" "w") 4141 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4142 VMINNMVQ_P_F)) 4143 ] 4144 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4145 "vpst\;vminnmvt.f%#<V_sz_elem> %0, %q2" 4146 [(set_attr "type" "mve_move") 4147 (set_attr "length""8")]) 4148 4149;; 4150;; [vmlaldavaq_s, vmlaldavaq_u]) 4151;; 4152(define_insn "mve_vmlaldavaq_<supf><mode>" 4153 [ 4154 (set (match_operand:DI 0 "s_register_operand" "=r") 4155 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4156 (match_operand:MVE_5 2 "s_register_operand" "w") 4157 (match_operand:MVE_5 3 "s_register_operand" "w")] 4158 VMLALDAVAQ)) 4159 ] 4160 "TARGET_HAVE_MVE" 4161 "vmlaldava.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 4162 [(set_attr "type" "mve_move") 4163]) 4164 4165;; 4166;; [vmlaldavaxq_s]) 4167;; 4168(define_insn "mve_vmlaldavaxq_s<mode>" 4169 [ 4170 (set (match_operand:DI 0 "s_register_operand" "=r") 4171 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4172 (match_operand:MVE_5 2 "s_register_operand" "w") 4173 (match_operand:MVE_5 3 "s_register_operand" "w")] 4174 VMLALDAVAXQ_S)) 4175 ] 4176 "TARGET_HAVE_MVE" 4177 "vmlaldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 4178 [(set_attr "type" "mve_move") 4179]) 4180 4181;; 4182;; [vmlaldavq_p_u, vmlaldavq_p_s]) 4183;; 4184(define_insn "mve_vmlaldavq_p_<supf><mode>" 4185 [ 4186 (set (match_operand:DI 0 "s_register_operand" "=r") 4187 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 4188 (match_operand:MVE_5 2 "s_register_operand" "w") 4189 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4190 VMLALDAVQ_P)) 4191 ] 4192 "TARGET_HAVE_MVE" 4193 "vpst\;vmlaldavt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 4194 [(set_attr "type" "mve_move") 4195 (set_attr "length""8")]) 4196 4197;; 4198;; [vmlaldavxq_p_s]) 4199;; 4200(define_insn "mve_vmlaldavxq_p_s<mode>" 4201 [ 4202 (set (match_operand:DI 0 "s_register_operand" "=r") 4203 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 4204 (match_operand:MVE_5 2 "s_register_operand" "w") 4205 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4206 VMLALDAVXQ_P_S)) 4207 ] 4208 "TARGET_HAVE_MVE" 4209 "vpst\;vmlaldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 4210 [(set_attr "type" "mve_move") 4211 (set_attr "length""8")]) 4212;; 4213;; [vmlsldavaq_s]) 4214;; 4215(define_insn "mve_vmlsldavaq_s<mode>" 4216 [ 4217 (set (match_operand:DI 0 "s_register_operand" "=r") 4218 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4219 (match_operand:MVE_5 2 "s_register_operand" "w") 4220 (match_operand:MVE_5 3 "s_register_operand" "w")] 4221 VMLSLDAVAQ_S)) 4222 ] 4223 "TARGET_HAVE_MVE" 4224 "vmlsldava.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 4225 [(set_attr "type" "mve_move") 4226]) 4227 4228;; 4229;; [vmlsldavaxq_s]) 4230;; 4231(define_insn "mve_vmlsldavaxq_s<mode>" 4232 [ 4233 (set (match_operand:DI 0 "s_register_operand" "=r") 4234 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4235 (match_operand:MVE_5 2 "s_register_operand" "w") 4236 (match_operand:MVE_5 3 "s_register_operand" "w")] 4237 VMLSLDAVAXQ_S)) 4238 ] 4239 "TARGET_HAVE_MVE" 4240 "vmlsldavax.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 4241 [(set_attr "type" "mve_move") 4242]) 4243 4244;; 4245;; [vmlsldavq_p_s]) 4246;; 4247(define_insn "mve_vmlsldavq_p_s<mode>" 4248 [ 4249 (set (match_operand:DI 0 "s_register_operand" "=r") 4250 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 4251 (match_operand:MVE_5 2 "s_register_operand" "w") 4252 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4253 VMLSLDAVQ_P_S)) 4254 ] 4255 "TARGET_HAVE_MVE" 4256 "vpst\;vmlsldavt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 4257 [(set_attr "type" "mve_move") 4258 (set_attr "length""8")]) 4259 4260;; 4261;; [vmlsldavxq_p_s]) 4262;; 4263(define_insn "mve_vmlsldavxq_p_s<mode>" 4264 [ 4265 (set (match_operand:DI 0 "s_register_operand" "=r") 4266 (unspec:DI [(match_operand:MVE_5 1 "s_register_operand" "w") 4267 (match_operand:MVE_5 2 "s_register_operand" "w") 4268 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4269 VMLSLDAVXQ_P_S)) 4270 ] 4271 "TARGET_HAVE_MVE" 4272 "vpst\;vmlsldavxt.s%#<V_sz_elem>\t%Q0, %R0, %q1, %q2" 4273 [(set_attr "type" "mve_move") 4274 (set_attr "length""8")]) 4275;; 4276;; [vmovlbq_m_u, vmovlbq_m_s]) 4277;; 4278(define_insn "mve_vmovlbq_m_<supf><mode>" 4279 [ 4280 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 4281 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 4282 (match_operand:MVE_3 2 "s_register_operand" "w") 4283 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4284 VMOVLBQ_M)) 4285 ] 4286 "TARGET_HAVE_MVE" 4287 "vpst\;vmovlbt.<supf>%#<V_sz_elem> %q0, %q2" 4288 [(set_attr "type" "mve_move") 4289 (set_attr "length""8")]) 4290;; 4291;; [vmovltq_m_u, vmovltq_m_s]) 4292;; 4293(define_insn "mve_vmovltq_m_<supf><mode>" 4294 [ 4295 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 4296 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 4297 (match_operand:MVE_3 2 "s_register_operand" "w") 4298 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4299 VMOVLTQ_M)) 4300 ] 4301 "TARGET_HAVE_MVE" 4302 "vpst\;vmovltt.<supf>%#<V_sz_elem> %q0, %q2" 4303 [(set_attr "type" "mve_move") 4304 (set_attr "length""8")]) 4305;; 4306;; [vmovnbq_m_u, vmovnbq_m_s]) 4307;; 4308(define_insn "mve_vmovnbq_m_<supf><mode>" 4309 [ 4310 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4311 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4312 (match_operand:MVE_5 2 "s_register_operand" "w") 4313 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4314 VMOVNBQ_M)) 4315 ] 4316 "TARGET_HAVE_MVE" 4317 "vpst\;vmovnbt.i%#<V_sz_elem> %q0, %q2" 4318 [(set_attr "type" "mve_move") 4319 (set_attr "length""8")]) 4320 4321;; 4322;; [vmovntq_m_u, vmovntq_m_s]) 4323;; 4324(define_insn "mve_vmovntq_m_<supf><mode>" 4325 [ 4326 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4327 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4328 (match_operand:MVE_5 2 "s_register_operand" "w") 4329 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4330 VMOVNTQ_M)) 4331 ] 4332 "TARGET_HAVE_MVE" 4333 "vpst\;vmovntt.i%#<V_sz_elem> %q0, %q2" 4334 [(set_attr "type" "mve_move") 4335 (set_attr "length""8")]) 4336 4337;; 4338;; [vmvnq_m_n_u, vmvnq_m_n_s]) 4339;; 4340(define_insn "mve_vmvnq_m_n_<supf><mode>" 4341 [ 4342 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4343 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4344 (match_operand:SI 2 "immediate_operand" "i") 4345 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4346 VMVNQ_M_N)) 4347 ] 4348 "TARGET_HAVE_MVE" 4349 "vpst\;vmvnt.i%#<V_sz_elem>\t%q0, %2" 4350 [(set_attr "type" "mve_move") 4351 (set_attr "length""8")]) 4352;; 4353;; [vnegq_m_f]) 4354;; 4355(define_insn "mve_vnegq_m_f<mode>" 4356 [ 4357 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4358 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4359 (match_operand:MVE_0 2 "s_register_operand" "w") 4360 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4361 VNEGQ_M_F)) 4362 ] 4363 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4364 "vpst\;vnegt.f%#<V_sz_elem> %q0, %q2" 4365 [(set_attr "type" "mve_move") 4366 (set_attr "length""8")]) 4367 4368;; 4369;; [vorrq_m_n_s, vorrq_m_n_u]) 4370;; 4371(define_insn "mve_vorrq_m_n_<supf><mode>" 4372 [ 4373 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4374 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4375 (match_operand:SI 2 "immediate_operand" "i") 4376 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4377 VORRQ_M_N)) 4378 ] 4379 "TARGET_HAVE_MVE" 4380 "vpst\;vorrt.i%#<V_sz_elem>\t%q0, %2" 4381 [(set_attr "type" "mve_move") 4382 (set_attr "length""8")]) 4383;; 4384;; [vpselq_f]) 4385;; 4386(define_insn "@mve_vpselq_f<mode>" 4387 [ 4388 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4389 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") 4390 (match_operand:MVE_0 2 "s_register_operand" "w") 4391 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4392 VPSELQ_F)) 4393 ] 4394 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4395 "vpsel\t%q0, %q1, %q2" 4396 [(set_attr "type" "mve_move") 4397]) 4398 4399;; 4400;; [vqmovnbq_m_s, vqmovnbq_m_u]) 4401;; 4402(define_insn "mve_vqmovnbq_m_<supf><mode>" 4403 [ 4404 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4405 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4406 (match_operand:MVE_5 2 "s_register_operand" "w") 4407 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4408 VQMOVNBQ_M)) 4409 ] 4410 "TARGET_HAVE_MVE" 4411 "vpst\;vqmovnbt.<supf>%#<V_sz_elem> %q0, %q2" 4412 [(set_attr "type" "mve_move") 4413 (set_attr "length""8")]) 4414 4415;; 4416;; [vqmovntq_m_u, vqmovntq_m_s]) 4417;; 4418(define_insn "mve_vqmovntq_m_<supf><mode>" 4419 [ 4420 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4421 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4422 (match_operand:MVE_5 2 "s_register_operand" "w") 4423 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4424 VQMOVNTQ_M)) 4425 ] 4426 "TARGET_HAVE_MVE" 4427 "vpst\;vqmovntt.<supf>%#<V_sz_elem> %q0, %q2" 4428 [(set_attr "type" "mve_move") 4429 (set_attr "length""8")]) 4430 4431;; 4432;; [vqmovunbq_m_s]) 4433;; 4434(define_insn "mve_vqmovunbq_m_s<mode>" 4435 [ 4436 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4437 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4438 (match_operand:MVE_5 2 "s_register_operand" "w") 4439 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4440 VQMOVUNBQ_M_S)) 4441 ] 4442 "TARGET_HAVE_MVE" 4443 "vpst\;vqmovunbt.s%#<V_sz_elem> %q0, %q2" 4444 [(set_attr "type" "mve_move") 4445 (set_attr "length""8")]) 4446 4447;; 4448;; [vqmovuntq_m_s]) 4449;; 4450(define_insn "mve_vqmovuntq_m_s<mode>" 4451 [ 4452 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4453 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4454 (match_operand:MVE_5 2 "s_register_operand" "w") 4455 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4456 VQMOVUNTQ_M_S)) 4457 ] 4458 "TARGET_HAVE_MVE" 4459 "vpst\;vqmovuntt.s%#<V_sz_elem> %q0, %q2" 4460 [(set_attr "type" "mve_move") 4461 (set_attr "length""8")]) 4462 4463;; 4464;; [vqrshrntq_n_u, vqrshrntq_n_s]) 4465;; 4466(define_insn "mve_vqrshrntq_n_<supf><mode>" 4467 [ 4468 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4469 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4470 (match_operand:MVE_5 2 "s_register_operand" "w") 4471 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4472 VQRSHRNTQ_N)) 4473 ] 4474 "TARGET_HAVE_MVE" 4475 "vqrshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3" 4476 [(set_attr "type" "mve_move") 4477]) 4478 4479;; 4480;; [vqrshruntq_n_s]) 4481;; 4482(define_insn "mve_vqrshruntq_n_s<mode>" 4483 [ 4484 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4485 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4486 (match_operand:MVE_5 2 "s_register_operand" "w") 4487 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4488 VQRSHRUNTQ_N_S)) 4489 ] 4490 "TARGET_HAVE_MVE" 4491 "vqrshrunt.s%#<V_sz_elem> %q0, %q2, %3" 4492 [(set_attr "type" "mve_move") 4493]) 4494 4495;; 4496;; [vqshrnbq_n_u, vqshrnbq_n_s]) 4497;; 4498(define_insn "mve_vqshrnbq_n_<supf><mode>" 4499 [ 4500 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4501 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4502 (match_operand:MVE_5 2 "s_register_operand" "w") 4503 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4504 VQSHRNBQ_N)) 4505 ] 4506 "TARGET_HAVE_MVE" 4507 "vqshrnb.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 4508 [(set_attr "type" "mve_move") 4509]) 4510 4511;; 4512;; [vqshrntq_n_u, vqshrntq_n_s]) 4513;; 4514(define_insn "mve_vqshrntq_n_<supf><mode>" 4515 [ 4516 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4517 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4518 (match_operand:MVE_5 2 "s_register_operand" "w") 4519 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4520 VQSHRNTQ_N)) 4521 ] 4522 "TARGET_HAVE_MVE" 4523 "vqshrnt.<supf>%#<V_sz_elem> %q0, %q2, %3" 4524 [(set_attr "type" "mve_move") 4525]) 4526 4527;; 4528;; [vqshrunbq_n_s]) 4529;; 4530(define_insn "mve_vqshrunbq_n_s<mode>" 4531 [ 4532 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4533 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4534 (match_operand:MVE_5 2 "s_register_operand" "w") 4535 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4536 VQSHRUNBQ_N_S)) 4537 ] 4538 "TARGET_HAVE_MVE" 4539 "vqshrunb.s%#<V_sz_elem> %q0, %q2, %3" 4540 [(set_attr "type" "mve_move") 4541]) 4542 4543;; 4544;; [vqshruntq_n_s]) 4545;; 4546(define_insn "mve_vqshruntq_n_s<mode>" 4547 [ 4548 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4549 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4550 (match_operand:MVE_5 2 "s_register_operand" "w") 4551 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4552 VQSHRUNTQ_N_S)) 4553 ] 4554 "TARGET_HAVE_MVE" 4555 "vqshrunt.s%#<V_sz_elem> %q0, %q2, %3" 4556 [(set_attr "type" "mve_move") 4557]) 4558 4559;; 4560;; [vrev32q_m_f]) 4561;; 4562(define_insn "mve_vrev32q_m_fv8hf" 4563 [ 4564 (set (match_operand:V8HF 0 "s_register_operand" "=w") 4565 (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0") 4566 (match_operand:V8HF 2 "s_register_operand" "w") 4567 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4568 VREV32Q_M_F)) 4569 ] 4570 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4571 "vpst\;vrev32t.16\t%q0, %q2" 4572 [(set_attr "type" "mve_move") 4573 (set_attr "length""8")]) 4574 4575;; 4576;; [vrev32q_m_s, vrev32q_m_u]) 4577;; 4578(define_insn "mve_vrev32q_m_<supf><mode>" 4579 [ 4580 (set (match_operand:MVE_3 0 "s_register_operand" "=w") 4581 (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "0") 4582 (match_operand:MVE_3 2 "s_register_operand" "w") 4583 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4584 VREV32Q_M)) 4585 ] 4586 "TARGET_HAVE_MVE" 4587 "vpst\;vrev32t.%#<V_sz_elem>\t%q0, %q2" 4588 [(set_attr "type" "mve_move") 4589 (set_attr "length""8")]) 4590 4591;; 4592;; [vrev64q_m_f]) 4593;; 4594(define_insn "mve_vrev64q_m_f<mode>" 4595 [ 4596 (set (match_operand:MVE_0 0 "s_register_operand" "=&w") 4597 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4598 (match_operand:MVE_0 2 "s_register_operand" "w") 4599 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4600 VREV64Q_M_F)) 4601 ] 4602 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4603 "vpst\;vrev64t.%#<V_sz_elem>\t%q0, %q2" 4604 [(set_attr "type" "mve_move") 4605 (set_attr "length""8")]) 4606 4607;; 4608;; [vrmlaldavhaxq_s]) 4609;; 4610(define_insn "mve_vrmlaldavhaxq_sv4si" 4611 [ 4612 (set (match_operand:DI 0 "s_register_operand" "=r") 4613 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4614 (match_operand:V4SI 2 "s_register_operand" "w") 4615 (match_operand:V4SI 3 "s_register_operand" "w")] 4616 VRMLALDAVHAXQ_S)) 4617 ] 4618 "TARGET_HAVE_MVE" 4619 "vrmlaldavhax.s32\t%Q0, %R0, %q2, %q3" 4620 [(set_attr "type" "mve_move") 4621]) 4622 4623;; 4624;; [vrmlaldavhxq_p_s]) 4625;; 4626(define_insn "mve_vrmlaldavhxq_p_sv4si" 4627 [ 4628 (set (match_operand:DI 0 "s_register_operand" "=r") 4629 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 4630 (match_operand:V4SI 2 "s_register_operand" "w") 4631 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4632 VRMLALDAVHXQ_P_S)) 4633 ] 4634 "TARGET_HAVE_MVE" 4635 "vpst\;vrmlaldavhxt.s32\t%Q0, %R0, %q1, %q2" 4636 [(set_attr "type" "mve_move") 4637 (set_attr "length""8")]) 4638 4639;; 4640;; [vrmlsldavhaxq_s]) 4641;; 4642(define_insn "mve_vrmlsldavhaxq_sv4si" 4643 [ 4644 (set (match_operand:DI 0 "s_register_operand" "=r") 4645 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4646 (match_operand:V4SI 2 "s_register_operand" "w") 4647 (match_operand:V4SI 3 "s_register_operand" "w")] 4648 VRMLSLDAVHAXQ_S)) 4649 ] 4650 "TARGET_HAVE_MVE" 4651 "vrmlsldavhax.s32\t%Q0, %R0, %q2, %q3" 4652 [(set_attr "type" "mve_move") 4653]) 4654 4655;; 4656;; [vrmlsldavhq_p_s]) 4657;; 4658(define_insn "mve_vrmlsldavhq_p_sv4si" 4659 [ 4660 (set (match_operand:DI 0 "s_register_operand" "=r") 4661 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 4662 (match_operand:V4SI 2 "s_register_operand" "w") 4663 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4664 VRMLSLDAVHQ_P_S)) 4665 ] 4666 "TARGET_HAVE_MVE" 4667 "vpst\;vrmlsldavht.s32\t%Q0, %R0, %q1, %q2" 4668 [(set_attr "type" "mve_move") 4669 (set_attr "length""8")]) 4670 4671;; 4672;; [vrmlsldavhxq_p_s]) 4673;; 4674(define_insn "mve_vrmlsldavhxq_p_sv4si" 4675 [ 4676 (set (match_operand:DI 0 "s_register_operand" "=r") 4677 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 4678 (match_operand:V4SI 2 "s_register_operand" "w") 4679 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4680 VRMLSLDAVHXQ_P_S)) 4681 ] 4682 "TARGET_HAVE_MVE" 4683 "vpst\;vrmlsldavhxt.s32\t%Q0, %R0, %q1, %q2" 4684 [(set_attr "type" "mve_move") 4685 (set_attr "length""8")]) 4686 4687;; 4688;; [vrndaq_m_f]) 4689;; 4690(define_insn "mve_vrndaq_m_f<mode>" 4691 [ 4692 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4693 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4694 (match_operand:MVE_0 2 "s_register_operand" "w") 4695 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4696 VRNDAQ_M_F)) 4697 ] 4698 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4699 "vpst\;vrintat.f%#<V_sz_elem> %q0, %q2" 4700 [(set_attr "type" "mve_move") 4701 (set_attr "length""8")]) 4702 4703;; 4704;; [vrndmq_m_f]) 4705;; 4706(define_insn "mve_vrndmq_m_f<mode>" 4707 [ 4708 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4709 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4710 (match_operand:MVE_0 2 "s_register_operand" "w") 4711 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4712 VRNDMQ_M_F)) 4713 ] 4714 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4715 "vpst\;vrintmt.f%#<V_sz_elem> %q0, %q2" 4716 [(set_attr "type" "mve_move") 4717 (set_attr "length""8")]) 4718 4719;; 4720;; [vrndnq_m_f]) 4721;; 4722(define_insn "mve_vrndnq_m_f<mode>" 4723 [ 4724 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4725 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4726 (match_operand:MVE_0 2 "s_register_operand" "w") 4727 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4728 VRNDNQ_M_F)) 4729 ] 4730 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4731 "vpst\;vrintnt.f%#<V_sz_elem> %q0, %q2" 4732 [(set_attr "type" "mve_move") 4733 (set_attr "length""8")]) 4734 4735;; 4736;; [vrndpq_m_f]) 4737;; 4738(define_insn "mve_vrndpq_m_f<mode>" 4739 [ 4740 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4741 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4742 (match_operand:MVE_0 2 "s_register_operand" "w") 4743 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4744 VRNDPQ_M_F)) 4745 ] 4746 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4747 "vpst\;vrintpt.f%#<V_sz_elem> %q0, %q2" 4748 [(set_attr "type" "mve_move") 4749 (set_attr "length""8")]) 4750 4751;; 4752;; [vrndxq_m_f]) 4753;; 4754(define_insn "mve_vrndxq_m_f<mode>" 4755 [ 4756 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 4757 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 4758 (match_operand:MVE_0 2 "s_register_operand" "w") 4759 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4760 VRNDXQ_M_F)) 4761 ] 4762 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4763 "vpst\;vrintxt.f%#<V_sz_elem> %q0, %q2" 4764 [(set_attr "type" "mve_move") 4765 (set_attr "length""8")]) 4766 4767;; 4768;; [vrshrnbq_n_s, vrshrnbq_n_u]) 4769;; 4770(define_insn "mve_vrshrnbq_n_<supf><mode>" 4771 [ 4772 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4773 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4774 (match_operand:MVE_5 2 "s_register_operand" "w") 4775 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4776 VRSHRNBQ_N)) 4777 ] 4778 "TARGET_HAVE_MVE" 4779 "vrshrnb.i%#<V_sz_elem> %q0, %q2, %3" 4780 [(set_attr "type" "mve_move") 4781]) 4782 4783;; 4784;; [vrshrntq_n_u, vrshrntq_n_s]) 4785;; 4786(define_insn "mve_vrshrntq_n_<supf><mode>" 4787 [ 4788 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4789 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4790 (match_operand:MVE_5 2 "s_register_operand" "w") 4791 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4792 VRSHRNTQ_N)) 4793 ] 4794 "TARGET_HAVE_MVE" 4795 "vrshrnt.i%#<V_sz_elem> %q0, %q2, %3" 4796 [(set_attr "type" "mve_move") 4797]) 4798 4799;; 4800;; [vshrnbq_n_u, vshrnbq_n_s]) 4801;; 4802(define_insn "mve_vshrnbq_n_<supf><mode>" 4803 [ 4804 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4805 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4806 (match_operand:MVE_5 2 "s_register_operand" "w") 4807 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4808 VSHRNBQ_N)) 4809 ] 4810 "TARGET_HAVE_MVE" 4811 "vshrnb.i%#<V_sz_elem> %q0, %q2, %3" 4812 [(set_attr "type" "mve_move") 4813]) 4814 4815;; 4816;; [vshrntq_n_s, vshrntq_n_u]) 4817;; 4818(define_insn "mve_vshrntq_n_<supf><mode>" 4819 [ 4820 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 4821 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 4822 (match_operand:MVE_5 2 "s_register_operand" "w") 4823 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>")] 4824 VSHRNTQ_N)) 4825 ] 4826 "TARGET_HAVE_MVE" 4827 "vshrnt.i%#<V_sz_elem>\t%q0, %q2, %3" 4828 [(set_attr "type" "mve_move") 4829]) 4830 4831;; 4832;; [vcvtmq_m_s, vcvtmq_m_u]) 4833;; 4834(define_insn "mve_vcvtmq_m_<supf><mode>" 4835 [ 4836 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4837 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4838 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 4839 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4840 VCVTMQ_M)) 4841 ] 4842 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4843 "vpst\;vcvtmt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" 4844 [(set_attr "type" "mve_move") 4845 (set_attr "length""8")]) 4846 4847;; 4848;; [vcvtpq_m_u, vcvtpq_m_s]) 4849;; 4850(define_insn "mve_vcvtpq_m_<supf><mode>" 4851 [ 4852 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4853 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4854 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 4855 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4856 VCVTPQ_M)) 4857 ] 4858 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4859 "vpst\;vcvtpt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" 4860 [(set_attr "type" "mve_move") 4861 (set_attr "length""8")]) 4862 4863;; 4864;; [vcvtnq_m_s, vcvtnq_m_u]) 4865;; 4866(define_insn "mve_vcvtnq_m_<supf><mode>" 4867 [ 4868 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4869 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4870 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 4871 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4872 VCVTNQ_M)) 4873 ] 4874 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4875 "vpst\;vcvtnt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" 4876 [(set_attr "type" "mve_move") 4877 (set_attr "length""8")]) 4878 4879;; 4880;; [vcvtq_m_n_from_f_s, vcvtq_m_n_from_f_u]) 4881;; 4882(define_insn "mve_vcvtq_m_n_from_f_<supf><mode>" 4883 [ 4884 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4885 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4886 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 4887 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") 4888 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 4889 VCVTQ_M_N_FROM_F)) 4890 ] 4891 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4892 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2, %3" 4893 [(set_attr "type" "mve_move") 4894 (set_attr "length""8")]) 4895 4896;; 4897;; [vrev16q_m_u, vrev16q_m_s]) 4898;; 4899(define_insn "mve_vrev16q_m_<supf>v16qi" 4900 [ 4901 (set (match_operand:V16QI 0 "s_register_operand" "=w") 4902 (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0") 4903 (match_operand:V16QI 2 "s_register_operand" "w") 4904 (match_operand:V16BI 3 "vpr_register_operand" "Up")] 4905 VREV16Q_M)) 4906 ] 4907 "TARGET_HAVE_MVE" 4908 "vpst\;vrev16t.8\t%q0, %q2" 4909 [(set_attr "type" "mve_move") 4910 (set_attr "length""8")]) 4911 4912;; 4913;; [vcvtq_m_from_f_u, vcvtq_m_from_f_s]) 4914;; 4915(define_insn "mve_vcvtq_m_from_f_<supf><mode>" 4916 [ 4917 (set (match_operand:MVE_5 0 "s_register_operand" "=w") 4918 (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0") 4919 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 4920 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 4921 VCVTQ_M_FROM_F)) 4922 ] 4923 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 4924 "vpst\;vcvtt.<supf>%#<V_sz_elem>.f%#<V_sz_elem>\t%q0, %q2" 4925 [(set_attr "type" "mve_move") 4926 (set_attr "length""8")]) 4927 4928;; 4929;; [vrmlaldavhq_p_u vrmlaldavhq_p_s]) 4930;; 4931(define_insn "mve_vrmlaldavhq_p_<supf>v4si" 4932 [ 4933 (set (match_operand:DI 0 "s_register_operand" "=r") 4934 (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w") 4935 (match_operand:V4SI 2 "s_register_operand" "w") 4936 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 4937 VRMLALDAVHQ_P)) 4938 ] 4939 "TARGET_HAVE_MVE" 4940 "vpst\;vrmlaldavht.<supf>32\t%Q0, %R0, %q1, %q2" 4941 [(set_attr "type" "mve_move") 4942 (set_attr "length""8")]) 4943 4944;; 4945;; [vrmlsldavhaq_s]) 4946;; 4947(define_insn "mve_vrmlsldavhaq_sv4si" 4948 [ 4949 (set (match_operand:DI 0 "s_register_operand" "=r") 4950 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 4951 (match_operand:V4SI 2 "s_register_operand" "w") 4952 (match_operand:V4SI 3 "s_register_operand" "w")] 4953 VRMLSLDAVHAQ_S)) 4954 ] 4955 "TARGET_HAVE_MVE" 4956 "vrmlsldavha.s32\t%Q0, %R0, %q2, %q3" 4957 [(set_attr "type" "mve_move") 4958]) 4959 4960;; 4961;; [vabavq_p_s, vabavq_p_u]) 4962;; 4963(define_insn "mve_vabavq_p_<supf><mode>" 4964 [ 4965 (set (match_operand:SI 0 "s_register_operand" "=r") 4966 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 4967 (match_operand:MVE_2 2 "s_register_operand" "w") 4968 (match_operand:MVE_2 3 "s_register_operand" "w") 4969 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 4970 VABAVQ_P)) 4971 ] 4972 "TARGET_HAVE_MVE" 4973 "vpst\;vabavt.<supf>%#<V_sz_elem>\t%0, %q2, %q3" 4974 [(set_attr "type" "mve_move") 4975 (set_attr "length" "8")]) 4976 4977;; 4978;; [vqshluq_m_n_s]) 4979;; 4980(define_insn "mve_vqshluq_m_n_s<mode>" 4981 [ 4982 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 4983 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 4984 (match_operand:MVE_2 2 "s_register_operand" "w") 4985 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") 4986 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 4987 VQSHLUQ_M_N_S)) 4988 ] 4989 "TARGET_HAVE_MVE" 4990 "vpst\n\tvqshlut.s%#<V_sz_elem>\t%q0, %q2, %3" 4991 [(set_attr "type" "mve_move") 4992 (set_attr "length" "8")]) 4993 4994;; 4995;; [vshlq_m_s, vshlq_m_u]) 4996;; 4997(define_insn "mve_vshlq_m_<supf><mode>" 4998 [ 4999 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5000 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5001 (match_operand:MVE_2 2 "s_register_operand" "w") 5002 (match_operand:MVE_2 3 "s_register_operand" "w") 5003 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5004 VSHLQ_M)) 5005 ] 5006 "TARGET_HAVE_MVE" 5007 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5008 [(set_attr "type" "mve_move") 5009 (set_attr "length" "8")]) 5010 5011;; 5012;; [vsriq_m_n_s, vsriq_m_n_u]) 5013;; 5014(define_insn "mve_vsriq_m_n_<supf><mode>" 5015 [ 5016 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5017 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5018 (match_operand:MVE_2 2 "s_register_operand" "w") 5019 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") 5020 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5021 VSRIQ_M_N)) 5022 ] 5023 "TARGET_HAVE_MVE" 5024 "vpst\;vsrit.%#<V_sz_elem>\t%q0, %q2, %3" 5025 [(set_attr "type" "mve_move") 5026 (set_attr "length" "8")]) 5027 5028;; 5029;; [vsubq_m_u, vsubq_m_s]) 5030;; 5031(define_insn "mve_vsubq_m_<supf><mode>" 5032 [ 5033 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5034 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5035 (match_operand:MVE_2 2 "s_register_operand" "w") 5036 (match_operand:MVE_2 3 "s_register_operand" "w") 5037 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5038 VSUBQ_M)) 5039 ] 5040 "TARGET_HAVE_MVE" 5041 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %q3" 5042 [(set_attr "type" "mve_move") 5043 (set_attr "length" "8")]) 5044 5045;; 5046;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) 5047;; 5048(define_insn "mve_vcvtq_m_n_to_f_<supf><mode>" 5049 [ 5050 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 5051 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 5052 (match_operand:<MVE_CNVT> 2 "s_register_operand" "w") 5053 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") 5054 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5055 VCVTQ_M_N_TO_F)) 5056 ] 5057 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 5058 "vpst\;vcvtt.f%#<V_sz_elem>.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5059 [(set_attr "type" "mve_move") 5060 (set_attr "length""8")]) 5061;; 5062;; [vabdq_m_s, vabdq_m_u]) 5063;; 5064(define_insn "mve_vabdq_m_<supf><mode>" 5065 [ 5066 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5067 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5068 (match_operand:MVE_2 2 "s_register_operand" "w") 5069 (match_operand:MVE_2 3 "s_register_operand" "w") 5070 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5071 VABDQ_M)) 5072 ] 5073 "TARGET_HAVE_MVE" 5074 "vpst\;vabdt.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5075 [(set_attr "type" "mve_move") 5076 (set_attr "length""8")]) 5077 5078;; 5079;; [vaddq_m_n_s, vaddq_m_n_u]) 5080;; 5081(define_insn "mve_vaddq_m_n_<supf><mode>" 5082 [ 5083 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5084 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5085 (match_operand:MVE_2 2 "s_register_operand" "w") 5086 (match_operand:<V_elem> 3 "s_register_operand" "r") 5087 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5088 VADDQ_M_N)) 5089 ] 5090 "TARGET_HAVE_MVE" 5091 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %3" 5092 [(set_attr "type" "mve_move") 5093 (set_attr "length""8")]) 5094 5095;; 5096;; [vaddq_m_u, vaddq_m_s]) 5097;; 5098(define_insn "mve_vaddq_m_<supf><mode>" 5099 [ 5100 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5101 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5102 (match_operand:MVE_2 2 "s_register_operand" "w") 5103 (match_operand:MVE_2 3 "s_register_operand" "w") 5104 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5105 VADDQ_M)) 5106 ] 5107 "TARGET_HAVE_MVE" 5108 "vpst\;vaddt.i%#<V_sz_elem> %q0, %q2, %q3" 5109 [(set_attr "type" "mve_move") 5110 (set_attr "length""8")]) 5111 5112;; 5113;; [vandq_m_u, vandq_m_s]) 5114;; 5115(define_insn "mve_vandq_m_<supf><mode>" 5116 [ 5117 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5118 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5119 (match_operand:MVE_2 2 "s_register_operand" "w") 5120 (match_operand:MVE_2 3 "s_register_operand" "w") 5121 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5122 VANDQ_M)) 5123 ] 5124 "TARGET_HAVE_MVE" 5125 "vpst\;vandt\t%q0, %q2, %q3" 5126 [(set_attr "type" "mve_move") 5127 (set_attr "length""8")]) 5128 5129;; 5130;; [vbicq_m_u, vbicq_m_s]) 5131;; 5132(define_insn "mve_vbicq_m_<supf><mode>" 5133 [ 5134 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5135 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5136 (match_operand:MVE_2 2 "s_register_operand" "w") 5137 (match_operand:MVE_2 3 "s_register_operand" "w") 5138 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5139 VBICQ_M)) 5140 ] 5141 "TARGET_HAVE_MVE" 5142 "vpst\;vbict\t%q0, %q2, %q3" 5143 [(set_attr "type" "mve_move") 5144 (set_attr "length""8")]) 5145 5146;; 5147;; [vbrsrq_m_n_u, vbrsrq_m_n_s]) 5148;; 5149(define_insn "mve_vbrsrq_m_n_<supf><mode>" 5150 [ 5151 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5152 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5153 (match_operand:MVE_2 2 "s_register_operand" "w") 5154 (match_operand:SI 3 "s_register_operand" "r") 5155 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5156 VBRSRQ_M_N)) 5157 ] 5158 "TARGET_HAVE_MVE" 5159 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3" 5160 [(set_attr "type" "mve_move") 5161 (set_attr "length""8")]) 5162 5163;; 5164;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]) 5165;; 5166(define_insn "mve_vcaddq_rot270_m_<supf><mode>" 5167 [ 5168 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 5169 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5170 (match_operand:MVE_2 2 "s_register_operand" "w") 5171 (match_operand:MVE_2 3 "s_register_operand" "w") 5172 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5173 VCADDQ_ROT270_M)) 5174 ] 5175 "TARGET_HAVE_MVE" 5176 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270" 5177 [(set_attr "type" "mve_move") 5178 (set_attr "length""8")]) 5179 5180;; 5181;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]) 5182;; 5183(define_insn "mve_vcaddq_rot90_m_<supf><mode>" 5184 [ 5185 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 5186 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5187 (match_operand:MVE_2 2 "s_register_operand" "w") 5188 (match_operand:MVE_2 3 "s_register_operand" "w") 5189 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5190 VCADDQ_ROT90_M)) 5191 ] 5192 "TARGET_HAVE_MVE" 5193 "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90" 5194 [(set_attr "type" "mve_move") 5195 (set_attr "length""8")]) 5196 5197;; 5198;; [veorq_m_s, veorq_m_u]) 5199;; 5200(define_insn "mve_veorq_m_<supf><mode>" 5201 [ 5202 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5203 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5204 (match_operand:MVE_2 2 "s_register_operand" "w") 5205 (match_operand:MVE_2 3 "s_register_operand" "w") 5206 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5207 VEORQ_M)) 5208 ] 5209 "TARGET_HAVE_MVE" 5210 "vpst\;veort\t%q0, %q2, %q3" 5211 [(set_attr "type" "mve_move") 5212 (set_attr "length""8")]) 5213 5214;; 5215;; [vhaddq_m_n_s, vhaddq_m_n_u]) 5216;; 5217(define_insn "mve_vhaddq_m_n_<supf><mode>" 5218 [ 5219 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5220 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5221 (match_operand:MVE_2 2 "s_register_operand" "w") 5222 (match_operand:<V_elem> 3 "s_register_operand" "r") 5223 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5224 VHADDQ_M_N)) 5225 ] 5226 "TARGET_HAVE_MVE" 5227 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3" 5228 [(set_attr "type" "mve_move") 5229 (set_attr "length""8")]) 5230 5231;; 5232;; [vhaddq_m_s, vhaddq_m_u]) 5233;; 5234(define_insn "mve_vhaddq_m_<supf><mode>" 5235 [ 5236 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5237 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5238 (match_operand:MVE_2 2 "s_register_operand" "w") 5239 (match_operand:MVE_2 3 "s_register_operand" "w") 5240 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5241 VHADDQ_M)) 5242 ] 5243 "TARGET_HAVE_MVE" 5244 "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5245 [(set_attr "type" "mve_move") 5246 (set_attr "length""8")]) 5247 5248;; 5249;; [vhsubq_m_n_s, vhsubq_m_n_u]) 5250;; 5251(define_insn "mve_vhsubq_m_n_<supf><mode>" 5252 [ 5253 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5254 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5255 (match_operand:MVE_2 2 "s_register_operand" "w") 5256 (match_operand:<V_elem> 3 "s_register_operand" "r") 5257 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5258 VHSUBQ_M_N)) 5259 ] 5260 "TARGET_HAVE_MVE" 5261 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3" 5262 [(set_attr "type" "mve_move") 5263 (set_attr "length""8")]) 5264 5265;; 5266;; [vhsubq_m_s, vhsubq_m_u]) 5267;; 5268(define_insn "mve_vhsubq_m_<supf><mode>" 5269 [ 5270 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5271 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5272 (match_operand:MVE_2 2 "s_register_operand" "w") 5273 (match_operand:MVE_2 3 "s_register_operand" "w") 5274 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5275 VHSUBQ_M)) 5276 ] 5277 "TARGET_HAVE_MVE" 5278 "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5279 [(set_attr "type" "mve_move") 5280 (set_attr "length""8")]) 5281 5282;; 5283;; [vmaxq_m_s, vmaxq_m_u]) 5284;; 5285(define_insn "mve_vmaxq_m_<supf><mode>" 5286 [ 5287 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5288 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5289 (match_operand:MVE_2 2 "s_register_operand" "w") 5290 (match_operand:MVE_2 3 "s_register_operand" "w") 5291 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5292 VMAXQ_M)) 5293 ] 5294 "TARGET_HAVE_MVE" 5295 "vpst\;vmaxt.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5296 [(set_attr "type" "mve_move") 5297 (set_attr "length""8")]) 5298 5299;; 5300;; [vminq_m_s, vminq_m_u]) 5301;; 5302(define_insn "mve_vminq_m_<supf><mode>" 5303 [ 5304 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5305 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5306 (match_operand:MVE_2 2 "s_register_operand" "w") 5307 (match_operand:MVE_2 3 "s_register_operand" "w") 5308 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5309 VMINQ_M)) 5310 ] 5311 "TARGET_HAVE_MVE" 5312 "vpst\;vmint.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5313 [(set_attr "type" "mve_move") 5314 (set_attr "length""8")]) 5315 5316;; 5317;; [vmladavaq_p_u, vmladavaq_p_s]) 5318;; 5319(define_insn "mve_vmladavaq_p_<supf><mode>" 5320 [ 5321 (set (match_operand:SI 0 "s_register_operand" "=Te") 5322 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 5323 (match_operand:MVE_2 2 "s_register_operand" "w") 5324 (match_operand:MVE_2 3 "s_register_operand" "w") 5325 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5326 VMLADAVAQ_P)) 5327 ] 5328 "TARGET_HAVE_MVE" 5329 "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3" 5330 [(set_attr "type" "mve_move") 5331 (set_attr "length""8")]) 5332 5333;; 5334;; [vmlaq_m_n_s, vmlaq_m_n_u]) 5335;; 5336(define_insn "mve_vmlaq_m_n_<supf><mode>" 5337 [ 5338 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5339 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5340 (match_operand:MVE_2 2 "s_register_operand" "w") 5341 (match_operand:<V_elem> 3 "s_register_operand" "r") 5342 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5343 VMLAQ_M_N)) 5344 ] 5345 "TARGET_HAVE_MVE" 5346 "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3" 5347 [(set_attr "type" "mve_move") 5348 (set_attr "length""8")]) 5349 5350;; 5351;; [vmlasq_m_n_u, vmlasq_m_n_s]) 5352;; 5353(define_insn "mve_vmlasq_m_n_<supf><mode>" 5354 [ 5355 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5356 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5357 (match_operand:MVE_2 2 "s_register_operand" "w") 5358 (match_operand:<V_elem> 3 "s_register_operand" "r") 5359 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5360 VMLASQ_M_N)) 5361 ] 5362 "TARGET_HAVE_MVE" 5363 "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3" 5364 [(set_attr "type" "mve_move") 5365 (set_attr "length""8")]) 5366 5367;; 5368;; [vmulhq_m_s, vmulhq_m_u]) 5369;; 5370(define_insn "mve_vmulhq_m_<supf><mode>" 5371 [ 5372 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5373 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5374 (match_operand:MVE_2 2 "s_register_operand" "w") 5375 (match_operand:MVE_2 3 "s_register_operand" "w") 5376 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5377 VMULHQ_M)) 5378 ] 5379 "TARGET_HAVE_MVE" 5380 "vpst\;vmulht.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5381 [(set_attr "type" "mve_move") 5382 (set_attr "length""8")]) 5383 5384;; 5385;; [vmullbq_int_m_u, vmullbq_int_m_s]) 5386;; 5387(define_insn "mve_vmullbq_int_m_<supf><mode>" 5388 [ 5389 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 5390 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 5391 (match_operand:MVE_2 2 "s_register_operand" "w") 5392 (match_operand:MVE_2 3 "s_register_operand" "w") 5393 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5394 VMULLBQ_INT_M)) 5395 ] 5396 "TARGET_HAVE_MVE" 5397 "vpst\;vmullbt.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5398 [(set_attr "type" "mve_move") 5399 (set_attr "length""8")]) 5400 5401;; 5402;; [vmulltq_int_m_s, vmulltq_int_m_u]) 5403;; 5404(define_insn "mve_vmulltq_int_m_<supf><mode>" 5405 [ 5406 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 5407 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 5408 (match_operand:MVE_2 2 "s_register_operand" "w") 5409 (match_operand:MVE_2 3 "s_register_operand" "w") 5410 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5411 VMULLTQ_INT_M)) 5412 ] 5413 "TARGET_HAVE_MVE" 5414 "vpst\;vmulltt.<supf>%#<V_sz_elem> %q0, %q2, %q3" 5415 [(set_attr "type" "mve_move") 5416 (set_attr "length""8")]) 5417 5418;; 5419;; [vmulq_m_n_u, vmulq_m_n_s]) 5420;; 5421(define_insn "mve_vmulq_m_n_<supf><mode>" 5422 [ 5423 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5424 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5425 (match_operand:MVE_2 2 "s_register_operand" "w") 5426 (match_operand:<V_elem> 3 "s_register_operand" "r") 5427 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5428 VMULQ_M_N)) 5429 ] 5430 "TARGET_HAVE_MVE" 5431 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %3" 5432 [(set_attr "type" "mve_move") 5433 (set_attr "length""8")]) 5434 5435;; 5436;; [vmulq_m_s, vmulq_m_u]) 5437;; 5438(define_insn "mve_vmulq_m_<supf><mode>" 5439 [ 5440 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5441 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5442 (match_operand:MVE_2 2 "s_register_operand" "w") 5443 (match_operand:MVE_2 3 "s_register_operand" "w") 5444 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5445 VMULQ_M)) 5446 ] 5447 "TARGET_HAVE_MVE" 5448 "vpst\;vmult.i%#<V_sz_elem> %q0, %q2, %q3" 5449 [(set_attr "type" "mve_move") 5450 (set_attr "length""8")]) 5451 5452;; 5453;; [vornq_m_u, vornq_m_s]) 5454;; 5455(define_insn "mve_vornq_m_<supf><mode>" 5456 [ 5457 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5458 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5459 (match_operand:MVE_2 2 "s_register_operand" "w") 5460 (match_operand:MVE_2 3 "s_register_operand" "w") 5461 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5462 VORNQ_M)) 5463 ] 5464 "TARGET_HAVE_MVE" 5465 "vpst\;vornt\t%q0, %q2, %q3" 5466 [(set_attr "type" "mve_move") 5467 (set_attr "length""8")]) 5468 5469;; 5470;; [vorrq_m_s, vorrq_m_u]) 5471;; 5472(define_insn "mve_vorrq_m_<supf><mode>" 5473 [ 5474 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5475 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5476 (match_operand:MVE_2 2 "s_register_operand" "w") 5477 (match_operand:MVE_2 3 "s_register_operand" "w") 5478 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5479 VORRQ_M)) 5480 ] 5481 "TARGET_HAVE_MVE" 5482 "vpst\;vorrt\t%q0, %q2, %q3" 5483 [(set_attr "type" "mve_move") 5484 (set_attr "length""8")]) 5485 5486;; 5487;; [vqaddq_m_n_u, vqaddq_m_n_s]) 5488;; 5489(define_insn "mve_vqaddq_m_n_<supf><mode>" 5490 [ 5491 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5492 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5493 (match_operand:MVE_2 2 "s_register_operand" "w") 5494 (match_operand:<V_elem> 3 "s_register_operand" "r") 5495 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5496 VQADDQ_M_N)) 5497 ] 5498 "TARGET_HAVE_MVE" 5499 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5500 [(set_attr "type" "mve_move") 5501 (set_attr "length""8")]) 5502 5503;; 5504;; [vqaddq_m_u, vqaddq_m_s]) 5505;; 5506(define_insn "mve_vqaddq_m_<supf><mode>" 5507 [ 5508 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5509 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5510 (match_operand:MVE_2 2 "s_register_operand" "w") 5511 (match_operand:MVE_2 3 "s_register_operand" "w") 5512 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5513 VQADDQ_M)) 5514 ] 5515 "TARGET_HAVE_MVE" 5516 "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5517 [(set_attr "type" "mve_move") 5518 (set_attr "length""8")]) 5519 5520;; 5521;; [vqdmlahq_m_n_s]) 5522;; 5523(define_insn "mve_vqdmlahq_m_n_s<mode>" 5524 [ 5525 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5526 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5527 (match_operand:MVE_2 2 "s_register_operand" "w") 5528 (match_operand:<V_elem> 3 "s_register_operand" "r") 5529 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5530 VQDMLAHQ_M_N_S)) 5531 ] 5532 "TARGET_HAVE_MVE" 5533 "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3" 5534 [(set_attr "type" "mve_move") 5535 (set_attr "length""8")]) 5536 5537;; 5538;; [vqdmlashq_m_n_s]) 5539;; 5540(define_insn "mve_vqdmlashq_m_n_s<mode>" 5541 [ 5542 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5543 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5544 (match_operand:MVE_2 2 "s_register_operand" "w") 5545 (match_operand:<V_elem> 3 "s_register_operand" "r") 5546 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5547 VQDMLASHQ_M_N_S)) 5548 ] 5549 "TARGET_HAVE_MVE" 5550 "vpst\;vqdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3" 5551 [(set_attr "type" "mve_move") 5552 (set_attr "length""8")]) 5553 5554;; 5555;; [vqrdmlahq_m_n_s]) 5556;; 5557(define_insn "mve_vqrdmlahq_m_n_s<mode>" 5558 [ 5559 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5560 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5561 (match_operand:MVE_2 2 "s_register_operand" "w") 5562 (match_operand:<V_elem> 3 "s_register_operand" "r") 5563 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5564 VQRDMLAHQ_M_N_S)) 5565 ] 5566 "TARGET_HAVE_MVE" 5567 "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3" 5568 [(set_attr "type" "mve_move") 5569 (set_attr "length""8")]) 5570 5571;; 5572;; [vqrdmlashq_m_n_s]) 5573;; 5574(define_insn "mve_vqrdmlashq_m_n_s<mode>" 5575 [ 5576 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5577 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5578 (match_operand:MVE_2 2 "s_register_operand" "w") 5579 (match_operand:<V_elem> 3 "s_register_operand" "r") 5580 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5581 VQRDMLASHQ_M_N_S)) 5582 ] 5583 "TARGET_HAVE_MVE" 5584 "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3" 5585 [(set_attr "type" "mve_move") 5586 (set_attr "length""8")]) 5587 5588;; 5589;; [vqrshlq_m_u, vqrshlq_m_s]) 5590;; 5591(define_insn "mve_vqrshlq_m_<supf><mode>" 5592 [ 5593 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5594 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5595 (match_operand:MVE_2 2 "s_register_operand" "w") 5596 (match_operand:MVE_2 3 "s_register_operand" "w") 5597 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5598 VQRSHLQ_M)) 5599 ] 5600 "TARGET_HAVE_MVE" 5601 "vpst\;vqrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5602 [(set_attr "type" "mve_move") 5603 (set_attr "length""8")]) 5604 5605;; 5606;; [vqshlq_m_n_s, vqshlq_m_n_u]) 5607;; 5608(define_insn "mve_vqshlq_m_n_<supf><mode>" 5609 [ 5610 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5611 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5612 (match_operand:MVE_2 2 "s_register_operand" "w") 5613 (match_operand:SI 3 "immediate_operand" "i") 5614 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5615 VQSHLQ_M_N)) 5616 ] 5617 "TARGET_HAVE_MVE" 5618 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5619 [(set_attr "type" "mve_move") 5620 (set_attr "length""8")]) 5621 5622;; 5623;; [vqshlq_m_u, vqshlq_m_s]) 5624;; 5625(define_insn "mve_vqshlq_m_<supf><mode>" 5626 [ 5627 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5628 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5629 (match_operand:MVE_2 2 "s_register_operand" "w") 5630 (match_operand:MVE_2 3 "s_register_operand" "w") 5631 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5632 VQSHLQ_M)) 5633 ] 5634 "TARGET_HAVE_MVE" 5635 "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5636 [(set_attr "type" "mve_move") 5637 (set_attr "length""8")]) 5638 5639;; 5640;; [vqsubq_m_n_u, vqsubq_m_n_s]) 5641;; 5642(define_insn "mve_vqsubq_m_n_<supf><mode>" 5643 [ 5644 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5645 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5646 (match_operand:MVE_2 2 "s_register_operand" "w") 5647 (match_operand:<V_elem> 3 "s_register_operand" "r") 5648 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5649 VQSUBQ_M_N)) 5650 ] 5651 "TARGET_HAVE_MVE" 5652 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5653 [(set_attr "type" "mve_move") 5654 (set_attr "length""8")]) 5655 5656;; 5657;; [vqsubq_m_u, vqsubq_m_s]) 5658;; 5659(define_insn "mve_vqsubq_m_<supf><mode>" 5660 [ 5661 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5662 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5663 (match_operand:MVE_2 2 "s_register_operand" "w") 5664 (match_operand:MVE_2 3 "s_register_operand" "w") 5665 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5666 VQSUBQ_M)) 5667 ] 5668 "TARGET_HAVE_MVE" 5669 "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5670 [(set_attr "type" "mve_move") 5671 (set_attr "length""8")]) 5672 5673;; 5674;; [vrhaddq_m_u, vrhaddq_m_s]) 5675;; 5676(define_insn "mve_vrhaddq_m_<supf><mode>" 5677 [ 5678 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5679 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5680 (match_operand:MVE_2 2 "s_register_operand" "w") 5681 (match_operand:MVE_2 3 "s_register_operand" "w") 5682 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5683 VRHADDQ_M)) 5684 ] 5685 "TARGET_HAVE_MVE" 5686 "vpst\;vrhaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5687 [(set_attr "type" "mve_move") 5688 (set_attr "length""8")]) 5689 5690;; 5691;; [vrmulhq_m_u, vrmulhq_m_s]) 5692;; 5693(define_insn "mve_vrmulhq_m_<supf><mode>" 5694 [ 5695 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5696 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5697 (match_operand:MVE_2 2 "s_register_operand" "w") 5698 (match_operand:MVE_2 3 "s_register_operand" "w") 5699 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5700 VRMULHQ_M)) 5701 ] 5702 "TARGET_HAVE_MVE" 5703 "vpst\;vrmulht.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5704 [(set_attr "type" "mve_move") 5705 (set_attr "length""8")]) 5706 5707;; 5708;; [vrshlq_m_s, vrshlq_m_u]) 5709;; 5710(define_insn "mve_vrshlq_m_<supf><mode>" 5711 [ 5712 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5713 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5714 (match_operand:MVE_2 2 "s_register_operand" "w") 5715 (match_operand:MVE_2 3 "s_register_operand" "w") 5716 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5717 VRSHLQ_M)) 5718 ] 5719 "TARGET_HAVE_MVE" 5720 "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %q3" 5721 [(set_attr "type" "mve_move") 5722 (set_attr "length""8")]) 5723 5724;; 5725;; [vrshrq_m_n_s, vrshrq_m_n_u]) 5726;; 5727(define_insn "mve_vrshrq_m_n_<supf><mode>" 5728 [ 5729 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5730 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5731 (match_operand:MVE_2 2 "s_register_operand" "w") 5732 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") 5733 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5734 VRSHRQ_M_N)) 5735 ] 5736 "TARGET_HAVE_MVE" 5737 "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5738 [(set_attr "type" "mve_move") 5739 (set_attr "length""8")]) 5740 5741;; 5742;; [vshlq_m_n_s, vshlq_m_n_u]) 5743;; 5744(define_insn "mve_vshlq_m_n_<supf><mode>" 5745 [ 5746 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5747 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5748 (match_operand:MVE_2 2 "s_register_operand" "w") 5749 (match_operand:SI 3 "immediate_operand" "i") 5750 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5751 VSHLQ_M_N)) 5752 ] 5753 "TARGET_HAVE_MVE" 5754 "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5755 [(set_attr "type" "mve_move") 5756 (set_attr "length""8")]) 5757 5758;; 5759;; [vshrq_m_n_s, vshrq_m_n_u]) 5760;; 5761(define_insn "mve_vshrq_m_n_<supf><mode>" 5762 [ 5763 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5764 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5765 (match_operand:MVE_2 2 "s_register_operand" "w") 5766 (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>") 5767 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5768 VSHRQ_M_N)) 5769 ] 5770 "TARGET_HAVE_MVE" 5771 "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 5772 [(set_attr "type" "mve_move") 5773 (set_attr "length""8")]) 5774 5775;; 5776;; [vsliq_m_n_u, vsliq_m_n_s]) 5777;; 5778(define_insn "mve_vsliq_m_n_<supf><mode>" 5779 [ 5780 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5781 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5782 (match_operand:MVE_2 2 "s_register_operand" "w") 5783 (match_operand:SI 3 "<MVE_pred>" "<MVE_constraint>") 5784 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5785 VSLIQ_M_N)) 5786 ] 5787 "TARGET_HAVE_MVE" 5788 "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3" 5789 [(set_attr "type" "mve_move") 5790 (set_attr "length""8")]) 5791 5792;; 5793;; [vsubq_m_n_s, vsubq_m_n_u]) 5794;; 5795(define_insn "mve_vsubq_m_n_<supf><mode>" 5796 [ 5797 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5798 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5799 (match_operand:MVE_2 2 "s_register_operand" "w") 5800 (match_operand:<V_elem> 3 "s_register_operand" "r") 5801 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5802 VSUBQ_M_N)) 5803 ] 5804 "TARGET_HAVE_MVE" 5805 "vpst\;vsubt.i%#<V_sz_elem>\t%q0, %q2, %3" 5806 [(set_attr "type" "mve_move") 5807 (set_attr "length""8")]) 5808 5809;; 5810;; [vhcaddq_rot270_m_s]) 5811;; 5812(define_insn "mve_vhcaddq_rot270_m_s<mode>" 5813 [ 5814 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 5815 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5816 (match_operand:MVE_2 2 "s_register_operand" "w") 5817 (match_operand:MVE_2 3 "s_register_operand" "w") 5818 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5819 VHCADDQ_ROT270_M_S)) 5820 ] 5821 "TARGET_HAVE_MVE" 5822 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270" 5823 [(set_attr "type" "mve_move") 5824 (set_attr "length""8")]) 5825 5826;; 5827;; [vhcaddq_rot90_m_s]) 5828;; 5829(define_insn "mve_vhcaddq_rot90_m_s<mode>" 5830 [ 5831 (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>") 5832 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5833 (match_operand:MVE_2 2 "s_register_operand" "w") 5834 (match_operand:MVE_2 3 "s_register_operand" "w") 5835 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5836 VHCADDQ_ROT90_M_S)) 5837 ] 5838 "TARGET_HAVE_MVE" 5839 "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90" 5840 [(set_attr "type" "mve_move") 5841 (set_attr "length""8")]) 5842 5843;; 5844;; [vmladavaxq_p_s]) 5845;; 5846(define_insn "mve_vmladavaxq_p_s<mode>" 5847 [ 5848 (set (match_operand:SI 0 "s_register_operand" "=Te") 5849 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 5850 (match_operand:MVE_2 2 "s_register_operand" "w") 5851 (match_operand:MVE_2 3 "s_register_operand" "w") 5852 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5853 VMLADAVAXQ_P_S)) 5854 ] 5855 "TARGET_HAVE_MVE" 5856 "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3" 5857 [(set_attr "type" "mve_move") 5858 (set_attr "length""8")]) 5859 5860;; 5861;; [vmlsdavaq_p_s]) 5862;; 5863(define_insn "mve_vmlsdavaq_p_s<mode>" 5864 [ 5865 (set (match_operand:SI 0 "s_register_operand" "=Te") 5866 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 5867 (match_operand:MVE_2 2 "s_register_operand" "w") 5868 (match_operand:MVE_2 3 "s_register_operand" "w") 5869 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5870 VMLSDAVAQ_P_S)) 5871 ] 5872 "TARGET_HAVE_MVE" 5873 "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3" 5874 [(set_attr "type" "mve_move") 5875 (set_attr "length""8")]) 5876 5877;; 5878;; [vmlsdavaxq_p_s]) 5879;; 5880(define_insn "mve_vmlsdavaxq_p_s<mode>" 5881 [ 5882 (set (match_operand:SI 0 "s_register_operand" "=Te") 5883 (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") 5884 (match_operand:MVE_2 2 "s_register_operand" "w") 5885 (match_operand:MVE_2 3 "s_register_operand" "w") 5886 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5887 VMLSDAVAXQ_P_S)) 5888 ] 5889 "TARGET_HAVE_MVE" 5890 "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3" 5891 [(set_attr "type" "mve_move") 5892 (set_attr "length""8")]) 5893 5894;; 5895;; [vqdmladhq_m_s]) 5896;; 5897(define_insn "mve_vqdmladhq_m_s<mode>" 5898 [ 5899 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5900 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5901 (match_operand:MVE_2 2 "s_register_operand" "w") 5902 (match_operand:MVE_2 3 "s_register_operand" "w") 5903 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5904 VQDMLADHQ_M_S)) 5905 ] 5906 "TARGET_HAVE_MVE" 5907 "vpst\;vqdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3" 5908 [(set_attr "type" "mve_move") 5909 (set_attr "length""8")]) 5910 5911;; 5912;; [vqdmladhxq_m_s]) 5913;; 5914(define_insn "mve_vqdmladhxq_m_s<mode>" 5915 [ 5916 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5917 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5918 (match_operand:MVE_2 2 "s_register_operand" "w") 5919 (match_operand:MVE_2 3 "s_register_operand" "w") 5920 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5921 VQDMLADHXQ_M_S)) 5922 ] 5923 "TARGET_HAVE_MVE" 5924 "vpst\;vqdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" 5925 [(set_attr "type" "mve_move") 5926 (set_attr "length""8")]) 5927 5928;; 5929;; [vqdmlsdhq_m_s]) 5930;; 5931(define_insn "mve_vqdmlsdhq_m_s<mode>" 5932 [ 5933 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5934 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5935 (match_operand:MVE_2 2 "s_register_operand" "w") 5936 (match_operand:MVE_2 3 "s_register_operand" "w") 5937 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5938 VQDMLSDHQ_M_S)) 5939 ] 5940 "TARGET_HAVE_MVE" 5941 "vpst\;vqdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3" 5942 [(set_attr "type" "mve_move") 5943 (set_attr "length""8")]) 5944 5945;; 5946;; [vqdmlsdhxq_m_s]) 5947;; 5948(define_insn "mve_vqdmlsdhxq_m_s<mode>" 5949 [ 5950 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5951 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5952 (match_operand:MVE_2 2 "s_register_operand" "w") 5953 (match_operand:MVE_2 3 "s_register_operand" "w") 5954 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5955 VQDMLSDHXQ_M_S)) 5956 ] 5957 "TARGET_HAVE_MVE" 5958 "vpst\;vqdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" 5959 [(set_attr "type" "mve_move") 5960 (set_attr "length""8")]) 5961 5962;; 5963;; [vqdmulhq_m_n_s]) 5964;; 5965(define_insn "mve_vqdmulhq_m_n_s<mode>" 5966 [ 5967 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5968 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5969 (match_operand:MVE_2 2 "s_register_operand" "w") 5970 (match_operand:<V_elem> 3 "s_register_operand" "r") 5971 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5972 VQDMULHQ_M_N_S)) 5973 ] 5974 "TARGET_HAVE_MVE" 5975 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3" 5976 [(set_attr "type" "mve_move") 5977 (set_attr "length""8")]) 5978 5979;; 5980;; [vqdmulhq_m_s]) 5981;; 5982(define_insn "mve_vqdmulhq_m_s<mode>" 5983 [ 5984 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 5985 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 5986 (match_operand:MVE_2 2 "s_register_operand" "w") 5987 (match_operand:MVE_2 3 "s_register_operand" "w") 5988 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 5989 VQDMULHQ_M_S)) 5990 ] 5991 "TARGET_HAVE_MVE" 5992 "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3" 5993 [(set_attr "type" "mve_move") 5994 (set_attr "length""8")]) 5995 5996;; 5997;; [vqrdmladhq_m_s]) 5998;; 5999(define_insn "mve_vqrdmladhq_m_s<mode>" 6000 [ 6001 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 6002 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 6003 (match_operand:MVE_2 2 "s_register_operand" "w") 6004 (match_operand:MVE_2 3 "s_register_operand" "w") 6005 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6006 VQRDMLADHQ_M_S)) 6007 ] 6008 "TARGET_HAVE_MVE" 6009 "vpst\;vqrdmladht.s%#<V_sz_elem>\t%q0, %q2, %q3" 6010 [(set_attr "type" "mve_move") 6011 (set_attr "length""8")]) 6012 6013;; 6014;; [vqrdmladhxq_m_s]) 6015;; 6016(define_insn "mve_vqrdmladhxq_m_s<mode>" 6017 [ 6018 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 6019 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 6020 (match_operand:MVE_2 2 "s_register_operand" "w") 6021 (match_operand:MVE_2 3 "s_register_operand" "w") 6022 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6023 VQRDMLADHXQ_M_S)) 6024 ] 6025 "TARGET_HAVE_MVE" 6026 "vpst\;vqrdmladhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" 6027 [(set_attr "type" "mve_move") 6028 (set_attr "length""8")]) 6029 6030;; 6031;; [vqrdmlsdhq_m_s]) 6032;; 6033(define_insn "mve_vqrdmlsdhq_m_s<mode>" 6034 [ 6035 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 6036 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 6037 (match_operand:MVE_2 2 "s_register_operand" "w") 6038 (match_operand:MVE_2 3 "s_register_operand" "w") 6039 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6040 VQRDMLSDHQ_M_S)) 6041 ] 6042 "TARGET_HAVE_MVE" 6043 "vpst\;vqrdmlsdht.s%#<V_sz_elem>\t%q0, %q2, %q3" 6044 [(set_attr "type" "mve_move") 6045 (set_attr "length""8")]) 6046 6047;; 6048;; [vqrdmlsdhxq_m_s]) 6049;; 6050(define_insn "mve_vqrdmlsdhxq_m_s<mode>" 6051 [ 6052 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 6053 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 6054 (match_operand:MVE_2 2 "s_register_operand" "w") 6055 (match_operand:MVE_2 3 "s_register_operand" "w") 6056 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6057 VQRDMLSDHXQ_M_S)) 6058 ] 6059 "TARGET_HAVE_MVE" 6060 "vpst\;vqrdmlsdhxt.s%#<V_sz_elem>\t%q0, %q2, %q3" 6061 [(set_attr "type" "mve_move") 6062 (set_attr "length""8")]) 6063 6064;; 6065;; [vqrdmulhq_m_n_s]) 6066;; 6067(define_insn "mve_vqrdmulhq_m_n_s<mode>" 6068 [ 6069 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 6070 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 6071 (match_operand:MVE_2 2 "s_register_operand" "w") 6072 (match_operand:<V_elem> 3 "s_register_operand" "r") 6073 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6074 VQRDMULHQ_M_N_S)) 6075 ] 6076 "TARGET_HAVE_MVE" 6077 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3" 6078 [(set_attr "type" "mve_move") 6079 (set_attr "length""8")]) 6080 6081;; 6082;; [vqrdmulhq_m_s]) 6083;; 6084(define_insn "mve_vqrdmulhq_m_s<mode>" 6085 [ 6086 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 6087 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 6088 (match_operand:MVE_2 2 "s_register_operand" "w") 6089 (match_operand:MVE_2 3 "s_register_operand" "w") 6090 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6091 VQRDMULHQ_M_S)) 6092 ] 6093 "TARGET_HAVE_MVE" 6094 "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %q3" 6095 [(set_attr "type" "mve_move") 6096 (set_attr "length""8")]) 6097 6098;; 6099;; [vmlaldavaq_p_u, vmlaldavaq_p_s]) 6100;; 6101(define_insn "mve_vmlaldavaq_p_<supf><mode>" 6102 [ 6103 (set (match_operand:DI 0 "s_register_operand" "=r") 6104 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6105 (match_operand:MVE_5 2 "s_register_operand" "w") 6106 (match_operand:MVE_5 3 "s_register_operand" "w") 6107 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6108 VMLALDAVAQ_P)) 6109 ] 6110 "TARGET_HAVE_MVE" 6111 "vpst\;vmlaldavat.<supf>%#<V_sz_elem> %Q0, %R0, %q2, %q3" 6112 [(set_attr "type" "mve_move") 6113 (set_attr "length""8")]) 6114 6115;; 6116;; [vmlaldavaxq_p_s]) 6117;; 6118(define_insn "mve_vmlaldavaxq_p_<supf><mode>" 6119 [ 6120 (set (match_operand:DI 0 "s_register_operand" "=r") 6121 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6122 (match_operand:MVE_5 2 "s_register_operand" "w") 6123 (match_operand:MVE_5 3 "s_register_operand" "w") 6124 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6125 VMLALDAVAXQ_P)) 6126 ] 6127 "TARGET_HAVE_MVE" 6128 "vpst\;vmlaldavaxt.<supf>%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 6129 [(set_attr "type" "mve_move") 6130 (set_attr "length""8")]) 6131 6132;; 6133;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s]) 6134;; 6135(define_insn "mve_vqrshrnbq_m_n_<supf><mode>" 6136 [ 6137 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6138 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6139 (match_operand:MVE_5 2 "s_register_operand" "w") 6140 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6141 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6142 VQRSHRNBQ_M_N)) 6143 ] 6144 "TARGET_HAVE_MVE" 6145 "vpst\;vqrshrnbt.<supf>%#<V_sz_elem> %q0, %q2, %3" 6146 [(set_attr "type" "mve_move") 6147 (set_attr "length""8")]) 6148 6149;; 6150;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u]) 6151;; 6152(define_insn "mve_vqrshrntq_m_n_<supf><mode>" 6153 [ 6154 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6155 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6156 (match_operand:MVE_5 2 "s_register_operand" "w") 6157 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6158 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6159 VQRSHRNTQ_M_N)) 6160 ] 6161 "TARGET_HAVE_MVE" 6162 "vpst\;vqrshrntt.<supf>%#<V_sz_elem> %q0, %q2, %3" 6163 [(set_attr "type" "mve_move") 6164 (set_attr "length""8")]) 6165 6166;; 6167;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s]) 6168;; 6169(define_insn "mve_vqshrnbq_m_n_<supf><mode>" 6170 [ 6171 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6172 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6173 (match_operand:MVE_5 2 "s_register_operand" "w") 6174 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6175 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6176 VQSHRNBQ_M_N)) 6177 ] 6178 "TARGET_HAVE_MVE" 6179 "vpst\n\tvqshrnbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 6180 [(set_attr "type" "mve_move") 6181 (set_attr "length""8")]) 6182 6183;; 6184;; [vqshrntq_m_n_s, vqshrntq_m_n_u]) 6185;; 6186(define_insn "mve_vqshrntq_m_n_<supf><mode>" 6187 [ 6188 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6189 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6190 (match_operand:MVE_5 2 "s_register_operand" "w") 6191 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6192 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6193 VQSHRNTQ_M_N)) 6194 ] 6195 "TARGET_HAVE_MVE" 6196 "vpst\;vqshrntt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 6197 [(set_attr "type" "mve_move") 6198 (set_attr "length""8")]) 6199 6200;; 6201;; [vrmlaldavhaq_p_s]) 6202;; 6203(define_insn "mve_vrmlaldavhaq_p_sv4si" 6204 [ 6205 (set (match_operand:DI 0 "s_register_operand" "=r") 6206 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6207 (match_operand:V4SI 2 "s_register_operand" "w") 6208 (match_operand:V4SI 3 "s_register_operand" "w") 6209 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6210 VRMLALDAVHAQ_P_S)) 6211 ] 6212 "TARGET_HAVE_MVE" 6213 "vpst\;vrmlaldavhat.s32\t%Q0, %R0, %q2, %q3" 6214 [(set_attr "type" "mve_move") 6215 (set_attr "length""8")]) 6216 6217;; 6218;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s]) 6219;; 6220(define_insn "mve_vrshrnbq_m_n_<supf><mode>" 6221 [ 6222 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6223 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6224 (match_operand:MVE_5 2 "s_register_operand" "w") 6225 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6226 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6227 VRSHRNBQ_M_N)) 6228 ] 6229 "TARGET_HAVE_MVE" 6230 "vpst\;vrshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3" 6231 [(set_attr "type" "mve_move") 6232 (set_attr "length""8")]) 6233 6234;; 6235;; [vrshrntq_m_n_u, vrshrntq_m_n_s]) 6236;; 6237(define_insn "mve_vrshrntq_m_n_<supf><mode>" 6238 [ 6239 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6240 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6241 (match_operand:MVE_5 2 "s_register_operand" "w") 6242 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6243 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6244 VRSHRNTQ_M_N)) 6245 ] 6246 "TARGET_HAVE_MVE" 6247 "vpst\;vrshrntt.i%#<V_sz_elem>\t%q0, %q2, %3" 6248 [(set_attr "type" "mve_move") 6249 (set_attr "length""8")]) 6250 6251;; 6252;; [vshllbq_m_n_u, vshllbq_m_n_s]) 6253;; 6254(define_insn "mve_vshllbq_m_n_<supf><mode>" 6255 [ 6256 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 6257 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6258 (match_operand:MVE_3 2 "s_register_operand" "w") 6259 (match_operand:SI 3 "immediate_operand" "i") 6260 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6261 VSHLLBQ_M_N)) 6262 ] 6263 "TARGET_HAVE_MVE" 6264 "vpst\;vshllbt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 6265 [(set_attr "type" "mve_move") 6266 (set_attr "length""8")]) 6267 6268;; 6269;; [vshlltq_m_n_u, vshlltq_m_n_s]) 6270;; 6271(define_insn "mve_vshlltq_m_n_<supf><mode>" 6272 [ 6273 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 6274 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6275 (match_operand:MVE_3 2 "s_register_operand" "w") 6276 (match_operand:SI 3 "immediate_operand" "i") 6277 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6278 VSHLLTQ_M_N)) 6279 ] 6280 "TARGET_HAVE_MVE" 6281 "vpst\;vshlltt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" 6282 [(set_attr "type" "mve_move") 6283 (set_attr "length""8")]) 6284 6285;; 6286;; [vshrnbq_m_n_s, vshrnbq_m_n_u]) 6287;; 6288(define_insn "mve_vshrnbq_m_n_<supf><mode>" 6289 [ 6290 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6291 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6292 (match_operand:MVE_5 2 "s_register_operand" "w") 6293 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6294 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6295 VSHRNBQ_M_N)) 6296 ] 6297 "TARGET_HAVE_MVE" 6298 "vpst\;vshrnbt.i%#<V_sz_elem>\t%q0, %q2, %3" 6299 [(set_attr "type" "mve_move") 6300 (set_attr "length""8")]) 6301 6302;; 6303;; [vshrntq_m_n_s, vshrntq_m_n_u]) 6304;; 6305(define_insn "mve_vshrntq_m_n_<supf><mode>" 6306 [ 6307 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6308 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6309 (match_operand:MVE_5 2 "s_register_operand" "w") 6310 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6311 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6312 VSHRNTQ_M_N)) 6313 ] 6314 "TARGET_HAVE_MVE" 6315 "vpst\;vshrntt.i%#<V_sz_elem>\t%q0, %q2, %3" 6316 [(set_attr "type" "mve_move") 6317 (set_attr "length""8")]) 6318 6319;; 6320;; [vmlsldavaq_p_s]) 6321;; 6322(define_insn "mve_vmlsldavaq_p_s<mode>" 6323 [ 6324 (set (match_operand:DI 0 "s_register_operand" "=r") 6325 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6326 (match_operand:MVE_5 2 "s_register_operand" "w") 6327 (match_operand:MVE_5 3 "s_register_operand" "w") 6328 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6329 VMLSLDAVAQ_P_S)) 6330 ] 6331 "TARGET_HAVE_MVE" 6332 "vpst\;vmlsldavat.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 6333 [(set_attr "type" "mve_move") 6334 (set_attr "length""8")]) 6335 6336;; 6337;; [vmlsldavaxq_p_s]) 6338;; 6339(define_insn "mve_vmlsldavaxq_p_s<mode>" 6340 [ 6341 (set (match_operand:DI 0 "s_register_operand" "=r") 6342 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6343 (match_operand:MVE_5 2 "s_register_operand" "w") 6344 (match_operand:MVE_5 3 "s_register_operand" "w") 6345 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6346 VMLSLDAVAXQ_P_S)) 6347 ] 6348 "TARGET_HAVE_MVE" 6349 "vpst\;vmlsldavaxt.s%#<V_sz_elem>\t%Q0, %R0, %q2, %q3" 6350 [(set_attr "type" "mve_move") 6351 (set_attr "length""8")]) 6352 6353;; 6354;; [vmullbq_poly_m_p]) 6355;; 6356(define_insn "mve_vmullbq_poly_m_p<mode>" 6357 [ 6358 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 6359 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6360 (match_operand:MVE_3 2 "s_register_operand" "w") 6361 (match_operand:MVE_3 3 "s_register_operand" "w") 6362 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6363 VMULLBQ_POLY_M_P)) 6364 ] 6365 "TARGET_HAVE_MVE" 6366 "vpst\;vmullbt.p%#<V_sz_elem>\t%q0, %q2, %q3" 6367 [(set_attr "type" "mve_move") 6368 (set_attr "length""8")]) 6369 6370;; 6371;; [vmulltq_poly_m_p]) 6372;; 6373(define_insn "mve_vmulltq_poly_m_p<mode>" 6374 [ 6375 (set (match_operand:<V_double_width> 0 "s_register_operand" "=w") 6376 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6377 (match_operand:MVE_3 2 "s_register_operand" "w") 6378 (match_operand:MVE_3 3 "s_register_operand" "w") 6379 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6380 VMULLTQ_POLY_M_P)) 6381 ] 6382 "TARGET_HAVE_MVE" 6383 "vpst\;vmulltt.p%#<V_sz_elem>\t%q0, %q2, %q3" 6384 [(set_attr "type" "mve_move") 6385 (set_attr "length""8")]) 6386 6387;; 6388;; [vqdmullbq_m_n_s]) 6389;; 6390(define_insn "mve_vqdmullbq_m_n_s<mode>" 6391 [ 6392 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 6393 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6394 (match_operand:MVE_5 2 "s_register_operand" "w") 6395 (match_operand:<V_elem> 3 "s_register_operand" "r") 6396 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6397 VQDMULLBQ_M_N_S)) 6398 ] 6399 "TARGET_HAVE_MVE" 6400 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3" 6401 [(set_attr "type" "mve_move") 6402 (set_attr "length""8")]) 6403 6404;; 6405;; [vqdmullbq_m_s]) 6406;; 6407(define_insn "mve_vqdmullbq_m_s<mode>" 6408 [ 6409 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 6410 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6411 (match_operand:MVE_5 2 "s_register_operand" "w") 6412 (match_operand:MVE_5 3 "s_register_operand" "w") 6413 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6414 VQDMULLBQ_M_S)) 6415 ] 6416 "TARGET_HAVE_MVE" 6417 "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3" 6418 [(set_attr "type" "mve_move") 6419 (set_attr "length""8")]) 6420 6421;; 6422;; [vqdmulltq_m_n_s]) 6423;; 6424(define_insn "mve_vqdmulltq_m_n_s<mode>" 6425 [ 6426 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 6427 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6428 (match_operand:MVE_5 2 "s_register_operand" "w") 6429 (match_operand:<V_elem> 3 "s_register_operand" "r") 6430 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6431 VQDMULLTQ_M_N_S)) 6432 ] 6433 "TARGET_HAVE_MVE" 6434 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3" 6435 [(set_attr "type" "mve_move") 6436 (set_attr "length""8")]) 6437 6438;; 6439;; [vqdmulltq_m_s]) 6440;; 6441(define_insn "mve_vqdmulltq_m_s<mode>" 6442 [ 6443 (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>") 6444 (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0") 6445 (match_operand:MVE_5 2 "s_register_operand" "w") 6446 (match_operand:MVE_5 3 "s_register_operand" "w") 6447 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6448 VQDMULLTQ_M_S)) 6449 ] 6450 "TARGET_HAVE_MVE" 6451 "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3" 6452 [(set_attr "type" "mve_move") 6453 (set_attr "length""8")]) 6454 6455;; 6456;; [vqrshrunbq_m_n_s]) 6457;; 6458(define_insn "mve_vqrshrunbq_m_n_s<mode>" 6459 [ 6460 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6461 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6462 (match_operand:MVE_5 2 "s_register_operand" "w") 6463 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6464 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6465 VQRSHRUNBQ_M_N_S)) 6466 ] 6467 "TARGET_HAVE_MVE" 6468 "vpst\;vqrshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3" 6469 [(set_attr "type" "mve_move") 6470 (set_attr "length""8")]) 6471 6472;; 6473;; [vqrshruntq_m_n_s]) 6474;; 6475(define_insn "mve_vqrshruntq_m_n_s<mode>" 6476 [ 6477 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6478 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6479 (match_operand:MVE_5 2 "s_register_operand" "w") 6480 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6481 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6482 VQRSHRUNTQ_M_N_S)) 6483 ] 6484 "TARGET_HAVE_MVE" 6485 "vpst\;vqrshruntt.s%#<V_sz_elem>\t%q0, %q2, %3" 6486 [(set_attr "type" "mve_move") 6487 (set_attr "length""8")]) 6488 6489;; 6490;; [vqshrunbq_m_n_s]) 6491;; 6492(define_insn "mve_vqshrunbq_m_n_s<mode>" 6493 [ 6494 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6495 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6496 (match_operand:MVE_5 2 "s_register_operand" "w") 6497 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6498 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6499 VQSHRUNBQ_M_N_S)) 6500 ] 6501 "TARGET_HAVE_MVE" 6502 "vpst\;vqshrunbt.s%#<V_sz_elem>\t%q0, %q2, %3" 6503 [(set_attr "type" "mve_move") 6504 (set_attr "length""8")]) 6505 6506;; 6507;; [vqshruntq_m_n_s]) 6508;; 6509(define_insn "mve_vqshruntq_m_n_s<mode>" 6510 [ 6511 (set (match_operand:<V_narrow_pack> 0 "s_register_operand" "=w") 6512 (unspec:<V_narrow_pack> [(match_operand:<V_narrow_pack> 1 "s_register_operand" "0") 6513 (match_operand:MVE_5 2 "s_register_operand" "w") 6514 (match_operand:SI 3 "<MVE_pred3>" "<MVE_constraint3>") 6515 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6516 VQSHRUNTQ_M_N_S)) 6517 ] 6518 "TARGET_HAVE_MVE" 6519 "vpst\;vqshruntt.s%#<V_sz_elem>\t%q0, %q2, %3" 6520 [(set_attr "type" "mve_move") 6521 (set_attr "length""8")]) 6522 6523;; 6524;; [vrmlaldavhaq_p_u]) 6525;; 6526(define_insn "mve_vrmlaldavhaq_p_uv4si" 6527 [ 6528 (set (match_operand:DI 0 "s_register_operand" "=r") 6529 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6530 (match_operand:V4SI 2 "s_register_operand" "w") 6531 (match_operand:V4SI 3 "s_register_operand" "w") 6532 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6533 VRMLALDAVHAQ_P_U)) 6534 ] 6535 "TARGET_HAVE_MVE" 6536 "vpst\;vrmlaldavhat.u32\t%Q0, %R0, %q2, %q3" 6537 [(set_attr "type" "mve_move") 6538 (set_attr "length""8")]) 6539 6540;; 6541;; [vrmlaldavhaxq_p_s]) 6542;; 6543(define_insn "mve_vrmlaldavhaxq_p_sv4si" 6544 [ 6545 (set (match_operand:DI 0 "s_register_operand" "=r") 6546 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6547 (match_operand:V4SI 2 "s_register_operand" "w") 6548 (match_operand:V4SI 3 "s_register_operand" "w") 6549 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6550 VRMLALDAVHAXQ_P_S)) 6551 ] 6552 "TARGET_HAVE_MVE" 6553 "vpst\;vrmlaldavhaxt.s32\t%Q0, %R0, %q2, %q3" 6554 [(set_attr "type" "mve_move") 6555 (set_attr "length""8")]) 6556 6557;; 6558;; [vrmlsldavhaq_p_s]) 6559;; 6560(define_insn "mve_vrmlsldavhaq_p_sv4si" 6561 [ 6562 (set (match_operand:DI 0 "s_register_operand" "=r") 6563 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6564 (match_operand:V4SI 2 "s_register_operand" "w") 6565 (match_operand:V4SI 3 "s_register_operand" "w") 6566 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6567 VRMLSLDAVHAQ_P_S)) 6568 ] 6569 "TARGET_HAVE_MVE" 6570 "vpst\;vrmlsldavhat.s32\t%Q0, %R0, %q2, %q3" 6571 [(set_attr "type" "mve_move") 6572 (set_attr "length""8")]) 6573 6574;; 6575;; [vrmlsldavhaxq_p_s]) 6576;; 6577(define_insn "mve_vrmlsldavhaxq_p_sv4si" 6578 [ 6579 (set (match_operand:DI 0 "s_register_operand" "=r") 6580 (unspec:DI [(match_operand:DI 1 "s_register_operand" "0") 6581 (match_operand:V4SI 2 "s_register_operand" "w") 6582 (match_operand:V4SI 3 "s_register_operand" "w") 6583 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6584 VRMLSLDAVHAXQ_P_S)) 6585 ] 6586 "TARGET_HAVE_MVE" 6587 "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" 6588 [(set_attr "type" "mve_move") 6589 (set_attr "length""8")]) 6590;; 6591;; [vabdq_m_f]) 6592;; 6593(define_insn "mve_vabdq_m_f<mode>" 6594 [ 6595 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6596 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6597 (match_operand:MVE_0 2 "s_register_operand" "w") 6598 (match_operand:MVE_0 3 "s_register_operand" "w") 6599 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6600 VABDQ_M_F)) 6601 ] 6602 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6603 "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3" 6604 [(set_attr "type" "mve_move") 6605 (set_attr "length""8")]) 6606 6607;; 6608;; [vaddq_m_f]) 6609;; 6610(define_insn "mve_vaddq_m_f<mode>" 6611 [ 6612 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6613 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6614 (match_operand:MVE_0 2 "s_register_operand" "w") 6615 (match_operand:MVE_0 3 "s_register_operand" "w") 6616 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6617 VADDQ_M_F)) 6618 ] 6619 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6620 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %q3" 6621 [(set_attr "type" "mve_move") 6622 (set_attr "length""8")]) 6623 6624;; 6625;; [vaddq_m_n_f]) 6626;; 6627(define_insn "mve_vaddq_m_n_f<mode>" 6628 [ 6629 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6630 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6631 (match_operand:MVE_0 2 "s_register_operand" "w") 6632 (match_operand:<V_elem> 3 "s_register_operand" "r") 6633 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6634 VADDQ_M_N_F)) 6635 ] 6636 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6637 "vpst\;vaddt.f%#<V_sz_elem> %q0, %q2, %3" 6638 [(set_attr "type" "mve_move") 6639 (set_attr "length""8")]) 6640 6641;; 6642;; [vandq_m_f]) 6643;; 6644(define_insn "mve_vandq_m_f<mode>" 6645 [ 6646 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6647 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6648 (match_operand:MVE_0 2 "s_register_operand" "w") 6649 (match_operand:MVE_0 3 "s_register_operand" "w") 6650 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6651 VANDQ_M_F)) 6652 ] 6653 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6654 "vpst\;vandt\t%q0, %q2, %q3" 6655 [(set_attr "type" "mve_move") 6656 (set_attr "length""8")]) 6657 6658;; 6659;; [vbicq_m_f]) 6660;; 6661(define_insn "mve_vbicq_m_f<mode>" 6662 [ 6663 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6664 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6665 (match_operand:MVE_0 2 "s_register_operand" "w") 6666 (match_operand:MVE_0 3 "s_register_operand" "w") 6667 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6668 VBICQ_M_F)) 6669 ] 6670 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6671 "vpst\;vbict\t%q0, %q2, %q3" 6672 [(set_attr "type" "mve_move") 6673 (set_attr "length""8")]) 6674 6675;; 6676;; [vbrsrq_m_n_f]) 6677;; 6678(define_insn "mve_vbrsrq_m_n_f<mode>" 6679 [ 6680 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6681 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6682 (match_operand:MVE_0 2 "s_register_operand" "w") 6683 (match_operand:SI 3 "s_register_operand" "r") 6684 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6685 VBRSRQ_M_N_F)) 6686 ] 6687 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6688 "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3" 6689 [(set_attr "type" "mve_move") 6690 (set_attr "length""8")]) 6691 6692;; 6693;; [vcaddq_rot270_m_f]) 6694;; 6695(define_insn "mve_vcaddq_rot270_m_f<mode>" 6696 [ 6697 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 6698 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6699 (match_operand:MVE_0 2 "s_register_operand" "w") 6700 (match_operand:MVE_0 3 "s_register_operand" "w") 6701 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6702 VCADDQ_ROT270_M_F)) 6703 ] 6704 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6705 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270" 6706 [(set_attr "type" "mve_move") 6707 (set_attr "length""8")]) 6708 6709;; 6710;; [vcaddq_rot90_m_f]) 6711;; 6712(define_insn "mve_vcaddq_rot90_m_f<mode>" 6713 [ 6714 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 6715 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6716 (match_operand:MVE_0 2 "s_register_operand" "w") 6717 (match_operand:MVE_0 3 "s_register_operand" "w") 6718 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6719 VCADDQ_ROT90_M_F)) 6720 ] 6721 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6722 "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90" 6723 [(set_attr "type" "mve_move") 6724 (set_attr "length""8")]) 6725 6726;; 6727;; [vcmlaq_m_f]) 6728;; 6729(define_insn "mve_vcmlaq_m_f<mode>" 6730 [ 6731 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6732 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6733 (match_operand:MVE_0 2 "s_register_operand" "w") 6734 (match_operand:MVE_0 3 "s_register_operand" "w") 6735 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6736 VCMLAQ_M_F)) 6737 ] 6738 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6739 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #0" 6740 [(set_attr "type" "mve_move") 6741 (set_attr "length""8")]) 6742 6743;; 6744;; [vcmlaq_rot180_m_f]) 6745;; 6746(define_insn "mve_vcmlaq_rot180_m_f<mode>" 6747 [ 6748 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6749 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6750 (match_operand:MVE_0 2 "s_register_operand" "w") 6751 (match_operand:MVE_0 3 "s_register_operand" "w") 6752 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6753 VCMLAQ_ROT180_M_F)) 6754 ] 6755 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6756 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #180" 6757 [(set_attr "type" "mve_move") 6758 (set_attr "length""8")]) 6759 6760;; 6761;; [vcmlaq_rot270_m_f]) 6762;; 6763(define_insn "mve_vcmlaq_rot270_m_f<mode>" 6764 [ 6765 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6766 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6767 (match_operand:MVE_0 2 "s_register_operand" "w") 6768 (match_operand:MVE_0 3 "s_register_operand" "w") 6769 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6770 VCMLAQ_ROT270_M_F)) 6771 ] 6772 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6773 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #270" 6774 [(set_attr "type" "mve_move") 6775 (set_attr "length""8")]) 6776 6777;; 6778;; [vcmlaq_rot90_m_f]) 6779;; 6780(define_insn "mve_vcmlaq_rot90_m_f<mode>" 6781 [ 6782 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6783 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6784 (match_operand:MVE_0 2 "s_register_operand" "w") 6785 (match_operand:MVE_0 3 "s_register_operand" "w") 6786 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6787 VCMLAQ_ROT90_M_F)) 6788 ] 6789 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6790 "vpst\;vcmlat.f%#<V_sz_elem> %q0, %q2, %q3, #90" 6791 [(set_attr "type" "mve_move") 6792 (set_attr "length""8")]) 6793 6794;; 6795;; [vcmulq_m_f]) 6796;; 6797(define_insn "mve_vcmulq_m_f<mode>" 6798 [ 6799 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 6800 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6801 (match_operand:MVE_0 2 "s_register_operand" "w") 6802 (match_operand:MVE_0 3 "s_register_operand" "w") 6803 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6804 VCMULQ_M_F)) 6805 ] 6806 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6807 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #0" 6808 [(set_attr "type" "mve_move") 6809 (set_attr "length""8")]) 6810 6811;; 6812;; [vcmulq_rot180_m_f]) 6813;; 6814(define_insn "mve_vcmulq_rot180_m_f<mode>" 6815 [ 6816 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 6817 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6818 (match_operand:MVE_0 2 "s_register_operand" "w") 6819 (match_operand:MVE_0 3 "s_register_operand" "w") 6820 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6821 VCMULQ_ROT180_M_F)) 6822 ] 6823 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6824 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #180" 6825 [(set_attr "type" "mve_move") 6826 (set_attr "length""8")]) 6827 6828;; 6829;; [vcmulq_rot270_m_f]) 6830;; 6831(define_insn "mve_vcmulq_rot270_m_f<mode>" 6832 [ 6833 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 6834 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6835 (match_operand:MVE_0 2 "s_register_operand" "w") 6836 (match_operand:MVE_0 3 "s_register_operand" "w") 6837 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6838 VCMULQ_ROT270_M_F)) 6839 ] 6840 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6841 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #270" 6842 [(set_attr "type" "mve_move") 6843 (set_attr "length""8")]) 6844 6845;; 6846;; [vcmulq_rot90_m_f]) 6847;; 6848(define_insn "mve_vcmulq_rot90_m_f<mode>" 6849 [ 6850 (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>") 6851 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6852 (match_operand:MVE_0 2 "s_register_operand" "w") 6853 (match_operand:MVE_0 3 "s_register_operand" "w") 6854 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6855 VCMULQ_ROT90_M_F)) 6856 ] 6857 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6858 "vpst\;vcmult.f%#<V_sz_elem> %q0, %q2, %q3, #90" 6859 [(set_attr "type" "mve_move") 6860 (set_attr "length""8")]) 6861 6862;; 6863;; [veorq_m_f]) 6864;; 6865(define_insn "mve_veorq_m_f<mode>" 6866 [ 6867 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6868 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6869 (match_operand:MVE_0 2 "s_register_operand" "w") 6870 (match_operand:MVE_0 3 "s_register_operand" "w") 6871 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6872 VEORQ_M_F)) 6873 ] 6874 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6875 "vpst\;veort\t%q0, %q2, %q3" 6876 [(set_attr "type" "mve_move") 6877 (set_attr "length""8")]) 6878 6879;; 6880;; [vfmaq_m_f]) 6881;; 6882(define_insn "mve_vfmaq_m_f<mode>" 6883 [ 6884 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6885 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6886 (match_operand:MVE_0 2 "s_register_operand" "w") 6887 (match_operand:MVE_0 3 "s_register_operand" "w") 6888 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6889 VFMAQ_M_F)) 6890 ] 6891 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6892 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %q3" 6893 [(set_attr "type" "mve_move") 6894 (set_attr "length""8")]) 6895 6896;; 6897;; [vfmaq_m_n_f]) 6898;; 6899(define_insn "mve_vfmaq_m_n_f<mode>" 6900 [ 6901 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6902 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6903 (match_operand:MVE_0 2 "s_register_operand" "w") 6904 (match_operand:<V_elem> 3 "s_register_operand" "r") 6905 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6906 VFMAQ_M_N_F)) 6907 ] 6908 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6909 "vpst\;vfmat.f%#<V_sz_elem> %q0, %q2, %3" 6910 [(set_attr "type" "mve_move") 6911 (set_attr "length""8")]) 6912 6913;; 6914;; [vfmasq_m_n_f]) 6915;; 6916(define_insn "mve_vfmasq_m_n_f<mode>" 6917 [ 6918 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6919 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6920 (match_operand:MVE_0 2 "s_register_operand" "w") 6921 (match_operand:<V_elem> 3 "s_register_operand" "r") 6922 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6923 VFMASQ_M_N_F)) 6924 ] 6925 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6926 "vpst\;vfmast.f%#<V_sz_elem> %q0, %q2, %3" 6927 [(set_attr "type" "mve_move") 6928 (set_attr "length""8")]) 6929 6930;; 6931;; [vfmsq_m_f]) 6932;; 6933(define_insn "mve_vfmsq_m_f<mode>" 6934 [ 6935 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6936 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6937 (match_operand:MVE_0 2 "s_register_operand" "w") 6938 (match_operand:MVE_0 3 "s_register_operand" "w") 6939 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6940 VFMSQ_M_F)) 6941 ] 6942 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6943 "vpst\;vfmst.f%#<V_sz_elem> %q0, %q2, %q3" 6944 [(set_attr "type" "mve_move") 6945 (set_attr "length""8")]) 6946 6947;; 6948;; [vmaxnmq_m_f]) 6949;; 6950(define_insn "mve_vmaxnmq_m_f<mode>" 6951 [ 6952 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6953 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6954 (match_operand:MVE_0 2 "s_register_operand" "w") 6955 (match_operand:MVE_0 3 "s_register_operand" "w") 6956 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6957 VMAXNMQ_M_F)) 6958 ] 6959 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6960 "vpst\;vmaxnmt.f%#<V_sz_elem> %q0, %q2, %q3" 6961 [(set_attr "type" "mve_move") 6962 (set_attr "length""8")]) 6963 6964;; 6965;; [vminnmq_m_f]) 6966;; 6967(define_insn "mve_vminnmq_m_f<mode>" 6968 [ 6969 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6970 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6971 (match_operand:MVE_0 2 "s_register_operand" "w") 6972 (match_operand:MVE_0 3 "s_register_operand" "w") 6973 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6974 VMINNMQ_M_F)) 6975 ] 6976 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6977 "vpst\;vminnmt.f%#<V_sz_elem> %q0, %q2, %q3" 6978 [(set_attr "type" "mve_move") 6979 (set_attr "length""8")]) 6980 6981;; 6982;; [vmulq_m_f]) 6983;; 6984(define_insn "mve_vmulq_m_f<mode>" 6985 [ 6986 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 6987 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 6988 (match_operand:MVE_0 2 "s_register_operand" "w") 6989 (match_operand:MVE_0 3 "s_register_operand" "w") 6990 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 6991 VMULQ_M_F)) 6992 ] 6993 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 6994 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %q3" 6995 [(set_attr "type" "mve_move") 6996 (set_attr "length""8")]) 6997 6998;; 6999;; [vmulq_m_n_f]) 7000;; 7001(define_insn "mve_vmulq_m_n_f<mode>" 7002 [ 7003 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 7004 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 7005 (match_operand:MVE_0 2 "s_register_operand" "w") 7006 (match_operand:<V_elem> 3 "s_register_operand" "r") 7007 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 7008 VMULQ_M_N_F)) 7009 ] 7010 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7011 "vpst\;vmult.f%#<V_sz_elem> %q0, %q2, %3" 7012 [(set_attr "type" "mve_move") 7013 (set_attr "length""8")]) 7014 7015;; 7016;; [vornq_m_f]) 7017;; 7018(define_insn "mve_vornq_m_f<mode>" 7019 [ 7020 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 7021 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 7022 (match_operand:MVE_0 2 "s_register_operand" "w") 7023 (match_operand:MVE_0 3 "s_register_operand" "w") 7024 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 7025 VORNQ_M_F)) 7026 ] 7027 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7028 "vpst\;vornt\t%q0, %q2, %q3" 7029 [(set_attr "type" "mve_move") 7030 (set_attr "length""8")]) 7031 7032;; 7033;; [vorrq_m_f]) 7034;; 7035(define_insn "mve_vorrq_m_f<mode>" 7036 [ 7037 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 7038 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 7039 (match_operand:MVE_0 2 "s_register_operand" "w") 7040 (match_operand:MVE_0 3 "s_register_operand" "w") 7041 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 7042 VORRQ_M_F)) 7043 ] 7044 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7045 "vpst\;vorrt\t%q0, %q2, %q3" 7046 [(set_attr "type" "mve_move") 7047 (set_attr "length""8")]) 7048 7049;; 7050;; [vsubq_m_f]) 7051;; 7052(define_insn "mve_vsubq_m_f<mode>" 7053 [ 7054 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 7055 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 7056 (match_operand:MVE_0 2 "s_register_operand" "w") 7057 (match_operand:MVE_0 3 "s_register_operand" "w") 7058 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 7059 VSUBQ_M_F)) 7060 ] 7061 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7062 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %q3" 7063 [(set_attr "type" "mve_move") 7064 (set_attr "length""8")]) 7065 7066;; 7067;; [vsubq_m_n_f]) 7068;; 7069(define_insn "mve_vsubq_m_n_f<mode>" 7070 [ 7071 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 7072 (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") 7073 (match_operand:MVE_0 2 "s_register_operand" "w") 7074 (match_operand:<V_elem> 3 "s_register_operand" "r") 7075 (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] 7076 VSUBQ_M_N_F)) 7077 ] 7078 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7079 "vpst\;vsubt.f%#<V_sz_elem>\t%q0, %q2, %3" 7080 [(set_attr "type" "mve_move") 7081 (set_attr "length""8")]) 7082 7083;; 7084;; [vstrbq_s vstrbq_u] 7085;; 7086(define_insn "mve_vstrbq_<supf><mode>" 7087 [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") 7088 (unspec:<MVE_B_ELEM> [(match_operand:MVE_2 1 "s_register_operand" "w")] 7089 VSTRBQ)) 7090 ] 7091 "TARGET_HAVE_MVE" 7092{ 7093 rtx ops[2]; 7094 int regno = REGNO (operands[1]); 7095 ops[1] = gen_rtx_REG (TImode, regno); 7096 ops[0] = operands[0]; 7097 output_asm_insn("vstrb.<V_sz_elem>\t%q1, %E0",ops); 7098 return ""; 7099} 7100 [(set_attr "length" "4")]) 7101 7102;; 7103;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] 7104;; 7105(define_expand "mve_vstrbq_scatter_offset_<supf><mode>" 7106 [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") 7107 (match_operand:MVE_2 1 "s_register_operand") 7108 (match_operand:MVE_2 2 "s_register_operand") 7109 (unspec:V4SI [(const_int 0)] VSTRBSOQ)] 7110 "TARGET_HAVE_MVE" 7111{ 7112 rtx ind = XEXP (operands[0], 0); 7113 gcc_assert (REG_P (ind)); 7114 emit_insn (gen_mve_vstrbq_scatter_offset_<supf><mode>_insn (ind, operands[1], 7115 operands[2])); 7116 DONE; 7117}) 7118 7119(define_insn "mve_vstrbq_scatter_offset_<supf><mode>_insn" 7120 [(set (mem:BLK (scratch)) 7121 (unspec:BLK 7122 [(match_operand:SI 0 "register_operand" "r") 7123 (match_operand:MVE_2 1 "s_register_operand" "w") 7124 (match_operand:MVE_2 2 "s_register_operand" "w")] 7125 VSTRBSOQ))] 7126 "TARGET_HAVE_MVE" 7127 "vstrb.<V_sz_elem>\t%q2, [%0, %q1]" 7128 [(set_attr "length" "4")]) 7129 7130;; 7131;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] 7132;; 7133(define_insn "mve_vstrwq_scatter_base_<supf>v4si" 7134 [(set (mem:BLK (scratch)) 7135 (unspec:BLK 7136 [(match_operand:V4SI 0 "s_register_operand" "w") 7137 (match_operand:SI 1 "immediate_operand" "i") 7138 (match_operand:V4SI 2 "s_register_operand" "w")] 7139 VSTRWSBQ)) 7140 ] 7141 "TARGET_HAVE_MVE" 7142{ 7143 rtx ops[3]; 7144 ops[0] = operands[0]; 7145 ops[1] = operands[1]; 7146 ops[2] = operands[2]; 7147 output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); 7148 return ""; 7149} 7150 [(set_attr "length" "4")]) 7151 7152;; 7153;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] 7154;; 7155(define_insn "mve_vldrbq_gather_offset_<supf><mode>" 7156 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") 7157 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") 7158 (match_operand:MVE_2 2 "s_register_operand" "w")] 7159 VLDRBGOQ)) 7160 ] 7161 "TARGET_HAVE_MVE" 7162{ 7163 rtx ops[3]; 7164 ops[0] = operands[0]; 7165 ops[1] = operands[1]; 7166 ops[2] = operands[2]; 7167 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8) 7168 output_asm_insn ("vldrb.u8\t%q0, [%m1, %q2]",ops); 7169 else 7170 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); 7171 return ""; 7172} 7173 [(set_attr "length" "4")]) 7174 7175;; 7176;; [vldrbq_s vldrbq_u] 7177;; 7178(define_insn "mve_vldrbq_<supf><mode>" 7179 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 7180 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux")] 7181 VLDRBQ)) 7182 ] 7183 "TARGET_HAVE_MVE" 7184{ 7185 rtx ops[2]; 7186 int regno = REGNO (operands[0]); 7187 ops[0] = gen_rtx_REG (TImode, regno); 7188 ops[1] = operands[1]; 7189 if (<V_sz_elem> == 8) 7190 output_asm_insn ("vldrb.<V_sz_elem>\t%q0, %E1",ops); 7191 else 7192 output_asm_insn ("vldrb.<supf><V_sz_elem>\t%q0, %E1",ops); 7193 return ""; 7194} 7195 [(set_attr "length" "4")]) 7196 7197;; 7198;; [vldrwq_gather_base_s vldrwq_gather_base_u] 7199;; 7200(define_insn "mve_vldrwq_gather_base_<supf>v4si" 7201 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 7202 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 7203 (match_operand:SI 2 "immediate_operand" "i")] 7204 VLDRWGBQ)) 7205 ] 7206 "TARGET_HAVE_MVE" 7207{ 7208 rtx ops[3]; 7209 ops[0] = operands[0]; 7210 ops[1] = operands[1]; 7211 ops[2] = operands[2]; 7212 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); 7213 return ""; 7214} 7215 [(set_attr "length" "4")]) 7216 7217;; 7218;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u] 7219;; 7220(define_expand "mve_vstrbq_scatter_offset_p_<supf><mode>" 7221 [(match_operand:<MVE_B_ELEM> 0 "mve_scatter_memory") 7222 (match_operand:MVE_2 1 "s_register_operand") 7223 (match_operand:MVE_2 2 "s_register_operand") 7224 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") 7225 (unspec:V4SI [(const_int 0)] VSTRBSOQ)] 7226 "TARGET_HAVE_MVE" 7227{ 7228 rtx ind = XEXP (operands[0], 0); 7229 gcc_assert (REG_P (ind)); 7230 emit_insn ( 7231 gen_mve_vstrbq_scatter_offset_p_<supf><mode>_insn (ind, operands[1], 7232 operands[2], 7233 operands[3])); 7234 DONE; 7235}) 7236 7237(define_insn "mve_vstrbq_scatter_offset_p_<supf><mode>_insn" 7238 [(set (mem:BLK (scratch)) 7239 (unspec:BLK 7240 [(match_operand:SI 0 "register_operand" "r") 7241 (match_operand:MVE_2 1 "s_register_operand" "w") 7242 (match_operand:MVE_2 2 "s_register_operand" "w") 7243 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 7244 VSTRBSOQ))] 7245 "TARGET_HAVE_MVE" 7246 "vpst\;vstrbt.<V_sz_elem>\t%q2, [%0, %q1]" 7247 [(set_attr "length" "8")]) 7248 7249;; 7250;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u] 7251;; 7252(define_insn "mve_vstrwq_scatter_base_p_<supf>v4si" 7253 [(set (mem:BLK (scratch)) 7254 (unspec:BLK 7255 [(match_operand:V4SI 0 "s_register_operand" "w") 7256 (match_operand:SI 1 "immediate_operand" "i") 7257 (match_operand:V4SI 2 "s_register_operand" "w") 7258 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 7259 VSTRWSBQ)) 7260 ] 7261 "TARGET_HAVE_MVE" 7262{ 7263 rtx ops[3]; 7264 ops[0] = operands[0]; 7265 ops[1] = operands[1]; 7266 ops[2] = operands[2]; 7267 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); 7268 return ""; 7269} 7270 [(set_attr "length" "8")]) 7271 7272(define_insn "mve_vstrbq_p_<supf><mode>" 7273 [(set (match_operand:<MVE_B_ELEM> 0 "mve_memory_operand" "=Ux") 7274 (unspec:<MVE_B_ELEM> 7275 [(match_operand:MVE_2 1 "s_register_operand" "w") 7276 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up") 7277 (match_dup 0)] 7278 VSTRBQ))] 7279 "TARGET_HAVE_MVE" 7280{ 7281 rtx ops[2]; 7282 int regno = REGNO (operands[1]); 7283 ops[1] = gen_rtx_REG (TImode, regno); 7284 ops[0] = operands[0]; 7285 output_asm_insn ("vpst\;vstrbt.<V_sz_elem>\t%q1, %E0",ops); 7286 return ""; 7287} 7288 [(set_attr "length" "8")]) 7289 7290;; 7291;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] 7292;; 7293(define_insn "mve_vldrbq_gather_offset_z_<supf><mode>" 7294 [(set (match_operand:MVE_2 0 "s_register_operand" "=&w") 7295 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "memory_operand" "Us") 7296 (match_operand:MVE_2 2 "s_register_operand" "w") 7297 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 7298 VLDRBGOQ)) 7299 ] 7300 "TARGET_HAVE_MVE" 7301{ 7302 rtx ops[4]; 7303 ops[0] = operands[0]; 7304 ops[1] = operands[1]; 7305 ops[2] = operands[2]; 7306 ops[3] = operands[3]; 7307 if (!strcmp ("<supf>","s") && <V_sz_elem> == 8) 7308 output_asm_insn ("vpst\n\tvldrbt.u8\t%q0, [%m1, %q2]",ops); 7309 else 7310 output_asm_insn ("vpst\n\tvldrbt.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); 7311 return ""; 7312} 7313 [(set_attr "length" "8")]) 7314 7315;; 7316;; [vldrbq_z_s vldrbq_z_u] 7317;; 7318(define_insn "mve_vldrbq_z_<supf><mode>" 7319 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 7320 (unspec:MVE_2 [(match_operand:<MVE_B_ELEM> 1 "mve_memory_operand" "Ux") 7321 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] 7322 VLDRBQ)) 7323 ] 7324 "TARGET_HAVE_MVE" 7325{ 7326 rtx ops[2]; 7327 int regno = REGNO (operands[0]); 7328 ops[0] = gen_rtx_REG (TImode, regno); 7329 ops[1] = operands[1]; 7330 if (<V_sz_elem> == 8) 7331 output_asm_insn ("vpst\;vldrbt.<V_sz_elem>\t%q0, %E1",ops); 7332 else 7333 output_asm_insn ("vpst\;vldrbt.<supf><V_sz_elem>\t%q0, %E1",ops); 7334 return ""; 7335} 7336 [(set_attr "length" "8")]) 7337 7338;; 7339;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] 7340;; 7341(define_insn "mve_vldrwq_gather_base_z_<supf>v4si" 7342 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 7343 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 7344 (match_operand:SI 2 "immediate_operand" "i") 7345 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 7346 VLDRWGBQ)) 7347 ] 7348 "TARGET_HAVE_MVE" 7349{ 7350 rtx ops[3]; 7351 ops[0] = operands[0]; 7352 ops[1] = operands[1]; 7353 ops[2] = operands[2]; 7354 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); 7355 return ""; 7356} 7357 [(set_attr "length" "8")]) 7358 7359;; 7360;; [vldrhq_f] 7361;; 7362(define_insn "mve_vldrhq_fv8hf" 7363 [(set (match_operand:V8HF 0 "s_register_operand" "=w") 7364 (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")] 7365 VLDRHQ_F)) 7366 ] 7367 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7368{ 7369 rtx ops[2]; 7370 int regno = REGNO (operands[0]); 7371 ops[0] = gen_rtx_REG (TImode, regno); 7372 ops[1] = operands[1]; 7373 output_asm_insn ("vldrh.16\t%q0, %E1",ops); 7374 return ""; 7375} 7376 [(set_attr "length" "4")]) 7377 7378;; 7379;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] 7380;; 7381(define_insn "mve_vldrhq_gather_offset_<supf><mode>" 7382 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") 7383 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") 7384 (match_operand:MVE_6 2 "s_register_operand" "w")] 7385 VLDRHGOQ)) 7386 ] 7387 "TARGET_HAVE_MVE" 7388{ 7389 rtx ops[3]; 7390 ops[0] = operands[0]; 7391 ops[1] = operands[1]; 7392 ops[2] = operands[2]; 7393 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) 7394 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2]",ops); 7395 else 7396 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); 7397 return ""; 7398} 7399 [(set_attr "length" "4")]) 7400 7401;; 7402;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] 7403;; 7404(define_insn "mve_vldrhq_gather_offset_z_<supf><mode>" 7405 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") 7406 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") 7407 (match_operand:MVE_6 2 "s_register_operand" "w") 7408 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") 7409 ]VLDRHGOQ)) 7410 ] 7411 "TARGET_HAVE_MVE" 7412{ 7413 rtx ops[4]; 7414 ops[0] = operands[0]; 7415 ops[1] = operands[1]; 7416 ops[2] = operands[2]; 7417 ops[3] = operands[3]; 7418 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) 7419 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2]",ops); 7420 else 7421 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2]",ops); 7422 return ""; 7423} 7424 [(set_attr "length" "8")]) 7425 7426;; 7427;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] 7428;; 7429(define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>" 7430 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") 7431 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") 7432 (match_operand:MVE_6 2 "s_register_operand" "w")] 7433 VLDRHGSOQ)) 7434 ] 7435 "TARGET_HAVE_MVE" 7436{ 7437 rtx ops[3]; 7438 ops[0] = operands[0]; 7439 ops[1] = operands[1]; 7440 ops[2] = operands[2]; 7441 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) 7442 output_asm_insn ("vldrh.u16\t%q0, [%m1, %q2, uxtw #1]",ops); 7443 else 7444 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops); 7445 return ""; 7446} 7447 [(set_attr "length" "4")]) 7448 7449;; 7450;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] 7451;; 7452(define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>" 7453 [(set (match_operand:MVE_6 0 "s_register_operand" "=&w") 7454 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us") 7455 (match_operand:MVE_6 2 "s_register_operand" "w") 7456 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up") 7457 ]VLDRHGSOQ)) 7458 ] 7459 "TARGET_HAVE_MVE" 7460{ 7461 rtx ops[4]; 7462 ops[0] = operands[0]; 7463 ops[1] = operands[1]; 7464 ops[2] = operands[2]; 7465 ops[3] = operands[3]; 7466 if (!strcmp ("<supf>","s") && <V_sz_elem> == 16) 7467 output_asm_insn ("vpst\n\tvldrht.u16\t%q0, [%m1, %q2, uxtw #1]",ops); 7468 else 7469 output_asm_insn ("vpst\n\tvldrht.<supf><V_sz_elem>\t%q0, [%m1, %q2, uxtw #1]",ops); 7470 return ""; 7471} 7472 [(set_attr "length" "8")]) 7473 7474;; 7475;; [vldrhq_s, vldrhq_u] 7476;; 7477(define_insn "mve_vldrhq_<supf><mode>" 7478 [(set (match_operand:MVE_6 0 "s_register_operand" "=w") 7479 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")] 7480 VLDRHQ)) 7481 ] 7482 "TARGET_HAVE_MVE" 7483{ 7484 rtx ops[2]; 7485 int regno = REGNO (operands[0]); 7486 ops[0] = gen_rtx_REG (TImode, regno); 7487 ops[1] = operands[1]; 7488 if (<V_sz_elem> == 16) 7489 output_asm_insn ("vldrh.16\t%q0, %E1",ops); 7490 else 7491 output_asm_insn ("vldrh.<supf><V_sz_elem>\t%q0, %E1",ops); 7492 return ""; 7493} 7494 [(set_attr "length" "4")]) 7495 7496;; 7497;; [vldrhq_z_f] 7498;; 7499(define_insn "mve_vldrhq_z_fv8hf" 7500 [(set (match_operand:V8HF 0 "s_register_operand" "=w") 7501 (unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux") 7502 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] 7503 VLDRHQ_F)) 7504 ] 7505 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7506{ 7507 rtx ops[2]; 7508 int regno = REGNO (operands[0]); 7509 ops[0] = gen_rtx_REG (TImode, regno); 7510 ops[1] = operands[1]; 7511 output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); 7512 return ""; 7513} 7514 [(set_attr "length" "8")]) 7515 7516;; 7517;; [vldrhq_z_s vldrhq_z_u] 7518;; 7519(define_insn "mve_vldrhq_z_<supf><mode>" 7520 [(set (match_operand:MVE_6 0 "s_register_operand" "=w") 7521 (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux") 7522 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")] 7523 VLDRHQ)) 7524 ] 7525 "TARGET_HAVE_MVE" 7526{ 7527 rtx ops[2]; 7528 int regno = REGNO (operands[0]); 7529 ops[0] = gen_rtx_REG (TImode, regno); 7530 ops[1] = operands[1]; 7531 if (<V_sz_elem> == 16) 7532 output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); 7533 else 7534 output_asm_insn ("vpst\;vldrht.<supf><V_sz_elem>\t%q0, %E1",ops); 7535 return ""; 7536} 7537 [(set_attr "length" "8")]) 7538 7539;; 7540;; [vldrwq_f] 7541;; 7542(define_insn "mve_vldrwq_fv4sf" 7543 [(set (match_operand:V4SF 0 "s_register_operand" "=w") 7544 (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux")] 7545 VLDRWQ_F)) 7546 ] 7547 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7548{ 7549 rtx ops[2]; 7550 int regno = REGNO (operands[0]); 7551 ops[0] = gen_rtx_REG (TImode, regno); 7552 ops[1] = operands[1]; 7553 output_asm_insn ("vldrw.32\t%q0, %E1",ops); 7554 return ""; 7555} 7556 [(set_attr "length" "4")]) 7557 7558;; 7559;; [vldrwq_s vldrwq_u] 7560;; 7561(define_insn "mve_vldrwq_<supf>v4si" 7562 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 7563 (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux")] 7564 VLDRWQ)) 7565 ] 7566 "TARGET_HAVE_MVE" 7567{ 7568 rtx ops[2]; 7569 int regno = REGNO (operands[0]); 7570 ops[0] = gen_rtx_REG (TImode, regno); 7571 ops[1] = operands[1]; 7572 output_asm_insn ("vldrw.32\t%q0, %E1",ops); 7573 return ""; 7574} 7575 [(set_attr "length" "4")]) 7576 7577;; 7578;; [vldrwq_z_f] 7579;; 7580(define_insn "mve_vldrwq_z_fv4sf" 7581 [(set (match_operand:V4SF 0 "s_register_operand" "=w") 7582 (unspec:V4SF [(match_operand:V4SI 1 "mve_memory_operand" "Ux") 7583 (match_operand:V4BI 2 "vpr_register_operand" "Up")] 7584 VLDRWQ_F)) 7585 ] 7586 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7587{ 7588 rtx ops[2]; 7589 int regno = REGNO (operands[0]); 7590 ops[0] = gen_rtx_REG (TImode, regno); 7591 ops[1] = operands[1]; 7592 output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); 7593 return ""; 7594} 7595 [(set_attr "length" "8")]) 7596 7597;; 7598;; [vldrwq_z_s vldrwq_z_u] 7599;; 7600(define_insn "mve_vldrwq_z_<supf>v4si" 7601 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 7602 (unspec:V4SI [(match_operand:V4SI 1 "mve_memory_operand" "Ux") 7603 (match_operand:V4BI 2 "vpr_register_operand" "Up")] 7604 VLDRWQ)) 7605 ] 7606 "TARGET_HAVE_MVE" 7607{ 7608 rtx ops[2]; 7609 int regno = REGNO (operands[0]); 7610 ops[0] = gen_rtx_REG (TImode, regno); 7611 ops[1] = operands[1]; 7612 output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); 7613 return ""; 7614} 7615 [(set_attr "length" "8")]) 7616 7617(define_expand "mve_vld1q_f<mode>" 7618 [(match_operand:MVE_0 0 "s_register_operand") 7619 (unspec:MVE_0 [(match_operand:<MVE_CNVT> 1 "mve_memory_operand")] VLD1Q_F) 7620 ] 7621 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" 7622{ 7623 emit_insn (gen_mve_vldr<V_sz_elem1>q_f<mode>(operands[0],operands[1])); 7624 DONE; 7625}) 7626 7627(define_expand "mve_vld1q_<supf><mode>" 7628 [(match_operand:MVE_2 0 "s_register_operand") 7629 (unspec:MVE_2 [(match_operand:MVE_2 1 "mve_memory_operand")] VLD1Q) 7630 ] 7631 "TARGET_HAVE_MVE" 7632{ 7633 emit_insn (gen_mve_vldr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1])); 7634 DONE; 7635}) 7636 7637;; 7638;; [vldrdq_gather_base_s vldrdq_gather_base_u] 7639;; 7640(define_insn "mve_vldrdq_gather_base_<supf>v2di" 7641 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 7642 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") 7643 (match_operand:SI 2 "immediate_operand" "i")] 7644 VLDRDGBQ)) 7645 ] 7646 "TARGET_HAVE_MVE" 7647{ 7648 rtx ops[3]; 7649 ops[0] = operands[0]; 7650 ops[1] = operands[1]; 7651 ops[2] = operands[2]; 7652 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops); 7653 return ""; 7654} 7655 [(set_attr "length" "4")]) 7656 7657;; 7658;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u] 7659;; 7660(define_insn "mve_vldrdq_gather_base_z_<supf>v2di" 7661 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 7662 (unspec:V2DI [(match_operand:V2DI 1 "s_register_operand" "w") 7663 (match_operand:SI 2 "immediate_operand" "i") 7664 (match_operand:HI 3 "vpr_register_operand" "Up")] 7665 VLDRDGBQ)) 7666 ] 7667 "TARGET_HAVE_MVE" 7668{ 7669 rtx ops[3]; 7670 ops[0] = operands[0]; 7671 ops[1] = operands[1]; 7672 ops[2] = operands[2]; 7673 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops); 7674 return ""; 7675} 7676 [(set_attr "length" "8")]) 7677 7678;; 7679;; [vldrdq_gather_offset_s vldrdq_gather_offset_u] 7680;; 7681(define_insn "mve_vldrdq_gather_offset_<supf>v2di" 7682 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 7683 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") 7684 (match_operand:V2DI 2 "s_register_operand" "w")] 7685 VLDRDGOQ)) 7686 ] 7687 "TARGET_HAVE_MVE" 7688{ 7689 rtx ops[3]; 7690 ops[0] = operands[0]; 7691 ops[1] = operands[1]; 7692 ops[2] = operands[2]; 7693 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops); 7694 return ""; 7695} 7696 [(set_attr "length" "4")]) 7697 7698;; 7699;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u] 7700;; 7701(define_insn "mve_vldrdq_gather_offset_z_<supf>v2di" 7702 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 7703 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") 7704 (match_operand:V2DI 2 "s_register_operand" "w") 7705 (match_operand:HI 3 "vpr_register_operand" "Up")] 7706 VLDRDGOQ)) 7707 ] 7708 "TARGET_HAVE_MVE" 7709{ 7710 rtx ops[3]; 7711 ops[0] = operands[0]; 7712 ops[1] = operands[1]; 7713 ops[2] = operands[2]; 7714 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops); 7715 return ""; 7716} 7717 [(set_attr "length" "8")]) 7718 7719;; 7720;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u] 7721;; 7722(define_insn "mve_vldrdq_gather_shifted_offset_<supf>v2di" 7723 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 7724 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") 7725 (match_operand:V2DI 2 "s_register_operand" "w")] 7726 VLDRDGSOQ)) 7727 ] 7728 "TARGET_HAVE_MVE" 7729{ 7730 rtx ops[3]; 7731 ops[0] = operands[0]; 7732 ops[1] = operands[1]; 7733 ops[2] = operands[2]; 7734 output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops); 7735 return ""; 7736} 7737 [(set_attr "length" "4")]) 7738 7739;; 7740;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u] 7741;; 7742(define_insn "mve_vldrdq_gather_shifted_offset_z_<supf>v2di" 7743 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 7744 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "Us") 7745 (match_operand:V2DI 2 "s_register_operand" "w") 7746 (match_operand:HI 3 "vpr_register_operand" "Up")] 7747 VLDRDGSOQ)) 7748 ] 7749 "TARGET_HAVE_MVE" 7750{ 7751 rtx ops[3]; 7752 ops[0] = operands[0]; 7753 ops[1] = operands[1]; 7754 ops[2] = operands[2]; 7755 output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops); 7756 return ""; 7757} 7758 [(set_attr "length" "8")]) 7759 7760;; 7761;; [vldrhq_gather_offset_f] 7762;; 7763(define_insn "mve_vldrhq_gather_offset_fv8hf" 7764 [(set (match_operand:V8HF 0 "s_register_operand" "=&w") 7765 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") 7766 (match_operand:V8HI 2 "s_register_operand" "w")] 7767 VLDRHQGO_F)) 7768 ] 7769 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7770{ 7771 rtx ops[3]; 7772 ops[0] = operands[0]; 7773 ops[1] = operands[1]; 7774 ops[2] = operands[2]; 7775 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops); 7776 return ""; 7777} 7778 [(set_attr "length" "4")]) 7779 7780;; 7781;; [vldrhq_gather_offset_z_f] 7782;; 7783(define_insn "mve_vldrhq_gather_offset_z_fv8hf" 7784 [(set (match_operand:V8HF 0 "s_register_operand" "=&w") 7785 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") 7786 (match_operand:V8HI 2 "s_register_operand" "w") 7787 (match_operand:V8BI 3 "vpr_register_operand" "Up")] 7788 VLDRHQGO_F)) 7789 ] 7790 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7791{ 7792 rtx ops[4]; 7793 ops[0] = operands[0]; 7794 ops[1] = operands[1]; 7795 ops[2] = operands[2]; 7796 ops[3] = operands[3]; 7797 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops); 7798 return ""; 7799} 7800 [(set_attr "length" "8")]) 7801 7802;; 7803;; [vldrhq_gather_shifted_offset_f] 7804;; 7805(define_insn "mve_vldrhq_gather_shifted_offset_fv8hf" 7806 [(set (match_operand:V8HF 0 "s_register_operand" "=&w") 7807 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") 7808 (match_operand:V8HI 2 "s_register_operand" "w")] 7809 VLDRHQGSO_F)) 7810 ] 7811 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7812{ 7813 rtx ops[3]; 7814 ops[0] = operands[0]; 7815 ops[1] = operands[1]; 7816 ops[2] = operands[2]; 7817 output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops); 7818 return ""; 7819} 7820 [(set_attr "length" "4")]) 7821 7822;; 7823;; [vldrhq_gather_shifted_offset_z_f] 7824;; 7825(define_insn "mve_vldrhq_gather_shifted_offset_z_fv8hf" 7826 [(set (match_operand:V8HF 0 "s_register_operand" "=&w") 7827 (unspec:V8HF [(match_operand:V8HI 1 "memory_operand" "Us") 7828 (match_operand:V8HI 2 "s_register_operand" "w") 7829 (match_operand:V8BI 3 "vpr_register_operand" "Up")] 7830 VLDRHQGSO_F)) 7831 ] 7832 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7833{ 7834 rtx ops[4]; 7835 ops[0] = operands[0]; 7836 ops[1] = operands[1]; 7837 ops[2] = operands[2]; 7838 ops[3] = operands[3]; 7839 output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops); 7840 return ""; 7841} 7842 [(set_attr "length" "8")]) 7843 7844;; 7845;; [vldrwq_gather_base_f] 7846;; 7847(define_insn "mve_vldrwq_gather_base_fv4sf" 7848 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 7849 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") 7850 (match_operand:SI 2 "immediate_operand" "i")] 7851 VLDRWQGB_F)) 7852 ] 7853 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7854{ 7855 rtx ops[3]; 7856 ops[0] = operands[0]; 7857 ops[1] = operands[1]; 7858 ops[2] = operands[2]; 7859 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); 7860 return ""; 7861} 7862 [(set_attr "length" "4")]) 7863 7864;; 7865;; [vldrwq_gather_base_z_f] 7866;; 7867(define_insn "mve_vldrwq_gather_base_z_fv4sf" 7868 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 7869 (unspec:V4SF [(match_operand:V4SI 1 "s_register_operand" "w") 7870 (match_operand:SI 2 "immediate_operand" "i") 7871 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 7872 VLDRWQGB_F)) 7873 ] 7874 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7875{ 7876 rtx ops[3]; 7877 ops[0] = operands[0]; 7878 ops[1] = operands[1]; 7879 ops[2] = operands[2]; 7880 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); 7881 return ""; 7882} 7883 [(set_attr "length" "8")]) 7884 7885;; 7886;; [vldrwq_gather_offset_f] 7887;; 7888(define_insn "mve_vldrwq_gather_offset_fv4sf" 7889 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 7890 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") 7891 (match_operand:V4SI 2 "s_register_operand" "w")] 7892 VLDRWQGO_F)) 7893 ] 7894 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7895{ 7896 rtx ops[3]; 7897 ops[0] = operands[0]; 7898 ops[1] = operands[1]; 7899 ops[2] = operands[2]; 7900 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); 7901 return ""; 7902} 7903 [(set_attr "length" "4")]) 7904 7905;; 7906;; [vldrwq_gather_offset_s vldrwq_gather_offset_u] 7907;; 7908(define_insn "mve_vldrwq_gather_offset_<supf>v4si" 7909 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 7910 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") 7911 (match_operand:V4SI 2 "s_register_operand" "w")] 7912 VLDRWGOQ)) 7913 ] 7914 "TARGET_HAVE_MVE" 7915{ 7916 rtx ops[3]; 7917 ops[0] = operands[0]; 7918 ops[1] = operands[1]; 7919 ops[2] = operands[2]; 7920 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); 7921 return ""; 7922} 7923 [(set_attr "length" "4")]) 7924 7925;; 7926;; [vldrwq_gather_offset_z_f] 7927;; 7928(define_insn "mve_vldrwq_gather_offset_z_fv4sf" 7929 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 7930 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") 7931 (match_operand:V4SI 2 "s_register_operand" "w") 7932 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 7933 VLDRWQGO_F)) 7934 ] 7935 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7936{ 7937 rtx ops[4]; 7938 ops[0] = operands[0]; 7939 ops[1] = operands[1]; 7940 ops[2] = operands[2]; 7941 ops[3] = operands[3]; 7942 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); 7943 return ""; 7944} 7945 [(set_attr "length" "8")]) 7946 7947;; 7948;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u] 7949;; 7950(define_insn "mve_vldrwq_gather_offset_z_<supf>v4si" 7951 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 7952 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") 7953 (match_operand:V4SI 2 "s_register_operand" "w") 7954 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 7955 VLDRWGOQ)) 7956 ] 7957 "TARGET_HAVE_MVE" 7958{ 7959 rtx ops[4]; 7960 ops[0] = operands[0]; 7961 ops[1] = operands[1]; 7962 ops[2] = operands[2]; 7963 ops[3] = operands[3]; 7964 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); 7965 return ""; 7966} 7967 [(set_attr "length" "8")]) 7968 7969;; 7970;; [vldrwq_gather_shifted_offset_f] 7971;; 7972(define_insn "mve_vldrwq_gather_shifted_offset_fv4sf" 7973 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 7974 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") 7975 (match_operand:V4SI 2 "s_register_operand" "w")] 7976 VLDRWQGSO_F)) 7977 ] 7978 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 7979{ 7980 rtx ops[3]; 7981 ops[0] = operands[0]; 7982 ops[1] = operands[1]; 7983 ops[2] = operands[2]; 7984 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); 7985 return ""; 7986} 7987 [(set_attr "length" "4")]) 7988 7989;; 7990;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u] 7991;; 7992(define_insn "mve_vldrwq_gather_shifted_offset_<supf>v4si" 7993 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 7994 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") 7995 (match_operand:V4SI 2 "s_register_operand" "w")] 7996 VLDRWGSOQ)) 7997 ] 7998 "TARGET_HAVE_MVE" 7999{ 8000 rtx ops[3]; 8001 ops[0] = operands[0]; 8002 ops[1] = operands[1]; 8003 ops[2] = operands[2]; 8004 output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); 8005 return ""; 8006} 8007 [(set_attr "length" "4")]) 8008 8009;; 8010;; [vldrwq_gather_shifted_offset_z_f] 8011;; 8012(define_insn "mve_vldrwq_gather_shifted_offset_z_fv4sf" 8013 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 8014 (unspec:V4SF [(match_operand:V4SI 1 "memory_operand" "Us") 8015 (match_operand:V4SI 2 "s_register_operand" "w") 8016 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8017 VLDRWQGSO_F)) 8018 ] 8019 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8020{ 8021 rtx ops[4]; 8022 ops[0] = operands[0]; 8023 ops[1] = operands[1]; 8024 ops[2] = operands[2]; 8025 ops[3] = operands[3]; 8026 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); 8027 return ""; 8028} 8029 [(set_attr "length" "8")]) 8030 8031;; 8032;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u] 8033;; 8034(define_insn "mve_vldrwq_gather_shifted_offset_z_<supf>v4si" 8035 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 8036 (unspec:V4SI [(match_operand:V4SI 1 "memory_operand" "Us") 8037 (match_operand:V4SI 2 "s_register_operand" "w") 8038 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8039 VLDRWGSOQ)) 8040 ] 8041 "TARGET_HAVE_MVE" 8042{ 8043 rtx ops[4]; 8044 ops[0] = operands[0]; 8045 ops[1] = operands[1]; 8046 ops[2] = operands[2]; 8047 ops[3] = operands[3]; 8048 output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); 8049 return ""; 8050} 8051 [(set_attr "length" "8")]) 8052 8053;; 8054;; [vstrhq_f] 8055;; 8056(define_insn "mve_vstrhq_fv8hf" 8057 [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") 8058 (unspec:V8HI [(match_operand:V8HF 1 "s_register_operand" "w")] 8059 VSTRHQ_F)) 8060 ] 8061 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8062{ 8063 rtx ops[2]; 8064 int regno = REGNO (operands[1]); 8065 ops[1] = gen_rtx_REG (TImode, regno); 8066 ops[0] = operands[0]; 8067 output_asm_insn ("vstrh.16\t%q1, %E0",ops); 8068 return ""; 8069} 8070 [(set_attr "length" "4")]) 8071 8072;; 8073;; [vstrhq_p_f] 8074;; 8075(define_insn "mve_vstrhq_p_fv8hf" 8076 [(set (match_operand:V8HI 0 "mve_memory_operand" "=Ux") 8077 (unspec:V8HI 8078 [(match_operand:V8HF 1 "s_register_operand" "w") 8079 (match_operand:V8BI 2 "vpr_register_operand" "Up") 8080 (match_dup 0)] 8081 VSTRHQ_F))] 8082 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8083{ 8084 rtx ops[2]; 8085 int regno = REGNO (operands[1]); 8086 ops[1] = gen_rtx_REG (TImode, regno); 8087 ops[0] = operands[0]; 8088 output_asm_insn ("vpst\;vstrht.16\t%q1, %E0",ops); 8089 return ""; 8090} 8091 [(set_attr "length" "8")]) 8092 8093;; 8094;; [vstrhq_p_s vstrhq_p_u] 8095;; 8096(define_insn "mve_vstrhq_p_<supf><mode>" 8097 [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") 8098 (unspec:<MVE_H_ELEM> 8099 [(match_operand:MVE_6 1 "s_register_operand" "w") 8100 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up") 8101 (match_dup 0)] 8102 VSTRHQ)) 8103 ] 8104 "TARGET_HAVE_MVE" 8105{ 8106 rtx ops[2]; 8107 int regno = REGNO (operands[1]); 8108 ops[1] = gen_rtx_REG (TImode, regno); 8109 ops[0] = operands[0]; 8110 output_asm_insn ("vpst\;vstrht.<V_sz_elem>\t%q1, %E0",ops); 8111 return ""; 8112} 8113 [(set_attr "length" "8")]) 8114 8115;; 8116;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u] 8117;; 8118(define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>" 8119 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") 8120 (match_operand:MVE_6 1 "s_register_operand") 8121 (match_operand:MVE_6 2 "s_register_operand") 8122 (match_operand:<MVE_VPRED> 3 "vpr_register_operand") 8123 (unspec:V4SI [(const_int 0)] VSTRHSOQ)] 8124 "TARGET_HAVE_MVE" 8125{ 8126 rtx ind = XEXP (operands[0], 0); 8127 gcc_assert (REG_P (ind)); 8128 emit_insn ( 8129 gen_mve_vstrhq_scatter_offset_p_<supf><mode>_insn (ind, operands[1], 8130 operands[2], 8131 operands[3])); 8132 DONE; 8133}) 8134 8135(define_insn "mve_vstrhq_scatter_offset_p_<supf><mode>_insn" 8136 [(set (mem:BLK (scratch)) 8137 (unspec:BLK 8138 [(match_operand:SI 0 "register_operand" "r") 8139 (match_operand:MVE_6 1 "s_register_operand" "w") 8140 (match_operand:MVE_6 2 "s_register_operand" "w") 8141 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 8142 VSTRHSOQ))] 8143 "TARGET_HAVE_MVE" 8144 "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1]" 8145 [(set_attr "length" "8")]) 8146 8147;; 8148;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u] 8149;; 8150(define_expand "mve_vstrhq_scatter_offset_<supf><mode>" 8151 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") 8152 (match_operand:MVE_6 1 "s_register_operand") 8153 (match_operand:MVE_6 2 "s_register_operand") 8154 (unspec:V4SI [(const_int 0)] VSTRHSOQ)] 8155 "TARGET_HAVE_MVE" 8156{ 8157 rtx ind = XEXP (operands[0], 0); 8158 gcc_assert (REG_P (ind)); 8159 emit_insn (gen_mve_vstrhq_scatter_offset_<supf><mode>_insn (ind, operands[1], 8160 operands[2])); 8161 DONE; 8162}) 8163 8164(define_insn "mve_vstrhq_scatter_offset_<supf><mode>_insn" 8165 [(set (mem:BLK (scratch)) 8166 (unspec:BLK 8167 [(match_operand:SI 0 "register_operand" "r") 8168 (match_operand:MVE_6 1 "s_register_operand" "w") 8169 (match_operand:MVE_6 2 "s_register_operand" "w")] 8170 VSTRHSOQ))] 8171 "TARGET_HAVE_MVE" 8172 "vstrh.<V_sz_elem>\t%q2, [%0, %q1]" 8173 [(set_attr "length" "4")]) 8174 8175;; 8176;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u] 8177;; 8178(define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>" 8179 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") 8180 (match_operand:MVE_6 1 "s_register_operand") 8181 (match_operand:MVE_6 2 "s_register_operand") 8182 (match_operand:<MVE_VPRED> 3 "vpr_register_operand") 8183 (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] 8184 "TARGET_HAVE_MVE" 8185{ 8186 rtx ind = XEXP (operands[0], 0); 8187 gcc_assert (REG_P (ind)); 8188 emit_insn ( 8189 gen_mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn (ind, operands[1], 8190 operands[2], 8191 operands[3])); 8192 DONE; 8193}) 8194 8195(define_insn "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn" 8196 [(set (mem:BLK (scratch)) 8197 (unspec:BLK 8198 [(match_operand:SI 0 "register_operand" "r") 8199 (match_operand:MVE_6 1 "s_register_operand" "w") 8200 (match_operand:MVE_6 2 "s_register_operand" "w") 8201 (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")] 8202 VSTRHSSOQ))] 8203 "TARGET_HAVE_MVE" 8204 "vpst\;vstrht.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" 8205 [(set_attr "length" "8")]) 8206 8207;; 8208;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u] 8209;; 8210(define_expand "mve_vstrhq_scatter_shifted_offset_<supf><mode>" 8211 [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory") 8212 (match_operand:MVE_6 1 "s_register_operand") 8213 (match_operand:MVE_6 2 "s_register_operand") 8214 (unspec:V4SI [(const_int 0)] VSTRHSSOQ)] 8215 "TARGET_HAVE_MVE" 8216{ 8217 rtx ind = XEXP (operands[0], 0); 8218 gcc_assert (REG_P (ind)); 8219 emit_insn ( 8220 gen_mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn (ind, operands[1], 8221 operands[2])); 8222 DONE; 8223}) 8224 8225(define_insn "mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn" 8226 [(set (mem:BLK (scratch)) 8227 (unspec:BLK 8228 [(match_operand:SI 0 "register_operand" "r") 8229 (match_operand:MVE_6 1 "s_register_operand" "w") 8230 (match_operand:MVE_6 2 "s_register_operand" "w")] 8231 VSTRHSSOQ))] 8232 "TARGET_HAVE_MVE" 8233 "vstrh.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]" 8234 [(set_attr "length" "4")]) 8235 8236;; 8237;; [vstrhq_s, vstrhq_u] 8238;; 8239(define_insn "mve_vstrhq_<supf><mode>" 8240 [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux") 8241 (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")] 8242 VSTRHQ)) 8243 ] 8244 "TARGET_HAVE_MVE" 8245{ 8246 rtx ops[2]; 8247 int regno = REGNO (operands[1]); 8248 ops[1] = gen_rtx_REG (TImode, regno); 8249 ops[0] = operands[0]; 8250 output_asm_insn ("vstrh.<V_sz_elem>\t%q1, %E0",ops); 8251 return ""; 8252} 8253 [(set_attr "length" "4")]) 8254 8255;; 8256;; [vstrwq_f] 8257;; 8258(define_insn "mve_vstrwq_fv4sf" 8259 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") 8260 (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")] 8261 VSTRWQ_F)) 8262 ] 8263 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8264{ 8265 rtx ops[2]; 8266 int regno = REGNO (operands[1]); 8267 ops[1] = gen_rtx_REG (TImode, regno); 8268 ops[0] = operands[0]; 8269 output_asm_insn ("vstrw.32\t%q1, %E0",ops); 8270 return ""; 8271} 8272 [(set_attr "length" "4")]) 8273 8274;; 8275;; [vstrwq_p_f] 8276;; 8277(define_insn "mve_vstrwq_p_fv4sf" 8278 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") 8279 (unspec:V4SI 8280 [(match_operand:V4SF 1 "s_register_operand" "w") 8281 (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up") 8282 (match_dup 0)] 8283 VSTRWQ_F))] 8284 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8285{ 8286 rtx ops[2]; 8287 int regno = REGNO (operands[1]); 8288 ops[1] = gen_rtx_REG (TImode, regno); 8289 ops[0] = operands[0]; 8290 output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); 8291 return ""; 8292} 8293 [(set_attr "length" "8")]) 8294 8295;; 8296;; [vstrwq_p_s vstrwq_p_u] 8297;; 8298(define_insn "mve_vstrwq_p_<supf>v4si" 8299 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") 8300 (unspec:V4SI 8301 [(match_operand:V4SI 1 "s_register_operand" "w") 8302 (match_operand:V4BI 2 "vpr_register_operand" "Up") 8303 (match_dup 0)] 8304 VSTRWQ))] 8305 "TARGET_HAVE_MVE" 8306{ 8307 rtx ops[2]; 8308 int regno = REGNO (operands[1]); 8309 ops[1] = gen_rtx_REG (TImode, regno); 8310 ops[0] = operands[0]; 8311 output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); 8312 return ""; 8313} 8314 [(set_attr "length" "8")]) 8315 8316;; 8317;; [vstrwq_s vstrwq_u] 8318;; 8319(define_insn "mve_vstrwq_<supf>v4si" 8320 [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") 8321 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")] 8322 VSTRWQ)) 8323 ] 8324 "TARGET_HAVE_MVE" 8325{ 8326 rtx ops[2]; 8327 int regno = REGNO (operands[1]); 8328 ops[1] = gen_rtx_REG (TImode, regno); 8329 ops[0] = operands[0]; 8330 output_asm_insn ("vstrw.32\t%q1, %E0",ops); 8331 return ""; 8332} 8333 [(set_attr "length" "4")]) 8334 8335(define_expand "mve_vst1q_f<mode>" 8336 [(match_operand:<MVE_CNVT> 0 "mve_memory_operand") 8337 (unspec:<MVE_CNVT> [(match_operand:MVE_0 1 "s_register_operand")] VST1Q_F) 8338 ] 8339 "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" 8340{ 8341 emit_insn (gen_mve_vstr<V_sz_elem1>q_f<mode>(operands[0],operands[1])); 8342 DONE; 8343}) 8344 8345(define_expand "mve_vst1q_<supf><mode>" 8346 [(match_operand:MVE_2 0 "mve_memory_operand") 8347 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand")] VST1Q) 8348 ] 8349 "TARGET_HAVE_MVE" 8350{ 8351 emit_insn (gen_mve_vstr<V_sz_elem1>q_<supf><mode>(operands[0],operands[1])); 8352 DONE; 8353}) 8354 8355;; 8356;; [vstrdq_scatter_base_p_s vstrdq_scatter_base_p_u] 8357;; 8358(define_insn "mve_vstrdq_scatter_base_p_<supf>v2di" 8359 [(set (mem:BLK (scratch)) 8360 (unspec:BLK 8361 [(match_operand:V2DI 0 "s_register_operand" "w") 8362 (match_operand:SI 1 "mve_vldrd_immediate" "Ri") 8363 (match_operand:V2DI 2 "s_register_operand" "w") 8364 (match_operand:HI 3 "vpr_register_operand" "Up")] 8365 VSTRDSBQ)) 8366 ] 8367 "TARGET_HAVE_MVE" 8368{ 8369 rtx ops[3]; 8370 ops[0] = operands[0]; 8371 ops[1] = operands[1]; 8372 ops[2] = operands[2]; 8373 output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops); 8374 return ""; 8375} 8376 [(set_attr "length" "8")]) 8377 8378;; 8379;; [vstrdq_scatter_base_s vstrdq_scatter_base_u] 8380;; 8381(define_insn "mve_vstrdq_scatter_base_<supf>v2di" 8382 [(set (mem:BLK (scratch)) 8383 (unspec:BLK 8384 [(match_operand:V2DI 0 "s_register_operand" "=w") 8385 (match_operand:SI 1 "mve_vldrd_immediate" "Ri") 8386 (match_operand:V2DI 2 "s_register_operand" "w")] 8387 VSTRDSBQ)) 8388 ] 8389 "TARGET_HAVE_MVE" 8390{ 8391 rtx ops[3]; 8392 ops[0] = operands[0]; 8393 ops[1] = operands[1]; 8394 ops[2] = operands[2]; 8395 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops); 8396 return ""; 8397} 8398 [(set_attr "length" "4")]) 8399 8400;; 8401;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u] 8402;; 8403(define_expand "mve_vstrdq_scatter_offset_p_<supf>v2di" 8404 [(match_operand:V2DI 0 "mve_scatter_memory") 8405 (match_operand:V2DI 1 "s_register_operand") 8406 (match_operand:V2DI 2 "s_register_operand") 8407 (match_operand:HI 3 "vpr_register_operand") 8408 (unspec:V4SI [(const_int 0)] VSTRDSOQ)] 8409 "TARGET_HAVE_MVE" 8410{ 8411 rtx ind = XEXP (operands[0], 0); 8412 gcc_assert (REG_P (ind)); 8413 emit_insn (gen_mve_vstrdq_scatter_offset_p_<supf>v2di_insn (ind, operands[1], 8414 operands[2], 8415 operands[3])); 8416 DONE; 8417}) 8418 8419(define_insn "mve_vstrdq_scatter_offset_p_<supf>v2di_insn" 8420 [(set (mem:BLK (scratch)) 8421 (unspec:BLK 8422 [(match_operand:SI 0 "register_operand" "r") 8423 (match_operand:V2DI 1 "s_register_operand" "w") 8424 (match_operand:V2DI 2 "s_register_operand" "w") 8425 (match_operand:HI 3 "vpr_register_operand" "Up")] 8426 VSTRDSOQ))] 8427 "TARGET_HAVE_MVE" 8428 "vpst\;vstrdt.64\t%q2, [%0, %q1]" 8429 [(set_attr "length" "8")]) 8430 8431;; 8432;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u] 8433;; 8434(define_expand "mve_vstrdq_scatter_offset_<supf>v2di" 8435 [(match_operand:V2DI 0 "mve_scatter_memory") 8436 (match_operand:V2DI 1 "s_register_operand") 8437 (match_operand:V2DI 2 "s_register_operand") 8438 (unspec:V4SI [(const_int 0)] VSTRDSOQ)] 8439 "TARGET_HAVE_MVE" 8440{ 8441 rtx ind = XEXP (operands[0], 0); 8442 gcc_assert (REG_P (ind)); 8443 emit_insn (gen_mve_vstrdq_scatter_offset_<supf>v2di_insn (ind, operands[1], 8444 operands[2])); 8445 DONE; 8446}) 8447 8448(define_insn "mve_vstrdq_scatter_offset_<supf>v2di_insn" 8449 [(set (mem:BLK (scratch)) 8450 (unspec:BLK 8451 [(match_operand:SI 0 "register_operand" "r") 8452 (match_operand:V2DI 1 "s_register_operand" "w") 8453 (match_operand:V2DI 2 "s_register_operand" "w")] 8454 VSTRDSOQ))] 8455 "TARGET_HAVE_MVE" 8456 "vstrd.64\t%q2, [%0, %q1]" 8457 [(set_attr "length" "4")]) 8458 8459;; 8460;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u] 8461;; 8462(define_expand "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di" 8463 [(match_operand:V2DI 0 "mve_scatter_memory") 8464 (match_operand:V2DI 1 "s_register_operand") 8465 (match_operand:V2DI 2 "s_register_operand") 8466 (match_operand:HI 3 "vpr_register_operand") 8467 (unspec:V4SI [(const_int 0)] VSTRDSSOQ)] 8468 "TARGET_HAVE_MVE" 8469{ 8470 rtx ind = XEXP (operands[0], 0); 8471 gcc_assert (REG_P (ind)); 8472 emit_insn ( 8473 gen_mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn (ind, operands[1], 8474 operands[2], 8475 operands[3])); 8476 DONE; 8477}) 8478 8479(define_insn "mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn" 8480 [(set (mem:BLK (scratch)) 8481 (unspec:BLK 8482 [(match_operand:SI 0 "register_operand" "r") 8483 (match_operand:V2DI 1 "s_register_operand" "w") 8484 (match_operand:V2DI 2 "s_register_operand" "w") 8485 (match_operand:HI 3 "vpr_register_operand" "Up")] 8486 VSTRDSSOQ))] 8487 "TARGET_HAVE_MVE" 8488 "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]" 8489 [(set_attr "length" "8")]) 8490 8491;; 8492;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u] 8493;; 8494(define_expand "mve_vstrdq_scatter_shifted_offset_<supf>v2di" 8495 [(match_operand:V2DI 0 "mve_scatter_memory") 8496 (match_operand:V2DI 1 "s_register_operand") 8497 (match_operand:V2DI 2 "s_register_operand") 8498 (unspec:V4SI [(const_int 0)] VSTRDSSOQ)] 8499 "TARGET_HAVE_MVE" 8500{ 8501 rtx ind = XEXP (operands[0], 0); 8502 gcc_assert (REG_P (ind)); 8503 emit_insn ( 8504 gen_mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn (ind, operands[1], 8505 operands[2])); 8506 DONE; 8507}) 8508 8509(define_insn "mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn" 8510 [(set (mem:BLK (scratch)) 8511 (unspec:BLK 8512 [(match_operand:SI 0 "register_operand" "r") 8513 (match_operand:V2DI 1 "s_register_operand" "w") 8514 (match_operand:V2DI 2 "s_register_operand" "w")] 8515 VSTRDSSOQ))] 8516 "TARGET_HAVE_MVE" 8517 "vstrd.64\t%q2, [%0, %q1, uxtw #3]" 8518 [(set_attr "length" "4")]) 8519 8520;; 8521;; [vstrhq_scatter_offset_f] 8522;; 8523(define_expand "mve_vstrhq_scatter_offset_fv8hf" 8524 [(match_operand:V8HI 0 "mve_scatter_memory") 8525 (match_operand:V8HI 1 "s_register_operand") 8526 (match_operand:V8HF 2 "s_register_operand") 8527 (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] 8528 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8529{ 8530 rtx ind = XEXP (operands[0], 0); 8531 gcc_assert (REG_P (ind)); 8532 emit_insn (gen_mve_vstrhq_scatter_offset_fv8hf_insn (ind, operands[1], 8533 operands[2])); 8534 DONE; 8535}) 8536 8537(define_insn "mve_vstrhq_scatter_offset_fv8hf_insn" 8538 [(set (mem:BLK (scratch)) 8539 (unspec:BLK 8540 [(match_operand:SI 0 "register_operand" "r") 8541 (match_operand:V8HI 1 "s_register_operand" "w") 8542 (match_operand:V8HF 2 "s_register_operand" "w")] 8543 VSTRHQSO_F))] 8544 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8545 "vstrh.16\t%q2, [%0, %q1]" 8546 [(set_attr "length" "4")]) 8547 8548;; 8549;; [vstrhq_scatter_offset_p_f] 8550;; 8551(define_expand "mve_vstrhq_scatter_offset_p_fv8hf" 8552 [(match_operand:V8HI 0 "mve_scatter_memory") 8553 (match_operand:V8HI 1 "s_register_operand") 8554 (match_operand:V8HF 2 "s_register_operand") 8555 (match_operand:V8BI 3 "vpr_register_operand") 8556 (unspec:V4SI [(const_int 0)] VSTRHQSO_F)] 8557 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8558{ 8559 rtx ind = XEXP (operands[0], 0); 8560 gcc_assert (REG_P (ind)); 8561 emit_insn (gen_mve_vstrhq_scatter_offset_p_fv8hf_insn (ind, operands[1], 8562 operands[2], 8563 operands[3])); 8564 DONE; 8565}) 8566 8567(define_insn "mve_vstrhq_scatter_offset_p_fv8hf_insn" 8568 [(set (mem:BLK (scratch)) 8569 (unspec:BLK 8570 [(match_operand:SI 0 "register_operand" "r") 8571 (match_operand:V8HI 1 "s_register_operand" "w") 8572 (match_operand:V8HF 2 "s_register_operand" "w") 8573 (match_operand:V8BI 3 "vpr_register_operand" "Up")] 8574 VSTRHQSO_F))] 8575 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8576 "vpst\;vstrht.16\t%q2, [%0, %q1]" 8577 [(set_attr "length" "8")]) 8578 8579;; 8580;; [vstrhq_scatter_shifted_offset_f] 8581;; 8582(define_expand "mve_vstrhq_scatter_shifted_offset_fv8hf" 8583 [(match_operand:V8HI 0 "memory_operand" "=Us") 8584 (match_operand:V8HI 1 "s_register_operand" "w") 8585 (match_operand:V8HF 2 "s_register_operand" "w") 8586 (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] 8587 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8588{ 8589 rtx ind = XEXP (operands[0], 0); 8590 gcc_assert (REG_P (ind)); 8591 emit_insn (gen_mve_vstrhq_scatter_shifted_offset_fv8hf_insn (ind, operands[1], 8592 operands[2])); 8593 DONE; 8594}) 8595 8596(define_insn "mve_vstrhq_scatter_shifted_offset_fv8hf_insn" 8597 [(set (mem:BLK (scratch)) 8598 (unspec:BLK 8599 [(match_operand:SI 0 "register_operand" "r") 8600 (match_operand:V8HI 1 "s_register_operand" "w") 8601 (match_operand:V8HF 2 "s_register_operand" "w")] 8602 VSTRHQSSO_F))] 8603 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8604 "vstrh.16\t%q2, [%0, %q1, uxtw #1]" 8605 [(set_attr "length" "4")]) 8606 8607;; 8608;; [vstrhq_scatter_shifted_offset_p_f] 8609;; 8610(define_expand "mve_vstrhq_scatter_shifted_offset_p_fv8hf" 8611 [(match_operand:V8HI 0 "memory_operand" "=Us") 8612 (match_operand:V8HI 1 "s_register_operand" "w") 8613 (match_operand:V8HF 2 "s_register_operand" "w") 8614 (match_operand:V8BI 3 "vpr_register_operand" "Up") 8615 (unspec:V4SI [(const_int 0)] VSTRHQSSO_F)] 8616 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8617{ 8618 rtx ind = XEXP (operands[0], 0); 8619 gcc_assert (REG_P (ind)); 8620 emit_insn ( 8621 gen_mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn (ind, operands[1], 8622 operands[2], 8623 operands[3])); 8624 DONE; 8625}) 8626 8627(define_insn "mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn" 8628 [(set (mem:BLK (scratch)) 8629 (unspec:BLK 8630 [(match_operand:SI 0 "register_operand" "r") 8631 (match_operand:V8HI 1 "s_register_operand" "w") 8632 (match_operand:V8HF 2 "s_register_operand" "w") 8633 (match_operand:V8BI 3 "vpr_register_operand" "Up")] 8634 VSTRHQSSO_F))] 8635 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8636 "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" 8637 [(set_attr "length" "8")]) 8638 8639;; 8640;; [vstrwq_scatter_base_f] 8641;; 8642(define_insn "mve_vstrwq_scatter_base_fv4sf" 8643 [(set (mem:BLK (scratch)) 8644 (unspec:BLK 8645 [(match_operand:V4SI 0 "s_register_operand" "w") 8646 (match_operand:SI 1 "immediate_operand" "i") 8647 (match_operand:V4SF 2 "s_register_operand" "w")] 8648 VSTRWQSB_F)) 8649 ] 8650 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8651{ 8652 rtx ops[3]; 8653 ops[0] = operands[0]; 8654 ops[1] = operands[1]; 8655 ops[2] = operands[2]; 8656 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops); 8657 return ""; 8658} 8659 [(set_attr "length" "4")]) 8660 8661;; 8662;; [vstrwq_scatter_base_p_f] 8663;; 8664(define_insn "mve_vstrwq_scatter_base_p_fv4sf" 8665 [(set (mem:BLK (scratch)) 8666 (unspec:BLK 8667 [(match_operand:V4SI 0 "s_register_operand" "w") 8668 (match_operand:SI 1 "immediate_operand" "i") 8669 (match_operand:V4SF 2 "s_register_operand" "w") 8670 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8671 VSTRWQSB_F)) 8672 ] 8673 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8674{ 8675 rtx ops[3]; 8676 ops[0] = operands[0]; 8677 ops[1] = operands[1]; 8678 ops[2] = operands[2]; 8679 output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); 8680 return ""; 8681} 8682 [(set_attr "length" "8")]) 8683 8684;; 8685;; [vstrwq_scatter_offset_f] 8686;; 8687(define_expand "mve_vstrwq_scatter_offset_fv4sf" 8688 [(match_operand:V4SI 0 "mve_scatter_memory") 8689 (match_operand:V4SI 1 "s_register_operand") 8690 (match_operand:V4SF 2 "s_register_operand") 8691 (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] 8692 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8693{ 8694 rtx ind = XEXP (operands[0], 0); 8695 gcc_assert (REG_P (ind)); 8696 emit_insn (gen_mve_vstrwq_scatter_offset_fv4sf_insn (ind, operands[1], 8697 operands[2])); 8698 DONE; 8699}) 8700 8701(define_insn "mve_vstrwq_scatter_offset_fv4sf_insn" 8702 [(set (mem:BLK (scratch)) 8703 (unspec:BLK 8704 [(match_operand:SI 0 "register_operand" "r") 8705 (match_operand:V4SI 1 "s_register_operand" "w") 8706 (match_operand:V4SF 2 "s_register_operand" "w")] 8707 VSTRWQSO_F))] 8708 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8709 "vstrw.32\t%q2, [%0, %q1]" 8710 [(set_attr "length" "4")]) 8711 8712;; 8713;; [vstrwq_scatter_offset_p_f] 8714;; 8715(define_expand "mve_vstrwq_scatter_offset_p_fv4sf" 8716 [(match_operand:V4SI 0 "mve_scatter_memory") 8717 (match_operand:V4SI 1 "s_register_operand") 8718 (match_operand:V4SF 2 "s_register_operand") 8719 (match_operand:V4BI 3 "vpr_register_operand") 8720 (unspec:V4SI [(const_int 0)] VSTRWQSO_F)] 8721 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8722{ 8723 rtx ind = XEXP (operands[0], 0); 8724 gcc_assert (REG_P (ind)); 8725 emit_insn (gen_mve_vstrwq_scatter_offset_p_fv4sf_insn (ind, operands[1], 8726 operands[2], 8727 operands[3])); 8728 DONE; 8729}) 8730 8731(define_insn "mve_vstrwq_scatter_offset_p_fv4sf_insn" 8732 [(set (mem:BLK (scratch)) 8733 (unspec:BLK 8734 [(match_operand:SI 0 "register_operand" "r") 8735 (match_operand:V4SI 1 "s_register_operand" "w") 8736 (match_operand:V4SF 2 "s_register_operand" "w") 8737 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8738 VSTRWQSO_F))] 8739 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8740 "vpst\;vstrwt.32\t%q2, [%0, %q1]" 8741 [(set_attr "length" "8")]) 8742 8743;; 8744;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] 8745;; 8746(define_expand "mve_vstrwq_scatter_offset_p_<supf>v4si" 8747 [(match_operand:V4SI 0 "mve_scatter_memory") 8748 (match_operand:V4SI 1 "s_register_operand") 8749 (match_operand:V4SI 2 "s_register_operand") 8750 (match_operand:V4BI 3 "vpr_register_operand") 8751 (unspec:V4SI [(const_int 0)] VSTRWSOQ)] 8752 "TARGET_HAVE_MVE" 8753{ 8754 rtx ind = XEXP (operands[0], 0); 8755 gcc_assert (REG_P (ind)); 8756 emit_insn (gen_mve_vstrwq_scatter_offset_p_<supf>v4si_insn (ind, operands[1], 8757 operands[2], 8758 operands[3])); 8759 DONE; 8760}) 8761 8762(define_insn "mve_vstrwq_scatter_offset_p_<supf>v4si_insn" 8763 [(set (mem:BLK (scratch)) 8764 (unspec:BLK 8765 [(match_operand:SI 0 "register_operand" "r") 8766 (match_operand:V4SI 1 "s_register_operand" "w") 8767 (match_operand:V4SI 2 "s_register_operand" "w") 8768 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8769 VSTRWSOQ))] 8770 "TARGET_HAVE_MVE" 8771 "vpst\;vstrwt.32\t%q2, [%0, %q1]" 8772 [(set_attr "length" "8")]) 8773 8774;; 8775;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] 8776;; 8777(define_expand "mve_vstrwq_scatter_offset_<supf>v4si" 8778 [(match_operand:V4SI 0 "mve_scatter_memory") 8779 (match_operand:V4SI 1 "s_register_operand") 8780 (match_operand:V4SI 2 "s_register_operand") 8781 (unspec:V4SI [(const_int 0)] VSTRWSOQ)] 8782 "TARGET_HAVE_MVE" 8783{ 8784 rtx ind = XEXP (operands[0], 0); 8785 gcc_assert (REG_P (ind)); 8786 emit_insn (gen_mve_vstrwq_scatter_offset_<supf>v4si_insn (ind, operands[1], 8787 operands[2])); 8788 DONE; 8789}) 8790 8791(define_insn "mve_vstrwq_scatter_offset_<supf>v4si_insn" 8792 [(set (mem:BLK (scratch)) 8793 (unspec:BLK 8794 [(match_operand:SI 0 "register_operand" "r") 8795 (match_operand:V4SI 1 "s_register_operand" "w") 8796 (match_operand:V4SI 2 "s_register_operand" "w")] 8797 VSTRWSOQ))] 8798 "TARGET_HAVE_MVE" 8799 "vstrw.32\t%q2, [%0, %q1]" 8800 [(set_attr "length" "4")]) 8801 8802;; 8803;; [vstrwq_scatter_shifted_offset_f] 8804;; 8805(define_expand "mve_vstrwq_scatter_shifted_offset_fv4sf" 8806 [(match_operand:V4SI 0 "mve_scatter_memory") 8807 (match_operand:V4SI 1 "s_register_operand") 8808 (match_operand:V4SF 2 "s_register_operand") 8809 (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] 8810 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8811{ 8812 rtx ind = XEXP (operands[0], 0); 8813 gcc_assert (REG_P (ind)); 8814 emit_insn (gen_mve_vstrwq_scatter_shifted_offset_fv4sf_insn (ind, operands[1], 8815 operands[2])); 8816 DONE; 8817}) 8818 8819(define_insn "mve_vstrwq_scatter_shifted_offset_fv4sf_insn" 8820 [(set (mem:BLK (scratch)) 8821 (unspec:BLK 8822 [(match_operand:SI 0 "register_operand" "r") 8823 (match_operand:V4SI 1 "s_register_operand" "w") 8824 (match_operand:V4SF 2 "s_register_operand" "w")] 8825 VSTRWQSSO_F))] 8826 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8827 "vstrw.32\t%q2, [%0, %q1, uxtw #2]" 8828 [(set_attr "length" "8")]) 8829 8830;; 8831;; [vstrwq_scatter_shifted_offset_p_f] 8832;; 8833(define_expand "mve_vstrwq_scatter_shifted_offset_p_fv4sf" 8834 [(match_operand:V4SI 0 "mve_scatter_memory") 8835 (match_operand:V4SI 1 "s_register_operand") 8836 (match_operand:V4SF 2 "s_register_operand") 8837 (match_operand:V4BI 3 "vpr_register_operand") 8838 (unspec:V4SI [(const_int 0)] VSTRWQSSO_F)] 8839 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8840{ 8841 rtx ind = XEXP (operands[0], 0); 8842 gcc_assert (REG_P (ind)); 8843 emit_insn ( 8844 gen_mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn (ind, operands[1], 8845 operands[2], 8846 operands[3])); 8847 DONE; 8848}) 8849 8850(define_insn "mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn" 8851 [(set (mem:BLK (scratch)) 8852 (unspec:BLK 8853 [(match_operand:SI 0 "register_operand" "r") 8854 (match_operand:V4SI 1 "s_register_operand" "w") 8855 (match_operand:V4SF 2 "s_register_operand" "w") 8856 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8857 VSTRWQSSO_F))] 8858 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8859 "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" 8860 [(set_attr "length" "8")]) 8861 8862;; 8863;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u] 8864;; 8865(define_expand "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si" 8866 [(match_operand:V4SI 0 "mve_scatter_memory") 8867 (match_operand:V4SI 1 "s_register_operand") 8868 (match_operand:V4SI 2 "s_register_operand") 8869 (match_operand:V4BI 3 "vpr_register_operand") 8870 (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] 8871 "TARGET_HAVE_MVE" 8872{ 8873 rtx ind = XEXP (operands[0], 0); 8874 gcc_assert (REG_P (ind)); 8875 emit_insn ( 8876 gen_mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn (ind, operands[1], 8877 operands[2], 8878 operands[3])); 8879 DONE; 8880}) 8881 8882(define_insn "mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn" 8883 [(set (mem:BLK (scratch)) 8884 (unspec:BLK 8885 [(match_operand:SI 0 "register_operand" "r") 8886 (match_operand:V4SI 1 "s_register_operand" "w") 8887 (match_operand:V4SI 2 "s_register_operand" "w") 8888 (match_operand:V4BI 3 "vpr_register_operand" "Up")] 8889 VSTRWSSOQ))] 8890 "TARGET_HAVE_MVE" 8891 "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" 8892 [(set_attr "length" "8")]) 8893 8894;; 8895;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u] 8896;; 8897(define_expand "mve_vstrwq_scatter_shifted_offset_<supf>v4si" 8898 [(match_operand:V4SI 0 "mve_scatter_memory") 8899 (match_operand:V4SI 1 "s_register_operand") 8900 (match_operand:V4SI 2 "s_register_operand") 8901 (unspec:V4SI [(const_int 0)] VSTRWSSOQ)] 8902 "TARGET_HAVE_MVE" 8903{ 8904 rtx ind = XEXP (operands[0], 0); 8905 gcc_assert (REG_P (ind)); 8906 emit_insn ( 8907 gen_mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn (ind, operands[1], 8908 operands[2])); 8909 DONE; 8910}) 8911 8912(define_insn "mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn" 8913 [(set (mem:BLK (scratch)) 8914 (unspec:BLK 8915 [(match_operand:SI 0 "register_operand" "r") 8916 (match_operand:V4SI 1 "s_register_operand" "w") 8917 (match_operand:V4SI 2 "s_register_operand" "w")] 8918 VSTRWSSOQ))] 8919 "TARGET_HAVE_MVE" 8920 "vstrw.32\t%q2, [%0, %q1, uxtw #2]" 8921 [(set_attr "length" "4")]) 8922 8923;; 8924;; [vaddq_s, vaddq_u]) 8925;; 8926(define_insn "mve_vaddq<mode>" 8927 [ 8928 (set (match_operand:MVE_2 0 "s_register_operand" "=w") 8929 (plus:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") 8930 (match_operand:MVE_2 2 "s_register_operand" "w"))) 8931 ] 8932 "TARGET_HAVE_MVE" 8933 "vadd.i%#<V_sz_elem>\t%q0, %q1, %q2" 8934 [(set_attr "type" "mve_move") 8935]) 8936 8937;; 8938;; [vaddq_f]) 8939;; 8940(define_insn "mve_vaddq_f<mode>" 8941 [ 8942 (set (match_operand:MVE_0 0 "s_register_operand" "=w") 8943 (plus:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w") 8944 (match_operand:MVE_0 2 "s_register_operand" "w"))) 8945 ] 8946 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 8947 "vadd.f%#<V_sz_elem>\t%q0, %q1, %q2" 8948 [(set_attr "type" "mve_move") 8949]) 8950 8951;; 8952;; [vidupq_n_u]) 8953;; 8954(define_expand "mve_vidupq_n_u<mode>" 8955 [(match_operand:MVE_2 0 "s_register_operand") 8956 (match_operand:SI 1 "s_register_operand") 8957 (match_operand:SI 2 "mve_imm_selective_upto_8")] 8958 "TARGET_HAVE_MVE" 8959{ 8960 rtx temp = gen_reg_rtx (SImode); 8961 emit_move_insn (temp, operands[1]); 8962 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode); 8963 emit_insn (gen_mve_vidupq_u<mode>_insn (operands[0], temp, operands[1], 8964 operands[2], inc)); 8965 DONE; 8966}) 8967 8968;; 8969;; [vidupq_u_insn]) 8970;; 8971(define_insn "mve_vidupq_u<mode>_insn" 8972 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 8973 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") 8974 (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] 8975 VIDUPQ)) 8976 (set (match_operand:SI 1 "s_register_operand" "=Te") 8977 (plus:SI (match_dup 2) 8978 (match_operand:SI 4 "immediate_operand" "i")))] 8979 "TARGET_HAVE_MVE" 8980 "vidup.u%#<V_sz_elem>\t%q0, %1, %3") 8981 8982;; 8983;; [vidupq_m_n_u]) 8984;; 8985(define_expand "mve_vidupq_m_n_u<mode>" 8986 [(match_operand:MVE_2 0 "s_register_operand") 8987 (match_operand:MVE_2 1 "s_register_operand") 8988 (match_operand:SI 2 "s_register_operand") 8989 (match_operand:SI 3 "mve_imm_selective_upto_8") 8990 (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] 8991 "TARGET_HAVE_MVE" 8992{ 8993 rtx temp = gen_reg_rtx (SImode); 8994 emit_move_insn (temp, operands[2]); 8995 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode); 8996 emit_insn (gen_mve_vidupq_m_wb_u<mode>_insn(operands[0], operands[1], temp, 8997 operands[2], operands[3], 8998 operands[4], inc)); 8999 DONE; 9000}) 9001 9002;; 9003;; [vidupq_m_wb_u_insn]) 9004;; 9005(define_insn "mve_vidupq_m_wb_u<mode>_insn" 9006 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9007 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 9008 (match_operand:SI 3 "s_register_operand" "2") 9009 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") 9010 (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] 9011 VIDUPQ_M)) 9012 (set (match_operand:SI 2 "s_register_operand" "=Te") 9013 (plus:SI (match_dup 3) 9014 (match_operand:SI 6 "immediate_operand" "i")))] 9015 "TARGET_HAVE_MVE" 9016 "vpst\;\tvidupt.u%#<V_sz_elem>\t%q0, %2, %4" 9017 [(set_attr "length""8")]) 9018 9019;; 9020;; [vddupq_n_u]) 9021;; 9022(define_expand "mve_vddupq_n_u<mode>" 9023 [(match_operand:MVE_2 0 "s_register_operand") 9024 (match_operand:SI 1 "s_register_operand") 9025 (match_operand:SI 2 "mve_imm_selective_upto_8")] 9026 "TARGET_HAVE_MVE" 9027{ 9028 rtx temp = gen_reg_rtx (SImode); 9029 emit_move_insn (temp, operands[1]); 9030 rtx inc = gen_int_mode (INTVAL(operands[2]) * <MVE_LANES>, SImode); 9031 emit_insn (gen_mve_vddupq_u<mode>_insn (operands[0], temp, operands[1], 9032 operands[2], inc)); 9033 DONE; 9034}) 9035 9036;; 9037;; [vddupq_u_insn]) 9038;; 9039(define_insn "mve_vddupq_u<mode>_insn" 9040 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9041 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") 9042 (match_operand:SI 3 "immediate_operand" "i")] 9043 VDDUPQ)) 9044 (set (match_operand:SI 1 "s_register_operand" "=Te") 9045 (minus:SI (match_dup 2) 9046 (match_operand:SI 4 "immediate_operand" "i")))] 9047 "TARGET_HAVE_MVE" 9048 "vddup.u%#<V_sz_elem>\t%q0, %1, %3") 9049 9050;; 9051;; [vddupq_m_n_u]) 9052;; 9053(define_expand "mve_vddupq_m_n_u<mode>" 9054 [(match_operand:MVE_2 0 "s_register_operand") 9055 (match_operand:MVE_2 1 "s_register_operand") 9056 (match_operand:SI 2 "s_register_operand") 9057 (match_operand:SI 3 "mve_imm_selective_upto_8") 9058 (match_operand:<MVE_VPRED> 4 "vpr_register_operand")] 9059 "TARGET_HAVE_MVE" 9060{ 9061 rtx temp = gen_reg_rtx (SImode); 9062 emit_move_insn (temp, operands[2]); 9063 rtx inc = gen_int_mode (INTVAL(operands[3]) * <MVE_LANES>, SImode); 9064 emit_insn (gen_mve_vddupq_m_wb_u<mode>_insn(operands[0], operands[1], temp, 9065 operands[2], operands[3], 9066 operands[4], inc)); 9067 DONE; 9068}) 9069 9070;; 9071;; [vddupq_m_wb_u_insn]) 9072;; 9073(define_insn "mve_vddupq_m_wb_u<mode>_insn" 9074 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9075 (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") 9076 (match_operand:SI 3 "s_register_operand" "2") 9077 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg") 9078 (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] 9079 VDDUPQ_M)) 9080 (set (match_operand:SI 2 "s_register_operand" "=Te") 9081 (minus:SI (match_dup 3) 9082 (match_operand:SI 6 "immediate_operand" "i")))] 9083 "TARGET_HAVE_MVE" 9084 "vpst\;vddupt.u%#<V_sz_elem>\t%q0, %2, %4" 9085 [(set_attr "length""8")]) 9086 9087;; 9088;; [vdwdupq_n_u]) 9089;; 9090(define_expand "mve_vdwdupq_n_u<mode>" 9091 [(match_operand:MVE_2 0 "s_register_operand") 9092 (match_operand:SI 1 "s_register_operand") 9093 (match_operand:DI 2 "s_register_operand") 9094 (match_operand:SI 3 "mve_imm_selective_upto_8")] 9095 "TARGET_HAVE_MVE" 9096{ 9097 rtx ignore_wb = gen_reg_rtx (SImode); 9098 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb, 9099 operands[1], operands[2], 9100 operands[3])); 9101 DONE; 9102}) 9103 9104;; 9105;; [vdwdupq_wb_u]) 9106;; 9107(define_expand "mve_vdwdupq_wb_u<mode>" 9108 [(match_operand:SI 0 "s_register_operand") 9109 (match_operand:SI 1 "s_register_operand") 9110 (match_operand:DI 2 "s_register_operand") 9111 (match_operand:SI 3 "mve_imm_selective_upto_8") 9112 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 9113 "TARGET_HAVE_MVE" 9114{ 9115 rtx ignore_vec = gen_reg_rtx (<MODE>mode); 9116 emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0], 9117 operands[1], operands[2], 9118 operands[3])); 9119 DONE; 9120}) 9121 9122;; 9123;; [vdwdupq_wb_u_insn]) 9124;; 9125(define_insn "mve_vdwdupq_wb_u<mode>_insn" 9126 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9127 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") 9128 (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4) 9129 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] 9130 VDWDUPQ)) 9131 (set (match_operand:SI 1 "s_register_operand" "=Te") 9132 (unspec:SI [(match_dup 2) 9133 (subreg:SI (match_dup 3) 4) 9134 (match_dup 4)] 9135 VDWDUPQ))] 9136 "TARGET_HAVE_MVE" 9137 "vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" 9138) 9139 9140;; 9141;; [vdwdupq_m_n_u]) 9142;; 9143(define_expand "mve_vdwdupq_m_n_u<mode>" 9144 [(match_operand:MVE_2 0 "s_register_operand") 9145 (match_operand:MVE_2 1 "s_register_operand") 9146 (match_operand:SI 2 "s_register_operand") 9147 (match_operand:DI 3 "s_register_operand") 9148 (match_operand:SI 4 "mve_imm_selective_upto_8") 9149 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] 9150 "TARGET_HAVE_MVE" 9151{ 9152 rtx ignore_wb = gen_reg_rtx (SImode); 9153 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, 9154 operands[1], operands[2], 9155 operands[3], operands[4], 9156 operands[5])); 9157 DONE; 9158}) 9159 9160;; 9161;; [vdwdupq_m_wb_u]) 9162;; 9163(define_expand "mve_vdwdupq_m_wb_u<mode>" 9164 [(match_operand:SI 0 "s_register_operand") 9165 (match_operand:MVE_2 1 "s_register_operand") 9166 (match_operand:SI 2 "s_register_operand") 9167 (match_operand:DI 3 "s_register_operand") 9168 (match_operand:SI 4 "mve_imm_selective_upto_8") 9169 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] 9170 "TARGET_HAVE_MVE" 9171{ 9172 rtx ignore_vec = gen_reg_rtx (<MODE>mode); 9173 emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], 9174 operands[1], operands[2], 9175 operands[3], operands[4], 9176 operands[5])); 9177 DONE; 9178}) 9179 9180;; 9181;; [vdwdupq_m_wb_u_insn]) 9182;; 9183(define_insn "mve_vdwdupq_m_wb_u<mode>_insn" 9184 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9185 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") 9186 (match_operand:SI 3 "s_register_operand" "1") 9187 (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) 9188 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") 9189 (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] 9190 VDWDUPQ_M)) 9191 (set (match_operand:SI 1 "s_register_operand" "=Te") 9192 (unspec:SI [(match_dup 2) 9193 (match_dup 3) 9194 (subreg:SI (match_dup 4) 4) 9195 (match_dup 5) 9196 (match_dup 6)] 9197 VDWDUPQ_M)) 9198 ] 9199 "TARGET_HAVE_MVE" 9200 "vpst\;vdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" 9201 [(set_attr "type" "mve_move") 9202 (set_attr "length""8")]) 9203 9204;; 9205;; [viwdupq_n_u]) 9206;; 9207(define_expand "mve_viwdupq_n_u<mode>" 9208 [(match_operand:MVE_2 0 "s_register_operand") 9209 (match_operand:SI 1 "s_register_operand") 9210 (match_operand:DI 2 "s_register_operand") 9211 (match_operand:SI 3 "mve_imm_selective_upto_8")] 9212 "TARGET_HAVE_MVE" 9213{ 9214 rtx ignore_wb = gen_reg_rtx (SImode); 9215 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (operands[0], ignore_wb, 9216 operands[1], operands[2], 9217 operands[3])); 9218 DONE; 9219}) 9220 9221;; 9222;; [viwdupq_wb_u]) 9223;; 9224(define_expand "mve_viwdupq_wb_u<mode>" 9225 [(match_operand:SI 0 "s_register_operand") 9226 (match_operand:SI 1 "s_register_operand") 9227 (match_operand:DI 2 "s_register_operand") 9228 (match_operand:SI 3 "mve_imm_selective_upto_8") 9229 (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 9230 "TARGET_HAVE_MVE" 9231{ 9232 rtx ignore_vec = gen_reg_rtx (<MODE>mode); 9233 emit_insn (gen_mve_viwdupq_wb_u<mode>_insn (ignore_vec, operands[0], 9234 operands[1], operands[2], 9235 operands[3])); 9236 DONE; 9237}) 9238 9239;; 9240;; [viwdupq_wb_u_insn]) 9241;; 9242(define_insn "mve_viwdupq_wb_u<mode>_insn" 9243 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9244 (unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1") 9245 (subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4) 9246 (match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")] 9247 VIWDUPQ)) 9248 (set (match_operand:SI 1 "s_register_operand" "=Te") 9249 (unspec:SI [(match_dup 2) 9250 (subreg:SI (match_dup 3) 4) 9251 (match_dup 4)] 9252 VIWDUPQ))] 9253 "TARGET_HAVE_MVE" 9254 "viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4" 9255) 9256 9257;; 9258;; [viwdupq_m_n_u]) 9259;; 9260(define_expand "mve_viwdupq_m_n_u<mode>" 9261 [(match_operand:MVE_2 0 "s_register_operand") 9262 (match_operand:MVE_2 1 "s_register_operand") 9263 (match_operand:SI 2 "s_register_operand") 9264 (match_operand:DI 3 "s_register_operand") 9265 (match_operand:SI 4 "mve_imm_selective_upto_8") 9266 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] 9267 "TARGET_HAVE_MVE" 9268{ 9269 rtx ignore_wb = gen_reg_rtx (SImode); 9270 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, 9271 operands[1], operands[2], 9272 operands[3], operands[4], 9273 operands[5])); 9274 DONE; 9275}) 9276 9277;; 9278;; [viwdupq_m_wb_u]) 9279;; 9280(define_expand "mve_viwdupq_m_wb_u<mode>" 9281 [(match_operand:SI 0 "s_register_operand") 9282 (match_operand:MVE_2 1 "s_register_operand") 9283 (match_operand:SI 2 "s_register_operand") 9284 (match_operand:DI 3 "s_register_operand") 9285 (match_operand:SI 4 "mve_imm_selective_upto_8") 9286 (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] 9287 "TARGET_HAVE_MVE" 9288{ 9289 rtx ignore_vec = gen_reg_rtx (<MODE>mode); 9290 emit_insn (gen_mve_viwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], 9291 operands[1], operands[2], 9292 operands[3], operands[4], 9293 operands[5])); 9294 DONE; 9295}) 9296 9297;; 9298;; [viwdupq_m_wb_u_insn]) 9299;; 9300(define_insn "mve_viwdupq_m_wb_u<mode>_insn" 9301 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 9302 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") 9303 (match_operand:SI 3 "s_register_operand" "1") 9304 (subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4) 9305 (match_operand:SI 5 "mve_imm_selective_upto_8" "Rg") 9306 (match_operand:<MVE_VPRED> 6 "vpr_register_operand" "Up")] 9307 VIWDUPQ_M)) 9308 (set (match_operand:SI 1 "s_register_operand" "=Te") 9309 (unspec:SI [(match_dup 2) 9310 (match_dup 3) 9311 (subreg:SI (match_dup 4) 4) 9312 (match_dup 5) 9313 (match_dup 6)] 9314 VIWDUPQ_M)) 9315 ] 9316 "TARGET_HAVE_MVE" 9317 "vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5" 9318 [(set_attr "type" "mve_move") 9319 (set_attr "length""8")]) 9320 9321;; 9322;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u] 9323;; 9324(define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si" 9325 [(set (mem:BLK (scratch)) 9326 (unspec:BLK 9327 [(match_operand:V4SI 1 "s_register_operand" "0") 9328 (match_operand:SI 2 "mve_vldrd_immediate" "Ri") 9329 (match_operand:V4SI 3 "s_register_operand" "w")] 9330 VSTRWSBWBQ)) 9331 (set (match_operand:V4SI 0 "s_register_operand" "=w") 9332 (unspec:V4SI [(match_dup 1) (match_dup 2)] 9333 VSTRWSBWBQ)) 9334 ] 9335 "TARGET_HAVE_MVE" 9336{ 9337 rtx ops[3]; 9338 ops[0] = operands[1]; 9339 ops[1] = operands[2]; 9340 ops[2] = operands[3]; 9341 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); 9342 return ""; 9343} 9344 [(set_attr "length" "4")]) 9345 9346;; 9347;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u] 9348;; 9349(define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" 9350 [(set (mem:BLK (scratch)) 9351 (unspec:BLK 9352 [(match_operand:V4SI 1 "s_register_operand" "0") 9353 (match_operand:SI 2 "mve_vldrd_immediate" "Ri") 9354 (match_operand:V4SI 3 "s_register_operand" "w") 9355 (match_operand:V4BI 4 "vpr_register_operand" "Up")] 9356 VSTRWSBWBQ)) 9357 (set (match_operand:V4SI 0 "s_register_operand" "=w") 9358 (unspec:V4SI [(match_dup 1) (match_dup 2)] 9359 VSTRWSBWBQ)) 9360 ] 9361 "TARGET_HAVE_MVE" 9362{ 9363 rtx ops[3]; 9364 ops[0] = operands[1]; 9365 ops[1] = operands[2]; 9366 ops[2] = operands[3]; 9367 output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); 9368 return ""; 9369} 9370 [(set_attr "length" "8")]) 9371 9372;; 9373;; [vstrwq_scatter_base_wb_f] 9374;; 9375(define_insn "mve_vstrwq_scatter_base_wb_fv4sf" 9376 [(set (mem:BLK (scratch)) 9377 (unspec:BLK 9378 [(match_operand:V4SI 1 "s_register_operand" "0") 9379 (match_operand:SI 2 "mve_vldrd_immediate" "Ri") 9380 (match_operand:V4SF 3 "s_register_operand" "w")] 9381 VSTRWQSBWB_F)) 9382 (set (match_operand:V4SI 0 "s_register_operand" "=w") 9383 (unspec:V4SI [(match_dup 1) (match_dup 2)] 9384 VSTRWQSBWB_F)) 9385 ] 9386 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9387{ 9388 rtx ops[3]; 9389 ops[0] = operands[1]; 9390 ops[1] = operands[2]; 9391 ops[2] = operands[3]; 9392 output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); 9393 return ""; 9394} 9395 [(set_attr "length" "4")]) 9396 9397;; 9398;; [vstrwq_scatter_base_wb_p_f] 9399;; 9400(define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" 9401 [(set (mem:BLK (scratch)) 9402 (unspec:BLK 9403 [(match_operand:V4SI 1 "s_register_operand" "0") 9404 (match_operand:SI 2 "mve_vstrw_immediate" "Rl") 9405 (match_operand:V4SF 3 "s_register_operand" "w") 9406 (match_operand:V4BI 4 "vpr_register_operand" "Up")] 9407 VSTRWQSBWB_F)) 9408 (set (match_operand:V4SI 0 "s_register_operand" "=w") 9409 (unspec:V4SI [(match_dup 1) (match_dup 2)] 9410 VSTRWQSBWB_F)) 9411 ] 9412 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9413{ 9414 rtx ops[3]; 9415 ops[0] = operands[1]; 9416 ops[1] = operands[2]; 9417 ops[2] = operands[3]; 9418 output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); 9419 return ""; 9420} 9421 [(set_attr "length" "8")]) 9422 9423;; 9424;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u] 9425;; 9426(define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di" 9427 [(set (mem:BLK (scratch)) 9428 (unspec:BLK 9429 [(match_operand:V2DI 1 "s_register_operand" "0") 9430 (match_operand:SI 2 "mve_vldrd_immediate" "Ri") 9431 (match_operand:V2DI 3 "s_register_operand" "w")] 9432 VSTRDSBWBQ)) 9433 (set (match_operand:V2DI 0 "s_register_operand" "=&w") 9434 (unspec:V2DI [(match_dup 1) (match_dup 2)] 9435 VSTRDSBWBQ)) 9436 ] 9437 "TARGET_HAVE_MVE" 9438{ 9439 rtx ops[3]; 9440 ops[0] = operands[1]; 9441 ops[1] = operands[2]; 9442 ops[2] = operands[3]; 9443 output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops); 9444 return ""; 9445} 9446 [(set_attr "length" "4")]) 9447 9448;; 9449;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u] 9450;; 9451(define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di" 9452 [(set (mem:BLK (scratch)) 9453 (unspec:BLK 9454 [(match_operand:V2DI 1 "s_register_operand" "0") 9455 (match_operand:SI 2 "mve_vldrd_immediate" "Ri") 9456 (match_operand:V2DI 3 "s_register_operand" "w") 9457 (match_operand:HI 4 "vpr_register_operand" "Up")] 9458 VSTRDSBWBQ)) 9459 (set (match_operand:V2DI 0 "s_register_operand" "=w") 9460 (unspec:V2DI [(match_dup 1) (match_dup 2)] 9461 VSTRDSBWBQ)) 9462 ] 9463 "TARGET_HAVE_MVE" 9464{ 9465 rtx ops[3]; 9466 ops[0] = operands[1]; 9467 ops[1] = operands[2]; 9468 ops[2] = operands[3]; 9469 output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops); 9470 return ""; 9471} 9472 [(set_attr "length" "8")]) 9473 9474(define_expand "mve_vldrwq_gather_base_wb_<supf>v4si" 9475 [(match_operand:V4SI 0 "s_register_operand") 9476 (match_operand:V4SI 1 "s_register_operand") 9477 (match_operand:SI 2 "mve_vldrd_immediate") 9478 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] 9479 "TARGET_HAVE_MVE" 9480{ 9481 rtx ignore_result = gen_reg_rtx (V4SImode); 9482 emit_insn ( 9483 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (ignore_result, operands[0], 9484 operands[1], operands[2])); 9485 DONE; 9486}) 9487 9488(define_expand "mve_vldrwq_gather_base_nowb_<supf>v4si" 9489 [(match_operand:V4SI 0 "s_register_operand") 9490 (match_operand:V4SI 1 "s_register_operand") 9491 (match_operand:SI 2 "mve_vldrd_immediate") 9492 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] 9493 "TARGET_HAVE_MVE" 9494{ 9495 rtx ignore_wb = gen_reg_rtx (V4SImode); 9496 emit_insn ( 9497 gen_mve_vldrwq_gather_base_wb_<supf>v4si_insn (operands[0], ignore_wb, 9498 operands[1], operands[2])); 9499 DONE; 9500}) 9501 9502;; 9503;; [vldrwq_gather_base_wb_s vldrwq_gather_base_wb_u] 9504;; 9505(define_insn "mve_vldrwq_gather_base_wb_<supf>v4si_insn" 9506 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 9507 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") 9508 (match_operand:SI 3 "mve_vldrd_immediate" "Ri") 9509 (mem:BLK (scratch))] 9510 VLDRWGBWBQ)) 9511 (set (match_operand:V4SI 1 "s_register_operand" "=&w") 9512 (unspec:V4SI [(match_dup 2) (match_dup 3)] 9513 VLDRWGBWBQ)) 9514 ] 9515 "TARGET_HAVE_MVE" 9516{ 9517 rtx ops[3]; 9518 ops[0] = operands[0]; 9519 ops[1] = operands[2]; 9520 ops[2] = operands[3]; 9521 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); 9522 return ""; 9523} 9524 [(set_attr "length" "4")]) 9525 9526(define_expand "mve_vldrwq_gather_base_wb_z_<supf>v4si" 9527 [(match_operand:V4SI 0 "s_register_operand") 9528 (match_operand:V4SI 1 "s_register_operand") 9529 (match_operand:SI 2 "mve_vldrd_immediate") 9530 (match_operand:V4BI 3 "vpr_register_operand") 9531 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] 9532 "TARGET_HAVE_MVE" 9533{ 9534 rtx ignore_result = gen_reg_rtx (V4SImode); 9535 emit_insn ( 9536 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (ignore_result, operands[0], 9537 operands[1], operands[2], 9538 operands[3])); 9539 DONE; 9540}) 9541(define_expand "mve_vldrwq_gather_base_nowb_z_<supf>v4si" 9542 [(match_operand:V4SI 0 "s_register_operand") 9543 (match_operand:V4SI 1 "s_register_operand") 9544 (match_operand:SI 2 "mve_vldrd_immediate") 9545 (match_operand:V4BI 3 "vpr_register_operand") 9546 (unspec:V4SI [(const_int 0)] VLDRWGBWBQ)] 9547 "TARGET_HAVE_MVE" 9548{ 9549 rtx ignore_wb = gen_reg_rtx (V4SImode); 9550 emit_insn ( 9551 gen_mve_vldrwq_gather_base_wb_z_<supf>v4si_insn (operands[0], ignore_wb, 9552 operands[1], operands[2], 9553 operands[3])); 9554 DONE; 9555}) 9556 9557;; 9558;; [vldrwq_gather_base_wb_z_s vldrwq_gather_base_wb_z_u] 9559;; 9560(define_insn "mve_vldrwq_gather_base_wb_z_<supf>v4si_insn" 9561 [(set (match_operand:V4SI 0 "s_register_operand" "=&w") 9562 (unspec:V4SI [(match_operand:V4SI 2 "s_register_operand" "1") 9563 (match_operand:SI 3 "mve_vldrd_immediate" "Ri") 9564 (match_operand:V4BI 4 "vpr_register_operand" "Up") 9565 (mem:BLK (scratch))] 9566 VLDRWGBWBQ)) 9567 (set (match_operand:V4SI 1 "s_register_operand" "=&w") 9568 (unspec:V4SI [(match_dup 2) (match_dup 3)] 9569 VLDRWGBWBQ)) 9570 ] 9571 "TARGET_HAVE_MVE" 9572{ 9573 rtx ops[3]; 9574 ops[0] = operands[0]; 9575 ops[1] = operands[2]; 9576 ops[2] = operands[3]; 9577 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); 9578 return ""; 9579} 9580 [(set_attr "length" "8")]) 9581 9582(define_expand "mve_vldrwq_gather_base_wb_fv4sf" 9583 [(match_operand:V4SI 0 "s_register_operand") 9584 (match_operand:V4SI 1 "s_register_operand") 9585 (match_operand:SI 2 "mve_vldrd_immediate") 9586 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] 9587 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9588{ 9589 rtx ignore_result = gen_reg_rtx (V4SFmode); 9590 emit_insn ( 9591 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (ignore_result, operands[0], 9592 operands[1], operands[2])); 9593 DONE; 9594}) 9595 9596(define_expand "mve_vldrwq_gather_base_nowb_fv4sf" 9597 [(match_operand:V4SF 0 "s_register_operand") 9598 (match_operand:V4SI 1 "s_register_operand") 9599 (match_operand:SI 2 "mve_vldrd_immediate") 9600 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] 9601 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9602{ 9603 rtx ignore_wb = gen_reg_rtx (V4SImode); 9604 emit_insn ( 9605 gen_mve_vldrwq_gather_base_wb_fv4sf_insn (operands[0], ignore_wb, 9606 operands[1], operands[2])); 9607 DONE; 9608}) 9609 9610;; 9611;; [vldrwq_gather_base_wb_f] 9612;; 9613(define_insn "mve_vldrwq_gather_base_wb_fv4sf_insn" 9614 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 9615 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") 9616 (match_operand:SI 3 "mve_vldrd_immediate" "Ri") 9617 (mem:BLK (scratch))] 9618 VLDRWQGBWB_F)) 9619 (set (match_operand:V4SI 1 "s_register_operand" "=&w") 9620 (unspec:V4SI [(match_dup 2) (match_dup 3)] 9621 VLDRWQGBWB_F)) 9622 ] 9623 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9624{ 9625 rtx ops[3]; 9626 ops[0] = operands[0]; 9627 ops[1] = operands[2]; 9628 ops[2] = operands[3]; 9629 output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); 9630 return ""; 9631} 9632 [(set_attr "length" "4")]) 9633 9634(define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" 9635 [(match_operand:V4SI 0 "s_register_operand") 9636 (match_operand:V4SI 1 "s_register_operand") 9637 (match_operand:SI 2 "mve_vldrd_immediate") 9638 (match_operand:V4BI 3 "vpr_register_operand") 9639 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] 9640 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9641{ 9642 rtx ignore_result = gen_reg_rtx (V4SFmode); 9643 emit_insn ( 9644 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (ignore_result, operands[0], 9645 operands[1], operands[2], 9646 operands[3])); 9647 DONE; 9648}) 9649 9650(define_expand "mve_vldrwq_gather_base_nowb_z_fv4sf" 9651 [(match_operand:V4SF 0 "s_register_operand") 9652 (match_operand:V4SI 1 "s_register_operand") 9653 (match_operand:SI 2 "mve_vldrd_immediate") 9654 (match_operand:V4BI 3 "vpr_register_operand") 9655 (unspec:V4SI [(const_int 0)] VLDRWQGBWB_F)] 9656 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9657{ 9658 rtx ignore_wb = gen_reg_rtx (V4SImode); 9659 emit_insn ( 9660 gen_mve_vldrwq_gather_base_wb_z_fv4sf_insn (operands[0], ignore_wb, 9661 operands[1], operands[2], 9662 operands[3])); 9663 DONE; 9664}) 9665 9666;; 9667;; [vldrwq_gather_base_wb_z_f] 9668;; 9669(define_insn "mve_vldrwq_gather_base_wb_z_fv4sf_insn" 9670 [(set (match_operand:V4SF 0 "s_register_operand" "=&w") 9671 (unspec:V4SF [(match_operand:V4SI 2 "s_register_operand" "1") 9672 (match_operand:SI 3 "mve_vldrd_immediate" "Ri") 9673 (match_operand:V4BI 4 "vpr_register_operand" "Up") 9674 (mem:BLK (scratch))] 9675 VLDRWQGBWB_F)) 9676 (set (match_operand:V4SI 1 "s_register_operand" "=&w") 9677 (unspec:V4SI [(match_dup 2) (match_dup 3)] 9678 VLDRWQGBWB_F)) 9679 ] 9680 "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" 9681{ 9682 rtx ops[3]; 9683 ops[0] = operands[0]; 9684 ops[1] = operands[2]; 9685 ops[2] = operands[3]; 9686 output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); 9687 return ""; 9688} 9689 [(set_attr "length" "8")]) 9690 9691(define_expand "mve_vldrdq_gather_base_wb_<supf>v2di" 9692 [(match_operand:V2DI 0 "s_register_operand") 9693 (match_operand:V2DI 1 "s_register_operand") 9694 (match_operand:SI 2 "mve_vldrd_immediate") 9695 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] 9696 "TARGET_HAVE_MVE" 9697{ 9698 rtx ignore_result = gen_reg_rtx (V2DImode); 9699 emit_insn ( 9700 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (ignore_result, operands[0], 9701 operands[1], operands[2])); 9702 DONE; 9703}) 9704 9705(define_expand "mve_vldrdq_gather_base_nowb_<supf>v2di" 9706 [(match_operand:V2DI 0 "s_register_operand") 9707 (match_operand:V2DI 1 "s_register_operand") 9708 (match_operand:SI 2 "mve_vldrd_immediate") 9709 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] 9710 "TARGET_HAVE_MVE" 9711{ 9712 rtx ignore_wb = gen_reg_rtx (V2DImode); 9713 emit_insn ( 9714 gen_mve_vldrdq_gather_base_wb_<supf>v2di_insn (operands[0], ignore_wb, 9715 operands[1], operands[2])); 9716 DONE; 9717}) 9718 9719 9720;; 9721;; [vldrdq_gather_base_wb_s vldrdq_gather_base_wb_u] 9722;; 9723(define_insn "mve_vldrdq_gather_base_wb_<supf>v2di_insn" 9724 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 9725 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") 9726 (match_operand:SI 3 "mve_vldrd_immediate" "Ri") 9727 (mem:BLK (scratch))] 9728 VLDRDGBWBQ)) 9729 (set (match_operand:V2DI 1 "s_register_operand" "=&w") 9730 (unspec:V2DI [(match_dup 2) (match_dup 3)] 9731 VLDRDGBWBQ)) 9732 ] 9733 "TARGET_HAVE_MVE" 9734{ 9735 rtx ops[3]; 9736 ops[0] = operands[0]; 9737 ops[1] = operands[2]; 9738 ops[2] = operands[3]; 9739 output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops); 9740 return ""; 9741} 9742 [(set_attr "length" "4")]) 9743 9744(define_expand "mve_vldrdq_gather_base_wb_z_<supf>v2di" 9745 [(match_operand:V2DI 0 "s_register_operand") 9746 (match_operand:V2DI 1 "s_register_operand") 9747 (match_operand:SI 2 "mve_vldrd_immediate") 9748 (match_operand:HI 3 "vpr_register_operand") 9749 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] 9750 "TARGET_HAVE_MVE" 9751{ 9752 rtx ignore_result = gen_reg_rtx (V2DImode); 9753 emit_insn ( 9754 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (ignore_result, operands[0], 9755 operands[1], operands[2], 9756 operands[3])); 9757 DONE; 9758}) 9759 9760(define_expand "mve_vldrdq_gather_base_nowb_z_<supf>v2di" 9761 [(match_operand:V2DI 0 "s_register_operand") 9762 (match_operand:V2DI 1 "s_register_operand") 9763 (match_operand:SI 2 "mve_vldrd_immediate") 9764 (match_operand:HI 3 "vpr_register_operand") 9765 (unspec:V2DI [(const_int 0)] VLDRDGBWBQ)] 9766 "TARGET_HAVE_MVE" 9767{ 9768 rtx ignore_wb = gen_reg_rtx (V2DImode); 9769 emit_insn ( 9770 gen_mve_vldrdq_gather_base_wb_z_<supf>v2di_insn (operands[0], ignore_wb, 9771 operands[1], operands[2], 9772 operands[3])); 9773 DONE; 9774}) 9775 9776(define_insn "get_fpscr_nzcvqc" 9777 [(set (match_operand:SI 0 "register_operand" "=r") 9778 (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] 9779 "TARGET_HAVE_MVE" 9780 "vmrs\\t%0, FPSCR_nzcvqc" 9781 [(set_attr "type" "mve_move")]) 9782 9783(define_insn "set_fpscr_nzcvqc" 9784 [(set (reg:SI VFPCC_REGNUM) 9785 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] 9786 VUNSPEC_SET_FPSCR_NZCVQC))] 9787 "TARGET_HAVE_MVE" 9788 "vmsr\\tFPSCR_nzcvqc, %0" 9789 [(set_attr "type" "mve_move")]) 9790 9791;; 9792;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u] 9793;; 9794(define_insn "mve_vldrdq_gather_base_wb_z_<supf>v2di_insn" 9795 [(set (match_operand:V2DI 0 "s_register_operand" "=&w") 9796 (unspec:V2DI [(match_operand:V2DI 2 "s_register_operand" "1") 9797 (match_operand:SI 3 "mve_vldrd_immediate" "Ri") 9798 (match_operand:HI 4 "vpr_register_operand" "Up") 9799 (mem:BLK (scratch))] 9800 VLDRDGBWBQ)) 9801 (set (match_operand:V2DI 1 "s_register_operand" "=&w") 9802 (unspec:V2DI [(match_dup 2) (match_dup 3)] 9803 VLDRDGBWBQ)) 9804 ] 9805 "TARGET_HAVE_MVE" 9806{ 9807 rtx ops[3]; 9808 ops[0] = operands[0]; 9809 ops[1] = operands[2]; 9810 ops[2] = operands[3]; 9811 output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops); 9812 return ""; 9813} 9814 [(set_attr "length" "8")]) 9815;; 9816;; [vadciq_m_s, vadciq_m_u]) 9817;; 9818(define_insn "mve_vadciq_m_<supf>v4si" 9819 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9820 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") 9821 (match_operand:V4SI 2 "s_register_operand" "w") 9822 (match_operand:V4SI 3 "s_register_operand" "w") 9823 (match_operand:V4BI 4 "vpr_register_operand" "Up")] 9824 VADCIQ_M)) 9825 (set (reg:SI VFPCC_REGNUM) 9826 (unspec:SI [(const_int 0)] 9827 VADCIQ_M)) 9828 ] 9829 "TARGET_HAVE_MVE" 9830 "vpst\;vadcit.i32\t%q0, %q2, %q3" 9831 [(set_attr "type" "mve_move") 9832 (set_attr "length" "8")]) 9833 9834;; 9835;; [vadciq_u, vadciq_s]) 9836;; 9837(define_insn "mve_vadciq_<supf>v4si" 9838 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9839 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 9840 (match_operand:V4SI 2 "s_register_operand" "w")] 9841 VADCIQ)) 9842 (set (reg:SI VFPCC_REGNUM) 9843 (unspec:SI [(const_int 0)] 9844 VADCIQ)) 9845 ] 9846 "TARGET_HAVE_MVE" 9847 "vadci.i32\t%q0, %q1, %q2" 9848 [(set_attr "type" "mve_move") 9849 (set_attr "length" "4")]) 9850 9851;; 9852;; [vadcq_m_s, vadcq_m_u]) 9853;; 9854(define_insn "mve_vadcq_m_<supf>v4si" 9855 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9856 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0") 9857 (match_operand:V4SI 2 "s_register_operand" "w") 9858 (match_operand:V4SI 3 "s_register_operand" "w") 9859 (match_operand:V4BI 4 "vpr_register_operand" "Up")] 9860 VADCQ_M)) 9861 (set (reg:SI VFPCC_REGNUM) 9862 (unspec:SI [(reg:SI VFPCC_REGNUM)] 9863 VADCQ_M)) 9864 ] 9865 "TARGET_HAVE_MVE" 9866 "vpst\;vadct.i32\t%q0, %q2, %q3" 9867 [(set_attr "type" "mve_move") 9868 (set_attr "length" "8")]) 9869 9870;; 9871;; [vadcq_u, vadcq_s]) 9872;; 9873(define_insn "mve_vadcq_<supf>v4si" 9874 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9875 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 9876 (match_operand:V4SI 2 "s_register_operand" "w")] 9877 VADCQ)) 9878 (set (reg:SI VFPCC_REGNUM) 9879 (unspec:SI [(reg:SI VFPCC_REGNUM)] 9880 VADCQ)) 9881 ] 9882 "TARGET_HAVE_MVE" 9883 "vadc.i32\t%q0, %q1, %q2" 9884 [(set_attr "type" "mve_move") 9885 (set_attr "length" "4") 9886 (set_attr "conds" "set")]) 9887 9888;; 9889;; [vsbciq_m_u, vsbciq_m_s]) 9890;; 9891(define_insn "mve_vsbciq_m_<supf>v4si" 9892 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9893 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 9894 (match_operand:V4SI 2 "s_register_operand" "w") 9895 (match_operand:V4SI 3 "s_register_operand" "w") 9896 (match_operand:V4BI 4 "vpr_register_operand" "Up")] 9897 VSBCIQ_M)) 9898 (set (reg:SI VFPCC_REGNUM) 9899 (unspec:SI [(const_int 0)] 9900 VSBCIQ_M)) 9901 ] 9902 "TARGET_HAVE_MVE" 9903 "vpst\;vsbcit.i32\t%q0, %q2, %q3" 9904 [(set_attr "type" "mve_move") 9905 (set_attr "length" "8")]) 9906 9907;; 9908;; [vsbciq_s, vsbciq_u]) 9909;; 9910(define_insn "mve_vsbciq_<supf>v4si" 9911 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9912 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 9913 (match_operand:V4SI 2 "s_register_operand" "w")] 9914 VSBCIQ)) 9915 (set (reg:SI VFPCC_REGNUM) 9916 (unspec:SI [(const_int 0)] 9917 VSBCIQ)) 9918 ] 9919 "TARGET_HAVE_MVE" 9920 "vsbci.i32\t%q0, %q1, %q2" 9921 [(set_attr "type" "mve_move") 9922 (set_attr "length" "4")]) 9923 9924;; 9925;; [vsbcq_m_u, vsbcq_m_s]) 9926;; 9927(define_insn "mve_vsbcq_m_<supf>v4si" 9928 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9929 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 9930 (match_operand:V4SI 2 "s_register_operand" "w") 9931 (match_operand:V4SI 3 "s_register_operand" "w") 9932 (match_operand:V4BI 4 "vpr_register_operand" "Up")] 9933 VSBCQ_M)) 9934 (set (reg:SI VFPCC_REGNUM) 9935 (unspec:SI [(reg:SI VFPCC_REGNUM)] 9936 VSBCQ_M)) 9937 ] 9938 "TARGET_HAVE_MVE" 9939 "vpst\;vsbct.i32\t%q0, %q2, %q3" 9940 [(set_attr "type" "mve_move") 9941 (set_attr "length" "8")]) 9942 9943;; 9944;; [vsbcq_s, vsbcq_u]) 9945;; 9946(define_insn "mve_vsbcq_<supf>v4si" 9947 [(set (match_operand:V4SI 0 "s_register_operand" "=w") 9948 (unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w") 9949 (match_operand:V4SI 2 "s_register_operand" "w")] 9950 VSBCQ)) 9951 (set (reg:SI VFPCC_REGNUM) 9952 (unspec:SI [(reg:SI VFPCC_REGNUM)] 9953 VSBCQ)) 9954 ] 9955 "TARGET_HAVE_MVE" 9956 "vsbc.i32\t%q0, %q1, %q2" 9957 [(set_attr "type" "mve_move") 9958 (set_attr "length" "4")]) 9959 9960;; 9961;; [vst2q]) 9962;; 9963(define_insn "mve_vst2q<mode>" 9964 [(set (match_operand:OI 0 "mve_struct_operand" "=Ug") 9965 (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") 9966 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 9967 VST2Q)) 9968 ] 9969 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 9970 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 9971{ 9972 rtx ops[4]; 9973 int regno = REGNO (operands[1]); 9974 ops[0] = gen_rtx_REG (TImode, regno); 9975 ops[1] = gen_rtx_REG (TImode, regno + 4); 9976 rtx reg = operands[0]; 9977 while (reg && !REG_P (reg)) 9978 reg = XEXP (reg, 0); 9979 gcc_assert (REG_P (reg)); 9980 ops[2] = reg; 9981 ops[3] = operands[0]; 9982 output_asm_insn ("vst20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t" 9983 "vst21.<V_sz_elem>\t{%q0, %q1}, %3", ops); 9984 return ""; 9985} 9986 [(set_attr "length" "8")]) 9987 9988;; 9989;; [vld2q]) 9990;; 9991(define_insn "mve_vld2q<mode>" 9992 [(set (match_operand:OI 0 "s_register_operand" "=w") 9993 (unspec:OI [(match_operand:OI 1 "mve_struct_operand" "Ug") 9994 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 9995 VLD2Q)) 9996 ] 9997 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 9998 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 9999{ 10000 rtx ops[4]; 10001 int regno = REGNO (operands[0]); 10002 ops[0] = gen_rtx_REG (TImode, regno); 10003 ops[1] = gen_rtx_REG (TImode, regno + 4); 10004 rtx reg = operands[1]; 10005 while (reg && !REG_P (reg)) 10006 reg = XEXP (reg, 0); 10007 gcc_assert (REG_P (reg)); 10008 ops[2] = reg; 10009 ops[3] = operands[1]; 10010 output_asm_insn ("vld20.<V_sz_elem>\t{%q0, %q1}, [%2]\n\t" 10011 "vld21.<V_sz_elem>\t{%q0, %q1}, %3", ops); 10012 return ""; 10013} 10014 [(set_attr "length" "8")]) 10015 10016;; 10017;; [vld4q]) 10018;; 10019(define_insn "mve_vld4q<mode>" 10020 [(set (match_operand:XI 0 "s_register_operand" "=w") 10021 (unspec:XI [(match_operand:XI 1 "mve_struct_operand" "Ug") 10022 (unspec:MVE_VLD_ST [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 10023 VLD4Q)) 10024 ] 10025 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10026 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 10027{ 10028 rtx ops[6]; 10029 int regno = REGNO (operands[0]); 10030 ops[0] = gen_rtx_REG (TImode, regno); 10031 ops[1] = gen_rtx_REG (TImode, regno+4); 10032 ops[2] = gen_rtx_REG (TImode, regno+8); 10033 ops[3] = gen_rtx_REG (TImode, regno + 12); 10034 rtx reg = operands[1]; 10035 while (reg && !REG_P (reg)) 10036 reg = XEXP (reg, 0); 10037 gcc_assert (REG_P (reg)); 10038 ops[4] = reg; 10039 ops[5] = operands[1]; 10040 output_asm_insn ("vld40.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" 10041 "vld41.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" 10042 "vld42.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, [%4]\n\t" 10043 "vld43.<V_sz_elem>\t{%q0, %q1, %q2, %q3}, %5", ops); 10044 return ""; 10045} 10046 [(set_attr "length" "16")]) 10047;; 10048;; [vgetq_lane_u, vgetq_lane_s, vgetq_lane_f]) 10049;; 10050(define_insn "mve_vec_extract<mode><V_elem_l>" 10051 [(set (match_operand:<V_elem> 0 "nonimmediate_operand" "=r") 10052 (vec_select:<V_elem> 10053 (match_operand:MVE_VLD_ST 1 "s_register_operand" "w") 10054 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] 10055 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10056 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 10057{ 10058 if (BYTES_BIG_ENDIAN) 10059 { 10060 int elt = INTVAL (operands[2]); 10061 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; 10062 operands[2] = GEN_INT (elt); 10063 } 10064 return "vmov.<V_extr_elem>\t%0, %q1[%c2]"; 10065} 10066 [(set_attr "type" "mve_move")]) 10067 10068(define_insn "mve_vec_extractv2didi" 10069 [(set (match_operand:DI 0 "nonimmediate_operand" "=r") 10070 (vec_select:DI 10071 (match_operand:V2DI 1 "s_register_operand" "w") 10072 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] 10073 "TARGET_HAVE_MVE" 10074{ 10075 int elt = INTVAL (operands[2]); 10076 if (BYTES_BIG_ENDIAN) 10077 elt = 1 - elt; 10078 10079 if (elt == 0) 10080 return "vmov\t%Q0, %R0, %e1"; 10081 else 10082 return "vmov\t%Q0, %R0, %f1"; 10083} 10084 [(set_attr "type" "mve_move")]) 10085 10086(define_insn "*mve_vec_extract_sext_internal<mode>" 10087 [(set (match_operand:SI 0 "s_register_operand" "=r") 10088 (sign_extend:SI 10089 (vec_select:<V_elem> 10090 (match_operand:MVE_2 1 "s_register_operand" "w") 10091 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] 10092 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10093 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 10094{ 10095 if (BYTES_BIG_ENDIAN) 10096 { 10097 int elt = INTVAL (operands[2]); 10098 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; 10099 operands[2] = GEN_INT (elt); 10100 } 10101 return "vmov.s<V_sz_elem>\t%0, %q1[%c2]"; 10102} 10103 [(set_attr "type" "mve_move")]) 10104 10105(define_insn "*mve_vec_extract_zext_internal<mode>" 10106 [(set (match_operand:SI 0 "s_register_operand" "=r") 10107 (zero_extend:SI 10108 (vec_select:<V_elem> 10109 (match_operand:MVE_2 1 "s_register_operand" "w") 10110 (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] 10111 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10112 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 10113{ 10114 if (BYTES_BIG_ENDIAN) 10115 { 10116 int elt = INTVAL (operands[2]); 10117 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; 10118 operands[2] = GEN_INT (elt); 10119 } 10120 return "vmov.u<V_sz_elem>\t%0, %q1[%c2]"; 10121} 10122 [(set_attr "type" "mve_move")]) 10123 10124;; 10125;; [vsetq_lane_u, vsetq_lane_s, vsetq_lane_f]) 10126;; 10127(define_insn "mve_vec_set<mode>_internal" 10128 [(set (match_operand:VQ2 0 "s_register_operand" "=w") 10129 (vec_merge:VQ2 10130 (vec_duplicate:VQ2 10131 (match_operand:<V_elem> 1 "nonimmediate_operand" "r")) 10132 (match_operand:VQ2 3 "s_register_operand" "0") 10133 (match_operand:SI 2 "immediate_operand" "i")))] 10134 "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10135 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))" 10136{ 10137 int elt = ffs ((int) INTVAL (operands[2])) - 1; 10138 if (BYTES_BIG_ENDIAN) 10139 elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt; 10140 operands[2] = GEN_INT (elt); 10141 10142 return "vmov.<V_sz_elem>\t%q0[%c2], %1"; 10143} 10144 [(set_attr "type" "mve_move")]) 10145 10146(define_insn "mve_vec_setv2di_internal" 10147 [(set (match_operand:V2DI 0 "s_register_operand" "=w") 10148 (vec_merge:V2DI 10149 (vec_duplicate:V2DI 10150 (match_operand:DI 1 "nonimmediate_operand" "r")) 10151 (match_operand:V2DI 3 "s_register_operand" "0") 10152 (match_operand:SI 2 "immediate_operand" "i")))] 10153 "TARGET_HAVE_MVE" 10154{ 10155 int elt = ffs ((int) INTVAL (operands[2])) - 1; 10156 if (BYTES_BIG_ENDIAN) 10157 elt = 1 - elt; 10158 10159 if (elt == 0) 10160 return "vmov\t%e0, %Q1, %R1"; 10161 else 10162 return "vmov\t%f0, %J1, %K1"; 10163} 10164 [(set_attr "type" "mve_move")]) 10165 10166;; 10167;; [uqrshll_di] 10168;; 10169(define_insn "mve_uqrshll_sat<supf>_di" 10170 [(set (match_operand:DI 0 "arm_low_register_operand" "=l") 10171 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") 10172 (match_operand:SI 2 "register_operand" "r")] 10173 UQRSHLLQ))] 10174 "TARGET_HAVE_MVE" 10175 "uqrshll%?\\t%Q1, %R1, #<supf>, %2" 10176 [(set_attr "predicable" "yes")]) 10177 10178;; 10179;; [sqrshrl_di] 10180;; 10181(define_insn "mve_sqrshrl_sat<supf>_di" 10182 [(set (match_operand:DI 0 "arm_low_register_operand" "=l") 10183 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") 10184 (match_operand:SI 2 "register_operand" "r")] 10185 SQRSHRLQ))] 10186 "TARGET_HAVE_MVE" 10187 "sqrshrl%?\\t%Q1, %R1, #<supf>, %2" 10188 [(set_attr "predicable" "yes")]) 10189 10190;; 10191;; [uqrshl_si] 10192;; 10193(define_insn "mve_uqrshl_si" 10194 [(set (match_operand:SI 0 "arm_general_register_operand" "=r") 10195 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") 10196 (match_operand:SI 2 "register_operand" "r")] 10197 UQRSHL))] 10198 "TARGET_HAVE_MVE" 10199 "uqrshl%?\\t%1, %2" 10200 [(set_attr "predicable" "yes")]) 10201 10202;; 10203;; [sqrshr_si] 10204;; 10205(define_insn "mve_sqrshr_si" 10206 [(set (match_operand:SI 0 "arm_general_register_operand" "=r") 10207 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") 10208 (match_operand:SI 2 "register_operand" "r")] 10209 SQRSHR))] 10210 "TARGET_HAVE_MVE" 10211 "sqrshr%?\\t%1, %2" 10212 [(set_attr "predicable" "yes")]) 10213 10214;; 10215;; [uqshll_di] 10216;; 10217(define_insn "mve_uqshll_di" 10218 [(set (match_operand:DI 0 "arm_low_register_operand" "=l") 10219 (us_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") 10220 (match_operand:SI 2 "immediate_operand" "Pg")))] 10221 "TARGET_HAVE_MVE" 10222 "uqshll%?\\t%Q1, %R1, %2" 10223 [(set_attr "predicable" "yes")]) 10224 10225;; 10226;; [urshrl_di] 10227;; 10228(define_insn "mve_urshrl_di" 10229 [(set (match_operand:DI 0 "arm_low_register_operand" "=l") 10230 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") 10231 (match_operand:SI 2 "immediate_operand" "Pg")] 10232 URSHRL))] 10233 "TARGET_HAVE_MVE" 10234 "urshrl%?\\t%Q1, %R1, %2" 10235 [(set_attr "predicable" "yes")]) 10236 10237;; 10238;; [uqshl_si] 10239;; 10240(define_insn "mve_uqshl_si" 10241 [(set (match_operand:SI 0 "arm_general_register_operand" "=r") 10242 (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "0") 10243 (match_operand:SI 2 "immediate_operand" "Pg")))] 10244 "TARGET_HAVE_MVE" 10245 "uqshl%?\\t%1, %2" 10246 [(set_attr "predicable" "yes")]) 10247 10248;; 10249;; [urshr_si] 10250;; 10251(define_insn "mve_urshr_si" 10252 [(set (match_operand:SI 0 "arm_general_register_operand" "=r") 10253 (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "0") 10254 (match_operand:SI 2 "immediate_operand" "Pg")] 10255 URSHR))] 10256 "TARGET_HAVE_MVE" 10257 "urshr%?\\t%1, %2" 10258 [(set_attr "predicable" "yes")]) 10259 10260;; 10261;; [sqshl_si] 10262;; 10263(define_insn "mve_sqshl_si" 10264 [(set (match_operand:SI 0 "arm_general_register_operand" "=r") 10265 (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "0") 10266 (match_operand:SI 2 "immediate_operand" "Pg")))] 10267 "TARGET_HAVE_MVE" 10268 "sqshl%?\\t%1, %2" 10269 [(set_attr "predicable" "yes")]) 10270 10271;; 10272;; [srshr_si] 10273;; 10274(define_insn "mve_srshr_si" 10275 [(set (match_operand:SI 0 "arm_general_register_operand" "=r") 10276 (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "0") 10277 (match_operand:SI 2 "immediate_operand" "Pg")] 10278 SRSHR))] 10279 "TARGET_HAVE_MVE" 10280 "srshr%?\\t%1, %2" 10281 [(set_attr "predicable" "yes")]) 10282 10283;; 10284;; [srshrl_di] 10285;; 10286(define_insn "mve_srshrl_di" 10287 [(set (match_operand:DI 0 "arm_low_register_operand" "=l") 10288 (unspec:DI [(match_operand:DI 1 "arm_low_register_operand" "0") 10289 (match_operand:SI 2 "immediate_operand" "Pg")] 10290 SRSHRL))] 10291 "TARGET_HAVE_MVE" 10292 "srshrl%?\\t%Q1, %R1, %2" 10293 [(set_attr "predicable" "yes")]) 10294 10295;; 10296;; [sqshll_di] 10297;; 10298(define_insn "mve_sqshll_di" 10299 [(set (match_operand:DI 0 "arm_low_register_operand" "=l") 10300 (ss_ashift:DI (match_operand:DI 1 "arm_low_register_operand" "0") 10301 (match_operand:SI 2 "immediate_operand" "Pg")))] 10302 "TARGET_HAVE_MVE" 10303 "sqshll%?\\t%Q1, %R1, %2" 10304 [(set_attr "predicable" "yes")]) 10305 10306;; 10307;; [vshlcq_m_u vshlcq_m_s] 10308;; 10309(define_expand "mve_vshlcq_m_vec_<supf><mode>" 10310 [(match_operand:MVE_2 0 "s_register_operand") 10311 (match_operand:MVE_2 1 "s_register_operand") 10312 (match_operand:SI 2 "s_register_operand") 10313 (match_operand:SI 3 "mve_imm_32") 10314 (match_operand:<MVE_VPRED> 4 "vpr_register_operand") 10315 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] 10316 "TARGET_HAVE_MVE" 10317{ 10318 rtx ignore_wb = gen_reg_rtx (SImode); 10319 emit_insn (gen_mve_vshlcq_m_<supf><mode> (operands[0], ignore_wb, operands[1], 10320 operands[2], operands[3], 10321 operands[4])); 10322 DONE; 10323}) 10324 10325(define_expand "mve_vshlcq_m_carry_<supf><mode>" 10326 [(match_operand:SI 0 "s_register_operand") 10327 (match_operand:MVE_2 1 "s_register_operand") 10328 (match_operand:SI 2 "s_register_operand") 10329 (match_operand:SI 3 "mve_imm_32") 10330 (match_operand:<MVE_VPRED> 4 "vpr_register_operand") 10331 (unspec:MVE_2 [(const_int 0)] VSHLCQ_M)] 10332 "TARGET_HAVE_MVE" 10333{ 10334 rtx ignore_vec = gen_reg_rtx (<MODE>mode); 10335 emit_insn (gen_mve_vshlcq_m_<supf><mode> (ignore_vec, operands[0], 10336 operands[1], operands[2], 10337 operands[3], operands[4])); 10338 DONE; 10339}) 10340 10341(define_insn "mve_vshlcq_m_<supf><mode>" 10342 [(set (match_operand:MVE_2 0 "s_register_operand" "=w") 10343 (unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0") 10344 (match_operand:SI 3 "s_register_operand" "1") 10345 (match_operand:SI 4 "mve_imm_32" "Rf") 10346 (match_operand:<MVE_VPRED> 5 "vpr_register_operand" "Up")] 10347 VSHLCQ_M)) 10348 (set (match_operand:SI 1 "s_register_operand" "=r") 10349 (unspec:SI [(match_dup 2) 10350 (match_dup 3) 10351 (match_dup 4) 10352 (match_dup 5)] 10353 VSHLCQ_M)) 10354 ] 10355 "TARGET_HAVE_MVE" 10356 "vpst\;vshlct\t%q0, %1, %4" 10357 [(set_attr "type" "mve_move") 10358 (set_attr "length" "8")]) 10359 10360;; CDE instructions on MVE registers. 10361 10362(define_insn "arm_vcx1qv16qi" 10363 [(set (match_operand:V16QI 0 "register_operand" "=t") 10364 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10365 (match_operand:SI 2 "const_int_mve_cde1_operand" "i")] 10366 UNSPEC_VCDE))] 10367 "TARGET_CDE && TARGET_HAVE_MVE" 10368 "vcx1\\tp%c1, %q0, #%c2" 10369 [(set_attr "type" "coproc")] 10370) 10371 10372(define_insn "arm_vcx1qav16qi" 10373 [(set (match_operand:V16QI 0 "register_operand" "=t") 10374 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10375 (match_operand:V16QI 2 "register_operand" "0") 10376 (match_operand:SI 3 "const_int_mve_cde1_operand" "i")] 10377 UNSPEC_VCDEA))] 10378 "TARGET_CDE && TARGET_HAVE_MVE" 10379 "vcx1a\\tp%c1, %q0, #%c3" 10380 [(set_attr "type" "coproc")] 10381) 10382 10383(define_insn "arm_vcx2qv16qi" 10384 [(set (match_operand:V16QI 0 "register_operand" "=t") 10385 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10386 (match_operand:V16QI 2 "register_operand" "t") 10387 (match_operand:SI 3 "const_int_mve_cde2_operand" "i")] 10388 UNSPEC_VCDE))] 10389 "TARGET_CDE && TARGET_HAVE_MVE" 10390 "vcx2\\tp%c1, %q0, %q2, #%c3" 10391 [(set_attr "type" "coproc")] 10392) 10393 10394(define_insn "arm_vcx2qav16qi" 10395 [(set (match_operand:V16QI 0 "register_operand" "=t") 10396 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10397 (match_operand:V16QI 2 "register_operand" "0") 10398 (match_operand:V16QI 3 "register_operand" "t") 10399 (match_operand:SI 4 "const_int_mve_cde2_operand" "i")] 10400 UNSPEC_VCDEA))] 10401 "TARGET_CDE && TARGET_HAVE_MVE" 10402 "vcx2a\\tp%c1, %q0, %q3, #%c4" 10403 [(set_attr "type" "coproc")] 10404) 10405 10406(define_insn "arm_vcx3qv16qi" 10407 [(set (match_operand:V16QI 0 "register_operand" "=t") 10408 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10409 (match_operand:V16QI 2 "register_operand" "t") 10410 (match_operand:V16QI 3 "register_operand" "t") 10411 (match_operand:SI 4 "const_int_mve_cde3_operand" "i")] 10412 UNSPEC_VCDE))] 10413 "TARGET_CDE && TARGET_HAVE_MVE" 10414 "vcx3\\tp%c1, %q0, %q2, %q3, #%c4" 10415 [(set_attr "type" "coproc")] 10416) 10417 10418(define_insn "arm_vcx3qav16qi" 10419 [(set (match_operand:V16QI 0 "register_operand" "=t") 10420 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10421 (match_operand:V16QI 2 "register_operand" "0") 10422 (match_operand:V16QI 3 "register_operand" "t") 10423 (match_operand:V16QI 4 "register_operand" "t") 10424 (match_operand:SI 5 "const_int_mve_cde3_operand" "i")] 10425 UNSPEC_VCDEA))] 10426 "TARGET_CDE && TARGET_HAVE_MVE" 10427 "vcx3a\\tp%c1, %q0, %q3, %q4, #%c5" 10428 [(set_attr "type" "coproc")] 10429) 10430 10431(define_insn "arm_vcx1q<a>_p_v16qi" 10432 [(set (match_operand:V16QI 0 "register_operand" "=t") 10433 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10434 (match_operand:V16QI 2 "register_operand" "0") 10435 (match_operand:SI 3 "const_int_mve_cde1_operand" "i") 10436 (match_operand:V16BI 4 "vpr_register_operand" "Up")] 10437 CDE_VCX))] 10438 "TARGET_CDE && TARGET_HAVE_MVE" 10439 "vpst\;vcx1<a>t\\tp%c1, %q0, #%c3" 10440 [(set_attr "type" "coproc") 10441 (set_attr "length" "8")] 10442) 10443 10444(define_insn "arm_vcx2q<a>_p_v16qi" 10445 [(set (match_operand:V16QI 0 "register_operand" "=t") 10446 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10447 (match_operand:V16QI 2 "register_operand" "0") 10448 (match_operand:V16QI 3 "register_operand" "t") 10449 (match_operand:SI 4 "const_int_mve_cde2_operand" "i") 10450 (match_operand:V16BI 5 "vpr_register_operand" "Up")] 10451 CDE_VCX))] 10452 "TARGET_CDE && TARGET_HAVE_MVE" 10453 "vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4" 10454 [(set_attr "type" "coproc") 10455 (set_attr "length" "8")] 10456) 10457 10458(define_insn "arm_vcx3q<a>_p_v16qi" 10459 [(set (match_operand:V16QI 0 "register_operand" "=t") 10460 (unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i") 10461 (match_operand:V16QI 2 "register_operand" "0") 10462 (match_operand:V16QI 3 "register_operand" "t") 10463 (match_operand:V16QI 4 "register_operand" "t") 10464 (match_operand:SI 5 "const_int_mve_cde3_operand" "i") 10465 (match_operand:V16BI 6 "vpr_register_operand" "Up")] 10466 CDE_VCX))] 10467 "TARGET_CDE && TARGET_HAVE_MVE" 10468 "vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5" 10469 [(set_attr "type" "coproc") 10470 (set_attr "length" "8")] 10471) 10472 10473(define_insn "*movmisalign<mode>_mve_store" 10474 [(set (match_operand:MVE_VLD_ST 0 "mve_memory_operand" "=Ux") 10475 (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")] 10476 UNSPEC_MISALIGNED_ACCESS))] 10477 "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10478 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))) 10479 && !BYTES_BIG_ENDIAN && unaligned_access" 10480 "vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0" 10481 [(set_attr "type" "mve_store")] 10482) 10483 10484 10485(define_insn "*movmisalign<mode>_mve_load" 10486 [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") 10487 (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "mve_memory_operand" " Ux")] 10488 UNSPEC_MISALIGNED_ACCESS))] 10489 "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode)) 10490 || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))) 10491 && !BYTES_BIG_ENDIAN && unaligned_access" 10492 "vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1" 10493 [(set_attr "type" "mve_load")] 10494) 10495 10496;; Expander for VxBI moves 10497(define_expand "mov<mode>" 10498 [(set (match_operand:MVE_7 0 "nonimmediate_operand") 10499 (match_operand:MVE_7 1 "general_operand"))] 10500 "TARGET_HAVE_MVE" 10501 { 10502 if (!register_operand (operands[0], <MODE>mode)) 10503 operands[1] = force_reg (<MODE>mode, operands[1]); 10504 } 10505) 10506 10507;; Expanders for vec_cmp and vcond 10508 10509(define_expand "vec_cmp<mode><MVE_vpred>" 10510 [(set (match_operand:<MVE_VPRED> 0 "s_register_operand") 10511 (match_operator:<MVE_VPRED> 1 "comparison_operator" 10512 [(match_operand:MVE_VLD_ST 2 "s_register_operand") 10513 (match_operand:MVE_VLD_ST 3 "reg_or_zero_operand")]))] 10514 "TARGET_HAVE_MVE 10515 && (!<Is_float_mode> || flag_unsafe_math_optimizations)" 10516{ 10517 arm_expand_vector_compare (operands[0], GET_CODE (operands[1]), 10518 operands[2], operands[3], false); 10519 DONE; 10520}) 10521 10522(define_expand "vec_cmpu<mode><MVE_vpred>" 10523 [(set (match_operand:<MVE_VPRED> 0 "s_register_operand") 10524 (match_operator:<MVE_VPRED> 1 "comparison_operator" 10525 [(match_operand:MVE_2 2 "s_register_operand") 10526 (match_operand:MVE_2 3 "reg_or_zero_operand")]))] 10527 "TARGET_HAVE_MVE" 10528{ 10529 arm_expand_vector_compare (operands[0], GET_CODE (operands[1]), 10530 operands[2], operands[3], false); 10531 DONE; 10532}) 10533 10534(define_expand "vcond_mask_<mode><MVE_vpred>" 10535 [(set (match_operand:MVE_VLD_ST 0 "s_register_operand") 10536 (if_then_else:MVE_VLD_ST 10537 (match_operand:<MVE_VPRED> 3 "s_register_operand") 10538 (match_operand:MVE_VLD_ST 1 "s_register_operand") 10539 (match_operand:MVE_VLD_ST 2 "s_register_operand")))] 10540 "TARGET_HAVE_MVE" 10541{ 10542 switch (GET_MODE_CLASS (<MODE>mode)) 10543 { 10544 case MODE_VECTOR_INT: 10545 emit_insn (gen_mve_vpselq (VPSELQ_S, <MODE>mode, operands[0], 10546 operands[1], operands[2], operands[3])); 10547 break; 10548 case MODE_VECTOR_FLOAT: 10549 emit_insn (gen_mve_vpselq_f (<MODE>mode, operands[0], 10550 operands[1], operands[2], operands[3])); 10551 break; 10552 default: 10553 gcc_unreachable (); 10554 } 10555 DONE; 10556}) 10557