1 /* $NetBSD: if_sq.c,v 1.60 2024/07/05 04:31:50 rin Exp $ */
2
3 /*
4 * Copyright (c) 2001 Rafal K. Boni
5 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * Portions of this code are derived from software contributed to The
9 * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace
10 * Simulation Facility, NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.60 2024/07/05 04:31:50 rin Exp $");
37
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42 #include <sys/callout.h>
43 #include <sys/mbuf.h>
44 #include <sys/kernel.h>
45 #include <sys/socket.h>
46 #include <sys/ioctl.h>
47 #include <sys/errno.h>
48 #include <sys/syslog.h>
49
50 #include <uvm/uvm_extern.h>
51
52 #include <machine/endian.h>
53
54 #include <net/if.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_ether.h>
58
59 #include <net/bpf.h>
60
61 #include <sys/bus.h>
62 #include <machine/intr.h>
63 #include <machine/sysconf.h>
64
65 #include <dev/ic/seeq8003reg.h>
66
67 #include <sgimips/hpc/sqvar.h>
68 #include <sgimips/hpc/hpcvar.h>
69 #include <sgimips/hpc/hpcreg.h>
70
71 #include <dev/arcbios/arcbios.h>
72 #include <dev/arcbios/arcbiosvar.h>
73
74 #define static
75
76 /*
77 * Short TODO list:
78 * (1) Do counters for bad-RX packets.
79 * (2) Allow multi-segment transmits, instead of copying to a single,
80 * contiguous mbuf.
81 * (3) Verify sq_stop() turns off enough stuff; I was still getting
82 * seeq interrupts after sq_stop().
83 * (4) Implement EDLC modes: especially packet auto-pad and simplex
84 * mode.
85 * (5) Should the driver filter out its own transmissions in non-EDLC
86 * mode?
87 * (6) Multicast support -- multicast filter, address management, ...
88 * (7) Deal with RB0 (recv buffer overflow) on reception. Will need
89 * to figure out if RB0 is read-only as stated in one spot in the
90 * HPC spec or read-write (ie, is the 'write a one to clear it')
91 * the correct thing?
92 */
93
94 #if defined(SQ_DEBUG)
95 int sq_debug = 0;
96 #define SQ_DPRINTF(x) if (sq_debug) printf x
97 #else
98 #define SQ_DPRINTF(x)
99 #endif
100
101 static int sq_match(device_t, cfdata_t, void *);
102 static void sq_attach(device_t, device_t, void *);
103 static int sq_init(struct ifnet *);
104 static void sq_start(struct ifnet *);
105 static void sq_stop(struct ifnet *, int);
106 static void sq_watchdog(struct ifnet *);
107 static int sq_ioctl(struct ifnet *, u_long, void *);
108
109 static void sq_set_filter(struct sq_softc *);
110 static int sq_intr(void *);
111 static int sq_rxintr(struct sq_softc *);
112 static int sq_txintr(struct sq_softc *);
113 static void sq_txring_hpc1(struct sq_softc *);
114 static void sq_txring_hpc3(struct sq_softc *);
115 static void sq_reset(struct sq_softc *);
116 static int sq_add_rxbuf(struct sq_softc *, int);
117 static void sq_dump_buffer(paddr_t, psize_t);
118 static void sq_trace_dump(struct sq_softc *);
119
120 CFATTACH_DECL_NEW(sq, sizeof(struct sq_softc),
121 sq_match, sq_attach, NULL, NULL);
122
123 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
124
125 #define sq_seeq_read(sc, off) \
126 bus_space_read_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3)
127 #define sq_seeq_write(sc, off, val) \
128 bus_space_write_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3, val)
129
130 #define sq_hpc_read(sc, off) \
131 bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off)
132 #define sq_hpc_write(sc, off, val) \
133 bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val)
134
135 /* MAC address offset for non-onboard implementations */
136 #define SQ_HPC_EEPROM_ENADDR 250
137
138 #define SGI_OUI_0 0x08
139 #define SGI_OUI_1 0x00
140 #define SGI_OUI_2 0x69
141
142 static int
sq_match(device_t parent,cfdata_t cf,void * aux)143 sq_match(device_t parent, cfdata_t cf, void *aux)
144 {
145 struct hpc_attach_args *ha = aux;
146
147 if (strcmp(ha->ha_name, cf->cf_name) == 0) {
148 vaddr_t reset, txstat;
149
150 reset = MIPS_PHYS_TO_KSEG1(ha->ha_sh +
151 ha->ha_dmaoff + ha->hpc_regs->enetr_reset);
152 txstat = MIPS_PHYS_TO_KSEG1(ha->ha_sh +
153 ha->ha_devoff + (SEEQ_TXSTAT << 2));
154
155 if (platform.badaddr((void *)reset, sizeof(reset)))
156 return 0;
157
158 *(volatile uint32_t *)reset = 0x1;
159 delay(20);
160 *(volatile uint32_t *)reset = 0x0;
161
162 if (platform.badaddr((void *)txstat, sizeof(txstat)))
163 return 0;
164
165 if ((*(volatile uint32_t *)txstat & 0xff) == TXSTAT_OLDNEW)
166 return 1;
167 }
168
169 return 0;
170 }
171
172 static void
sq_attach(device_t parent,device_t self,void * aux)173 sq_attach(device_t parent, device_t self, void *aux)
174 {
175 int i, err;
176 const char* macaddr;
177 struct sq_softc *sc = device_private(self);
178 struct hpc_attach_args *haa = aux;
179 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
180
181 sc->sc_dev = self;
182 sc->sc_hpct = haa->ha_st;
183 sc->hpc_regs = haa->hpc_regs; /* HPC register definitions */
184
185 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
186 haa->ha_dmaoff, sc->hpc_regs->enet_regs_size,
187 &sc->sc_hpch)) != 0) {
188 printf(": unable to map HPC DMA registers, error = %d\n", err);
189 goto fail_0;
190 }
191
192 sc->sc_regt = haa->ha_st;
193 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
194 haa->ha_devoff, sc->hpc_regs->enet_devregs_size,
195 &sc->sc_regh)) != 0) {
196 printf(": unable to map Seeq registers, error = %d\n", err);
197 goto fail_0;
198 }
199
200 sc->sc_dmat = haa->ha_dmat;
201
202 if ((err = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control),
203 PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg, 1, &sc->sc_ncdseg,
204 BUS_DMA_NOWAIT)) != 0) {
205 printf(": unable to allocate control data, error = %d\n", err);
206 goto fail_0;
207 }
208
209 if ((err = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg,
210 sizeof(struct sq_control), (void **)&sc->sc_control,
211 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
212 printf(": unable to map control data, error = %d\n", err);
213 goto fail_1;
214 }
215
216 if ((err = bus_dmamap_create(sc->sc_dmat,
217 sizeof(struct sq_control), 1, sizeof(struct sq_control), PAGE_SIZE,
218 BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) {
219 printf(": unable to create DMA map for control data, error "
220 "= %d\n", err);
221 goto fail_2;
222 }
223
224 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap,
225 sc->sc_control, sizeof(struct sq_control), NULL,
226 BUS_DMA_NOWAIT)) != 0) {
227 printf(": unable to load DMA map for control data, error "
228 "= %d\n", err);
229 goto fail_3;
230 }
231
232 memset(sc->sc_control, 0, sizeof(struct sq_control));
233
234 /* Create transmit buffer DMA maps */
235 for (i = 0; i < SQ_NTXDESC; i++) {
236 if ((err = bus_dmamap_create(sc->sc_dmat,
237 MCLBYTES, 1, MCLBYTES, 0,
238 BUS_DMA_NOWAIT, &sc->sc_txmap[i])) != 0) {
239 printf(": unable to create tx DMA map %d, error = %d\n",
240 i, err);
241 goto fail_4;
242 }
243 }
244
245 /* Create receive buffer DMA maps */
246 for (i = 0; i < SQ_NRXDESC; i++) {
247 if ((err = bus_dmamap_create(sc->sc_dmat,
248 MCLBYTES, 1, MCLBYTES, 0,
249 BUS_DMA_NOWAIT, &sc->sc_rxmap[i])) != 0) {
250 printf(": unable to create rx DMA map %d, error = %d\n",
251 i, err);
252 goto fail_5;
253 }
254 }
255
256 /* Pre-allocate the receive buffers. */
257 for (i = 0; i < SQ_NRXDESC; i++) {
258 if ((err = sq_add_rxbuf(sc, i)) != 0) {
259 printf(": unable to allocate or map rx buffer %d\n,"
260 " error = %d\n", i, err);
261 goto fail_6;
262 }
263 }
264
265 memcpy(sc->sc_enaddr, &haa->hpc_eeprom[SQ_HPC_EEPROM_ENADDR],
266 ETHER_ADDR_LEN);
267
268 /*
269 * If our mac address is bogus, obtain it from ARCBIOS. This will
270 * be true of the onboard HPC3 on IP22, since there is no eeprom,
271 * but rather the DS1386 RTC's battery-backed ram is used.
272 */
273 if (sc->sc_enaddr[0] != SGI_OUI_0 ||
274 sc->sc_enaddr[1] != SGI_OUI_1 ||
275 sc->sc_enaddr[2] != SGI_OUI_2) {
276 macaddr = arcbios_GetEnvironmentVariable("eaddr");
277 if (macaddr == NULL) {
278 printf(": unable to get MAC address!\n");
279 goto fail_6;
280 }
281 ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr);
282 }
283
284 evcnt_attach_dynamic(&sc->sq_intrcnt, EVCNT_TYPE_INTR, NULL,
285 device_xname(self), "intr");
286
287 if ((cpu_intr_establish(haa->ha_irq, IPL_NET, sq_intr, sc)) == NULL) {
288 printf(": unable to establish interrupt!\n");
289 goto fail_6;
290 }
291
292 /* Reset the chip to a known state. */
293 sq_reset(sc);
294
295 /*
296 * Determine if we're an 8003 or 80c03 by setting the first
297 * MAC address register to non-zero, and then reading it back.
298 * If it's zero, we have an 80c03, because we will have read
299 * the TxCollLSB register.
300 */
301 sq_seeq_write(sc, SEEQ_TXCOLLS0, 0xa5);
302 if (sq_seeq_read(sc, SEEQ_TXCOLLS0) == 0)
303 sc->sc_type = SQ_TYPE_80C03;
304 else
305 sc->sc_type = SQ_TYPE_8003;
306 sq_seeq_write(sc, SEEQ_TXCOLLS0, 0x00);
307
308 printf(": SGI Seeq %s\n",
309 sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003");
310
311 printf("%s: Ethernet address %s\n",
312 device_xname(self), ether_sprintf(sc->sc_enaddr));
313
314 strcpy(ifp->if_xname, device_xname(self));
315 ifp->if_softc = sc;
316 ifp->if_mtu = ETHERMTU;
317 ifp->if_init = sq_init;
318 ifp->if_stop = sq_stop;
319 ifp->if_start = sq_start;
320 ifp->if_ioctl = sq_ioctl;
321 ifp->if_watchdog = sq_watchdog;
322 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST;
323 IFQ_SET_READY(&ifp->if_snd);
324
325 if_attach(ifp);
326 if_deferred_start_init(ifp, NULL);
327 ether_ifattach(ifp, sc->sc_enaddr);
328
329 memset(&sc->sq_trace, 0, sizeof(sc->sq_trace));
330 /* Done! */
331 return;
332
333 /*
334 * Free any resources we've allocated during the failed attach
335 * attempt. Do this in reverse order and fall through.
336 */
337 fail_6:
338 for (i = 0; i < SQ_NRXDESC; i++) {
339 if (sc->sc_rxmbuf[i] != NULL) {
340 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]);
341 m_freem(sc->sc_rxmbuf[i]);
342 }
343 }
344 fail_5:
345 for (i = 0; i < SQ_NRXDESC; i++) {
346 if (sc->sc_rxmap[i] != NULL)
347 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]);
348 }
349 fail_4:
350 for (i = 0; i < SQ_NTXDESC; i++) {
351 if (sc->sc_txmap[i] != NULL)
352 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]);
353 }
354 bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap);
355 fail_3:
356 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap);
357 fail_2:
358 bus_dmamem_unmap(sc->sc_dmat,
359 (void *)sc->sc_control, sizeof(struct sq_control));
360 fail_1:
361 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg);
362 fail_0:
363 return;
364 }
365
366 /* Set up data to get the interface up and running. */
367 int
sq_init(struct ifnet * ifp)368 sq_init(struct ifnet *ifp)
369 {
370 int i;
371 struct sq_softc *sc = ifp->if_softc;
372
373 /* Cancel any in-progress I/O */
374 sq_stop(ifp, 0);
375
376 sc->sc_nextrx = 0;
377
378 sc->sc_nfreetx = SQ_NTXDESC;
379 sc->sc_nexttx = sc->sc_prevtx = 0;
380
381 SQ_TRACE(SQ_RESET, sc, 0, 0);
382
383 /* Set into 8003 mode, bank 0 to program ethernet address */
384 sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0);
385
386 /* Now write the address */
387 for (i = 0; i < ETHER_ADDR_LEN; i++)
388 sq_seeq_write(sc, i, sc->sc_enaddr[i]);
389
390 sc->sc_rxcmd =
391 RXCMD_IE_CRC |
392 RXCMD_IE_DRIB |
393 RXCMD_IE_SHORT |
394 RXCMD_IE_END |
395 RXCMD_IE_GOOD;
396
397 /*
398 * Set the receive filter -- this will add some bits to the
399 * prototype RXCMD register. Do this before setting the
400 * transmit config register, since we might need to switch
401 * banks.
402 */
403 sq_set_filter(sc);
404
405 /* Set up Seeq transmit command register */
406 sq_seeq_write(sc, SEEQ_TXCMD,
407 TXCMD_IE_UFLOW |
408 TXCMD_IE_COLL |
409 TXCMD_IE_16COLL |
410 TXCMD_IE_GOOD);
411
412 /* Now write the receive command register. */
413 sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd);
414
415 /*
416 * Set up HPC ethernet PIO and DMA configurations.
417 *
418 * The PROM appears to do most of this for the onboard HPC3, but
419 * not for the Challenge S's IOPLUS chip. We copy how the onboard
420 * chip is configured and assume that it's correct for both.
421 */
422 if (sc->hpc_regs->revision == 3) {
423 uint32_t dmareg, pioreg;
424
425 pioreg =
426 HPC3_ENETR_PIOCFG_P1(1) |
427 HPC3_ENETR_PIOCFG_P2(6) |
428 HPC3_ENETR_PIOCFG_P3(1);
429
430 dmareg =
431 HPC3_ENETR_DMACFG_D1(6) |
432 HPC3_ENETR_DMACFG_D2(2) |
433 HPC3_ENETR_DMACFG_D3(0) |
434 HPC3_ENETR_DMACFG_FIX_RXDC |
435 HPC3_ENETR_DMACFG_FIX_INTR |
436 HPC3_ENETR_DMACFG_FIX_EOP |
437 HPC3_ENETR_DMACFG_TIMEOUT;
438
439 sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg);
440 sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg);
441 }
442
443 /* Pass the start of the receive ring to the HPC */
444 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0));
445
446 /* And turn on the HPC ethernet receive channel */
447 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
448 sc->hpc_regs->enetr_ctl_active);
449
450 /*
451 * Turn off delayed receive interrupts on HPC1.
452 * (see Hollywood HPC Specification 2.1.4.3)
453 */
454 if (sc->hpc_regs->revision != 3)
455 sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF);
456
457 ifp->if_flags |= IFF_RUNNING;
458
459 return 0;
460 }
461
462 static void
sq_set_filter(struct sq_softc * sc)463 sq_set_filter(struct sq_softc *sc)
464 {
465 struct ethercom *ec = &sc->sc_ethercom;
466 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
467 struct ether_multi *enm;
468 struct ether_multistep step;
469
470 /*
471 * Check for promiscuous mode. Also implies
472 * all-multicast.
473 */
474 if (ifp->if_flags & IFF_PROMISC) {
475 sc->sc_rxcmd |= RXCMD_REC_ALL;
476 ifp->if_flags |= IFF_ALLMULTI;
477 return;
478 }
479
480 /*
481 * The 8003 has no hash table. If we have any multicast
482 * addresses on the list, enable reception of all multicast
483 * frames.
484 *
485 * XXX The 80c03 has a hash table. We should use it.
486 */
487
488 ETHER_FIRST_MULTI(step, ec, enm);
489
490 if (enm == NULL) {
491 sc->sc_rxcmd &= ~RXCMD_REC_MASK;
492 sc->sc_rxcmd |= RXCMD_REC_BROAD;
493
494 ifp->if_flags &= ~IFF_ALLMULTI;
495 return;
496 }
497
498 sc->sc_rxcmd |= RXCMD_REC_MULTI;
499 ifp->if_flags |= IFF_ALLMULTI;
500 }
501
502 int
sq_ioctl(struct ifnet * ifp,u_long cmd,void * data)503 sq_ioctl(struct ifnet *ifp, u_long cmd, void *data)
504 {
505 int s, error = 0;
506
507 SQ_TRACE(SQ_IOCTL, (struct sq_softc *)ifp->if_softc, 0, 0);
508
509 s = splnet();
510
511 error = ether_ioctl(ifp, cmd, data);
512 if (error == ENETRESET) {
513 /*
514 * Multicast list has changed; set the hardware filter
515 * accordingly.
516 */
517 if (ifp->if_flags & IFF_RUNNING)
518 error = sq_init(ifp);
519 else
520 error = 0;
521 }
522
523 splx(s);
524 return error;
525 }
526
527 void
sq_start(struct ifnet * ifp)528 sq_start(struct ifnet *ifp)
529 {
530 struct sq_softc *sc = ifp->if_softc;
531 uint32_t status;
532 struct mbuf *m0, *m;
533 bus_dmamap_t dmamap;
534 int err, totlen, nexttx, firsttx, lasttx = -1, ofree, seg;
535
536 if ((ifp->if_flags & IFF_RUNNING) == 0)
537 return;
538
539 /*
540 * Remember the previous number of free descriptors and
541 * the first descriptor we'll use.
542 */
543 ofree = sc->sc_nfreetx;
544 firsttx = sc->sc_nexttx;
545
546 /*
547 * Loop through the send queue, setting up transmit descriptors
548 * until we drain the queue, or use up all available transmit
549 * descriptors.
550 */
551 while (sc->sc_nfreetx != 0) {
552 /*
553 * Grab a packet off the queue.
554 */
555 IFQ_POLL(&ifp->if_snd, m0);
556 if (m0 == NULL)
557 break;
558 m = NULL;
559
560 dmamap = sc->sc_txmap[sc->sc_nexttx];
561
562 /*
563 * Load the DMA map. If this fails, the packet either
564 * didn't fit in the allotted number of segments, or we were
565 * short on resources. In this case, we'll copy and try
566 * again.
567 * Also copy it if we need to pad, so that we are sure there
568 * is room for the pad buffer.
569 * XXX the right way of doing this is to use a static buffer
570 * for padding and adding it to the transmit descriptor (see
571 * sys/dev/pci/if_tl.c for example). We can't do this here yet
572 * because we can't send packets with more than one fragment.
573 */
574 if (m0->m_pkthdr.len < ETHER_PAD_LEN ||
575 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
576 BUS_DMA_NOWAIT) != 0) {
577 MGETHDR(m, M_DONTWAIT, MT_DATA);
578 if (m == NULL) {
579 printf("%s: unable to allocate Tx mbuf\n",
580 device_xname(sc->sc_dev));
581 break;
582 }
583 if (m0->m_pkthdr.len > MHLEN) {
584 MCLGET(m, M_DONTWAIT);
585 if ((m->m_flags & M_EXT) == 0) {
586 printf("%s: unable to allocate Tx "
587 "cluster\n",
588 device_xname(sc->sc_dev));
589 m_freem(m);
590 break;
591 }
592 }
593
594 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
595 if (m0->m_pkthdr.len < ETHER_PAD_LEN) {
596 memset(mtod(m, char *) + m0->m_pkthdr.len, 0,
597 ETHER_PAD_LEN - m0->m_pkthdr.len);
598 m->m_pkthdr.len = m->m_len = ETHER_PAD_LEN;
599 } else
600 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
601
602 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
603 m, BUS_DMA_NOWAIT)) != 0) {
604 printf("%s: unable to load Tx buffer, "
605 "error = %d\n",
606 device_xname(sc->sc_dev), err);
607 break;
608 }
609 }
610
611 /*
612 * Ensure we have enough descriptors free to describe
613 * the packet.
614 */
615 if (dmamap->dm_nsegs > sc->sc_nfreetx) {
616 /*
617 * Not enough free descriptors to transmit this
618 * packet. We haven't committed to anything yet,
619 * so just unload the DMA map, put the packet
620 * back on the queue, and punt.
621 *
622 * XXX We could allocate an mbuf and copy, but
623 * XXX it is worth it?
624 */
625 bus_dmamap_unload(sc->sc_dmat, dmamap);
626 m_freem(m);
627 break;
628 }
629
630 IFQ_DEQUEUE(&ifp->if_snd, m0);
631 /*
632 * Pass the packet to any BPF listeners.
633 */
634 bpf_mtap(ifp, m0, BPF_D_OUT);
635 if (m != NULL) {
636 m_freem(m0);
637 m0 = m;
638 }
639
640 /*
641 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
642 */
643
644 SQ_TRACE(SQ_ENQUEUE, sc, sc->sc_nexttx, 0);
645
646 /* Sync the DMA map. */
647 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
648 BUS_DMASYNC_PREWRITE);
649
650 /*
651 * Initialize the transmit descriptors.
652 */
653 for (nexttx = sc->sc_nexttx, seg = 0, totlen = 0;
654 seg < dmamap->dm_nsegs;
655 seg++, nexttx = SQ_NEXTTX(nexttx)) {
656 if (sc->hpc_regs->revision == 3) {
657 sc->sc_txdesc[nexttx].hpc3_hdd_bufptr =
658 dmamap->dm_segs[seg].ds_addr;
659 sc->sc_txdesc[nexttx].hpc3_hdd_ctl =
660 dmamap->dm_segs[seg].ds_len;
661 } else {
662 sc->sc_txdesc[nexttx].hpc1_hdd_bufptr =
663 dmamap->dm_segs[seg].ds_addr;
664 sc->sc_txdesc[nexttx].hpc1_hdd_ctl =
665 dmamap->dm_segs[seg].ds_len;
666 }
667 sc->sc_txdesc[nexttx].hdd_descptr =
668 SQ_CDTXADDR(sc, SQ_NEXTTX(nexttx));
669 lasttx = nexttx;
670 totlen += dmamap->dm_segs[seg].ds_len;
671 }
672
673 /* Last descriptor gets end-of-packet */
674 KASSERT(lasttx != -1);
675 if (sc->hpc_regs->revision == 3)
676 sc->sc_txdesc[lasttx].hpc3_hdd_ctl |=
677 HPC3_HDD_CTL_EOPACKET;
678 else
679 sc->sc_txdesc[lasttx].hpc1_hdd_ctl |=
680 HPC1_HDD_CTL_EOPACKET;
681
682 SQ_DPRINTF(("%s: transmit %d-%d, len %d\n",
683 device_xname(sc->sc_dev), sc->sc_nexttx, lasttx, totlen));
684
685 if (ifp->if_flags & IFF_DEBUG) {
686 printf(" transmit chain:\n");
687 for (seg = sc->sc_nexttx;; seg = SQ_NEXTTX(seg)) {
688 printf(" descriptor %d:\n", seg);
689 printf(" hdd_bufptr: 0x%08x\n",
690 (sc->hpc_regs->revision == 3) ?
691 sc->sc_txdesc[seg].hpc3_hdd_bufptr :
692 sc->sc_txdesc[seg].hpc1_hdd_bufptr);
693 printf(" hdd_ctl: 0x%08x\n",
694 (sc->hpc_regs->revision == 3) ?
695 sc->sc_txdesc[seg].hpc3_hdd_ctl:
696 sc->sc_txdesc[seg].hpc1_hdd_ctl);
697 printf(" hdd_descptr: 0x%08x\n",
698 sc->sc_txdesc[seg].hdd_descptr);
699
700 if (seg == lasttx)
701 break;
702 }
703 }
704
705 /* Sync the descriptors we're using. */
706 SQ_CDTXSYNC(sc, sc->sc_nexttx, dmamap->dm_nsegs,
707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
708
709 /* Store a pointer to the packet so we can free it later */
710 sc->sc_txmbuf[sc->sc_nexttx] = m0;
711
712 /* Advance the tx pointer. */
713 sc->sc_nfreetx -= dmamap->dm_nsegs;
714 sc->sc_nexttx = nexttx;
715 }
716
717 if (sc->sc_nfreetx != ofree) {
718 SQ_DPRINTF(("%s: %d packets enqueued, first %d, INTR on %d\n",
719 device_xname(sc->sc_dev), lasttx - firsttx + 1,
720 firsttx, lasttx));
721
722 /*
723 * Cause a transmit interrupt to happen on the
724 * last packet we enqueued, mark it as the last
725 * descriptor.
726 *
727 * HPC1_HDD_CTL_INTR will generate an interrupt on
728 * HPC1. HPC3 requires HPC3_HDD_CTL_EOPACKET in
729 * addition to HPC3_HDD_CTL_INTR to interrupt.
730 */
731 KASSERT(lasttx != -1);
732 if (sc->hpc_regs->revision == 3) {
733 sc->sc_txdesc[lasttx].hpc3_hdd_ctl |=
734 HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOCHAIN;
735 } else {
736 sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= HPC1_HDD_CTL_INTR;
737 sc->sc_txdesc[lasttx].hpc1_hdd_bufptr |=
738 HPC1_HDD_CTL_EOCHAIN;
739 }
740
741 SQ_CDTXSYNC(sc, lasttx, 1,
742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
743
744 /*
745 * There is a potential race condition here if the HPC
746 * DMA channel is active and we try and either update
747 * the 'next descriptor' pointer in the HPC PIO space
748 * or the 'next descriptor' pointer in a previous desc-
749 * riptor.
750 *
751 * To avoid this, if the channel is active, we rely on
752 * the transmit interrupt routine noticing that there
753 * are more packets to send and restarting the HPC DMA
754 * engine, rather than mucking with the DMA state here.
755 */
756 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl);
757
758 if ((status & sc->hpc_regs->enetx_ctl_active) != 0) {
759 SQ_TRACE(SQ_ADD_TO_DMA, sc, firsttx, status);
760
761 /*
762 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and
763 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN
764 */
765 sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc3_hdd_ctl &=
766 ~HPC3_HDD_CTL_EOCHAIN;
767
768 if (sc->hpc_regs->revision != 3)
769 sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc1_hdd_ctl
770 &= ~HPC1_HDD_CTL_INTR;
771
772 SQ_CDTXSYNC(sc, SQ_PREVTX(firsttx), 1,
773 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
774 } else if (sc->hpc_regs->revision == 3) {
775 SQ_TRACE(SQ_START_DMA, sc, firsttx, status);
776
777 sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc,
778 firsttx));
779
780 /* Kick DMA channel into life */
781 sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE);
782 } else {
783 /*
784 * In the HPC1 case where transmit DMA is
785 * inactive, we can either kick off if
786 * the ring was previously empty, or call
787 * our transmit interrupt handler to
788 * figure out if the ring stopped short
789 * and restart at the right place.
790 */
791 if (ofree == SQ_NTXDESC) {
792 SQ_TRACE(SQ_START_DMA, sc, firsttx, status);
793
794 sq_hpc_write(sc, HPC1_ENETX_NDBP,
795 SQ_CDTXADDR(sc, firsttx));
796 sq_hpc_write(sc, HPC1_ENETX_CFXBP,
797 SQ_CDTXADDR(sc, firsttx));
798 sq_hpc_write(sc, HPC1_ENETX_CBP,
799 SQ_CDTXADDR(sc, firsttx));
800
801 /* Kick DMA channel into life */
802 sq_hpc_write(sc, HPC1_ENETX_CTL,
803 HPC1_ENETX_CTL_ACTIVE);
804 } else
805 sq_txring_hpc1(sc);
806 }
807
808 /* Set a watchdog timer in case the chip flakes out. */
809 ifp->if_timer = 5;
810 }
811 }
812
813 void
sq_stop(struct ifnet * ifp,int disable)814 sq_stop(struct ifnet *ifp, int disable)
815 {
816 int i;
817 struct sq_softc *sc = ifp->if_softc;
818
819 for (i = 0; i < SQ_NTXDESC; i++) {
820 if (sc->sc_txmbuf[i] != NULL) {
821 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]);
822 m_freem(sc->sc_txmbuf[i]);
823 sc->sc_txmbuf[i] = NULL;
824 }
825 }
826
827 /* Clear Seeq transmit/receive command registers */
828 sq_seeq_write(sc, SEEQ_TXCMD, 0);
829 sq_seeq_write(sc, SEEQ_RXCMD, 0);
830
831 sq_reset(sc);
832
833 ifp->if_flags &= ~IFF_RUNNING;
834 ifp->if_timer = 0;
835 }
836
837 /* Device timeout/watchdog routine. */
838 void
sq_watchdog(struct ifnet * ifp)839 sq_watchdog(struct ifnet *ifp)
840 {
841 uint32_t status;
842 struct sq_softc *sc = ifp->if_softc;
843
844 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl);
845 log(LOG_ERR, "%s: device timeout (prev %d, next %d, free %d, "
846 "status %08x)\n", device_xname(sc->sc_dev), sc->sc_prevtx,
847 sc->sc_nexttx, sc->sc_nfreetx, status);
848
849 sq_trace_dump(sc);
850
851 memset(&sc->sq_trace, 0, sizeof(sc->sq_trace));
852 sc->sq_trace_idx = 0;
853
854 if_statinc(ifp, if_oerrors);
855
856 sq_init(ifp);
857 }
858
859 static void
sq_trace_dump(struct sq_softc * sc)860 sq_trace_dump(struct sq_softc *sc)
861 {
862 int i;
863 const char *act;
864
865 for (i = 0; i < sc->sq_trace_idx; i++) {
866 switch (sc->sq_trace[i].action) {
867 case SQ_RESET: act = "SQ_RESET"; break;
868 case SQ_ADD_TO_DMA: act = "SQ_ADD_TO_DMA"; break;
869 case SQ_START_DMA: act = "SQ_START_DMA"; break;
870 case SQ_DONE_DMA: act = "SQ_DONE_DMA"; break;
871 case SQ_RESTART_DMA: act = "SQ_RESTART_DMA"; break;
872 case SQ_TXINTR_ENTER: act = "SQ_TXINTR_ENTER"; break;
873 case SQ_TXINTR_EXIT: act = "SQ_TXINTR_EXIT"; break;
874 case SQ_TXINTR_BUSY: act = "SQ_TXINTR_BUSY"; break;
875 case SQ_IOCTL: act = "SQ_IOCTL"; break;
876 case SQ_ENQUEUE: act = "SQ_ENQUEUE"; break;
877 default: act = "UNKNOWN";
878 }
879
880 printf("%s: [%03d] action %-16s buf %03d free %03d "
881 "status %08x line %d\n", device_xname(sc->sc_dev), i, act,
882 sc->sq_trace[i].bufno, sc->sq_trace[i].freebuf,
883 sc->sq_trace[i].status, sc->sq_trace[i].line);
884 }
885 }
886
887 static int
sq_intr(void * arg)888 sq_intr(void *arg)
889 {
890 struct sq_softc *sc = arg;
891 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
892 int handled = 0;
893 uint32_t stat;
894
895 stat = sq_hpc_read(sc, sc->hpc_regs->enetr_reset);
896
897 if ((stat & 2) == 0) {
898 SQ_DPRINTF(("%s: Unexpected interrupt!\n",
899 device_xname(sc->sc_dev)));
900 } else
901 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, (stat | 2));
902
903 /*
904 * If the interface isn't running, the interrupt couldn't
905 * possibly have come from us.
906 */
907 if ((ifp->if_flags & IFF_RUNNING) == 0)
908 return 0;
909
910 sc->sq_intrcnt.ev_count++;
911
912 /* Always check for received packets */
913 if (sq_rxintr(sc) != 0)
914 handled++;
915
916 /* Only handle transmit interrupts if we actually sent something */
917 if (sc->sc_nfreetx < SQ_NTXDESC) {
918 sq_txintr(sc);
919 handled++;
920 }
921
922 if (handled)
923 rnd_add_uint32(&sc->rnd_source, stat);
924 return handled;
925 }
926
927 static int
sq_rxintr(struct sq_softc * sc)928 sq_rxintr(struct sq_softc *sc)
929 {
930 int count = 0;
931 struct mbuf* m;
932 int i, framelen;
933 uint8_t pktstat;
934 uint32_t status;
935 uint32_t ctl_reg;
936 int new_end, orig_end;
937 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
938
939 for (i = sc->sc_nextrx;; i = SQ_NEXTRX(i)) {
940 SQ_CDRXSYNC(sc, i,
941 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
942
943 /*
944 * If this is a CPU-owned buffer, we're at the end of the list.
945 */
946 if (sc->hpc_regs->revision == 3)
947 ctl_reg =
948 sc->sc_rxdesc[i].hpc3_hdd_ctl & HPC3_HDD_CTL_OWN;
949 else
950 ctl_reg =
951 sc->sc_rxdesc[i].hpc1_hdd_ctl & HPC1_HDD_CTL_OWN;
952
953 if (ctl_reg) {
954 #if defined(SQ_DEBUG)
955 uint32_t reg;
956
957 reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);
958 SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n",
959 device_xname(sc->sc_dev), i, reg));
960 #endif
961 break;
962 }
963
964 count++;
965
966 m = sc->sc_rxmbuf[i];
967 framelen = m->m_ext.ext_size - 3;
968 if (sc->hpc_regs->revision == 3)
969 framelen -=
970 HPC3_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl);
971 else
972 framelen -=
973 HPC1_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc1_hdd_ctl);
974
975 /* Now sync the actual packet data */
976 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
977 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_POSTREAD);
978
979 pktstat = *((uint8_t *)m->m_data + framelen + 2);
980
981 if ((pktstat & RXSTAT_GOOD) == 0) {
982 if_statinc(ifp, if_ierrors);
983
984 if (pktstat & RXSTAT_OFLOW)
985 printf("%s: receive FIFO overflow\n",
986 device_xname(sc->sc_dev));
987
988 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
989 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD);
990 SQ_INIT_RXDESC(sc, i);
991 SQ_DPRINTF(("%s: sq_rxintr: buf %d no RXSTAT_GOOD\n",
992 device_xname(sc->sc_dev), i));
993 continue;
994 }
995
996 if (sq_add_rxbuf(sc, i) != 0) {
997 if_statinc(ifp, if_ierrors);
998 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0,
999 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD);
1000 SQ_INIT_RXDESC(sc, i);
1001 SQ_DPRINTF(("%s: sq_rxintr: buf %d sq_add_rxbuf() "
1002 "failed\n", device_xname(sc->sc_dev), i));
1003 continue;
1004 }
1005
1006
1007 m->m_data += 2;
1008 m_set_rcvif(m, ifp);
1009 m->m_pkthdr.len = m->m_len = framelen;
1010
1011 SQ_DPRINTF(("%s: sq_rxintr: buf %d len %d\n",
1012 device_xname(sc->sc_dev), i, framelen));
1013
1014 if_percpuq_enqueue(ifp->if_percpuq, m);
1015 }
1016
1017
1018 /* If anything happened, move ring start/end pointers to new spot */
1019 if (i != sc->sc_nextrx) {
1020 /*
1021 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and
1022 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN
1023 */
1024
1025 new_end = SQ_PREVRX(i);
1026 sc->sc_rxdesc[new_end].hpc3_hdd_ctl |= HPC3_HDD_CTL_EOCHAIN;
1027 SQ_CDRXSYNC(sc, new_end,
1028 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1029
1030 orig_end = SQ_PREVRX(sc->sc_nextrx);
1031 sc->sc_rxdesc[orig_end].hpc3_hdd_ctl &= ~HPC3_HDD_CTL_EOCHAIN;
1032 SQ_CDRXSYNC(sc, orig_end,
1033 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1034
1035 sc->sc_nextrx = i;
1036 }
1037
1038 status = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl);
1039
1040 /* If receive channel is stopped, restart it... */
1041 if ((status & sc->hpc_regs->enetr_ctl_active) == 0) {
1042 /* Pass the start of the receive ring to the HPC */
1043 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp,
1044 SQ_CDRXADDR(sc, sc->sc_nextrx));
1045
1046 /* And turn on the HPC ethernet receive channel */
1047 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
1048 sc->hpc_regs->enetr_ctl_active);
1049 }
1050
1051 return count;
1052 }
1053
1054 static int
sq_txintr(struct sq_softc * sc)1055 sq_txintr(struct sq_softc *sc)
1056 {
1057 int shift = 0;
1058 uint32_t status, tmp;
1059 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1060
1061 if (sc->hpc_regs->revision != 3)
1062 shift = 16;
1063
1064 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl) >> shift;
1065
1066 SQ_TRACE(SQ_TXINTR_ENTER, sc, sc->sc_prevtx, status);
1067
1068 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1069 tmp = (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD;
1070 if ((status & tmp) == 0) {
1071 if (status & TXSTAT_COLL)
1072 if_statinc_ref(ifp, nsr, if_collisions);
1073
1074 if (status & TXSTAT_UFLOW) {
1075 printf("%s: transmit underflow\n",
1076 device_xname(sc->sc_dev));
1077 if_statinc_ref(ifp, nsr, if_oerrors);
1078 }
1079
1080 if (status & TXSTAT_16COLL) {
1081 printf("%s: max collisions reached\n",
1082 device_xname(sc->sc_dev));
1083 if_statinc_ref(ifp, nsr, if_oerrors);
1084 if_statadd_ref(ifp, nsr, if_collisions, 16);
1085 }
1086 }
1087 IF_STAT_PUTREF(ifp);
1088
1089 /* prevtx now points to next xmit packet not yet finished */
1090 if (sc->hpc_regs->revision == 3)
1091 sq_txring_hpc3(sc);
1092 else
1093 sq_txring_hpc1(sc);
1094
1095 /* If all packets have left the coop, cancel watchdog */
1096 if (sc->sc_nfreetx == SQ_NTXDESC)
1097 ifp->if_timer = 0;
1098
1099 SQ_TRACE(SQ_TXINTR_EXIT, sc, sc->sc_prevtx, status);
1100 if_schedule_deferred_start(ifp);
1101
1102 return 1;
1103 }
1104
1105 /*
1106 * Reclaim used transmit descriptors and restart the transmit DMA
1107 * engine if necessary.
1108 */
1109 static void
sq_txring_hpc1(struct sq_softc * sc)1110 sq_txring_hpc1(struct sq_softc *sc)
1111 {
1112 /*
1113 * HPC1 doesn't tag transmitted descriptors, however,
1114 * the NDBP register points to the next descriptor that
1115 * has not yet been processed. If DMA is not in progress,
1116 * we can safely reclaim all descriptors up to NDBP, and,
1117 * if necessary, restart DMA at NDBP. Otherwise, if DMA
1118 * is active, we can only safely reclaim up to CBP.
1119 *
1120 * For now, we'll only reclaim on inactive DMA and assume
1121 * that a sufficiently large ring keeps us out of trouble.
1122 */
1123 uint32_t reclaimto, status;
1124 int reclaimall, i = sc->sc_prevtx;
1125 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1126
1127 status = sq_hpc_read(sc, HPC1_ENETX_CTL);
1128 if (status & HPC1_ENETX_CTL_ACTIVE) {
1129 SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status);
1130 return;
1131 } else
1132 reclaimto = sq_hpc_read(sc, HPC1_ENETX_NDBP);
1133
1134 if (sc->sc_nfreetx == 0 && SQ_CDTXADDR(sc, i) == reclaimto)
1135 reclaimall = 1;
1136 else
1137 reclaimall = 0;
1138
1139 while (sc->sc_nfreetx < SQ_NTXDESC) {
1140 if (SQ_CDTXADDR(sc, i) == reclaimto && !reclaimall)
1141 break;
1142
1143 SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs,
1144 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1145
1146 /* Sync the packet data, unload DMA map, free mbuf */
1147 bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i],
1148 0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1149 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]);
1150 m_freem(sc->sc_txmbuf[i]);
1151 sc->sc_txmbuf[i] = NULL;
1152
1153 if_statinc(ifp, if_opackets);
1154 sc->sc_nfreetx++;
1155
1156 SQ_TRACE(SQ_DONE_DMA, sc, i, status);
1157
1158 i = SQ_NEXTTX(i);
1159 }
1160
1161 if (sc->sc_nfreetx < SQ_NTXDESC) {
1162 SQ_TRACE(SQ_RESTART_DMA, sc, i, status);
1163
1164 KASSERT(reclaimto == SQ_CDTXADDR(sc, i));
1165
1166 sq_hpc_write(sc, HPC1_ENETX_CFXBP, reclaimto);
1167 sq_hpc_write(sc, HPC1_ENETX_CBP, reclaimto);
1168
1169 /* Kick DMA channel into life */
1170 sq_hpc_write(sc, HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE);
1171
1172 /*
1173 * Set a watchdog timer in case the chip
1174 * flakes out.
1175 */
1176 ifp->if_timer = 5;
1177 }
1178
1179 sc->sc_prevtx = i;
1180 }
1181
1182 /*
1183 * Reclaim used transmit descriptors and restart the transmit DMA
1184 * engine if necessary.
1185 */
1186 static void
sq_txring_hpc3(struct sq_softc * sc)1187 sq_txring_hpc3(struct sq_softc *sc)
1188 {
1189 /*
1190 * HPC3 tags descriptors with a bit once they've been
1191 * transmitted. We need only free each XMITDONE'd
1192 * descriptor, and restart the DMA engine if any
1193 * descriptors are left over.
1194 */
1195 int i;
1196 uint32_t status = 0;
1197 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1198
1199 i = sc->sc_prevtx;
1200 while (sc->sc_nfreetx < SQ_NTXDESC) {
1201 /*
1202 * Check status first so we don't end up with a case of
1203 * the buffer not being finished while the DMA channel
1204 * has gone idle.
1205 */
1206 status = sq_hpc_read(sc, HPC3_ENETX_CTL);
1207
1208 SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs,
1209 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1210
1211 /* Check for used descriptor and restart DMA chain if needed */
1212 if ((sc->sc_txdesc[i].hpc3_hdd_ctl &
1213 HPC3_HDD_CTL_XMITDONE) == 0) {
1214 if ((status & HPC3_ENETX_CTL_ACTIVE) == 0) {
1215 SQ_TRACE(SQ_RESTART_DMA, sc, i, status);
1216
1217 sq_hpc_write(sc, HPC3_ENETX_NDBP,
1218 SQ_CDTXADDR(sc, i));
1219
1220 /* Kick DMA channel into life */
1221 sq_hpc_write(sc, HPC3_ENETX_CTL,
1222 HPC3_ENETX_CTL_ACTIVE);
1223
1224 /*
1225 * Set a watchdog timer in case the chip
1226 * flakes out.
1227 */
1228 ifp->if_timer = 5;
1229 } else
1230 SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status);
1231 break;
1232 }
1233
1234 /* Sync the packet data, unload DMA map, free mbuf */
1235 bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i],
1236 0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1237 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]);
1238 m_freem(sc->sc_txmbuf[i]);
1239 sc->sc_txmbuf[i] = NULL;
1240
1241 if_statinc(ifp, if_opackets);
1242 sc->sc_nfreetx++;
1243
1244 SQ_TRACE(SQ_DONE_DMA, sc, i, status);
1245 i = SQ_NEXTTX(i);
1246 }
1247
1248 sc->sc_prevtx = i;
1249 }
1250
1251 void
sq_reset(struct sq_softc * sc)1252 sq_reset(struct sq_softc *sc)
1253 {
1254
1255 /* Stop HPC dma channels */
1256 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 0);
1257 sq_hpc_write(sc, sc->hpc_regs->enetx_ctl, 0);
1258
1259 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 3);
1260 delay(20);
1261 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 0);
1262 }
1263
1264 /* sq_add_rxbuf: Add a receive buffer to the indicated descriptor. */
1265 int
sq_add_rxbuf(struct sq_softc * sc,int idx)1266 sq_add_rxbuf(struct sq_softc *sc, int idx)
1267 {
1268 int err;
1269 struct mbuf *m;
1270
1271 MGETHDR(m, M_DONTWAIT, MT_DATA);
1272 if (m == NULL)
1273 return ENOBUFS;
1274
1275 MCLGET(m, M_DONTWAIT);
1276 if ((m->m_flags & M_EXT) == 0) {
1277 m_freem(m);
1278 return ENOBUFS;
1279 }
1280
1281 if (sc->sc_rxmbuf[idx] != NULL)
1282 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[idx]);
1283
1284 sc->sc_rxmbuf[idx] = m;
1285
1286 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap[idx],
1287 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) {
1288 printf("%s: can't load rx DMA map %d, error = %d\n",
1289 device_xname(sc->sc_dev), idx, err);
1290 panic("sq_add_rxbuf"); /* XXX */
1291 }
1292
1293 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[idx],
1294 0, sc->sc_rxmap[idx]->dm_mapsize, BUS_DMASYNC_PREREAD);
1295
1296 SQ_INIT_RXDESC(sc, idx);
1297
1298 return 0;
1299 }
1300
1301 void
sq_dump_buffer(paddr_t addr,psize_t len)1302 sq_dump_buffer(paddr_t addr, psize_t len)
1303 {
1304 u_int i;
1305 uint8_t *physaddr = (uint8_t *)MIPS_PHYS_TO_KSEG1(addr);
1306
1307 if (len == 0)
1308 return;
1309
1310 printf("%p: ", physaddr);
1311
1312 for (i = 0; i < len; i++) {
1313 printf("%02x ", *(physaddr + i) & 0xff);
1314 if ((i % 16) == 15 && i != len - 1)
1315 printf("\n%p: ", physaddr + i);
1316 }
1317
1318 printf("\n");
1319 }
1320