1 /* $NetBSD: mb8795reg.h,v 1.5 2023/06/10 17:14:57 dbj Exp $ */ 2 /* 3 * Copyright (c) 1998 Darrin B. Jewell 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Fujitsu Ethernet Data Link Controller (MB8795) 29 * and the Fujitsu Manchester Encoder/Decoder (MB502). 30 */ 31 32 #if 0 33 struct mb8795_regs { 34 unsigned char mb8795_txstat; /* tx status */ 35 unsigned char mb8795_txmask; /* tx interrupt condition mask */ 36 unsigned char mb8795_rxstat; /* rx status */ 37 unsigned char mb8795_rxmask; /* rx interrupt condition mask */ 38 unsigned char mb8795_txmode; /* tx control/mode register */ 39 unsigned char mb8795_rxmode; /* rx control/mode register */ 40 unsigned char mb8795_reset; /* reset mode */ 41 unsigned char mb8795_tdc_lsb; /* transmit data count LSB */ 42 unsigned char mb8795_addr[6]; /* physical address */ 43 unsigned char mb8795_reserved; 44 unsigned char mb8795_tdc_msb; /* transmit data count MSB */ 45 }; 46 #endif 47 48 /* transmitter status (address 0) */ 49 #define MB8795_TXSTAT 0 50 51 #define MB8795_TXSTAT_READY 0x80 /* ready for packet */ 52 #define MB8795_TXSTAT_BUSY 0x40 /* receive carrier detect */ 53 #define MB8795_TXSTAT_TXRECV 0x20 /* transmission received */ 54 #define MB8795_TXSTAT_SHORTED 0x10 /* possible coax short */ 55 #define MB8795_TXSTAT_UNDERFLOW 0x08 /* underflow on xmit */ 56 #define MB8795_TXSTAT_COLLERR 0x04 /* collision detected */ 57 #define MB8795_TXSTAT_COLLERR16 0x02 /* 16th collision error */ 58 #define MB8795_TXSTAT_PARERR 0x01 /* parity error in tx data */ 59 #define MB8795_TXSTAT_CLEAR 0xff /* clear all status bits */ 60 61 #define MB8795_TXSTAT_BITS \ 62 "\20\10READY\07BUSY\06TXRECV\05SHORTED\ 63 \04UNDERFLOW\03COLLERR\02COLLERR16\01PARERR" 64 65 /* transmit masks (address 1) */ 66 #define MB8795_TXMASK 1 67 68 #define MB8795_TXMASK_READYIE 0x80 /* tx int on packet ready */ 69 #define MB8795_TXMASK_TXRXIE 0x20 /* tx int on transmit rec'd */ 70 #define MB8795_TXMASK_UNDERFLOWIE 0x08 /* tx int on underflow */ 71 #define MB8795_TXMASK_COLLIE 0x04 /* tx int on collision */ 72 #define MB8795_TXMASK_COLL16IE 0x02 /* tx int on 16th collision */ 73 #define MB8795_TXMASK_PARERRIE 0x01 /* tx int on parity error */ 74 75 #define MB8795_TXMASK_BITS \ 76 "\20\10READYIE\06TXRXIE\04UNDERFLOWIE\03COLLIE\02COLL16IE\01PARERRIE" 77 78 /* cumulative receiver status (address 2) */ 79 #define MB8795_RXSTAT 2 80 81 #define MB8795_RXSTAT_OK 0x80 /* packet received is correct */ 82 #define MB8795_RXSTAT_RESET 0x10 /* reset packet received */ 83 #define MB8795_RXSTAT_SHORT 0x08 /* < minimum length */ 84 #define MB8795_RXSTAT_ALIGNERR 0x04 /* alignment error */ 85 #define MB8795_RXSTAT_CRCERR 0x02 /* CRC error */ 86 #define MB8795_RXSTAT_OVERFLOW 0x01 /* receiver FIFO overflow */ 87 #define MB8795_RXSTAT_CLEAR 0xff /* clear all status bits */ 88 89 #define MB8795_RXSTAT_BITS \ 90 "\20\10OK\05RESET\04SHORT\03ALIGNERR\02CRCERR\01OVERFLOW" 91 92 /* receiver masks (address 3) */ 93 #define MB8795_RXMASK 3 94 95 #define MB8795_RXMASK_OKIE 0x80 /* rx int on packet ok */ 96 #define MB8795_RXMASK_RESETIE 0x10 /* rx int on reset packet */ 97 #define MB8795_RXMASK_SHORTIE 0x08 /* rx int on short packet */ 98 #define MB8795_RXMASK_ALIGNERRIE 0x04 /* rx int on align error */ 99 #define MB8795_RXMASK_CRCERRIE 0x02 /* rx int on CRC error */ 100 #define MB8795_RXMASK_OVERFLOWIE 0x01 /* rx int on overflow error */ 101 102 #define MB8795_RXMASK_BITS \ 103 "\20\10OKIE\05RESETIE\04SHORTIE\03ALIGNERRIE\02CRCERRIE\01OVERFLOWIE" 104 105 /* transmitter mode (address 4) */ 106 #define MB8795_TXMODE 4 107 108 #define MB8795_TXMODE_COLLMASK 0xF0 /* collision count */ 109 #define MB8795_TXMODE_TURBOSTART 0x80 110 #define MB8795_TXMODE_PARIGNORE 0x08 /* ignore parity */ 111 #define MB8795_TXMODE_TURBO1 0x04 112 #define MB8795_TXMODE_LB_DISABLE 0x02 /* loop back disabled */ 113 #define MB8795_TXMODE_DISCONTENT 0x01 /* disable contention (rx carrier) */ 114 115 /* Should probably figure out how to put in the COLLMASK value in here */ 116 #define MB8795_TXMODE_BITS \ 117 "\20\04PARIGNORE\02LB_DISABLE\01DISCONTENT" 118 119 /* receiver mode (address 5) */ 120 #define MB8795_RXMODE 5 121 122 #define MB8795_RXMODE_TEST 0x80 /* Must be zero for normal op */ 123 #define MB8795_RXMODE_ADDRSIZE 0x10 /* reduces NODE match to 5 chars */ 124 #define MB8795_RXMODE_SHORTENABLE 0x08 /* rx packets >= 10 bytes */ 125 #define MB8795_RXMODE_RESETENABLE 0x04 /* must be zero */ 126 #define MB8795_RXMODE_PROMISCUOUS 0x03 /* accept all packets */ 127 #define MB8795_RXMODE_MULTICAST 0x02 /* accept broad/multicasts */ 128 #define MB8795_RXMODE_NORMAL 0x01 /* accept broad/limited multicasts */ 129 #define MB8795_RXMODE_OFF 0x00 /* accept no packets */ 130 131 /* this define is less useful for the promiscuous bits, bit I leave it here */ 132 #define MB8795_RXMODE_BITS \ 133 "\20\10TEST\05ADDRSIZE\04SHORTENABLE\03RESETENABLE\02MULTICAST\01NORMAL" 134 135 /* reset mode (address 6) */ 136 #define MB8795_RESET_MODE 0x80 /* reset mode */ 137 #define MB8795_RESET 6 138 139 #define MB8795_TDC_LSB 7 140 #define MB8795_ENADDR 8 141 #define MB8795_TDC_MSB 15 142 143 #define ENRX_EOP 0x80000000 /* end-of-packet flag */ 144 #define ENRX_BOP 0x40000000 /* beginning-of-packet flag */ 145 #define ENTX_EOP 0x80000000 /* end-of-packet flag */ 146