1.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.\" $FreeBSD$ 25.\" 26.Dd October 4, 2008 27.Dt PMC.P6 3 28.Os 29.Sh NAME 30.Nm pmc.p6 31.Nd measurement events for 32.Tn Intel 33Pentium Pro, P-II, P-III family CPUs 34.Sh LIBRARY 35.Lb libpmc 36.Sh SYNOPSIS 37.In pmc.h 38.Sh DESCRIPTION 39Intel P6 PMCs are present in Intel 40.Tn "Pentium Pro" , 41.Tn "Pentium II" , 42.Tn Celeron , 43.Tn "Pentium III" 44and 45.Tn "Pentium M" 46processors. 47.Pp 48They are documented in 49.Rs 50.%B "IA-32 Intel(R) Architecture Software Developer's Manual" 51.%T "Volume 3: System Programming Guide" 52.%N "Order Number 245472-012" 53.%D 2003 54.%Q "Intel Corporation" 55.Re 56.Pp 57Some of these events are affected by processor errata described in 58.Rs 59.%B "Intel(R) Pentium(R) III Processor Specification Update" 60.%N "Document Number: 244453-054" 61.%D "April 2005" 62.%Q "Intel Corporation" 63.Re 64.Ss PMC Features 65These CPUs have two counters, each 40 bits wide. 66Some events may only be used on specific counters and some events are 67defined only on specific processor models. 68These PMCs support the following capabilities: 69.Bl -column "PMC_CAP_INTERRUPT" "Support" 70.It Em Capability Ta Em Support 71.It PMC_CAP_CASCADE Ta \&No 72.It PMC_CAP_EDGE Ta Yes 73.It PMC_CAP_INTERRUPT Ta Yes 74.It PMC_CAP_INVERT Ta Yes 75.It PMC_CAP_READ Ta Yes 76.It PMC_CAP_PRECISE Ta \&No 77.It PMC_CAP_SYSTEM Ta Yes 78.It PMC_CAP_TAGGING Ta \&No 79.It PMC_CAP_THRESHOLD Ta Yes 80.It PMC_CAP_USER Ta Yes 81.It PMC_CAP_WRITE Ta Yes 82.El 83.Ss Event Qualifiers 84Event specifiers for Intel P6 PMCs can have the following common 85qualifiers: 86.Bl -tag -width indent 87.It Li cmask= Ns Ar value 88Configure the PMC to increment only if the number of configured 89events measured in a cycle is greater than or equal to 90.Ar value . 91.It Li edge 92Configure the PMC to count the number of de-asserted to asserted 93transitions of the conditions expressed by the other qualifiers. 94If specified, the counter will increment only once whenever a 95condition becomes true, irrespective of the number of clocks during 96which the condition remains true. 97.It Li inv 98Invert the sense of comparison when the 99.Dq Li cmask 100qualifier is present, making the counter increment when the number of 101events per cycle is less than the value specified by the 102.Dq Li cmask 103qualifier. 104.It Li os 105Configure the PMC to count events happening at processor privilege 106level 0. 107.It Li umask= Ns Ar value 108This qualifier is used to further qualify the event selected (see 109below). 110.It Li usr 111Configure the PMC to count events occurring at privilege levels 1, 2 112or 3. 113.El 114.Pp 115If neither of the 116.Dq Li os 117or 118.Dq Li usr 119qualifiers are specified, the default is to enable both. 120.Pp 121The event specifiers supported by Intel P6 PMCs are: 122.Bl -tag -width indent 123.It Li p6-baclears 124.Pq Event E6H 125Count the number of times a static branch prediction was made by the 126branch decoder because the BTB did not have a prediction. 127.It Li p6-br-bac-missp-exec 128.Pq Event 8AH , Tn "Pentium M" 129Count the number of branch instructions executed that where 130mispredicted at the Front End (BAC). 131.It Li p6-br-bogus 132.Pq Event E4H 133Count the number of bogus branches. 134.It Li p6-br-call-exec 135.Pq Event 92H , Tn "Pentium M" 136Count the number of call instructions executed. 137.It Li p6-br-call-missp-exec 138.Pq Event 93H , Tn "Pentium M" 139Count the number of call instructions executed that were mispredicted. 140.It Li p6-br-cnd-exec 141.Pq Event 8BH , Tn "Pentium M" 142Count the number of conditional branch instructions executed. 143.It Li p6-br-cnd-missp-exec 144.Pq Event 8CH , Tn "Pentium M" 145Count the number of conditional branch instructions executed that were 146mispredicted. 147.It Li p6-br-ind-call-exec 148.Pq Event 94H , Tn "Pentium M" 149Count the number of indirect call instructions executed. 150.It Li p6-br-ind-exec 151.Pq Event 8DH , Tn "Pentium M" 152Count the number of indirect branch instructions executed. 153.It Li p6-br-ind-missp-exec 154.Pq Event 8EH , Tn "Pentium M" 155Count the number of indirect branch instructions executed that were 156mispredicted. 157.It Li p6-br-inst-decoded 158.Pq Event E0H 159Count the number of branch instructions decoded. 160.It Li p6-br-inst-exec 161.Pq Event 88H , Tn "Pentium M" 162Count the number of branch instructions executed but necessarily retired. 163.It Li p6-br-inst-retired 164.Pq Event C4H 165Count the number of branch instructions retired. 166.It Li p6-br-miss-pred-retired 167.Pq Event C5H 168Count the number of mispredicted branch instructions retired. 169.It Li p6-br-miss-pred-taken-ret 170.Pq Event C9H 171Count the number of taken mispredicted branches retired. 172.It Li p6-br-missp-exec 173.Pq Event 89H , Tn "Pentium M" 174Count the number of branch instructions executed that were 175mispredicted at execution. 176.It Li p6-br-ret-bac-missp-exec 177.Pq Event 91H , Tn "Pentium M" 178Count the number of return instructions executed that were 179mispredicted at the Front End (BAC). 180.It Li p6-br-ret-exec 181.Pq Event 8FH , Tn "Pentium M" 182Count the number of return instructions executed. 183.It Li p6-br-ret-missp-exec 184.Pq Event 90H , Tn "Pentium M" 185Count the number of return instructions executed that were 186mispredicted at execution. 187.It Li p6-br-taken-retired 188.Pq Event C9H 189Count the number of taken branches retired. 190.It Li p6-btb-misses 191.Pq Event E2H 192Count the number of branches for which the BTB did not produce a 193prediction. 194.It Li p6-bus-bnr-drv 195.Pq Event 61H 196Count the number of bus clock cycles during which this processor is 197driving the BNR# pin. 198.It Li p6-bus-data-rcv 199.Pq Event 64H 200Count the number of bus clock cycles during which this processor is 201receiving data. 202.It Li p6-bus-drdy-clocks Op Li ,umask= Ns Ar qualifier 203.Pq Event 62H 204Count the number of clocks during which DRDY# is asserted. 205An additional qualifier may be specified, and comprises one of the 206following keywords: 207.Pp 208.Bl -tag -width indent -compact 209.It Li any 210Count transactions generated by any agent on the bus. 211.It Li self 212Count transactions generated by this processor. 213.El 214.Pp 215The default is to count operations generated by this processor. 216.It Li p6-bus-hit-drv 217.Pq Event 7AH 218Count the number of bus clock cycles during which this processor is 219driving the HIT# pin. 220.It Li p6-bus-hitm-drv 221.Pq Event 7BH 222Count the number of bus clock cycles during which this processor is 223driving the HITM# pin. 224.It Li p6-bus-lock-clocks Op Li ,umask= Ns Ar qualifier 225.Pq Event 63H 226Count the number of clocks during with LOCK# is asserted on the 227external system bus. 228An additional qualifier may be specified and comprises one of the following 229keywords: 230.Pp 231.Bl -tag -width indent -compact 232.It Li any 233Count transactions generated by any agent on the bus. 234.It Li self 235Count transactions generated by this processor. 236.El 237.Pp 238The default is to count operations generated by this processor. 239.It Li p6-bus-req-outstanding 240.Pq Event 60H 241Count the number of bus requests outstanding in any given cycle. 242.It Li p6-bus-snoop-stall 243.Pq Event 7EH 244Count the number of clock cycles during which the bus is snoop stalled. 245.It Li p6-bus-tran-any Op Li ,umask= Ns Ar qualifier 246.Pq Event 70H 247Count the number of completed bus transactions of any kind. 248An additional qualifier may be specified and comprises one of the following 249keywords: 250.Pp 251.Bl -tag -width indent -compact 252.It Li any 253Count transactions generated by any agent on the bus. 254.It Li self 255Count transactions generated by this processor. 256.El 257.Pp 258The default is to count operations generated by this processor. 259.It Li p6-bus-tran-brd Op Li ,umask= Ns Ar qualifier 260.Pq Event 65H 261Count the number of burst read transactions. 262An additional qualifier may be specified and comprises one of the following 263keywords: 264.Pp 265.Bl -tag -width indent -compact 266.It Li any 267Count transactions generated by any agent on the bus. 268.It Li self 269Count transactions generated by this processor. 270.El 271.Pp 272The default is to count operations generated by this processor. 273.It Li p6-bus-tran-burst Op Li ,umask= Ns Ar qualifier 274.Pq Event 6EH 275Count the number of completed burst transactions. 276An additional qualifier may be specified and comprises one of the following 277keywords: 278.Pp 279.Bl -tag -width indent -compact 280.It Li any 281Count transactions generated by any agent on the bus. 282.It Li self 283Count transactions generated by this processor. 284.El 285.Pp 286The default is to count operations generated by this processor. 287.It Li p6-bus-tran-def Op Li ,umask= Ns Ar qualifier 288.Pq Event 6DH 289Count the number of completed deferred transactions. 290An additional qualifier may be specified and comprises one of the following 291keywords: 292.Pp 293.Bl -tag -width indent -compact 294.It Li any 295Count transactions generated by any agent on the bus. 296.It Li self 297Count transactions generated by this processor. 298.El 299.Pp 300The default is to count operations generated by this processor. 301.It Li p6-bus-tran-ifetch Op Li ,umask= Ns Ar qualifier 302.Pq Event 68H 303Count the number of completed instruction fetch transactions. 304An additional qualifier may be specified and comprises one of the following 305keywords: 306.Pp 307.Bl -tag -width indent -compact 308.It Li any 309Count transactions generated by any agent on the bus. 310.It Li self 311Count transactions generated by this processor. 312.El 313.Pp 314The default is to count operations generated by this processor. 315.It Li p6-bus-tran-inval Op Li ,umask= Ns Ar qualifier 316.Pq Event 69H 317Count the number of completed invalidate transactions. 318An additional qualifier may be specified and comprises one of the following 319keywords: 320.Pp 321.Bl -tag -width indent -compact 322.It Li any 323Count transactions generated by any agent on the bus. 324.It Li self 325Count transactions generated by this processor. 326.El 327.Pp 328The default is to count operations generated by this processor. 329.It Li p6-bus-tran-mem Op Li ,umask= Ns Ar qualifier 330.Pq Event 6FH 331Count the number of completed memory transactions. 332An additional qualifier may be specified and comprises one of the following 333keywords: 334.Pp 335.Bl -tag -width indent -compact 336.It Li any 337Count transactions generated by any agent on the bus. 338.It Li self 339Count transactions generated by this processor. 340.El 341.Pp 342The default is to count operations generated by this processor. 343.It Li p6-bus-tran-pwr Op Li ,umask= Ns Ar qualifier 344.Pq Event 6AH 345Count the number of completed partial write transactions. 346An additional qualifier may be specified and comprises one of the following 347keywords: 348.Pp 349.Bl -tag -width indent -compact 350.It Li any 351Count transactions generated by any agent on the bus. 352.It Li self 353Count transactions generated by this processor. 354.El 355.Pp 356The default is to count operations generated by this processor. 357.It Li p6-bus-tran-rfo Op Li ,umask= Ns Ar qualifier 358.Pq Event 66H 359Count the number of completed read-for-ownership transactions. 360An additional qualifier may be specified and comprises one of the following 361keywords: 362.Pp 363.Bl -tag -width indent -compact 364.It Li any 365Count transactions generated by any agent on the bus. 366.It Li self 367Count transactions generated by this processor. 368.El 369.Pp 370The default is to count operations generated by this processor. 371.It Li p6-bus-trans-io Op Li ,umask= Ns Ar qualifier 372.Pq Event 6CH 373Count the number of completed I/O transactions. 374An additional qualifier may be specified and comprises one of the following 375keywords: 376.Pp 377.Bl -tag -width indent -compact 378.It Li any 379Count transactions generated by any agent on the bus. 380.It Li self 381Count transactions generated by this processor. 382.El 383.Pp 384The default is to count operations generated by this processor. 385.It Li p6-bus-trans-p Op Li ,umask= Ns Ar qualifier 386.Pq Event 6BH 387Count the number of completed partial transactions. 388An additional qualifier may be specified and comprises one of the following 389keywords: 390.Pp 391.Bl -tag -width indent -compact 392.It Li any 393Count transactions generated by any agent on the bus. 394.It Li self 395Count transactions generated by this processor. 396.El 397.Pp 398The default is to count operations generated by this processor. 399.It Li p6-bus-trans-wb Op Li ,umask= Ns Ar qualifier 400.Pq Event 67H 401Count the number of completed write-back transactions. 402An additional qualifier may be specified and comprises one of the following 403keywords: 404.Pp 405.Bl -tag -width indent -compact 406.It Li any 407Count transactions generated by any agent on the bus. 408.It Li self 409Count transactions generated by this processor. 410.El 411.Pp 412The default is to count operations generated by this processor. 413.It Li p6-cpu-clk-unhalted 414.Pq Event 79H 415Count the number of cycles during with the processor was not halted. 416.Pp 417.Pq Tn "Pentium M" 418Count the number of cycles during with the processor was not halted 419and not in a thermal trip. 420.It Li p6-cycles-div-busy 421.Pq Event 14H 422Count the number of cycles during which the divider is busy and cannot 423accept new divides. 424This event is only allocated on counter 0. 425.It Li p6-cycles-int-pending-and-masked 426.Pq Event C7H 427Count the number of processor cycles for which interrupts were 428disabled and interrupts were pending. 429.It Li p6-cycles-int-masked 430.Pq Event C6H 431Count the number of processor cycles for which interrupts were 432disabled. 433.It Li p6-data-mem-refs 434.Pq Event 43H 435Count all loads and all stores using any memory type, including 436internal retries. 437Each part of a split store is counted separately. 438.It Li p6-dcu-lines-in 439.Pq Event 45H 440Count the total lines allocated in the data cache unit. 441.It Li p6-dcu-m-lines-in 442.Pq Event 46H 443Count the number of M state lines allocated in the data cache unit. 444.It Li p6-dcu-m-lines-out 445.Pq Event 47H 446Count the number of M state lines evicted from the data cache unit. 447.It Li p6-dcu-miss-outstanding 448.Pq Event 48H 449Count the weighted number of cycles while a data cache unit miss is 450outstanding, incremented by the number of outstanding cache misses at 451any time. 452.It Li p6-div 453.Pq Event 13H 454Count the number of integer and floating-point divides including 455speculative divides. 456This event is only allocated on counter 1. 457.It Li p6-emon-esp-uops 458.Pq Event D7H , Tn "Pentium M" 459Count the total number of micro-ops. 460.It Li p6-emon-est-trans Op Li ,umask= Ns Ar qualifier 461.Pq Event 58H , Tn "Pentium M" 462Count the number of 463.Tn "Enhanced Intel SpeedStep" 464transitions. 465An additional qualifier may be specified, and can be one of the 466following keywords: 467.Pp 468.Bl -tag -width indent -compact 469.It Li all 470Count all transitions. 471.It Li freq 472Count only frequency transitions. 473.El 474.Pp 475The default is to count all transitions. 476.It Li p6-emon-fused-uops-ret Op Li ,umask= Ns Ar qualifier 477.Pq Event DAH , Tn "Pentium M" 478Count the number of retired fused micro-ops. 479An additional qualifier may be specified, and may be one of the 480following keywords: 481.Pp 482.Bl -tag -width indent -compact 483.It Li all 484Count all fused micro-ops. 485.It Li loadop 486Count only load and op micro-ops. 487.It Li stdsta 488Count only STD/STA micro-ops. 489.El 490.Pp 491The default is to count all fused micro-ops. 492.It Li p6-emon-kni-comp-inst-ret 493.Pq Event D9H , Tn "Pentium III" 494Count the number of SSE computational instructions retired. 495An additional qualifier may be specified, and comprises one of the 496following keywords: 497.Pp 498.Bl -tag -width indent -compact 499.It Li packed-and-scalar 500Count packed and scalar operations. 501.It Li scalar 502Count scalar operations only. 503.El 504.Pp 505The default is to count packed and scalar operations. 506.It Li p6-emon-kni-inst-retired Op Li ,umask= Ns Ar qualifier 507.Pq Event D8H , Tn "Pentium III" 508Count the number of SSE instructions retired. 509An additional qualifier may be specified, and comprises one of the 510following keywords: 511.Pp 512.Bl -tag -width indent -compact 513.It Li packed-and-scalar 514Count packed and scalar operations. 515.It Li scalar 516Count scalar operations only. 517.El 518.Pp 519The default is to count packed and scalar operations. 520.It Li p6-emon-kni-pref-dispatched Op Li ,umask= Ns Ar qualifier 521.Pq Event 07H , Tn "Pentium III" 522Count the number of SSE prefetch or weakly ordered instructions 523dispatched (including speculative prefetches). 524An additional qualifier may be specified, and comprises one of the 525following keywords: 526.Pp 527.Bl -tag -width indent -compact 528.It Li nta 529Count non-temporal prefetches. 530.It Li t1 531Count prefetches to L1. 532.It Li t2 533Count prefetches to L2. 534.It Li wos 535Count weakly ordered stores. 536.El 537.Pp 538The default is to count non-temporal prefetches. 539.It Li p6-emon-kni-pref-miss Op Li ,umask= Ns Ar qualifier 540.Pq Event 4BH , Tn "Pentium III" 541Count the number of prefetch or weakly ordered instructions that miss 542all caches. 543An additional qualifier may be specified, and comprises one of the 544following keywords: 545.Pp 546.Bl -tag -width indent -compact 547.It Li nta 548Count non-temporal prefetches. 549.It Li t1 550Count prefetches to L1. 551.It Li t2 552Count prefetches to L2. 553.It Li wos 554Count weakly ordered stores. 555.El 556.Pp 557The default is to count non-temporal prefetches. 558.It Li p6-emon-pref-rqsts-dn 559.Pq Event F8H , Tn "Pentium M" 560Count the number of downward prefetches issued. 561.It Li p6-emon-pref-rqsts-up 562.Pq Event F0H , Tn "Pentium M" 563Count the number of upward prefetches issued. 564.It Li p6-emon-simd-instr-retired 565.Pq Event CEH , Tn "Pentium M" 566Count the number of retired 567.Tn MMX 568instructions. 569.It Li p6-emon-sse-sse2-comp-inst-retired Op Li ,umask= Ns Ar qualifier 570.Pq Event D9H , Tn "Pentium M" 571Count the number of computational SSE instructions retired. 572An additional qualifier may be specified and can be one of the 573following keywords: 574.Pp 575.Bl -tag -width indent -compact 576.It Li sse-packed-single 577Count SSE packed-single instructions. 578.It Li sse-scalar-single 579Count SSE scalar-single instructions. 580.It Li sse2-packed-double 581Count SSE2 packed-double instructions. 582.It Li sse2-scalar-double 583Count SSE2 scalar-double instructions. 584.El 585.Pp 586The default is to count SSE packed-single instructions. 587.It Li p6-emon-sse-sse2-inst-retired Op Li ,umask= Ns Ar qualifier 588.Pq Event D8H , Tn "Pentium M" 589Count the number of SSE instructions retired. 590An additional qualifier can be specified, and can be one of the 591following keywords: 592.Pp 593.Bl -tag -width indent -compact 594.It Li sse-packed-single 595Count SSE packed-single instructions. 596.It Li sse-packed-single-scalar-single 597Count SSE packed-single and scalar-single instructions. 598.It Li sse2-packed-double 599Count SSE2 packed-double instructions. 600.It Li sse2-scalar-double 601Count SSE2 scalar-double instructions. 602.El 603.Pp 604The default is to count SSE packed-single instructions. 605.It Li p6-emon-synch-uops 606.Pq Event D3H , Tn "Pentium M" 607Count the number of sync micro-ops. 608.It Li p6-emon-thermal-trip 609.Pq Event 59H , Tn "Pentium M" 610Count the duration or occurrences of thermal trips. 611Use the 612.Dq Li edge 613qualifier to count occurrences of thermal trips. 614.It Li p6-emon-unfusion 615.Pq Event DBH , Tn "Pentium M" 616Count the number of unfusion events in the reorder buffer. 617.It Li p6-flops 618.Pq Event C1H 619Count the number of computational floating point operations retired. 620This event is only allocated on counter 0. 621.It Li p6-fp-assist 622.Pq Event 11H 623Count the number of floating point exceptions handled by microcode. 624This event is only allocated on counter 1. 625.It Li p6-fp-comps-ops-exe 626.Pq Event 10H 627Count the number of computation floating point operations executed. 628This event is only allocated on counter 0. 629.It Li p6-fp-mmx-trans Op Li ,umask= Ns Ar qualifier 630.Pq Event CCH , Tn "Pentium II" , Tn "Pentium III" 631Count the number of transitions between MMX and floating-point 632instructions. 633An additional qualifier may be specified, and comprises one of the 634following keywords: 635.Pp 636.Bl -tag -width indent -compact 637.It Li mmxtofp 638Count transitions from MMX instructions to floating-point instructions. 639.It Li fptommx 640Count transitions from floating-point instructions to MMX instructions. 641.El 642.Pp 643The default is to count MMX to floating-point transitions. 644.It Li p6-hw-int-rx 645.Pq Event C8H 646Count the number of hardware interrupts received. 647.It Li p6-ifu-ifetch 648.Pq Event 80H 649Count the number of instruction fetches, both cacheable and non-cacheable. 650.It Li p6-ifu-ifetch-miss 651.Pq Event 81H 652Count the number of instruction fetch misses (i.e., those that produce 653memory accesses). 654.It Li p6-ifu-mem-stall 655.Pq Event 86H 656Count the number of cycles instruction fetch is stalled for any reason. 657.It Li p6-ild-stall 658.Pq Event 87H 659Count the number of cycles the instruction length decoder is stalled. 660.It Li p6-inst-decoded 661.Pq Event D0H 662Count the number of instructions decoded. 663.It Li p6-inst-retired 664.Pq Event C0H 665Count the number of instructions retired. 666.It Li p6-itlb-miss 667.Pq Event 85H 668Count the number of instruction TLB misses. 669.It Li p6-l2-ads 670.Pq Event 21H 671Count the number of L2 address strobes. 672.It Li p6-l2-dbus-busy 673.Pq Event 22H 674Count the number of cycles during which the L2 cache data bus was busy. 675.It Li p6-l2-dbus-busy-rd 676.Pq Event 23H 677Count the number of cycles during which the L2 cache data bus was busy 678transferring read data from L2 to the processor. 679.It Li p6-l2-ifetch Op Li ,umask= Ns Ar qualifier 680.Pq Event 28H 681Count the number of L2 instruction fetches. 682An additional qualifier may be specified and comprises a list of the following 683keywords separated by 684.Ql + 685characters: 686.Pp 687.Bl -tag -width indent -compact 688.It Li e 689Count operations affecting E (exclusive) state lines. 690.It Li i 691Count operations affecting I (invalid) state lines. 692.It Li m 693Count operations affecting M (modified) state lines. 694.It Li s 695Count operations affecting S (shared) state lines. 696.El 697.Pp 698The default is to count operations affecting all (MESI) state lines. 699.It Li p6-l2-ld Op Li ,umask= Ns Ar qualifier 700.Pq Event 29H 701Count the number of L2 data loads. 702An additional qualifier may be specified and comprises a list of the following 703keywords separated by 704.Ql + 705characters: 706.Pp 707.Bl -tag -width indent -compact 708.It Li both 709.Pq Tn "Pentium M" 710Count both hardware-prefetched lines and non-hardware-prefetched lines. 711.It Li e 712Count operations affecting E (exclusive) state lines. 713.It Li hw 714.Pq Tn "Pentium M" 715Count hardware-prefetched lines only. 716.It Li i 717Count operations affecting I (invalid) state lines. 718.It Li m 719Count operations affecting M (modified) state lines. 720.It Li nonhw 721.Pq Tn "Pentium M" 722Exclude hardware-prefetched lines. 723.It Li s 724Count operations affecting S (shared) state lines. 725.El 726.Pp 727The default on processors other than 728.Tn "Pentium M" 729processors is to count operations affecting all (MESI) state lines. 730The default on 731.Tn "Pentium M" 732processors is to count both hardware-prefetched and 733non-hardware-prefetch operations on all (MESI) state lines. 734.Pq Errata 735This event is affected by processor errata E53. 736.It Li p6-l2-lines-in Op Li ,umask= Ns Ar qualifier 737.Pq Event 24H 738Count the number of L2 lines allocated. 739An additional qualifier may be specified and comprises a list of the following 740keywords separated by 741.Ql + 742characters: 743.Pp 744.Bl -tag -width indent -compact 745.It Li both 746.Pq Tn "Pentium M" 747Count both hardware-prefetched lines and non-hardware-prefetched lines. 748.It Li e 749Count operations affecting E (exclusive) state lines. 750.It Li hw 751.Pq Tn "Pentium M" 752Count hardware-prefetched lines only. 753.It Li i 754Count operations affecting I (invalid) state lines. 755.It Li m 756Count operations affecting M (modified) state lines. 757.It Li nonhw 758.Pq Tn "Pentium M" 759Exclude hardware-prefetched lines. 760.It Li s 761Count operations affecting S (shared) state lines. 762.El 763.Pp 764The default on processors other than 765.Tn "Pentium M" 766processors is to count operations affecting all (MESI) state lines. 767The default on 768.Tn "Pentium M" 769processors is to count both hardware-prefetched and 770non-hardware-prefetch operations on all (MESI) state lines. 771.Pq Errata 772This event is affected by processor errata E45. 773.It Li p6-l2-lines-out Op Li ,umask= Ns Ar qualifier 774.Pq Event 26H 775Count the number of L2 lines evicted. 776An additional qualifier may be specified and comprises a list of the following 777keywords separated by 778.Ql + 779characters: 780.Pp 781.Bl -tag -width indent -compact 782.It Li both 783.Pq Tn "Pentium M" 784Count both hardware-prefetched lines and non-hardware-prefetched lines. 785.It Li e 786Count operations affecting E (exclusive) state lines. 787.It Li hw 788.Pq Tn "Pentium M" 789Count hardware-prefetched lines only. 790.It Li i 791Count operations affecting I (invalid) state lines. 792.It Li m 793Count operations affecting M (modified) state lines. 794.It Li nonhw 795.Pq Tn "Pentium M" only 796Exclude hardware-prefetched lines. 797.It Li s 798Count operations affecting S (shared) state lines. 799.El 800.Pp 801The default on processors other than 802.Tn "Pentium M" 803processors is to count operations affecting all (MESI) state lines. 804The default on 805.Tn "Pentium M" 806processors is to count both hardware-prefetched and 807non-hardware-prefetch operations on all (MESI) state lines. 808.Pq Errata 809This event is affected by processor errata E45. 810.It Li p6-l2-m-lines-inm 811.Pq Event 25H 812Count the number of modified lines allocated in L2 cache. 813.It Li p6-l2-m-lines-outm Op Li ,umask= Ns Ar qualifier 814.Pq Event 27H 815Count the number of L2 M-state lines evicted. 816.Pp 817.Pq Tn "Pentium M" 818On these processors an additional qualifier may be specified and 819comprises a list of the following keywords separated by 820.Ql + 821characters: 822.Pp 823.Bl -tag -width indent -compact 824.It Li both 825Count both hardware-prefetched lines and non-hardware-prefetched lines. 826.It Li hw 827Count hardware-prefetched lines only. 828.It Li nonhw 829Exclude hardware-prefetched lines. 830.El 831.Pp 832The default is to count both hardware-prefetched and 833non-hardware-prefetch operations. 834.Pq Errata 835This event is affected by processor errata E53. 836.It Li p6-l2-rqsts Op Li ,umask= Ns Ar qualifier 837.Pq Event 2EH 838Count the total number of L2 requests. 839An additional qualifier may be specified and comprises a list of the following 840keywords separated by 841.Ql + 842characters: 843.Pp 844.Bl -tag -width indent -compact 845.It Li e 846Count operations affecting E (exclusive) state lines. 847.It Li i 848Count operations affecting I (invalid) state lines. 849.It Li m 850Count operations affecting M (modified) state lines. 851.It Li s 852Count operations affecting S (shared) state lines. 853.El 854.Pp 855The default is to count operations affecting all (MESI) state lines. 856.It Li p6-l2-st 857.Pq Event 2AH 858Count the number of L2 data stores. 859An additional qualifier may be specified and comprises a list of the following 860keywords separated by 861.Ql + 862characters: 863.Pp 864.Bl -tag -width indent -compact 865.It Li e 866Count operations affecting E (exclusive) state lines. 867.It Li i 868Count operations affecting I (invalid) state lines. 869.It Li m 870Count operations affecting M (modified) state lines. 871.It Li s 872Count operations affecting S (shared) state lines. 873.El 874.Pp 875The default is to count operations affecting all (MESI) state lines. 876.It Li p6-ld-blocks 877.Pq Event 03H 878Count the number of load operations delayed due to store buffer blocks. 879.It Li p6-misalign-mem-ref 880.Pq Event 05H 881Count the number of misaligned data memory references (crossing a 64 882bit boundary). 883.It Li p6-mmx-assist 884.Pq Event CDH , Tn "Pentium II" , Tn "Pentium III" 885Count the number of MMX assists executed. 886.It Li p6-mmx-instr-exec 887.Pq Event B0H 888.Pq Tn Celeron , Tn "Pentium II" 889Count the number of MMX instructions executed, except MOVQ and MOVD 890stores from register to memory. 891.It Li p6-mmx-instr-ret 892.Pq Event CEH , Tn "Pentium II" 893Count the number of MMX instructions retired. 894.It Li p6-mmx-instr-type-exec Op Li ,umask= Ns Ar qualifier 895.Pq Event B3H , Tn "Pentium II" , Tn "Pentium III" 896Count the number of MMX instructions executed. 897An additional qualifier may be specified and comprises a list of 898the following keywords separated by 899.Ql + 900characters: 901.Pp 902.Bl -tag -width indent -compact 903.It Li pack 904Count MMX pack operation instructions. 905.It Li packed-arithmetic 906Count MMX packed arithmetic instructions. 907.It Li packed-logical 908Count MMX packed logical instructions. 909.It Li packed-multiply 910Count MMX packed multiply instructions. 911.It Li packed-shift 912Count MMX packed shift instructions. 913.It Li unpack 914Count MMX unpack operation instructions. 915.El 916.Pp 917The default is to count all operations. 918.It Li p6-mmx-sat-instr-exec 919.Pq Event B1H , Tn "Pentium II" , Tn "Pentium III" 920Count the number of MMX saturating instructions executed. 921.It Li p6-mmx-uops-exec 922.Pq Event B2H , Tn "Pentium II" , Tn "Pentium III" 923Count the number of MMX micro-ops executed. 924.It Li p6-mul 925.Pq Event 12H 926Count the number of integer and floating-point multiplies, including 927speculative multiplies. 928This event is only allocated on counter 1. 929.It Li p6-partial-rat-stalls 930.Pq Event D2H 931Count the number of cycles or events for partial stalls. 932.It Li p6-resource-stalls 933.Pq Event A2H 934Count the number of cycles there was a resource related stall of any kind. 935.It Li p6-ret-seg-renames 936.Pq Event D6H , Tn "Pentium II" , Tn "Pentium III" 937Count the number of segment register rename events retired. 938.It Li p6-sb-drains 939.Pq Event 04H 940Count the number of cycles the store buffer is draining. 941.It Li p6-seg-reg-renames Op Li ,umask= Ns Ar qualifier 942.Pq Event D5H , Tn "Pentium II" , Tn "Pentium III" 943Count the number of segment register renames. 944An additional qualifier may be specified, and comprises a list of the 945following keywords separated by 946.Ql + 947characters: 948.Pp 949.Bl -tag -width indent -compact 950.It Li ds 951Count renames for segment register DS. 952.It Li es 953Count renames for segment register ES. 954.It Li fs 955Count renames for segment register FS. 956.It Li gs 957Count renames for segment register GS. 958.El 959.Pp 960The default is to count operations affecting all segment registers. 961.It Li p6-seg-rename-stalls 962.Pq Event D4H , Tn "Pentium II" , Tn "Pentium III" 963Count the number of segment register renaming stalls. 964An additional qualifier may be specified, and comprises a list of the 965following keywords separated by 966.Ql + 967characters: 968.Pp 969.Bl -tag -width indent -compact 970.It Li ds 971Count stalls for segment register DS. 972.It Li es 973Count stalls for segment register ES. 974.It Li fs 975Count stalls for segment register FS. 976.It Li gs 977Count stalls for segment register GS. 978.El 979.Pp 980The default is to count operations affecting all the segment registers. 981.It Li p6-segment-reg-loads 982.Pq Event 06H 983Count the number of segment register loads. 984.It Li p6-uops-retired 985.Pq Event C2H 986Count the number of micro-ops retired. 987.El 988.Ss Event Name Aliases 989The following table shows the mapping between the PMC-independent 990aliases supported by 991.Lb libpmc 992and the underlying hardware events used. 993.Bl -column "branch-mispredicts" "Description" 994.It Em Alias Ta Em Event 995.It Li branches Ta Li p6-br-inst-retired 996.It Li branch-mispredicts Ta Li p6-br-miss-pred-retired 997.It Li dc-misses Ta Li p6-dcu-lines-in 998.It Li ic-misses Ta Li p6-ifu-fetch-miss 999.It Li instructions Ta Li p6-inst-retired 1000.It Li interrupts Ta Li p6-hw-int-rx 1001.It Li unhalted-cycles Ta Li p6-cpu-clk-unhalted 1002.El 1003.Sh SEE ALSO 1004.Xr pmc 3 , 1005.Xr pmc.atom 3 , 1006.Xr pmc.core 3 , 1007.Xr pmc.core2 3 , 1008.Xr pmc.iaf 3 , 1009.Xr pmc.k7 3 , 1010.Xr pmc.k8 3 , 1011.Xr pmc.p4 3 , 1012.Xr pmc.p5 3 , 1013.Xr pmc.soft 3 , 1014.Xr pmc.tsc 3 , 1015.Xr pmclog 3 , 1016.Xr hwpmc 4 1017.Sh HISTORY 1018The 1019.Nm pmc 1020library first appeared in 1021.Fx 6.0 . 1022.Sh AUTHORS 1023The 1024.Lb libpmc 1025library was written by 1026.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 1027