| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetOpcodes.h | 69 DBG_VALUE = 11, enumerator
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| HD | Target.td | 806 def DBG_VALUE : Instruction {
809 let AsmString = "DBG_VALUE";
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonAsmPrinter.cpp | 191 if (MII->getOpcode() == TargetOpcode::DBG_VALUE || in EmitInstruction()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | ExpandPostRAPseudos.cpp | 217 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
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| HD | LiveDebugVariables.cpp | 988 BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE), in insertDebugValue()
991 BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE)) in insertDebugValue()
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| HD | RegAllocFast.cpp | 308 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE)) in spillVirtReg()
880 TII->get(TargetOpcode::DBG_VALUE)) in AllocateBasicBlock()
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| HD | InlineSpiller.cpp | 1238 BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE)) in spillAroundUses()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64AsmPrinter.cpp | 378 MII->getOpcode() == AArch64::DBG_VALUE || in LowerSTACKMAP()
454 case AArch64::DBG_VALUE: { in EmitInstruction()
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| HD | AArch64InstrInfo.cpp | 51 case TargetOpcode::DBG_VALUE: in GetInstSizeInBytes()
1470 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) in emitFrameIndexDebugValue()
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | MachineInstr.h | 748 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
819 case TargetOpcode::DBG_VALUE:
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreAsmPrinter.cpp | 272 case XCore::DBG_VALUE: in EmitInstruction()
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430InstrInfo.cpp | 306 case TargetOpcode::DBG_VALUE: in GetInstSizeInBytes()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCRegisterInfo.cpp | 816 assert(OpC != PPC::DBG_VALUE && in eliminateFrameIndex()
1027 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm in isFrameOffsetLegal()
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| HD | PPCAsmPrinter.cpp | 346 MII->getOpcode() == PPC::DBG_VALUE || in LowerSTACKMAP()
506 case TargetOpcode::DBG_VALUE: in EmitInstruction()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | InstrEmitter.cpp | 661 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) in EmitDbgValue()
668 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
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| HD | FastISel.cpp | 1158 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0, in selectIntrinsicCall()
1162 TII.get(TargetOpcode::DBG_VALUE)) in selectIntrinsicCall()
1177 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in selectIntrinsicCall()
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| HD | SelectionDAGISel.cpp | 510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE), in runOnMachineFunction()
532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect, in runOnMachineFunction()
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| HD | SelectionDAGBuilder.cpp | 4072 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect, in EmitFuncArgumentDbgValue()
4076 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE)) in EmitFuncArgumentDbgValue()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcAsmPrinter.cpp | 263 case TargetOpcode::DBG_VALUE: in EmitInstruction()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86MCInstLower.cpp | 1048 case TargetOpcode::DBG_VALUE: in EmitInstruction()
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| HD | X86FrameLowering.cpp | 1066 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE && in emitEpilogue()
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| HD | X86FastISel.cpp | 2439 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in fastLowerIntrinsicCall()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMAsmPrinter.cpp | 1225 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); in EmitInstruction()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXAsmPrinter.cpp | 2017 case NVPTX::DBG_VALUE: in ignoreLoc()
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| /NextBSD/contrib/llvm/lib/CodeGen/AsmPrinter/ |
| HD | AsmPrinter.cpp | 833 case TargetOpcode::DBG_VALUE: in EmitFunctionBody()
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