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Searched refs:DPLL_VCO_ENABLE (Results 1 – 5 of 5) sorted by relevance

/NextBSD/sys/dev/drm/
HDi915_suspend.c43 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
45 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
390 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { in i915_restore_state()
392 ~DPLL_VCO_ENABLE); in i915_restore_state()
432 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { in i915_restore_state()
434 ~DPLL_VCO_ENABLE); in i915_restore_state()
HDi915_reg.h352 #define DPLL_VCO_ENABLE (1U << 31) macro
/NextBSD/sys/dev/drm2/i915/
HDi915_suspend.c49 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE); in i915_pipe_enabled()
459 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { in i915_restore_modeset_reg()
461 ~DPLL_VCO_ENABLE); in i915_restore_modeset_reg()
528 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { in i915_restore_modeset_reg()
530 ~DPLL_VCO_ENABLE); in i915_restore_modeset_reg()
HDintel_display.c922 cur_state = !!(val & DPLL_VCO_ENABLE); in assert_pll()
961 cur_state = !!(val & DPLL_VCO_ENABLE); in assert_pch_pll()
1313 val |= DPLL_VCO_ENABLE; in intel_enable_pll()
1350 val &= ~DPLL_VCO_ENABLE; in intel_disable_pll()
1454 val |= DPLL_VCO_ENABLE; in intel_enable_pch_pll()
1501 val &= ~DPLL_VCO_ENABLE; in intel_disable_pch_pll()
2993 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); in intel_get_pch_pll()
2998 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); in intel_get_pch_pll()
3879 dpll |= DPLL_VCO_ENABLE; in i9xx_update_pll()
3880 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); in i9xx_update_pll()
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HDi915_reg.h949 #define DPLL_VCO_ENABLE (1 << 31) macro