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Searched refs:DefMI (Results 1 – 25 of 35) sorted by relevance

12

/NextBSD/contrib/llvm/lib/Target/ARM/
HDMLxExpansionPass.cpp95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
97 if (DefMI->getParent() != MBB) in getAccDefMI()
99 if (DefMI->isCopyLike()) { in getAccDefMI()
100 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
106 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
114 return DefMI; in getAccDefMI()
149 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local
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HDARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
45 MachineInstr *DefMI = LastMI; in getHazardType() local
59 DefMI = &*I; in getHazardType()
63 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
65 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
HDARMBaseInstrInfo.cpp1837 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); in optimizeSelect() local
1838 bool Invert = !DefMI; in optimizeSelect()
1839 if (!DefMI) in optimizeSelect()
1840 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); in optimizeSelect()
1841 if (!DefMI) in optimizeSelect()
1854 DefMI->getDesc(), DestReg); in optimizeSelect()
1857 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
1860 NewMI.addOperand(DefMI->getOperand(i)); in optimizeSelect()
1883 SeenMIs.erase(DefMI); in optimizeSelect()
1889 if (DefMI->getParent() != MI->getParent()) in optimizeSelect()
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HDARMBaseInstrInfo.h269 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
276 const MachineInstr *DefMI, unsigned DefIdx,
332 const MachineInstr *DefMI, unsigned DefIdx,
336 const MachineInstr *DefMI,
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetSchedule.cpp155 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
159 return TII->defaultDefLatency(SchedModel, DefMI); in computeOperandLatency()
164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, in computeOperandLatency()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); in computeOperandLatency()
183 TII->defaultDefLatency(SchedModel, DefMI)); in computeOperandLatency()
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() in computeOperandLatency()
212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
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HDLiveRangeEdit.cpp52 const MachineInstr *DefMI, in checkRematerializable() argument
54 assert(DefMI && "Missing instruction"); in checkRematerializable()
56 if (!TII.isTriviallyReMaterializable(DefMI, aa)) in checkRematerializable()
66 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); in scanRemattable() local
67 if (!DefMI) in scanRemattable()
69 checkRematerializable(VNI, DefMI, aa); in scanRemattable()
166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
172 if (DefMI && DefMI != MI) in foldAsLoad()
176 DefMI = MI; in foldAsLoad()
186 if (!DefMI || !UseMI) in foldAsLoad()
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HDMachineTraceMetrics.cpp602 const MachineInstr *DefMI; member
606 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
607 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
615 DefMI = DefI->getParent(); in DataDep()
763 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local
765 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath()
768 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
836 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in computeInstrDepths()
841 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in computeInstrDepths()
843 if (!Dep.DefMI->isTransient()) in computeInstrDepths()
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HDTargetInstrInfo.cpp779 const MachineInstr *DefMI) const { in defaultDefLatency()
780 if (DefMI->isTransient()) in defaultDefLatency()
782 if (DefMI->mayLoad()) in defaultDefLatency()
784 if (isHighLatencyDef(DefMI->getOpcode())) in defaultDefLatency()
806 const MachineInstr *DefMI, in hasLowDefLatency() argument
812 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
821 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
823 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
832 const MachineInstr *DefMI) const { in computeDefOperandLatency()
836 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency()
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HDInlineSpiller.cpp113 MachineInstr *DefMI; member
124 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {} in SibValueInfo()
127 bool hasDef() const { return DefByOrigPHI || DefMI; } in hasDef()
335 if (SVI.DefMI) in operator <<()
336 OS << " def: " << *SVI.DefMI; in operator <<()
399 DepSV.DefMI = SV.DefMI; in propagateSiblingValue()
500 return SVI->second.DefMI; in traceSiblingValue()
621 SVI->second.DefMI = MI; in traceSiblingValue()
642 return SVI->second.DefMI; in traceSiblingValue()
665 MachineInstr *DefMI = nullptr; in analyzeSiblingValues() local
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HDRegisterCoalescer.cpp670 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local
671 if (!DefMI) in removeCopyByCommutingDef()
673 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
677 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef()
680 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
683 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) in removeCopyByCommutingDef()
692 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef()
717 << *DefMI); in removeCopyByCommutingDef()
721 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef()
722 MachineInstr *NewMI = TII->commuteInstruction(DefMI); in removeCopyByCommutingDef()
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HDPHIElimination.cpp158 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
159 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
162 LIS->RemoveMachineInstrFromMaps(DefMI); in runOnMachineFunction()
163 DefMI->eraseFromParent(); in runOnMachineFunction()
395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
396 if (DefMI->isImplicitDef()) in LowerPHINode()
397 ImpDefs.insert(DefMI); in LowerPHINode()
HDMachineCSE.cpp133 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
134 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
136 unsigned SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
139 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
153 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
158 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
165 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
HDTwoAddressInstructionPass.cpp320 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in getSingleDef()
321 if (DefMI.getParent() != BB || DefMI.isDebugValue()) in getSingleDef()
324 Ret = &DefMI; in getSingleDef()
325 else if (Ret != &DefMI) in getSingleDef()
449 MachineInstr *DefMI = &MI; in isKilled() local
455 if (!isPlainlyKilled(DefMI, Reg, LIS)) in isKilled()
464 DefMI = Begin->getParent(); in isKilled()
469 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
991 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in isDefTooClose()
992 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) in isDefTooClose()
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HDEarlyIfConversion.cpp245 MachineInstr *DefMI = MRI->getVRegDef(Reg); in canSpeculateInstrs() local
246 if (!DefMI || DefMI->getParent() != Head) in canSpeculateInstrs()
248 if (InsertAfter.insert(DefMI).second) in canSpeculateInstrs()
249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); in canSpeculateInstrs()
250 if (DefMI->isTerminator()) { in canSpeculateInstrs()
HDMachineSink.cpp174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in INITIALIZE_PASS_DEPENDENCY() local
175 if (DefMI->isCopyLike()) in INITIALIZE_PASS_DEPENDENCY()
177 DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
393 MachineInstr *DefMI = MRI->getVRegDef(Reg); in isWorthBreakingCriticalEdge() local
394 if (DefMI->getParent() == MI->getParent()) in isWorthBreakingCriticalEdge()
HDPeepholeOptimizer.cpp1163 MachineInstr *DefMI = nullptr; in runOnMachineFunction() local
1166 DefMI); in runOnMachineFunction()
1173 LocalMIs.erase(DefMI); in runOnMachineFunction()
1176 DefMI->eraseFromParent(); in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsOptimizePICCall.cpp261 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
263 assert(DefMI); in isCallViaRegister()
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
276 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
277 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
279 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetInstrInfo.h1022 MachineInstr *&DefMI) const { in optimizeLoadInstr() argument
1032 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument
1065 const MachineInstr *DefMI, unsigned DefIdx,
1072 const MachineInstr *DefMI, unsigned DefIdx,
1090 const MachineInstr *DefMI) const;
1093 const MachineInstr *DefMI) const;
1106 const MachineInstr *DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1115 const MachineInstr *DefMI, unsigned DefIdx) const;
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCVSXSwapRemoval.cpp592 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
593 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
595 int DefIdx = SwapMap[DefMI]; in formWebs()
602 DEBUG(DefMI->dump()); in formWebs()
672 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
673 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
683 DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
728 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval() local
729 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval()
733 DEBUG(DefMI->dump()); in markSwapsForRemoval()
HDPPCInstrInfo.h103 const MachineInstr *DefMI, unsigned DefIdx,
114 const MachineInstr *DefMI, in hasLowDefLatency() argument
178 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
HDPPCInstrInfo.cpp141 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
147 const MachineOperand &DefMO = DefMI->getOperand(DefIdx); in getOperandLatency()
153 &DefMI->getParent()->getParent()->getRegInfo(); in getOperandLatency()
163 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
1131 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, in FoldImmediate() argument
1135 unsigned DefOpc = DefMI->getOpcode(); in FoldImmediate()
1138 if (!DefMI->getOperand(1).isImm()) in FoldImmediate()
1140 if (DefMI->getOperand(1).getImm() != 0) in FoldImmediate()
1194 DefMI->eraseFromParent(); in FoldImmediate()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86CallFrameOptimization.cpp527 MachineBasicBlock::iterator DefMI = MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
531 if (DefMI->getOpcode() != X86::MOV32rm || in canFoldIntoRegPush()
532 DefMI->getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
540 for (auto I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
544 return DefMI; in canFoldIntoRegPush()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDTargetSchedule.h156 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
178 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
HDMachineTraceMetrics.h294 bool isDepInTrace(const MachineInstr *DefMI,
314 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.cpp286 const MachineInstr *DefMI = MRI.getVRegDef(VReg); in removeCopies() local
287 if (!DefMI->isFullCopy()) in removeCopies()
289 VReg = DefMI->getOperand(1).getReg(); in removeCopies()
304 const MachineInstr *DefMI = MRI.getVRegDef(VReg); in canFoldIntoCSel() local
307 switch (DefMI->getOpcode()) { in canFoldIntoCSel()
311 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
317 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 || in canFoldIntoCSel()
318 DefMI->getOperand(3).getImm() != 0) in canFoldIntoCSel()
327 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel()
338 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
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