Searched refs:FMAD (Results 1 – 9 of 9) sorted by relevance
| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 244 FMAD, enumerator
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | SIISelLowering.cpp | 1849 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS); in PerformDAGCombine()
1858 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS); in PerformDAGCombine()
1887 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS); in PerformDAGCombine()
1897 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS); in PerformDAGCombine()
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| HD | AMDGPUISelLowering.cpp | 140 setOperationAction(ISD::FMAD, MVT::f32, Legal); in AMDGPUTargetLowering()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 192 case ISD::FMAD: return "fmad"; in getOperationName()
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| HD | LegalizeFloatTypes.cpp | 1772 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
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| HD | DAGCombiner.cpp | 7439 TLI.isOperationLegal(ISD::FMAD, VT)); in visitFADDForFMACombine()
7452 unsigned int PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
7616 TLI.isOperationLegal(ISD::FMAD, VT)); in visitFSUBForFMACombine()
7629 unsigned int PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
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| HD | LegalizeDAG.cpp | 3475 case ISD::FMAD: in ExpandNode()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 817 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 411 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
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