Searched refs:FMINNUM (Results 1 – 18 of 18) sorted by relevance
| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 509 FMINNUM, FMAXNUM, enumerator
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| HD | BasicTTIImpl.h | 647 ISD = ISD::FMINNUM; in getIntrinsicInstrCost()
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| HD | SelectionDAG.h | 1089 case ISD::FMINNUM:
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | SIISelLowering.cpp | 79 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
212 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
1700 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
1789 case ISD::FMINNUM: in PerformDAGCombine()
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| HD | AMDGPUISelLowering.cpp | 129 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
379 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering()
970 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SelectionDAGDumper.cpp | 146 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| HD | LegalizeFloatTypes.cpp | 71 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
894 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
1765 case ISD::FMINNUM: in PromoteFloatResult()
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| HD | LegalizeVectorOps.cpp | 299 case ISD::FMINNUM: in LegalizeOp()
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| HD | LegalizeVectorTypes.cpp | 109 case ISD::FMINNUM: in ScalarizeVectorResult()
662 case ISD::FMINNUM: in SplitVectorResult()
1950 case ISD::FMINNUM: in WidenVectorResult()
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| HD | LegalizeDAG.cpp | 3347 case ISD::FMINNUM: in ExpandNode()
4285 case ISD::FMINNUM: in PromoteNode()
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| HD | DAGCombiner.cpp | 1390 case ISD::FMINNUM: return visitFMINNUM(N); in visit()
4879 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; in combineMinNumMaxNum()
4890 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; in combineMinNumMaxNum()
8866 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0); in visitFMINNUM()
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| HD | SelectionDAGBuilder.cpp | 4583 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl, in visitIntrinsicCall()
5575 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 815 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
863 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
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| /NextBSD/contrib/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 413 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelLowering.cpp | 1494 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 682 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering()
728 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 316 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand); in X86TargetLowering()
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