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Searched refs:FSQRT (Results 1 – 25 of 32) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86IntrinsicsInfo.h753 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
754 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
755 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
757 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
758 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
759 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
980 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
981 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
1048 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0),
1094 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0),
/NextBSD/contrib/one-true-awk/
HDawk.h116 #define FSQRT 2 macro
HDlex.c82 { "sqrt", FSQRT, BLTIN },
HDrun.c1502 case FSQRT: in bltin()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h506 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
HDBasicTTIImpl.h191 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
620 ISD = ISD::FSQRT; in getIntrinsicInstrCost()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCCTRLoops.cpp299 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
340 Opcode = ISD::FSQRT; break; in mightUseCTR()
HDPPCISelLowering.cpp182 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
448 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
561 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
779 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
785 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
853 setTargetDAGCombine(ISD::FSQRT); in PPCTargetLowering()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp149 case ISD::FSQRT: return "fsqrt"; in getOperationName()
HDLegalizeFloatTypes.cpp97 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
917 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
1758 case ISD::FSQRT: in PromoteFloatResult()
HDLegalizeVectorOps.cpp302 case ISD::FSQRT: in LegalizeOp()
HDLegalizeVectorTypes.cpp93 case ISD::FSQRT: in ScalarizeVectorResult()
641 case ISD::FSQRT: in SplitVectorResult()
2010 case ISD::FSQRT: in WidenVectorResult()
HDDAGCombiner.cpp1378 case ISD::FSQRT: return visitFSQRT(N); in visit()
8296 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
8301 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
8308 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
8319 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
8322 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
13161 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
HDLegalizeDAG.cpp3357 case ISD::FSQRT: in ExpandNode()
4321 case ISD::FSQRT: in PromoteNode()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64SchedCyclone.td546 // FDIV,FSQRT
548 // TODO: Specialize FSQRT for longer latency.
HDAArch64ISelLowering.cpp176 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
308 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in AArch64TargetLowering()
352 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); in AArch64TargetLowering()
384 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); in AArch64TargetLowering()
539 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); in AArch64TargetLowering()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1603 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1628 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
2831 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsInstrFPU.td350 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
HDMipsSEISelLowering.cpp318 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1887 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1431 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1490 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td417 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp1228 if (RHS.getOpcode() == ISD::FSQRT) in LowerFastFDIV()
HDAMDGPUISelLowering.cpp395 setOperationAction(ISD::FSQRT, VT, Expand); in AMDGPUTargetLowering()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp462 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); in ARMTargetLowering()
480 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in ARMTargetLowering()
497 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand); in ARMTargetLowering()
622 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in ARMTargetLowering()
/NextBSD/contrib/llvm/tools/clang/include/clang/Basic/
HDarm_neon.td958 def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">;

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