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Searched refs:FalseReg (Results 1 – 9 of 9) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetInstrInfo.h580 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
604 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.cpp363 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, in canInsertSelect() argument
368 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
384 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
406 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
514 TrueReg = FalseReg; in insertSelect()
516 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
520 FalseReg = NewVReg; in insertSelect()
529 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
532 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
HDAArch64InstrInfo.h151 unsigned TrueReg, unsigned FalseReg) const override;
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrInfo.h156 unsigned TrueReg, unsigned FalseReg) const override;
HDPPCInstrInfo.cpp626 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
642 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
667 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
677 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
706 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
707 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrInfo.h293 unsigned TrueReg, unsigned FalseReg) const override;
HDX86InstrInfo.cpp3731 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
3745 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3768 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
3774 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); in insertSelect()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseInstrInfo.cpp1845 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1); in optimizeSelect() local
1847 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
1877 FalseReg.setImplicit(); in optimizeSelect()
1878 NewMI.addOperand(FalseReg); in optimizeSelect()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp4844 unsigned FalseReg = MI->getOperand(2).getReg(); in emitSelect() local
4873 .addReg(FalseReg).addMBB(FalseMBB); in emitSelect()